CN109215563B - Data writing control method, unit, pixel driving circuit and display device - Google Patents
Data writing control method, unit, pixel driving circuit and display device Download PDFInfo
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- CN109215563B CN109215563B CN201811415527.5A CN201811415527A CN109215563B CN 109215563 B CN109215563 B CN 109215563B CN 201811415527 A CN201811415527 A CN 201811415527A CN 109215563 B CN109215563 B CN 109215563B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/02—Improving the quality of display appearance
- G09G2320/0233—Improving the luminance or brightness uniformity across the screen
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Abstract
The invention provides a data writing control method, a unit, a pixel driving circuit and a display device. The data write control method includes: in the nth pre-writing time period, the data driving circuit provides an nth data voltage to the data line so that the voltage on the data line is changed to the nth data voltage; there is no overlap between different data providing periods. N is a positive integer less than or equal to N, N being an integer greater than 1. The invention can effectively reduce the influence of the load generated by resistance-capacitance on the display brightness, the charging efficiency can reach that the difference between the first row of sub-pixel circuits and the following rows of sub-pixel circuits is not large in the time of starting the corresponding multiplexing control signal, the influence of panel load is reduced, and the image quality under the condition of low gray scale is optimized.
Description
Technical Field
The present invention relates to the field of display technologies, and in particular, to a data writing control method, a data writing control unit, a pixel driving circuit, and a display device.
Background
With the advent of the full-screen design era, in order to pursue the process and cost, a data line is used to supply a data voltage to N columns of sub-pixel circuits, where N is an integer greater than 1. When N is equal to 2, the data line is controlled by the first multiplexing control signal MUX1 and the second multiplexing control signal MUX2 to time-share and provide the corresponding data voltages for the two columns of sub-pixel circuits, however, each row of sub-pixel circuits has equivalent resistance and equivalent capacitance, which may cause an RC Delay effect on the transmission path of the data voltage signal, that is: when the scanning starts to the first row of scanning lines, the data voltage signal can be completely started, the charging time can be basically ensured, however, the more backward, due to the existence of the equivalent RC (resistance capacitance), when scanning the scan line at the back end (i.e. the scan line at the back end, i.e. the scan line farther from the data driving circuit), the data voltage charging time will be less and less, thus, in the case of low gray scale, when the influence of IR Drop (IR Drop, which is a phenomenon indicating that the voltage drops or rises on the power supply and ground network in the integrated circuit) is slight, Source Loading (data line Loading) is a main factor, and when the scan line farther from the data driving circuit is scanned, the sub-pixel circuits in the corresponding row will have larger abnormal brightness due to the shorter charging time than the previous one, resulting in non-uniform brightness of the display panel, which will affect the subjective feeling of the client.
Disclosure of Invention
The present invention is directed to a data writing control method, a data writing control unit, a pixel driving circuit and a display device, which solve the problem in the prior art that when a scan line farther from a data driving circuit is scanned, sub-pixel circuits in a corresponding row will have a shorter charging time than before, resulting in non-uniform brightness of a display panel.
In order to achieve the above object, the present invention provides a data writing control method, applied to a pixel driving circuit, where the pixel driving circuit includes N multiplexing control circuits, where the nth multiplexing control circuit is used to control a data line to communicate with an nth column of sub-pixel circuits in an nth writing time period under the control of an nth multiplexing control signal, where N is an integer greater than 1, and N is a positive integer less than or equal to N; the data line is connected with the data driving circuit, and the nth data providing time period comprises an nth pre-writing time period and an nth writing time period which are sequentially arranged; the data write control method includes:
in the nth pre-write period, the data driving circuit supplies an nth data voltage to a data line so that a voltage on the data line is changed to the nth data voltage;
there is no overlap between different data providing periods.
In practice, the data writing control method of the present invention further includes:
in the nth writing period, the data driving circuit supplies an nth data voltage to the data line so that a voltage on the data line is maintained as the nth data voltage.
When the method is implemented, the mth row of pixels charging stage comprises an mth row of data providing stage and an mth row of scanning line opening stage which are sequentially arranged; m is a positive integer;
the mth row of data providing stage comprises N data providing time periods which are sequentially set;
the data write control method further includes:
and in the m-th row scanning line opening stage, the m-th row scanning line is opened to control the m-th row and n-th column sub-pixel circuits to be charged through the n-th data voltage.
In practice, the data writing control method of the present invention further includes: providing an m-th row synchronizing signal to the m-th row scanning line;
and controlling the m-th line synchronizing signal to be effective before the m-th line data providing phase starts.
The invention also provides a data writing control unit which is applied to a pixel driving circuit, wherein the pixel driving circuit comprises N multiplexing control circuits, the nth multiplexing control circuit is used for controlling a data line to be communicated with the nth column of sub-pixel circuits under the control of the nth multiplexing control signal in the nth writing time period, N is an integer larger than 1, and N is a positive integer smaller than or equal to N; the data line is connected with the data driving circuit, and the data writing control unit includes:
a write control circuit for controlling the data driving circuit to supply an nth data voltage to a data line in an nth pre-write period so that a voltage on the data line is changed to the nth data voltage; the nth pre-writing time period and the nth writing time period are sequentially set, the nth pre-writing time period and the nth writing time period are included in the nth data providing time period, and N is a positive integer less than or equal to N; there is no overlap between different data providing periods.
In practice, the write control circuit is further configured to control the data driving circuit to provide the nth data voltage to the data line in the nth write period, so that the voltage on the data line is maintained at the nth data voltage.
When the method is implemented, the mth row of pixels charging stage comprises an mth row of data providing stage and an mth row of scanning line opening stage which are sequentially arranged; m is a positive integer; the mth row of data providing stage comprises N data providing time periods which are sequentially set;
the data write control unit further includes:
and the scanning line control circuit is used for controlling the scanning line of the mth row to be opened in the scanning line opening stage of the mth row so as to control the charging of the sub-pixel circuit of the nth row and the nth column through the nth data voltage.
In practice, the data write control unit of the present invention further includes: and the line synchronizing signal providing circuit is used for providing an mth line synchronizing signal for the mth line scanning line and controlling the mth line synchronizing signal to be effective before the mth line data providing stage begins.
The invention also provides a pixel driving circuit which comprises the data writing control unit.
In practice, the pixel driving circuit of the present invention further comprises N multiplexing control circuits;
the control end of the nth multiplexing control circuit is connected with the nth multiplexing control end, the first end of the nth multiplexing control circuit is connected with a data line, the second end of the nth multiplexing control circuit is connected with the nth column of sub-pixel circuits, and the nth multiplexing control end is used for inputting an nth multiplexing control signal;
the nth multiplexing control circuit is used for controlling a data line to be communicated with the nth column of sub-pixel circuits under the control of an nth multiplexing control signal in an nth writing time period;
n is an integer greater than 1, and N is a positive integer less than or equal to N.
The display device comprises the pixel driving circuit.
In practice, the mth row and nth column sub-pixel circuit comprises an mth row and nth column charging control sub-circuit, an mth row and nth column energy storage sub-circuit, an mth row and nth column pixel driving sub-circuit and an mth row and nth column light-emitting element; m is a positive integer;
the control end of the charging control sub-circuit of the nth row and the nth column of the mth row is connected with the scanning line of the mth row, and the charging control sub-circuit of the nth row and the nth column of the mth row is used for controlling the charging of the energy storage sub-circuit of the nth row and the mth column through the nth data voltage under the control of the scanning line of the mth row;
the pixel driving sub-circuit of the mth row and the nth column is used for driving the light-emitting element of the mth row and the nth column to emit light according to the charges stored in the energy storage sub-circuit of the mth row and the nth column.
Compared with the prior art, in the nth data providing time period, the nth pre-writing time period is set before the nth writing time period, and in the nth pre-writing time period, the data driving circuit provides the nth data voltage to the data line, so that the voltage on the data line is changed to the nth data voltage, that is, the time for providing the data voltage by the data line is advanced, so that the voltage on the data line is changed to the nth data voltage before the nth writing time period starts, thereby effectively alleviating the influence of a load generated by resistance and capacitance on display brightness, and in the time when a corresponding multiplexing control signal is turned on, the charging efficiency can reach that the difference between a first row of sub-pixel circuits and a plurality of rows of sub-pixel circuits positioned behind is not large, the influence of panel load is reduced, and the image quality under the condition of low gray scale is optimized.
Drawings
Fig. 1 is a circuit diagram of a pixel driving circuit to which a data write control method according to an embodiment of the present invention is applied;
FIG. 2 is a waveform diagram illustrating operation of an embodiment of the pixel driving circuit shown in FIG. 1;
FIG. 3 is a block diagram of one embodiment of the m-th row and first column subpixel circuit Pixel 1;
fig. 4 is an operation waveform diagram of the waveform of the m-th row synchronizing signal HSYNC-m added to fig. 2.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The transistors used in all embodiments of the present invention may be transistors, thin film transistors, or field effect transistors or other devices with the same characteristics. In the embodiment of the present invention, in order to distinguish two poles of the transistor except the control pole, one pole is called a first pole, and the other pole is called a second pole.
In practical operation, when the transistor is a triode, the control electrode may be a base electrode, the first electrode may be a collector electrode, and the second electrode may be an emitter electrode; alternatively, the control electrode may be a base electrode, the first electrode may be an emitter electrode, and the second electrode may be a collector electrode.
In practical operation, when the transistor is a thin film transistor or a field effect transistor, the control electrode may be a gate electrode, the first electrode may be a drain electrode, and the second electrode may be a source electrode; alternatively, the control electrode may be a gate electrode, the first electrode may be a source electrode, and the second electrode may be a drain electrode.
The data writing control method is applied to a pixel driving circuit, the pixel driving circuit comprises N multiplexing control circuits, the nth multiplexing control circuit is used for controlling a data line to be communicated with an nth column of sub-pixel circuits under the control of an nth multiplexing control signal in an nth writing time period, N is an integer larger than 1, and N is a positive integer smaller than or equal to N; the data line is connected with the data driving circuit, and the nth data providing time period comprises an nth pre-writing time period and an nth writing time period which are sequentially arranged; the data write control method includes:
in the nth pre-write period, the data driving circuit supplies an nth data voltage to a data line so that a voltage on the data line is changed to the nth data voltage;
there is no overlap between different data providing periods.
In the following specific embodiment of the present invention, N is equal to 2 as an example, but in actual operation, N may also be an integer greater than 2, and the value of N may be selected according to actual situations.
In the data write control method according to the embodiment of the present invention, in the nth data providing period, the nth pre-write period is set before the nth write period, the data driving circuit supplies an nth data voltage to a data line during the nth pre-write period, so that the voltage on the data line is changed to the nth data voltage, that is, the time for providing the data voltage by the data line is shifted forward in the embodiment of the present invention, so that the voltage on the data line is changed into the nth data voltage before the nth writing time period is started, thereby effectively alleviating the influence of the load generated by the resistance-capacitance on the display brightness, in the time of opening the corresponding multiplexing control signal, the charging efficiency can reach the condition that the phase difference between the first row of sub-pixel circuits and the following rows of sub-pixel circuits is not large, the influence of panel load is reduced, and the image quality under the condition of low gray scale is optimized.
The first row of sub-pixel circuits refers to a row of sub-pixel circuits closest to a data driving circuit for supplying data voltages, and the following rows of sub-pixel circuits refer to rows of sub-pixel circuits farther from the data driving circuit.
Since it takes a certain time for the voltage on the data line to rise from 0 to the corresponding data voltage, in order to increase the time for writing the corresponding data voltage into the corresponding sub-pixel circuit, the embodiment of the invention advances the turn-on time of the data line by a predetermined time T1, so as to reduce the influence of the panel load.
In specific implementation, the data write control method may further include: in the nth writing period, the data driving circuit supplies an nth data voltage to the data line so that a voltage on the data line is maintained as the nth data voltage. Specifically, the m-th row of pixels charging phase may include an m-th row of data providing phase and an m-th row of scan line opening phase that are sequentially set; m is a positive integer;
the mth row of data providing stage comprises N data providing time periods which are sequentially set;
the data write control method further includes:
and in the m-th row scanning line opening stage, the m-th row scanning line is opened to control the m-th row and n-th column sub-pixel circuits to be charged through the n-th data voltage.
As shown in fig. 1, the pixel driving circuit to which the data writing control method according to the embodiment of the present invention is applied may include a first multiplexing control circuit 11 and a second multiplexing control circuit 12;
the first multiplexing control circuit 11 is used for controlling a Data line Data to write a first Data voltage Vdata1 to a first column sub-pixel circuit (only an mth row and a first column sub-pixel circuit Pixelm1 are exemplarily shown in fig. 1, m is a positive integer) under the control of a first multiplexing control signal MUX1 in a first writing period;
the second multiplexing control circuit 12 is used for controlling the Data lines Data to write a second Data voltage Vdata2 to the second column sub-pixel circuit (only the mth row and second column sub-pixel circuit Pixelm2 are exemplarily shown in fig. 1, m is a positive integer) under the control of a second multiplexing control signal MUX2 in a second writing period;
both the pixel 1 and the pixel 2 are connected to the m-th scan line Scanm.
In operation of the pixel driving circuit shown in fig. 1, the second writing period is set after the second pre-writing period, and an m-th row scan line turn-on phase is set after the second writing period, in the m-th row scan line turn-on phase, the m-th row scan line is turned on to control charging of the m-th row first column sub-pixel circuit by the first data voltage Vdata1, and charging of the m-th row second column sub-pixel circuit by the second data voltage Vdata 2.
Fig. 2 is an operation waveform diagram of an embodiment of the pixel driving circuit shown in fig. 1.
As shown in fig. 2, a first data providing period denoted by S1, a first writing period denoted by S12, and a first pre-writing period denoted by S11; a second data providing period denoted by S2, a second writing period denoted by S22, a second pre-writing period denoted by S21, and an m-th row scan line turn-on phase denoted by Sgm, wherein the first data providing period S1 and the second data providing period S2 do not overlap.
As shown in fig. 2, in operation of the embodiment of the pixel driving circuit shown in fig. 1,
in the first pre-write period S11, the Data driving circuit supplies the first Data voltage Vdata1 to the Data line Data, and the voltage on the Data gradually rises from the beginning to the rise to Vdata 1;
in the first write period S12, the Data driving circuit supplies a first Data voltage Vdata1 to the Data line Data such that the voltage on the Data line Data is maintained as the first Data voltage Vdata 1; the MUX1 is at low level, the first multiplexing control circuit 11 controls the Data lines Data to write the first Data voltage Vdata1 to Pixelm1 under the control of the MUX 1;
in the second pre-write period S21, the Data driving circuit supplies the second Data voltage Vdata2 to the Data line Data, and the voltage on the Data is gradually changed to Vdata2 (the process of changing the voltage on the Data line Data from Vdata1 to Vdata2 is not shown in fig. 2);
in a second writing period S22, the Data driving circuit supplies a second Data voltage Vdata2 to the Data line Data such that the voltage on the Data line Data is maintained as the second Data voltage Vdata 2; the MUX2 is at low level, the second multiplexing control circuit 12 controls the Data lines Data to write the second Data voltages Vdata2 to Pixelm2 under the control of the MUX 1;
in the m-th row scan line on phase Sgm, Scanm outputs a low level to charge Pixelm1 through Vdata1 and Pixelm2 through Vdata 2.
According to a specific embodiment, as shown in fig. 3, the mth row and first column sub-pixel circuit Pixelm1 may include an mth row and first column charge control sub-circuit 31, an mth row and first column energy storage sub-circuit 32, an mth row and first column pixel driving sub-circuit 33, and an mth row and first column light-emitting element Elm 1; m is a positive integer;
the control end of the m-th row and first column charging control sub-circuit 31 is connected to a m-th row scan line Scanm, and the m-th row and first column charging control sub-circuit 31 is configured to control charging of the m-th row and first column energy storage sub-circuit 32 through a first Data voltage Data1 under the control of the m-th row scan line Scanm;
the m-th row and first column pixel driving sub-circuit 33 is configured to drive the m-th row and first column light-emitting element Elm1 to emit light according to the charge stored in the m-th row and first column energy storage sub-circuit 32.
In specific implementation, in the first writing period S12, the MUX1 is at a low level, and the first multiplexing control circuit 11 controls the Data lines Data to write the first Data voltage Vdata1 to the m-th row and first column charge control sub-circuit 31 included in the Pixelm1 under the control of the MUX 1;
scann outputs a low level during the scan line on phase Sgm of the mth row, and the charge control sub-circuit 31 in the mth row and the first column controls the charge of the energy storage sub-circuit 32 in the mth row and the first column through the first Data voltage Data1 under the control of the scan line Scann of the mth row.
In actual operation, the structure of the mth row and second column sub-pixel circuit Pixelm2 may be the same as that of the mth row and first column sub-pixel circuit Pixelm1 shown in fig. 3.
Specifically, the data write control method of the present invention further includes: providing an m-th row synchronizing signal to the m-th row scanning line;
and controlling the m-th line synchronizing signal to be effective before the m-th line data providing phase starts.
In specific implementation, the corresponding row synchronization signal needs to be valid before the data line outputs the data voltage, so that the mth row synchronization signal needs to be controlled to be valid before the mth row data providing phase starts.
In FIG. 4, designated HSYNC-m is the m-th row sync signal, HSYNC-m is active when HSYNC-m is high. As shown in fig. 4, the time gap between the first falling edge of HSYNC and the first falling edge of MUX1 is T, and the Data turn-on time is advanced by a predetermined time T1 compared to the prior art, and T needs to be set to be greater than T1, so as to ensure that the mth row synchronizing signal HSYNC-m is controlled to be valid before the mth Data providing phase starts.
The data writing control unit is applied to a pixel driving circuit, the pixel driving circuit comprises N multiplexing control circuits, the nth multiplexing control circuit is used for controlling a data line to be communicated with an nth column of sub-pixel circuits under the control of an nth multiplexing control signal in an nth writing time period, N is an integer larger than 1, and N is a positive integer smaller than or equal to N; the data line is connected with the data driving circuit, and the data writing control unit includes:
a write control circuit for controlling the data driving circuit to supply an nth data voltage to the data line so that a voltage on the data line changes to the nth data voltage in an nth pre-write period;
the nth pre-writing time period and the nth writing time period are sequentially set, and the nth pre-writing time period and the nth writing time period are included in the nth data providing time period; there is no overlap between different data providing periods.
The data write control unit controls the data driving circuit to provide the nth data voltage to the corresponding data line in the nth pre-write time period through the write control circuit, so that the voltage on the data line is changed to the nth data voltage, and the time for providing the data voltage by the data line is moved forward, so that the influence of a load generated by resistance-capacitance on display brightness can be effectively relieved.
In a specific implementation, the write control circuit is further configured to control the data driving circuit to provide the nth data voltage to the data line in the nth write period, so that the voltage on the data line is maintained at the nth data voltage.
Specifically, the m-th row of pixels charging phase may include an m-th row of data providing phase and an m-th row of scan line opening phase that are sequentially set; m is a positive integer; the mth row of data providing stage comprises N data providing time periods which are sequentially set;
the data write control unit further includes:
and the scanning line control circuit is used for controlling the scanning line of the mth row to be opened in the scanning line opening stage of the mth row so as to control the charging of the sub-pixel circuit of the nth row and the nth column through the nth data voltage.
Specifically, the data write control unit of the present invention may further include: and the line synchronizing signal providing circuit is used for providing an mth line synchronizing signal for the mth line scanning line and controlling the mth line synchronizing signal to be effective before the mth line data providing stage begins.
In specific implementation, the corresponding row synchronization signal needs to be valid before the data line outputs the data voltage, so that the mth row synchronization signal needs to be valid through the control of the row synchronization signal providing circuit before the mth row data providing phase begins.
The pixel driving circuit according to the embodiment of the invention includes the data writing control unit.
In a specific implementation, the pixel driving circuit of the present invention may further include N multiplexing control circuits;
the control end of the nth multiplexing control circuit is connected with the nth multiplexing control end, the first end of the nth multiplexing control circuit is connected with a data line, the second end of the nth multiplexing control circuit is connected with the nth column of sub-pixel circuits, and the nth multiplexing control end is used for inputting an nth multiplexing control signal;
the nth multiplexing control circuit is used for controlling a data line to be communicated with the nth column of sub-pixel circuits under the control of an nth multiplexing control signal in an nth writing time period so as to write an nth data voltage into the nth column of sub-pixel circuits;
n is an integer greater than 1, and N is a positive integer less than or equal to N.
In practical operation, N may be equal to 2, or may be an integer greater than 2.
The display device provided by the embodiment of the invention comprises the pixel driving circuit.
In specific implementation, the mth row and nth column sub-pixel circuit comprises an mth row and nth column charging control sub-circuit, an mth row and nth column energy storage sub-circuit, an mth row and nth column pixel driving sub-circuit and an mth row and nth column light-emitting element; m is a positive integer;
the control end of the charging control sub-circuit of the nth row and the nth column of the mth row is connected with the scanning line of the mth row, and the charging control sub-circuit of the nth row and the nth column of the mth row is used for controlling the charging of the energy storage sub-circuit of the nth row and the mth column through the nth data voltage under the control of the scanning line of the mth row;
the pixel driving sub-circuit of the mth row and the nth column is used for driving the light-emitting element of the mth row and the nth column to emit light according to the charges stored in the energy storage sub-circuit of the mth row and the nth column.
The display device provided by the embodiment of the invention can be any product or component with a display function, such as a mobile phone, a tablet personal computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like.
While the foregoing is directed to the preferred embodiment of the present invention, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (10)
1. A data write-in control method is applied to a pixel drive circuit, the pixel drive circuit comprises N multiplexing control circuits, the nth multiplexing control circuit is used for controlling a data line to be communicated with an nth column of sub-pixel circuits under the control of an nth multiplexing control signal in an nth write-in time period, N is an integer larger than 1, and N is a positive integer smaller than or equal to N; the data line is connected with the data driving circuit, and the nth data providing time period comprises an nth pre-writing time period and an nth writing time period which are sequentially arranged; the data write control method includes:
in the nth pre-write period, the data driving circuit supplies an nth data voltage to a data line so that a voltage on the data line is changed to the nth data voltage;
the different data providing time periods do not overlap;
the data write control method further includes:
in the nth writing period, the data driving circuit supplies an nth data voltage to the data line so that a voltage on the data line is maintained as the nth data voltage.
2. The data write control method according to claim 1, wherein the m-th row of pixel charging phases includes an m-th row of data supplying phase and an m-th row of scanning line opening phase which are sequentially arranged; m is a positive integer;
the mth row of data providing stage comprises N data providing time periods which are sequentially set;
the data write control method further includes:
and in the m-th row scanning line opening stage, the m-th row scanning line is opened to control the m-th row and n-th column sub-pixel circuits to be charged through the n-th data voltage.
3. The data write control method according to claim 2, further comprising: providing an m-th row synchronizing signal to the m-th row scanning line;
and controlling the m-th line synchronizing signal to be effective before the m-th line data providing phase starts.
4. A data write-in control unit is applied to a pixel drive circuit, the pixel drive circuit comprises N multiplexing control circuits, the nth multiplexing control circuit is used for controlling a data line to be communicated with an nth column of sub-pixel circuits under the control of an nth multiplexing control signal in an nth write-in time period, N is an integer larger than 1, and N is a positive integer smaller than or equal to N; the data line is connected to a data driving circuit, and the data write control unit includes:
a write control circuit for controlling the data driving circuit to supply an nth data voltage to a data line in an nth pre-write period so that a voltage on the data line is changed to the nth data voltage; the nth pre-writing time period and the nth writing time period are sequentially set, the nth pre-writing time period and the nth writing time period are included in the nth data providing time period, and N is a positive integer less than or equal to N; the different data providing time periods do not overlap;
the write control circuit is further configured to control the data driving circuit to provide an nth data voltage to the data line in the nth write period, so that the voltage on the data line is maintained at the nth data voltage.
5. The data write control unit of claim 4, wherein the m-th row of pixel charging phases includes an m-th row of data supplying phase and an m-th row of scanning line opening phase which are sequentially arranged; m is a positive integer; the mth row of data providing stage comprises N data providing time periods which are sequentially set;
the data write control unit further includes:
and the scanning line control circuit is used for controlling the scanning line of the mth row to be opened in the scanning line opening stage of the mth row so as to control the charging of the sub-pixel circuit of the nth row and the nth column through the nth data voltage.
6. The data write control unit of claim 5, further comprising: and the line synchronizing signal providing circuit is used for providing an mth line synchronizing signal for the mth line scanning line and controlling the mth line synchronizing signal to be effective before the mth line data providing stage begins.
7. A pixel drive circuit comprising the data write control unit according to any one of claims 4 to 6.
8. The pixel driving circuit according to claim 7, further comprising N multiplexing control circuits;
the control end of the nth multiplexing control circuit is connected with the nth multiplexing control end, the first end of the nth multiplexing control circuit is connected with a data line, the second end of the nth multiplexing control circuit is connected with the nth column of sub-pixel circuits, and the nth multiplexing control end is used for inputting an nth multiplexing control signal;
the nth multiplexing control circuit is used for controlling a data line to be communicated with the nth column of sub-pixel circuits under the control of an nth multiplexing control signal in an nth writing time period;
n is an integer greater than 1, and N is a positive integer less than or equal to N.
9. A display device comprising the pixel drive circuit according to claim 7 or 8.
10. The display device according to claim 9, wherein the mth row and nth column sub-pixel circuit comprises an mth row and nth column charge control sub-circuit, an mth row and nth column energy storage sub-circuit, an mth row and nth column pixel drive sub-circuit and an mth row and nth column light emitting element; m is a positive integer;
the control end of the charging control sub-circuit of the nth row and the nth column of the mth row is connected with the scanning line of the mth row, and the charging control sub-circuit of the nth row and the nth column of the mth row is used for controlling the charging of the energy storage sub-circuit of the nth row and the mth column through the nth data voltage under the control of the scanning line of the mth row;
the pixel driving sub-circuit of the mth row and the nth column is used for driving the light-emitting element of the mth row and the nth column to emit light according to the charges stored in the energy storage sub-circuit of the mth row and the nth column.
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| CN112530369B (en) * | 2020-12-25 | 2022-03-25 | 京东方科技集团股份有限公司 | Display panel, display device and driving method |
| CN115064105B (en) * | 2022-05-30 | 2023-05-26 | 惠科股份有限公司 | Pixel driving circuit and driving method of display panel and display device |
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