CN107103878B

CN107103878B - Array substrate, driving method thereof, organic light emitting display panel and display device

Info

Publication number: CN107103878B
Application number: CN201710385243.5A
Authority: CN
Inventors: 向东旭; 李玥; 高娅娜; 陈泽源
Original assignee: Shanghai Tianma AM OLED Co Ltd
Current assignee: Wuhan Tianma Microelectronics Co Ltd
Priority date: 2017-05-26
Filing date: 2017-05-26
Publication date: 2020-07-03
Anticipated expiration: 2037-05-26
Also published as: CN107103878A

Abstract

The invention discloses an array substrate, a driving method thereof, an organic light emitting display panel and a display device, comprising: a plurality of light emitting devices, a pixel compensation circuit connected to each light emitting device, and a plurality of initialization control circuits located in a peripheral region of the array substrate; all the pixel compensation circuits in each row share one initialization control circuit, so that the structure of each pixel compensation circuit can be simplified, and the occupied area of the pixel compensation circuits in a display area can be reduced. And the first poles of the driving transistors in all the pixel compensation circuits in each row are connected with a common initialization control circuit; the initialization control circuit is used for providing signals of the initialization signal end to the first electrodes of the driving transistors under the control of the first scanning signal end, so that the first electrodes of the driving transistors can be prevented from being under the same bias voltage for a long time, the drift of the threshold voltage and the mobility of the driving transistors can be improved, the decline rate of the driving transistors can be reduced, and the display stability can be improved.

Description

Array substrate, driving method thereof, organic light emitting display panel and display device

Technical Field

The invention relates to the technical field of display, in particular to an array substrate, a driving method thereof, an organic light-emitting display panel and a display device.

Background

Organic Light Emitting Diodes (OLEDs) are one of the hot spots in the research field of flat panel displays, and compared with Liquid Crystal Displays (LCDs), OLED displays have the advantages of low energy consumption, low production cost, self-luminescence, wide viewing angle, fast response speed, and the like. Currently, in the display fields of mobile phones, tablet computers, digital cameras, and the like, OLED displays have begun to replace traditional LCD displays.

Unlike LCDs, which control brightness using a stable voltage, OLEDs are current driven and require a stable current to control their light emission. The OLED is typically driven to emit light by a drive transistor of a pixel drive circuit in the OLED display. When the driving transistor is operated, because the driving transistor has a defect state inside and is in an operating state most of the time, when the source of the driving transistor is under the same bias voltage for a long time, the threshold voltage drift and mobility change of the driving transistor become worse gradually, which causes the characteristic drift of the driving transistor, thereby causing abnormal display. Which in turn affects the stability of the display.

Disclosure of Invention

Embodiments of the present invention provide an array substrate, a driving method thereof, an organic light emitting display panel and a display device, which are used for solving the problems in the prior art that display abnormality and display stability are affected due to characteristic drift of a driving transistor caused by long-time source electrodes of the driving transistor under the same bias voltage.

Therefore, an embodiment of the present invention provides an array substrate, including: a plurality of light emitting devices and a pixel compensation circuit connected to each of the light emitting devices; the pixel compensation circuit comprises a driving transistor; the array substrate further includes: a plurality of initialization control circuits located at a peripheral region of the array substrate; the pixel compensation circuits in one row share one initialization control circuit, the first poles of the driving transistors in the pixel compensation circuits in one row are connected with the shared initialization control circuit, and the second poles of the driving transistors are connected with the light-emitting devices in a one-to-one correspondence mode;

the initialization control circuit is used for supplying a signal of an initialization signal end to a first pole of each connected driving transistor under the control of a first scanning signal end.

Preferably, in the array substrate provided in an embodiment of the present invention, the array substrate further includes: a plurality of voltage control circuits; the voltage control circuit is correspondingly connected with the first pole of the driving transistor of the pixel compensation circuit and used for supplying a signal of a first power supply end to the first pole of the correspondingly connected driving transistor under the control of the light-emitting control signal end, and charging the correspondingly connected pixel compensation circuit or controlling the correspondingly connected pixel compensation circuit to drive the connected light-emitting device to emit light.

Preferably, in the array substrate provided in an embodiment of the present invention, the array substrate further includes: a plurality of pixel units, each pixel unit including one of the light emitting devices and one of the pixel compensation circuits; each pixel compensation circuit is respectively connected with one voltage control circuit in a one-to-one correspondence mode, and the voltage control circuits are located in the pixel units where the connected pixel compensation circuits are located.

Preferably, in the array substrate provided in the embodiment of the present invention, at least two adjacent pixel compensation circuits in the same row are connected to the same voltage control circuit.

Preferably, in the array substrate provided in an embodiment of the present invention, the array substrate further includes: a plurality of pixel units, each pixel unit including one of the light emitting devices and one of the pixel compensation circuits; the pixel compensation circuits in two adjacent pixel units in the same row are connected with the same voltage control circuit, and the voltage control circuit is positioned between the pixel units where the two connected pixel compensation circuits are positioned; alternatively, the first and second electrodes may be,

the pixel compensation circuits in the same row are all connected with the same voltage control circuit, and the voltage control circuit is located in the peripheral area of the array substrate.

Preferably, in the array substrate provided in an embodiment of the present invention, the initialization control circuit includes: a first switching transistor; wherein the content of the first and second substances,

and the control electrode of the first switching transistor is connected with the first scanning signal end, the first electrode of the first switching transistor is connected with the initialization signal end, and the second electrode of the first switching transistor is connected with the first electrode of the driving transistor of each pixel compensation circuit in the corresponding row.

Preferably, in the array substrate provided in an embodiment of the present invention, the voltage control circuit includes: a second switching transistor; wherein the content of the first and second substances,

and the control electrode of the second switching transistor is connected with the light-emitting control signal end, the first electrode of the second switching transistor is connected with the first power supply end, and the second electrode of the second switching transistor is connected with the first electrode of the driving transistor in the pixel compensation circuit connected with the voltage control circuit.

Preferably, in the array substrate provided in the embodiment of the present invention, the pixel compensation circuit further includes: the device comprises a first data writing module, a voltage division module and a first storage module; the second pole of the driving transistor is connected with the first end of the corresponding light-emitting device, and the second end of the light-emitting device is connected with a second power supply end;

the first data writing module is respectively connected with a second scanning signal end, a data signal end and the control electrode of the driving transistor and is used for providing a signal of the data signal end to the control electrode of the driving transistor under the control of the second scanning signal end;

the first storage module is respectively connected with the control electrode of the driving transistor and the second electrode of the driving transistor and used for charging or discharging under the control of a signal of the control electrode of the driving transistor and a signal of the second electrode of the driving transistor and keeping a voltage difference between the control electrode of the driving transistor and the second electrode of the driving transistor stable when the second electrode or the control electrode of the driving transistor is in a floating state;

the voltage division module is respectively connected with the first power end and the second pole of the driving transistor and is used for dividing the voltage of the signal of the second pole of the driving transistor.

Preferably, in the array substrate provided in an embodiment of the present invention, the first data writing module includes: a third switching transistor; a control electrode of the third switching transistor is connected with the second scanning signal end, a first electrode of the third switching transistor is connected with the data signal end, and a second electrode of the third switching transistor is connected with a control electrode of the driving transistor;

the first storage module includes: a first capacitor; the first end of the first capacitor is connected with the control electrode of the driving transistor, and the second end of the first capacitor is connected with the second electrode of the driving transistor;

the voltage division module includes: a second capacitor; the first end of the second capacitor is connected with the first power supply end, and the second end of the second capacitor is connected with the second pole of the driving transistor.

Correspondingly, the embodiment of the invention also provides an organic light-emitting display panel which comprises any one of the array substrates provided by the embodiment of the invention.

Correspondingly, the embodiment of the invention also provides a display device which comprises the organic light-emitting display panel provided by the embodiment of the invention.

Correspondingly, an embodiment of the present invention further provides a driving method for the array substrate provided by the embodiment of the present invention, including: an initialization stage, a threshold compensation stage, a data writing stage and a light emitting stage; wherein the content of the first and second substances,

in the initialization stage, the initialization control circuit supplies a signal of the initialization signal terminal to a first pole of a connected driving transistor under the control of the first scanning signal terminal; the first data writing module supplies the signal of the data signal end to the control electrode of the driving transistor under the control of the second scanning signal end; the driving transistor is conducted under the control of signals of a control electrode and a first electrode of the driving transistor, and discharges the first storage module;

in the threshold compensation stage, the voltage control circuit supplies the signal of the first power supply end to the first electrode of the driving transistor in the correspondingly connected pixel compensation circuit under the control of the light-emitting control signal end; the first data writing module supplies the signal of the data signal end to the control electrode of the driving transistor under the control of the second scanning signal end; the driving transistor is conducted under the control of signals of a control electrode and a first electrode of the driving transistor, and the first storage module is charged;

in the data writing phase, the first data writing module supplies the signal of the data signal end to the control electrode of the driving transistor under the control of the second scanning signal end; when the second pole of the driving transistor is in a floating state, the first storage module keeps the voltage difference between the control pole of the driving transistor and the second pole of the driving transistor stable; the voltage division module divides the voltage of the signal of the second pole of the driving transistor;

in the light-emitting stage, the voltage control circuit supplies the signal of the first power supply terminal to the first electrode of the connected driving transistor under the control of the light-emitting control signal terminal; when the control electrode of the driving transistor is in a floating state, the first storage module keeps the voltage difference between the control electrode of the driving transistor and the second electrode of the driving transistor stable; the driving transistor is conducted under the control of signals of a control electrode and a first electrode of the driving transistor, and the connected light-emitting device is driven to emit light.

Preferably, in the above method provided by the embodiment of the present invention, the voltage control circuit supplies the signal of the first power supply terminal to the first poles of the driving transistors of the pixel compensation circuits connected in one-to-one correspondence.

Preferably, in the above method provided by the embodiment of the present invention, the voltage control circuit supplies the signal of the first power supply terminal to the first poles of the driving transistors of at least two adjacent pixel compensation circuits in the corresponding same row.

Preferably, in the above method provided by the embodiment of the present invention, the voltage control circuit supplies the signal of the first power supply terminal to the first electrodes of the driving transistors of all the pixel compensation circuits in the same row.

The invention has the following beneficial effects:

the array substrate, the driving method thereof, the organic light emitting display panel and the display device provided by the embodiment of the invention comprise the following steps: a plurality of light emitting devices, a pixel compensation circuit connected to each light emitting device, and a plurality of initialization control circuits located in a peripheral region of the array substrate; all the pixel compensation circuits in each row share one initialization control circuit, so that the structure of each pixel compensation circuit can be simplified, and the occupied area of the pixel compensation circuits in a display area can be reduced. And the first poles of the driving transistors in all the pixel compensation circuits in each row are connected with a common initialization control circuit; and the initialization control circuit is used for providing the signal of the initialization signal end to the first poles of the connected driving transistors under the control of the first scanning signal end, so that the first poles of the driving transistors can be prevented from being under the same bias voltage for a long time, the drift of the threshold voltage and the mobility of the driving transistors can be improved, the decline rate of the driving transistors can be reduced, and the display stability can be further improved.

Drawings

Fig. 1 is a schematic view of an array substrate according to an embodiment of the present invention;

fig. 2a is a schematic structural diagram of an array substrate according to an embodiment of the present invention;

fig. 2b is a second schematic structural diagram of an array substrate according to an embodiment of the invention;

fig. 2c is a third schematic structural diagram of an array substrate according to an embodiment of the invention;

fig. 3a is a schematic structural diagram of the array substrate shown in fig. 2 a;

FIG. 3b is a schematic structural diagram of the array substrate shown in FIG. 2 b;

FIG. 3c is a schematic structural diagram of the array substrate shown in FIG. 2 c;

fig. 4 is a fourth schematic structural diagram of an array substrate according to an embodiment of the present invention;

FIG. 5a is a schematic view of a specific structure of the array substrate shown in FIG. 3 a;

FIG. 5b is a schematic diagram of a specific structure of the array substrate shown in FIG. 3 b;

FIG. 5c is a schematic diagram of a specific structure of the array substrate shown in FIG. 3 c;

fig. 6a is a schematic view of a specific structure of the array substrate shown in fig. 4;

FIG. 6b is a second schematic view illustrating a specific structure of the array substrate shown in FIG. 4;

FIG. 7a is a timing diagram corresponding to the structure shown in FIG. 5a to FIG. 5 c;

FIG. 7b is a timing diagram corresponding to the structures shown in FIG. 6a and FIG. 6b, respectively;

FIG. 8a is a schematic diagram of simulation of signals according to the second embodiment;

FIG. 8b is a simulation diagram of the gate voltage of the driving transistor when the threshold voltage varies from-0.5 v to 0.5v in the second embodiment;

FIG. 8c is a simulation diagram of the drain voltage of the driving transistor when the threshold voltage varies from-0.5 v to 0.5v in the second embodiment;

fig. 9 is a flowchart of a driving method according to an embodiment of the present invention;

fig. 10 is a display device according to an embodiment of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention clearer, specific embodiments of an array substrate, a driving method thereof, an organic light emitting display panel and a display device according to embodiments of the present invention are described in detail below with reference to the accompanying drawings. It should be understood that the preferred embodiments described below are only for illustrating and explaining the present invention and are not to be used for limiting the present invention. And the embodiments and features of the embodiments in the present application may be combined with each other without conflict.

An embodiment of the present invention provides an array substrate, as shown in fig. 1, including: a plurality of light emitting devices L and a pixel compensation circuit 10 connected to each light emitting device L; the pixel compensation circuit 10 includes a drive transistor (not shown in fig. 1); the array substrate further includes: a plurality of initialization control circuits 20 located in a peripheral area of the array substrate; wherein, a row of pixel compensation circuits 10 share one initialization control circuit 20, and the first poles of the driving transistors in a row of pixel compensation circuits 10 are connected with the shared initialization control circuit 20;

the initialization control circuit 20 is configured to provide a signal of the initialization signal terminal Vinit to first poles of the connected driving transistors under the control of the first scan signal terminal S1, and second poles of the driving transistors are connected to the light emitting devices in a one-to-one correspondence.

The array substrate provided by the embodiment of the invention comprises: a plurality of light emitting devices, a pixel compensation circuit connected to each light emitting device, and a plurality of initialization control circuits located in a peripheral region of the array substrate; all the pixel compensation circuits in each row share one initialization control circuit, so that the structure of each pixel compensation circuit can be simplified, and the occupied area of the pixel compensation circuits in a display area can be reduced. And the first poles of the driving transistors in all the pixel compensation circuits in each row are connected with a common initialization control circuit; and the initialization control circuit is used for providing the signal of the initialization signal end to the first poles of the connected driving transistors under the control of the first scanning signal end, so that the first poles of the driving transistors can be prevented from being under the same bias voltage for a long time, the drift of the threshold voltage and the mobility of the driving transistors can be improved, the decline rate of the driving transistors can be reduced, and the display stability can be further improved.

In a specific implementation, as shown in fig. 2a to 2c, in the array substrate provided in the embodiment of the present invention, the array substrate may further include: a plurality of voltage control circuits 30;

the voltage control circuit 30 is connected to a first electrode of a driving transistor (not shown in fig. 2a to 2 c) of the pixel compensation circuit 10, and is configured to supply a signal of the first power supply terminal VDD to the first electrode of the driving transistor under the control of the light emission control signal terminal EM, so as to charge the pixel compensation circuit 10 or control the pixel compensation circuit 10 to drive the connected light emitting device L to emit light. Therefore, the voltage of the first electrode of the driving transistor can be switched between the signal of the first power supply end and the signal of the initialization signal end, so that the characteristic of the driving transistor is recovered, the characteristic drift of the driving transistor is further improved, and the decline rate of the driving transistor is slowed down.

In a specific implementation, as shown in fig. 1 to 2c, in the array substrate provided in the embodiment of the present invention, the array substrate may further include: a plurality of pixel units 40 located in the display area AA, wherein each pixel unit 40 includes a light emitting device L and a pixel compensation circuit 10. As shown in fig. 2a, each pixel compensation circuit 10 may be connected to one voltage control circuit 30 in a one-to-one correspondence, and each voltage control circuit 30 is located in the pixel unit 40 where the connected pixel compensation circuit 10 is located.

In order to increase the aperture ratio of the pixel unit, in a specific implementation, as shown in fig. 2b and fig. 2c, in the array substrate provided in the embodiment of the present invention, at least two adjacent pixel compensation circuits 10 in the same row may be connected to the same voltage control circuit 30. Specifically, as shown in fig. 2b, the pixel compensation circuits 10 in two adjacent pixel units 40 in the same row are connected to the same voltage control circuit 30, and the voltage control circuit 30 is located between the pixel units 40 where the two connected pixel compensation circuits 10 are located. Alternatively, the pixel compensation circuits in three adjacent pixel units in the same row may be connected to the same voltage control circuit, and the voltage control circuit is located between any two of the pixel units where the three connected pixel compensation circuits are located, or located within one of the pixel units where the three connected pixel compensation circuits are located, which is not limited herein. When the pixel compensation circuits in the adjacent four and five … pixel units in the same row are connected to the same voltage control circuit, and so on, which are not described herein again. Alternatively, as shown in fig. 2c, all the pixel compensation circuits 10 in the same row are connected to the same voltage control circuit 30, and the voltage control circuit 30 is located in the peripheral area of the array substrate. Thus, the occupation area of the pixel compensation circuit in the display area can be reduced by sharing the voltage control circuit.

Generally, the pixel compensation circuit has various structures, and in a specific implementation, as shown in fig. 3a to 3c, in the array substrate provided in the embodiment of the present invention, the pixel compensation circuit may further include: a first data writing module 11, a voltage dividing module 12 and a first storage module 13; wherein the first pole S of the driving transistor M0 is connected to the corresponding initialization control circuit 20, the first pole S of the driving transistor M0 is further connected to the corresponding voltage control circuit 30, the second pole D of the driving transistor M0 is connected to the first end of the corresponding light emitting device L, and the second end of the light emitting device L is connected to the second power supply terminal VSS;

the first Data writing module 11 is respectively connected to the second scan signal terminal S2, the Data signal terminal Data, and the control electrode G of the driving transistor M0, and is configured to provide the signal of the Data signal terminal Data to the control electrode G of the driving transistor M0 under the control of the second scan signal terminal S2;

the first memory module 13 is respectively connected to the control electrode G of the driving transistor M0 and the second electrode D of the driving transistor M0, and is configured to charge or discharge under the control of the signal of the control electrode G of the driving transistor M0 and the signal of the second electrode D of the driving transistor M0, and to keep the voltage difference between the control electrode G of the driving transistor M0 and the second electrode D of the driving transistor M0 stable when the second electrode D or the control electrode G of the driving transistor M0 is in a floating state;

the voltage dividing module 12 is respectively connected to the first power terminal VDD and the second pole D of the driving transistor M0, and is configured to divide the voltage of the signal of the second pole D of the driving transistor M0.

According to the array substrate provided by the embodiment of the invention, through the mutual cooperation of the initialization control circuit, the voltage control circuit, the first data writing module, the voltage division module, the first storage module and the driving transistor, different voltages can be input to the first pole of the driving transistor at different moments through the initialization control circuit and the voltage control circuit, the driving transistor can be prevented from being under the same bias voltage for a long time, so that the drift of the threshold voltage and the mobility of the driving transistor can be improved, the decline rate of the driving transistor can be reduced, and the stability of display can be further improved. And through the mutual cooperation of the circuits and the modules, the luminous working current of the light-emitting device which is connected with the driving transistor in a driving mode can be unrelated to the threshold voltage of the driving transistor, so that the effect of compensating the threshold voltage drift of the driving transistor can be achieved, and the adverse effect of the drift of the threshold voltage of the driving transistor on display can be further avoided.

Alternatively, as shown in fig. 4, the pixel compensation circuit may further include: a second data writing module 11 ', a second storage module 12', a conduction control module 13 'and a voltage input module 14'; wherein the content of the first and second substances,

a first electrode S of the driving transistor M0 is respectively connected to a first end of the corresponding light emitting device L and the initialization control circuit 20 corresponding to the pixel compensation circuit, and a second end of the light emitting device L is connected to a second power supply terminal VSS;

the second Data writing module 11' is respectively connected to a third scan signal terminal S3, a Data signal terminal Data and a first node a, and is configured to provide a signal of the Data signal terminal Data to the first node a under the control of the third scan signal terminal S3; the first node a is located on a connection line between the second data writing module 11 'and the second storage module 12';

the turn-on control module 13' is respectively connected to the first scan signal terminal S1, the control electrode G of the driving transistor M0, the first electrode S of the driving transistor M0, the second electrode D of the driving transistor M0 and the first node a, and is configured to turn on the second electrode D of the driving transistor M0 and the first node a under the control of the first scan signal terminal S1, and turn on the control electrode G of the driving transistor M0 and the first electrode S thereof;

the second memory module 12' is respectively connected to the first node a and the gate G of the driving transistor M0, and is used for charging or discharging under the control of the signal of the first node a and the signal of the gate G of the driving transistor M0, and keeping the voltage difference between the first node a and the gate G of the driving transistor M0 stable when the gate of the driving transistor M0 is in a floating state;

the voltage input block 14' is respectively connected to the first power terminal VDD, the light-emission control signal terminal EM, and the second pole D of the driving transistor M0, for supplying the signal of the first power terminal VDD to the second pole D of the driving transistor M0 under the control of the light-emission control signal terminal EM.

According to the array substrate provided by the embodiment of the invention, through the mutual cooperation of the initialization control circuit, the voltage input module, the second data writing module, the conduction control module, the second storage module and the driving transistor, the structure of each pixel compensation circuit can be simplified, and the occupied area of the pixel compensation circuit in the display area can be reduced. And the working current of the light-emitting device which is in driving connection with the driving transistor is unrelated to the threshold voltage of the driving transistor, so that the effect of compensating the threshold voltage drift of the driving transistor can be realized, and the adverse effect of the drift of the threshold voltage of the driving transistor on display can be further avoided.

The above is merely to illustrate the structure of the pixel compensation circuit provided in the embodiment of the present invention, and in a specific implementation, the structure of the pixel compensation circuit is not limited to the structure provided in the embodiment of the present invention, and may be other structures known to those skilled in the art, and is not limited herein.

In practical implementation, in the array substrate provided in the embodiment of the present invention, the light emitting device is generally an organic electroluminescent diode, an anode of the organic electroluminescent diode is a first end of the light emitting device, and a cathode of the organic electroluminescent diode is a second end of the light emitting device, and the organic electroluminescent diode realizes light emission under the action of a current when the driving transistor is in a saturation state.

In practical implementation, in the array substrate provided by the embodiment of the invention, as shown in fig. 3a to 3c, the driving transistor M0 for driving the light emitting device L to emit light may be an N-type transistor, a gate of the N-type transistor is the control electrode G of the driving transistor M0, a source of the N-type transistor is the first electrode S of the driving transistor M0, and a drain of the N-type transistor is the second electrode D of the driving transistor M0. The operating current for driving the connected light emitting device L to emit light by the driving transistor M0 at this time flows from the source S to the drain D of the driving transistor M0. Alternatively, as shown in fig. 4, the driving transistor M0 for driving the light emitting device L to emit light may be a P-type transistor, the gate of which is the control electrode G of the driving transistor M0, the source of which is the second electrode D of the driving transistor M0, and the drain of which is the first electrode S of the driving transistor M0. The operating current for driving the connected light emitting device L to emit light by the driving transistor M0 at this time flows from the source S to the drain D of the driving transistor M0.

In practical application, in the array substrate provided by the embodiment of the invention, the voltage V of the first power source terminal_ddPositive, the voltage V of the second supply terminal_ssNegative or ground. The voltage V of the second power supply terminal_ssThe ground voltage is exemplified.

In practical implementation, in the array substrate provided by the embodiment of the invention, the array substrate further includes a plurality of voltage transmission signal lines, the voltage transmission signal lines are used for inputting voltage signals to the first power source end, and the voltage transmission signal lines are wired in a mesh manner so as to reduce the IR drop.

The present invention will be described in detail with reference to specific examples. It should be noted that the present embodiment is intended to better explain the present invention, but not to limit the present invention.

In a specific implementation, as shown in fig. 5a to 6b, in the array substrate provided in the embodiment of the present invention, the initialization control circuit 20 may specifically include: a first switching transistor M1; wherein the content of the first and second substances,

the first switching transistor M1 has a control electrode connected to the first scan signal terminal S1, a first electrode connected to the initialization signal terminal Vinit, and a second electrode connected to the first electrode S of the driving transistor M0 of each pixel compensation circuit in the corresponding row.

In specific implementation, in the array substrate provided in the embodiment of the invention, as shown in fig. 5a to 5c, the first switch transistor M1 may be an N-type transistor. Alternatively, as shown in fig. 6a and 6b, the first switching transistor may be a P-type transistor, which is not limited herein.

In a specific implementation, in the array substrate provided in the embodiment of the present invention, when the first switching transistor is in a conducting state under the control of the signal of the first scan signal terminal, the signal of the initialization signal terminal is provided to the first pole of each connected driving transistor.

In a specific implementation, as shown in fig. 5a to 5c, in the array substrate provided in the embodiment of the present invention, the voltage control circuit 30 may specifically include: a second switching transistor M2; wherein the content of the first and second substances,

the second switching transistor M2 has a control electrode connected to the emission control signal terminal EM, a first electrode connected to the first power source terminal VDD, and a second electrode connected to the first electrode S of the driving transistor M0 in the pixel compensation circuit connected to the voltage control circuit 30.

In specific implementation, in the array substrate provided in the embodiment of the invention, as shown in fig. 5a to 5c, the second switch transistor M2 may be an N-type transistor. Of course, the second switch transistor may also be a P-type transistor, which is not limited herein.

In a specific implementation manner, in the array substrate provided by the embodiment of the present invention, when the second switching transistor is in a conducting state under the control of the signal of the light-emitting control signal terminal, the signal of the first power terminal is provided to the first electrode of the connected driving transistor.

In a specific implementation, as shown in fig. 5a to 5c, in the array substrate provided in the embodiment of the present invention, the first data writing module 11 may specifically include: a third switching transistor M3; wherein the content of the first and second substances,

a control electrode of the third switching transistor M3 is connected to the second scan signal terminal S2, a first electrode of the third switching transistor M3 is connected to the Data signal terminal Data, and a second electrode of the third switching transistor M3 is connected to the control electrode G of the driving transistor M0.

In specific implementation, in the array substrate provided in the embodiment of the invention, as shown in fig. 5a to 5c, the third switching transistor M3 may be an N-type transistor. Of course, the third switching transistor may also be a P-type transistor, which is not limited herein.

In a specific implementation, in the array substrate provided in the embodiment of the present invention, when the third switching transistor is in an on state under the control of the second scan signal terminal, a signal of the data signal terminal is provided to the control electrode of the connected driving transistor.

In a specific implementation, as shown in fig. 5a to 5c, in the array substrate provided in the embodiment of the present invention, the first storage module 13 may specifically include: a first capacitance C1; wherein the content of the first and second substances,

a first terminal of the first capacitor C1 is connected to the control electrode G of the driving transistor M0, and a second terminal of the first capacitor C1 is connected to the second electrode D of the driving transistor M0.

In a specific implementation manner, in the array substrate provided by the embodiment of the invention, the first capacitor is charged or discharged under the common control of the signal of the control electrode of the driving transistor and the signal of the second electrode of the driving transistor, and the voltage difference between the control electrode of the driving transistor and the second electrode of the driving transistor is kept stable when the control electrode of the driving transistor is in a floating state, and the voltage difference between the control electrode of the driving transistor and the second electrode of the driving transistor is kept stable when the second electrode of the driving transistor is in a floating state.

In a specific implementation, as shown in fig. 5a to 5c, in the array substrate provided in the embodiment of the present invention, the voltage dividing module 12 may specifically include: a second capacitance C2; wherein the content of the first and second substances,

a first terminal of the second capacitor C2 is connected to the first power terminal VDD, and a second terminal of the second capacitor C2 is connected to the second pole D of the driving transistor M0.

In a specific implementation manner, in the array substrate provided by the embodiment of the invention, the second capacitor may be charged under the common control of the signal at the first power end and the signal at the second pole of the driving transistor, so as to divide the voltage of the signal at the second pole of the driving transistor through a coupling effect.

In a specific implementation, as shown in fig. 6a and 6b, in the array substrate provided in the embodiment of the present invention, the second data writing module 11' may specifically include: a fourth switching transistor M4; wherein the content of the first and second substances,

a control electrode of the fourth switching transistor M4 is connected to the third scan signal terminal S3, a first electrode of the fourth switching transistor M4 is connected to the Data signal terminal Data, and a second electrode of the fourth switching transistor M4 is connected to the first node a.

In a specific implementation, in the array substrate provided in the embodiment of the invention, as shown in fig. 6a and 6b, the fourth switching transistor M4 may be a P-type transistor. Of course, the fourth switching transistor may also be an N-type transistor, and is not limited herein.

In a specific implementation, in the array substrate provided in the embodiment of the present invention, when the fourth switching transistor is in a conducting state under the control of the third scan signal terminal, the signal of the data signal terminal is provided to the first node.

In a specific implementation, as shown in fig. 6a and 6b, in the array substrate provided in the embodiment of the present invention, the conduction control module 13' may specifically include: a fifth switching transistor M5 and a sixth switching transistor M6; wherein the content of the first and second substances,

a control electrode of the fifth switching transistor M5 is connected to the first scan signal terminal S1, a first electrode of the fifth switching transistor M5 is connected to the control electrode G of the driving transistor M0, and a second electrode of the fifth switching transistor M5 is connected to the first electrode S of the driving transistor M0;

a control electrode of the sixth switching transistor M6 is connected to the first scan signal terminal S1, a first electrode of the sixth switching transistor M6 is connected to the first node a, and a second electrode of the sixth switching transistor M6 is connected to the second electrode D of the driving transistor M0.

In a specific implementation, in the array substrate provided in the embodiment of the invention, as shown in fig. 6a and 6b, the fifth switching transistor M5 and the sixth switching transistor M6 may be P-type transistors. Of course, the fifth switching transistor and the sixth switching transistor may also be N-type transistors, and are not limited herein.

In a specific implementation, in the array substrate provided in the embodiment of the invention, when the fifth switching transistor is in a conducting state under the control of the first scan signal terminal, the control electrode of the driving transistor and the first electrode of the driving transistor may be conducted. The sixth switching transistor may turn on the second pole and the first node of the driving transistor when being in a turn-on state under the control of the first scan signal terminal.

In a specific implementation, as shown in fig. 6a and 6b, in the array substrate provided in the embodiment of the present invention, the voltage input module 14' may specifically include: a seventh switching transistor M7; wherein the content of the first and second substances,

a control electrode of the seventh switching transistor M7 is connected to the light emission control signal terminal EM, a first electrode of the seventh switching transistor M7 is connected to the first power source terminal VDD, and a second electrode of the seventh switching transistor M7 is connected to the second electrode D of the driving transistor M0.

In a specific implementation, in the array substrate provided in the embodiment of the invention, as shown in fig. 6a and 6b, the seventh switching transistor M7 may be a P-type transistor. Of course, the seventh switching transistor may also be an N-type transistor, and is not limited herein.

In a specific implementation manner, in the array substrate provided by the embodiment of the invention, when the seventh switching transistor is in an on state under the control of the light-emitting control signal terminal, the signal of the first power terminal is provided to the second pole of the driving transistor.

In a specific implementation, as shown in fig. 6a, in the array substrate provided in the embodiment of the present invention, the second storage module 12' may specifically include: a third capacitance C3; wherein the content of the first and second substances,

a first terminal of the third capacitor C3 is connected to the first node a, and a second terminal of the third capacitor C3 is connected to the gate G of the driving transistor M0.

In a specific implementation manner, in the array substrate provided in the embodiment of the present invention, the third capacitor is charged or discharged under the control of the signal of the first node and the signal of the control electrode of the driving transistor, and the voltage difference between the first node and the control electrode of the driving transistor is kept stable when the control electrode of the driving transistor is in a floating state.

In order to stabilize the signal of the first node a, in a specific implementation, as shown in fig. 6b, in the array substrate provided in the embodiment of the present invention, the second memory module 12' may further include: a fourth capacitance C4; wherein the content of the first and second substances,

a first terminal of the fourth capacitor C4 is connected to the first power supply terminal VDD, and a second terminal is connected to the first node a.

In practical implementation, in the array substrate provided by the embodiment of the invention, the fourth capacitor can maintain a stable change in voltage of the signal at the first node.

The above description is only an example of the specific structures of each circuit and each module in the array substrate provided by the embodiment of the present invention, and in the implementation, the specific structures of each circuit and each module are not limited to the structures provided by the embodiment of the present invention, and may be other structures known to those skilled in the art, and are not limited herein.

Preferably, in a specific implementation, all of the driving transistors and all of the switching transistors in the array substrate provided by the embodiments of the present invention may be designed as N-type transistors, or all of the driving transistors and all of the switching transistors may be designed as P-type transistors, so that the manufacturing process of the array substrate may be simplified.

In a specific implementation, in the array substrate provided in the embodiment of the present invention, the N-type transistor is turned on under a high potential and turned off under a low potential; the P-type transistor is turned off under the action of a high potential and turned on under the action of a low potential.

In the array substrate according to an embodiment of the present invention, the driving transistors and the switching transistors may be Thin Film Transistors (TFTs) or Metal Oxide semiconductor field effect transistors (MOS), and are not limited herein. In a specific implementation, the control electrode of each of the switching transistors is used as the gate thereof, and the first electrode and the second electrode may be used as the source or the drain thereof and the second electrode may be used as the drain or the source thereof, depending on the type of the switching transistor and the signal at the signal terminal, which is not limited herein. In describing the embodiments, the driving transistor and the switching transistor are MOS transistors as an example for explanation.

The following describes the operation process of the array substrate provided by the embodiment of the present invention with reference to a circuit timing diagram, by taking the structures of the circuits in the array substrate shown in fig. 5a to 5c and fig. 6b as examples. In the following description, 1 denotes a high potential, and 0 denotes a low potential. It should be noted that 1 and 0 are logic potentials, which are only used to better explain the specific operation of the embodiment of the present invention, and are not voltages applied to the gates of the switching transistors in the specific implementation.

The first embodiment,

In fig. 5a, each pixel unit 40 includes a pixel compensation circuit and a voltage control circuit, i.e. each pixel unit 40 includes 3 transistors and 2 capacitors. The structure of the circuit in the pixel unit 40 on the left side of the array substrate shown in fig. 5a will be described with reference to the timing chart shown in fig. 7 a. Specifically, four phases of the initialization phase T1, the threshold compensation phase T2, the data writing phase T3, and the light emitting phase T4 in the input timing diagram shown in fig. 7a are selected. Wherein the voltage of the Data signal output from the Data signal terminal is V during the initialization period T1 and the threshold compensation period T2_inThe V is_inVoltage V of signal far less than that of initialization signal end Vinit_initI.e. V_in<<V_init. Data ofThe signal output by the signal terminal Data at least in the Data writing phase T3 is a specific gray scale voltage V_dataThe data signal of (1).

In the initialization phase T1, EM is 0, S1 is 1, and S2 is 1.

Since S1 is equal to 1, the first switching transistor M1 is turned on. Since EM is 0, the second switching transistor M2 is turned off. Since S2 is equal to 1, the third switching transistor M3 is turned on. The turned-on first switching transistor M1 provides the signal of the initialization signal terminal Vinit to the source S of the driving transistor M0, so that the voltage of the source S of the driving transistor M0 is V_init. The turned-on third switching transistor M3 supplies the signal of the Data signal terminal Data to the gate G of the driving transistor M0, and makes the gate G of the driving transistor M0 have a voltage V_in. Due to V_in<<V_initTherefore, the driving transistor M0 is turned on to provide the signal of its source S to its drain D, making the voltage of the drain of the driving transistor M0V_initTo discharge the first capacitor C1 and to discharge the anode of the connected light emitting device L for resetting, and also to release carriers trapped by charge traps in the channel of the driving transistor M0 and the insulating layer in the previous display frame, the decay rate of the driving transistor M0 can be effectively mitigated. Therefore, the voltage at the first end of the first capacitor C1 is V_inThe voltage at the second terminal is V_init(ii) a The voltage at the first end of the second capacitor C2 is V_ddThe voltage at the second terminal is V_init. Wherein V is used to avoid that the connected light emitting device L emits light at this stage_initAnd V_ssThe relationship needs to be satisfied: v_init-V_ss<V_th(L); wherein, V_th(L) is the threshold voltage of the light emitting device L.

In the threshold compensation stage T2, EM is 1, S1 is 0, and S2 is 1.

Since S1 is equal to 0, the first switching transistor M1 is turned off. Since EM is 1, the second switching transistor M2 is turned on. Since S2 is equal to 1, the third switching transistor M3 is turned on. The turned-on third switching transistor M3 supplies the signal of the Data signal terminal Data to the gate G of the driving transistor M0, and makes the gate G of the driving transistor M0 have a voltage V_in. The turned-on second switching transistor M2 supplies a signal of the first power terminal VDD to the source S of the connected driving transistor M0, causing the first power terminal VDD to charge its drain D through the turned-on driving transistor M0 until the voltage of the drain D of the driving transistor M0 becomes: v_in-V_th(M0); wherein, V_th(M0) is the threshold voltage of the drive transistor M0. Therefore, the first capacitor C1 is charged and the voltage difference between the two ends is V_th(M0) to drive V of transistor M0_th(M0) storing. The voltage at the first end of the second capacitor C2 is V_ddThe voltage at the second terminal is V_in-V_th(M0)。

In the data writing phase T3, EM is 0, S1 is 0, and S2 is 1.

Since S1 is equal to 0, the first switching transistor M1 is turned off. Since EM is 0, the second switching transistor M2 is turned off. Since S2 is equal to 1, the third switching transistor M3 is turned on. The turned-on third switching transistor M3 supplies the signal of the Data signal terminal Data to the gate G of the driving transistor M0, and makes the gate G of the driving transistor M0 have a voltage V_data. Since the drain D of the driving transistor M0 is in a floating state, the voltage of the drain D of the driving transistor M0 becomes:

wherein c is₁Represents the capacitance value, C, of the first capacitor C1₂Representing the capacitance value of the second capacitor C2. At this time, the gate-drain voltage of the driving transistor M0

The driving transistor M0 has a gate-drain voltage V_GDIs in a saturated state.

In the light emitting period T4, EM is 1, S1 is 0, and S2 is 0.

Since S1 is equal to 0, the first switching transistor M1 is turned off. Since EM is 1, the second switching transistor M2 is turned on. Since S2 is equal to 0, the third switching transistor M3 is turned off. The turned-on second switching transistor M2 turns on the first power source terminal VDD is provided to the source S of the connected driving transistor M0, since the driving transistor M0 is at its gate-drain voltage V_GDIs in a saturation state, and an operating current I for driving the connected light emitting device L to emit light, which flows through the driving transistor M0, is known from the saturation-state current characteristic_LSatisfies the formula:

can obtain

Where K is a structural parameter, this number is relatively stable in the same structure and can be calculated as a constant.

An initialization preparation phase T0, i.e., EM 0, S1 0, and S2 0, may also be included before the initialization phase T1. Each switching transistor is turned off during this phase to prepare for the operation of the initialization phase T1.

In the first embodiment, the source of the driving transistor may be at the voltage V of the initialization signal terminal during the period from T1 to T4_initVoltage V to the first power supply terminal_ddThe down switching can avoid the source electrode of the driving transistor being under the same bias voltage for a long time, thereby improving the drift of the threshold voltage and the mobility of the driving transistor and slowing down the decline rate of the driving transistor. And according to the above formula

It can be seen that the operating current I driving the light emitting device L_LVoltage V of signal inputted only with Data signal terminal Data_dataAnd V_inA capacitance C of the first capacitor C1₁And a second capacitor C₂C2, and therefore I_LHas not been influenced by the threshold voltage V of the driving transistor M0_th(M0) influence on the threshold voltage V of the driving transistor M0 due to its long-term operation_th(M0) drifting towards the operating current I driving the light-emitting device L_LThereby further ensuring the normal operation of the light emitting device L and improving the stability of the display.

Example II,

The pixel compensation circuits in two adjacent pixel units 40 in fig. 5b share one voltage control circuit, i.e. each pixel unit 40 includes 2.5 transistors and 2 capacitors. The structure of the circuits in the left pixel unit 40 and the right pixel unit 40 in the array substrate shown in fig. 5b is taken as an example, and the description is given with reference to the timing chart shown in fig. 7 a. Specifically, four phases of the initialization phase T1, the threshold compensation phase T2, the data writing phase T3, and the light emitting phase T4 in the input timing diagram shown in fig. 7a are selected. Wherein the voltage of the Data signal output from the Data signal terminal is V during the initialization period T1 and the threshold compensation period T2_inThe V is_inVoltage V of signal far less than that of initialization signal end Vinit_initI.e. V_in<<V_init. The Data signal terminal Data outputs a specific gray scale voltage V at least in the Data writing phase T3_dataThe data signal of (1). The operation of the third switching transistor M3, the driving transistor M0, the first capacitor C1 and the second capacitor C2 in the left pixel cell 40 in fig. 5b will be described in priority.

In the initialization phase T1, EM is 0, S1 is 1, and S2 is 1.

Since S1 is equal to 1, the first switching transistor M1 is turned on. Since EM is 0, the second switching transistor M2 is turned off. Since S2 is equal to 1, the third switching transistor M3 is turned on. The turned-on first switching transistor M1 provides the signal of the initialization signal terminal Vinit to the source S of the driving transistor M0, so that the voltage of the source S of the driving transistor M0 is V_init. The turned-on third switching transistor M3 supplies the signal of the Data signal terminal Data to the gate G of the driving transistor M0, and makes the gate G of the driving transistor M0 have a voltage V_in. Due to V_in<<V_initTherefore, the driving transistor M0 is turned on to provide the signal of its source S to its drain D, making the voltage of the drain of the driving transistor M0V_initTo discharge the first capacitor C1 and to discharge the anode of the connected light emitting device L for reset, and also to release the charge trap in the channel of the driving transistor M0 and the insulating layer in the previous display frameThe attenuation rate of the driving transistor M0 can be effectively alleviated. Therefore, the voltage at the first end of the first capacitor C1 is V_inThe voltage at the second terminal is V_init(ii) a The voltage at the first end of the second capacitor C2 is V_ddThe voltage at the second terminal is V_init. Wherein V is used to avoid that the connected light emitting device L emits light at this stage_initAnd V_ssThe relationship needs to be satisfied: v_init-V_ss<V_th(L); wherein, V_th(L) is the threshold voltage of the light emitting device L. At this stage, the operation processes of the third switching transistor M3, the driving transistor M0, the first capacitor C1 and the second capacitor C2 in the right pixel unit 40 are the same as those of the left pixel unit, and are not described herein again.

In the threshold compensation stage T2, EM is 1, S1 is 0, and S2 is 1.

Since S1 is equal to 0, the first switching transistor M1 is turned off. Since EM is 1, the second switching transistor M2 is turned on. Since S2 is equal to 1, the third switching transistor M3 is turned on. The turned-on third switching transistor M3 supplies the signal of the Data signal terminal Data to the gate G of the driving transistor M0, and makes the gate G of the driving transistor M0 have a voltage V_in. The turned-on second switching transistor M2 supplies a signal of the first power terminal VDD to the source S of the connected driving transistor M0, causing the first power terminal VDD to charge its drain D through the turned-on driving transistor M0 until the voltage of the drain D of the driving transistor M0 becomes: v_in-V_th(M0); wherein, V_th(M0) is the threshold voltage of the drive transistor M0. Therefore, the first capacitor C1 is charged and the voltage difference between the two ends is V_th(M0) to drive V of transistor M0_th(M0) storing. The voltage at the first end of the second capacitor C2 is V_ddThe voltage at the second terminal is V_in-V_th(M0). At this stage, the operation processes of the third switching transistor M3, the driving transistor M0, the first capacitor C1 and the second capacitor C2 in the right pixel unit 40 are the same as those of the left pixel unit, and are not described herein again.

In the data writing phase T3, EM is 0, S1 is 0, and S2 is 1.

Due to S1 is 0, and therefore the first switching transistor M1 is turned off. Since EM is 0, the second switching transistor M2 is turned off. Since S2 is equal to 1, the third switching transistor M3 is turned on. The turned-on third switching transistor M3 supplies the signal of the Data signal terminal Data to the gate G of the driving transistor M0, and makes the gate G of the driving transistor M0 have a voltage V_data. Since the drain D of the driving transistor M0 is in a floating state, the voltage of the drain D of the driving transistor M0 becomes:

The driving transistor M0 has a gate-drain voltage V_GDIs in a saturated state. At this stage, the operation processes of the third switching transistor M3, the driving transistor M0, the first capacitor C1 and the second capacitor C2 in the right pixel unit 40 are the same as those of the left pixel unit, and are not described herein again.

In the light emitting period T4, EM is 1, S1 is 0, and S2 is 0.

Since S1 is equal to 0, the first switching transistor M1 is turned off. Since EM is 1, the second switching transistor M2 is turned on. Since S2 is equal to 0, the third switching transistor M3 is turned off. The turned-on second switching transistor M2 supplies a signal of the first power terminal VDD to the source S of the connected driving transistor M0 since the driving transistor M0 is at its gate-drain voltage V_GDIs in a saturation state, and an operating current I for driving the connected light emitting device L to emit light, which flows through the driving transistor M0, is known from the saturation-state current characteristic_LSatisfies the formula:

can obtain

Where K is a structural parameter, this number is relatively stable in the same structure and can be calculated as a constant. At this stage, the operation processes of the third switching transistor M3, the driving transistor M0, the first capacitor C1 and the second capacitor C2 in the right pixel unit 40 are the same as those of the left pixel unit, and are not described herein again.

In the second embodiment, the source of the driving transistor can be at the voltage V of the initialization signal terminal during the period from T1 to T4_initVoltage V to the first power supply terminal_ddThe down switching can avoid the source electrode of the driving transistor being under the same bias voltage for a long time, thereby improving the drift of the threshold voltage and the mobility of the driving transistor and slowing down the decline rate of the driving transistor. And according to the above formula

Taking the structure shown in FIG. 5b as an example, the threshold voltage V of the driving transistor M0 is adjusted by using the simulated analog timing diagram of each input signal shown in FIG. 8a_th(M0) simulation of the gate G and drain D voltages respectively, as they drift between-0.5 v-0.5v in steps of 0.2 v. In FIG. 8a, the ordinate represents voltage, the abscissa represents time, a1 represents the signal of the emission control signal terminal EM, and a2 representsRepresents the signal of the first scan signal terminal S1, and a3 represents the signal of the second scan signal terminal S2. In the simulation process, the voltage of the gate G of the driving transistor M0 is varied as shown in fig. 8b, and the voltage of the drain D of the driving transistor M0 is varied as shown in fig. 8 c. In FIG. 8b, the ordinate represents voltage and the abscissa represents time, and b1, b2, b3, b4, b5 and b6 represent V, respectively_th(M0) shows a voltage change curve of the gate G of the driving transistor M0 when the voltage changes from-0.5 v, -0.3v, -0.1v, 0.3v, and 0.5 v. In FIG. 8c, the ordinate represents voltage and the abscissa represents time, and c1, c2, c3, c4, c5 and c6 represent V, respectively_th(M0) drift-0.5 v, -0.3v, -0.1v, 0.3v and 0.5v, the voltage change curve of the drain D of the driving transistor M0. In fig. 8a to 8c, the vertical line h0 corresponds to the time when the threshold compensation phase is completed, wherein in fig. 8b, the voltages corresponding to the positions where the curves b1, b2, b3, b4, b5 and b6 intersect the vertical line h0 are-1.50 v, -1.50v and-1.50 v, respectively. In FIG. 8c, the voltages corresponding to the positions where the curves c1, c2, c3, c4, c5 and c6 intersect the vertical line h0 are-2.62555, -2.81661, -3.00591, -3.19471, -3.39343 and-3.59896, respectively. Thus, at V_th(M0) when the voltage difference between the grid G and the drain D of the driving transistor M0 is equivalent to 0.2V increase within an error allowable range when the voltage is simulated by shifting the voltage from-0.5V to 0.5V by 0.2V of step length, thereby better realizing the threshold voltage V of the driving transistor M0_th(M0).

Example III,

The pixel compensation circuits in all pixel cells 40 in a row in fig. 5c share one voltage control circuit, i.e. each pixel cell 40 comprises 2 transistors and 2 capacitors. In this case, as shown in fig. 5c, only one row of two pixel units 40 is taken as an example, and the structure of the circuits in the left pixel unit 40 and the right pixel unit 40 in the array substrate shown in fig. 5c is taken as an example, which is described with reference to the timing diagram shown in fig. 7 a. Specifically, four phases of the initialization phase T1, the threshold compensation phase T2, the data writing phase T3, and the light emitting phase T4 in the input timing diagram shown in fig. 7a are selected. Wherein the initialization period T1 is equal to the thresholdDuring the value compensation period T2, the voltage of the signal output from the Data signal terminal is V_inThe V is_inVoltage V of signal far less than that of initialization signal end Vinit_initI.e. V_in<<V_init. The Data signal terminal Data outputs a specific gray scale voltage V at least in the Data writing phase T3_dataThe data signal of (1). The operation of the third switching transistor M3, the driving transistor M0, the first capacitor C1 and the second capacitor C2 in the left pixel cell 40 in fig. 5C will be described in priority.

In the initialization phase T1, EM is 0, S1 is 1, and S2 is 1.

Since S1 is equal to 1, the first switching transistor M1 is turned on. Since EM is 0, the second switching transistor M2 is turned off. Since S2 is equal to 1, the third switching transistor M3 is turned on. The turned-on first switching transistor M1 provides the signal of the initialization signal terminal Vinit to the source S of the driving transistor M0, so that the voltage of the source S of the driving transistor M0 is V_init. The turned-on third switching transistor M3 supplies the signal of the Data signal terminal Data to the gate G of the driving transistor M0, and makes the gate G of the driving transistor M0 have a voltage V_in. Due to V_in<<V_initTherefore, the driving transistor M0 is turned on to provide the signal of its source S to its drain D, making the voltage of the drain of the driving transistor M0V_initTo discharge the first capacitor C1 and to discharge the anode of the connected light emitting device L for resetting, and also to release carriers trapped by charge traps in the channel of the driving transistor M0 and the insulating layer in the previous display frame, the decay rate of the driving transistor M0 can be effectively mitigated. Therefore, the voltage at the first end of the first capacitor C1 is V_inThe voltage at the second terminal is V_init(ii) a The voltage at the first end of the second capacitor C2 is V_ddThe voltage at the second terminal is V_init. Wherein V is used to avoid that the connected light emitting device L emits light at this stage_initAnd V_ssThe relationship needs to be satisfied: v_init-V_ss<V_th(L); wherein, V_th(L) is the threshold voltage of the light emitting device L. At this stage, the third switching transistor in the pixel cell 40 on the rightThe operation process of M3, the driving transistor M0, the first capacitor C1 and the second capacitor C2 is the same as that of the left side, and is not described herein again.

In the threshold compensation stage T2, EM is 1, S1 is 0, and S2 is 1.

In the data writing phase T3, EM is 0, S1 is 0, and S2 is 1.

In the light emitting period T4, EM is 1, S1 is 0, and S2 is 0.

can obtain

An initialization preparation phase T0, i.e., EM 0, S1 0, and S2 0, may also be included before the initialization phase T1. The switching transistors in each pixel cell 40 in a row are turned off during this phase to prepare for the operation of the initialization phase T1.

In the third embodiment, the source of the driving transistor may be at the voltage V of the initialization signal terminal during the period from T1 to T4_initVoltage V to the first power supply terminal_ddThe down switching can avoid the source electrode of the driving transistor being under the same bias voltage for a long time, thereby improving the drift of the threshold voltage and the mobility of the driving transistor and slowing down the decline rate of the driving transistor. And according to the above formula

Example four,

The pixel compensation circuits in all pixel cells 40 in a row in fig. 6b share one initialization control circuit, i.e. each pixel cell 40 comprises 5 transistors and 2 capacitors. The structure of the circuit in the pixel unit 40 on the left side of the array substrate shown in fig. 6b will be described with reference to the timing chart shown in fig. 7 b. Specifically, four phases of the initialization phase T1, the threshold compensation phase T2, the data writing phase T3, and the light emitting phase T4 in the input timing diagram shown in fig. 7b are selected.

In the initialization phase T1, EM is 0, S1 is 0, and S3 is 1.

Since EM is 0, the seventh switching transistor M7 is turned on. Since S1 is equal to 0, the first switching transistor M1, the fifth switching transistor M5, and the sixth switching transistor M6 are all turned on. Since S3 is equal to 1, the fourth switching transistor M4 is turned off. The turned-on seventh switching transistor M7 turns on the first power source terminal VDVoltage V of signal of D_ddTo the source D of the driving transistor M0. The turned-on sixth switching transistor M6 turns on the first node A and the source D of the driving transistor M0, thereby turning V on_ddIs provided to the first node a. The turned-on first switching transistor M1 provides the signal of the initialization signal terminal Vinit to the drain S of the driving transistor M0, so that the voltage of the drain S of the driving transistor M0 is V_initAnd the turned-on fifth switching transistor M5 turns on the gate G of the driving transistor M0 and the drain S thereof to discharge the third capacitor C3 and to discharge the anode of the connected light emitting device L for reset. The fourth capacitor C4 may stabilize the first node a.

In the threshold compensation stage T2, EM is 1, S1 is 0, and S3 is 1.

Since S1 is equal to 0, the first switching transistor M1, the fifth switching transistor M5, and the sixth switching transistor M6 are all turned on. Since EM is 1, the seventh switching transistor M7 is turned off. Since S3 is equal to 1, the fourth switching transistor M4 is turned off. The turned-on first switching transistor M1 provides a signal of the initialization signal terminal Vinit to the drain S of the driving transistor M0, the turned-on sixth switching transistor M6 turns on the first node a and the source D of the driving transistor M0, the turned-on fifth switching transistor M5 turns on the gate G and the drain S of the driving transistor M0, and the voltage V of the signal of the first node a is caused to be_ddIs discharged through the driving transistor M0 until the voltage of the first node a becomes V_init+|V_th(M0) | or less. Therefore, the voltage at the first end of the third capacitor C3 is V_init+|V_th(M0) |, the voltage at the second end is V_initThe voltage difference between both ends is | V_th(M0) |. The fourth capacitor C4 may stabilize the first node a.

In the data writing phase T3, EM is 1, S1 is 1, and S3 is 0.

Since EM is 1, the seventh switching transistor M7 is turned off. Since S1 is equal to 1, the first switching transistor M1, the fifth switching transistor M5, and the sixth switching transistor M6 are all turned off. Since S3 is equal to 0, the fourth switching transistor M4 is turned on. The turned-on fourth switching transistor M4 supplies the Data signal of the Data signal terminal Data to the first node a, making the first node aThe voltage at point A is the voltage V of the data signal_data. Since the gate G of the driving transistor M0 is floating, the voltage difference across the third capacitor C3 is still V due to the coupling effect of the third capacitor C3_th(M0) |, so that the voltage of the second terminal of the third capacitor C3, i.e., the gate G of the driving transistor M0, becomes V_data-|V_th(M0)|。

In the light emitting period T4, EM is 0, S1 is 1, and S3 is 1.

Since EM is 0, the seventh switching transistor M7 is turned on. Since S1 is equal to 1, the first switching transistor M1, the fifth switching transistor M5, and the sixth switching transistor M6 are all turned off. Since S3 is equal to 1, the fourth switching transistor M4 is turned off. The turned-on seventh switching transistor M7 applies the voltage V of the signal of the first power source terminal VDD_ddIs supplied to the source D of the driving transistor M0, so that the voltage at the source D of the driving transistor M0 is V_ddAnd the voltage of the gate G of the driving transistor M0 is V_data-|V_th(M0) |, the driving transistor M0 is in a saturation state, and the operating current I flowing through the driving transistor M0 for driving the connected light emitting device L to emit light is known from the saturation state current characteristic_LSatisfies the formula: i is_L＝K(V_DG-|V_th(M0)|)²＝K[(V_dd-V_data+|V_th(M0)|-|V_th(M0)|]²＝K[V_dd-V_data]²From this equation, the current when the driving transistor M0 is in the saturation state and the threshold voltage V of the driving transistor M0_th(M0) is irrelevant, so that the threshold voltage V caused by the process of the driving transistor M0 and long-term operation can be solved_thThe drift affects the current flowing through the light emitting device L, so that the operating current of the light emitting device L is kept stable, and the normal operation of the light emitting device L is further ensured.

Based on the same inventive concept, an embodiment of the present invention further provides a driving method of an array substrate according to an embodiment of the present invention, as shown in fig. 9, including: an initialization stage, a threshold compensation stage, a data writing stage and a light emitting stage; wherein the content of the first and second substances,

s901, in an initialization stage, an initialization control circuit supplies a signal of an initialization signal end to a first pole of a connected driving transistor under the control of a first scanning signal end; the first data writing module supplies a signal of a data signal end to a control electrode of the driving transistor under the control of a second scanning signal end; the driving transistor is conducted under the control of signals of a control electrode and a first electrode of the driving transistor, and discharges the first storage module;

s902, in a threshold compensation stage, the voltage control circuit supplies a signal of a first power supply end to a first electrode of a driving transistor in a pixel compensation circuit connected correspondingly under the control of a light-emitting control signal end; the first data writing module supplies a signal of a data signal end to a control electrode of the driving transistor under the control of a second scanning signal end; the driving transistor is conducted under the control of signals of a control electrode and a first electrode of the driving transistor to charge the first storage module;

s903, in the data writing stage, the first data writing module supplies the signal of the data signal end to the control electrode of the driving transistor under the control of the second scanning signal end; when the second pole of the driving transistor is in a floating state, the first storage module keeps the voltage difference between the control pole of the driving transistor and the second pole of the driving transistor stable; the voltage division module divides the voltage of the signal of the second pole of the driving transistor;

s904, in the light-emitting stage, the voltage control circuit supplies the signal of the first power supply end to the first electrode of the connected driving transistor under the control of the light-emitting control signal end; when the control electrode of the driving transistor is in a floating state, the first storage module keeps the voltage difference between the control electrode of the driving transistor and the second electrode of the driving transistor stable; the driving transistor is conducted under the control of signals of a control electrode and a first electrode of the driving transistor, and the connected light-emitting device is driven to emit light.

The driving method provided by the embodiment of the invention can prevent the first electrode of the driving transistor from being under the same bias voltage for a long time, thereby improving the drift of the threshold voltage and the mobility of the driving transistor, slowing down the decline rate of the driving transistor and further improving the display stability.

In the method provided by the embodiment of the present invention, when each pixel compensation circuit in the array substrate is connected to one voltage control circuit in a one-to-one correspondence manner, the voltage control circuit supplies the signal of the first power source terminal to the first electrode of the driving transistor of the pixel compensation circuit connected in a one-to-one correspondence manner.

In the method provided by the embodiment of the present invention, when at least two adjacent pixel compensation circuits in the same row in the array substrate are connected to the same voltage control circuit, the voltage control circuit supplies a signal of the first power source terminal to the first electrodes of the driving transistors of the at least two adjacent pixel compensation circuits in the corresponding same row.

Further, when the pixel compensation circuits in the same row in the array substrate are all connected to the same voltage control circuit, in the above method provided by the embodiment of the present invention, the voltage control circuit provides the signal of the first power end to the first electrodes of the driving transistors of all the pixel compensation circuits in the same row.

Based on the same inventive concept, the embodiment of the invention also provides an organic light emitting display panel, which comprises any one of the array substrates provided by the embodiment of the invention. The principle of the organic light emitting display panel to solve the problem is similar to the array substrate, so the implementation of the organic light emitting display panel can refer to the implementation of the array substrate, and repeated details are not repeated herein.

In practical applications, an organic light emitting display panel is generally assembled with a gate driving circuit and a source driving circuit, and a timing controller for controlling the operation of the gate driving circuit and the source driving circuit. It should be understood by those skilled in the art that the working principle and the specific structure of the gate driving circuit, the source driving circuit and the timing controller are all the same, and are not described herein nor should they be taken as a limitation to the present invention.

In practical applications, the organic light emitting display panel generally scans from the first row of pixel units to the last row of pixel units in sequence to perform light emitting display.

Based on the same inventive concept, an embodiment of the present invention further provides a display device, as shown in fig. 10, including the organic light emitting display panel provided by the embodiment of the present invention. The display device may be: any product or component with a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like. Other essential components of the display device are understood by those skilled in the art, and are not described herein or should not be construed as limiting the invention. The implementation of the display device can refer to the above embodiments of the array substrate, and repeated descriptions are omitted.

It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.

Claims

1. An array substrate, comprising: a plurality of light emitting devices and a pixel compensation circuit connected to each of the light emitting devices; the pixel compensation circuit comprises a driving transistor; characterized in that, the array substrate still includes: a plurality of initialization control circuits located at a peripheral region of the array substrate; the pixel compensation circuits in one row share one initialization control circuit, the first poles of the driving transistors in the pixel compensation circuits in one row are connected with the shared initialization control circuit, and the first poles of the driving transistors are connected with the light-emitting devices in a one-to-one correspondence mode;

the initialization control circuit is used for supplying a signal of an initialization signal end to a first pole of each connected driving transistor under the control of a first scanning signal end;

the pixel compensation circuit further includes: the fourth switching transistor, the second storage module, the fifth switching transistor, the sixth switching transistor, the third capacitor and the seventh switching transistor; wherein the content of the first and second substances,

the first electrode of the driving transistor is respectively connected with the first end of the corresponding light-emitting device and the initialization control circuit corresponding to the pixel compensation circuit, and the second end of the light-emitting device is connected with the second power supply end;

a control electrode of the fourth switching transistor is connected with a third scanning signal end, a first electrode of the fourth switching transistor is connected with a data signal end, and a second electrode of the fourth switching transistor is connected with a first node; the fourth switching transistor is configured to supply a signal of the data signal terminal to the first node under control of the third scan signal terminal in a data write phase;

a control electrode of the fifth switching transistor is connected with the first scanning signal end, a first electrode of the fifth switching transistor is connected with a control electrode of the driving transistor, and a second electrode of the fifth switching transistor is connected with the first electrode of the driving transistor; the fifth switching transistor is used for conducting the control electrode of the driving transistor and the first electrode of the driving transistor under the control of the first scanning signal end in an initialization stage and a threshold compensation stage respectively;

a control electrode of the sixth switching transistor is connected with the first scanning signal end, a first electrode of the sixth switching transistor is connected with the first node, and a second electrode of the sixth switching transistor is connected with the second electrode of the driving transistor; the sixth switching transistor is used for conducting the second pole of the driving transistor and the first node under the control of the first scanning signal end in an initialization stage and a threshold compensation stage respectively;

a first end of the third capacitor is connected with the first node, and a second end of the third capacitor is connected with the control electrode of the driving transistor;

a control electrode of the seventh switching transistor is connected with the light-emitting control signal end, a first electrode of the seventh switching transistor is connected with a first power supply end, and a second electrode of the seventh switching transistor is connected with a second electrode of the driving transistor; the seventh switching transistor is configured to supply the signal of the first power supply terminal to the second pole of the driving transistor under the control of the light emission control signal terminal in the initialization phase and the light emission phase, respectively;

all transistors are P-type transistors;

wherein, in the initialization phase, the initialization control circuit supplies a signal of the initialization signal terminal to a first pole of a connected drive transistor under the control of the first scan signal terminal; the fifth switching transistor is controlled by the first scanning signal end to conduct the control electrode of the driving transistor and the first electrode of the driving transistor; the sixth switching transistor turns on the second pole of the driving transistor and the first node under the control of the first scan signal terminal; the seventh switching transistor supplies the signal of the first power source terminal to the second pole of the driving transistor under the control of the light emission control signal terminal; the driving transistor is conducted under the control of signals of a control electrode and a first electrode of the driving transistor, and discharges the first storage module;

in the threshold compensation stage, the initialization control circuit supplies a signal of the initialization signal terminal to a first pole of a connected driving transistor under the control of the first scanning signal terminal; the fifth switching transistor is controlled by the first scanning signal end to conduct the control electrode of the driving transistor and the first electrode of the driving transistor; the sixth switching transistor turns on the second pole of the driving transistor and the first node under the control of the first scan signal terminal; the driving transistor is conducted under the control of signals of a control electrode and a first electrode of the driving transistor, and the first storage module is charged;

in the data writing phase, the fourth switching transistor supplies a signal of the data signal terminal to the first node under the control of the third scan signal terminal; the third capacitor keeps a voltage difference between the control electrode of the driving transistor and the second electrode of the driving transistor stable when the second electrode of the driving transistor is in a floating state;

the seventh switching transistor supplies the signal of the first power source terminal to the second pole of the driving transistor under the control of the light emission control signal terminal in the light emission period; the third capacitor keeps the voltage difference between the control electrode of the driving transistor and the second electrode of the driving transistor stable when the control electrode of the driving transistor is in a floating state; the driving transistor is conducted under the control of signals of a control electrode and a first electrode of the driving transistor, and the connected light-emitting device is driven to emit light.

2. The array substrate of claim 1, wherein the initialization control circuit comprises: a first switching transistor; wherein the content of the first and second substances,

3. An organic light emitting display panel comprising the array substrate according to claim 1 or 2.

4. A display device characterized by comprising the organic light-emitting display panel according to claim 3.