CN116013202A - Pixel driving circuit, display panel and electronic equipment - Google Patents
Pixel driving circuit, display panel and electronic equipment Download PDFInfo
- Publication number
- CN116013202A CN116013202A CN202310092593.8A CN202310092593A CN116013202A CN 116013202 A CN116013202 A CN 116013202A CN 202310092593 A CN202310092593 A CN 202310092593A CN 116013202 A CN116013202 A CN 116013202A
- Authority
- CN
- China
- Prior art keywords
- transistor
- pixel
- sub
- signal
- driving circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000003990 capacitor Substances 0.000 claims description 41
- 238000010586 diagram Methods 0.000 description 9
- 208000032005 Spinocerebellar ataxia with axonal neuropathy type 2 Diseases 0.000 description 7
- 208000033361 autosomal recessive with axonal neuropathy 2 spinocerebellar ataxia Diseases 0.000 description 7
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000006855 networking Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Images
Abstract
The application provides a pixel driving circuit, a display panel and electronic equipment, wherein the pixel driving circuit comprises a plurality of enabling transistors and a plurality of driving sub-circuits, each enabling transistor is used for receiving a first voltage signal and is respectively and electrically connected with the driving sub-circuits, the enabling transistors are used for being conducted under the control of the enabling signals so as to transmit the first voltage signal to corresponding pixel units through the driving sub-circuits, the other ends of the pixel units are used for receiving a second voltage signal, and the pixel units are used for working under the loading of the first voltage signal and the second voltage signal; the driving sub-circuits and the pixel units are arranged in an array form, and the driving sub-circuits respectively electrically connected with each enable transistor are positioned in the same row. By controlling the plurality of driving sub-circuits simultaneously per enable transistor, the goal of reducing the number of transistors in the pixel driving circuit can be achieved, thereby enabling design space saving for setting more pixel cells.
Description
Technical Field
The present disclosure relates to the field of display technologies, and in particular, to a pixel driving circuit, a display panel, and an electronic device.
Background
Display technology has long been one of the important research directions in electronic devices. In the display panel, since the circuit for driving the pixel units is usually also disposed in the display area of the display panel, the more complex the driving circuit is, the fewer the pixel units can be increased in the display area.
At present, the number of transistors in the driving circuit is large, so that it is difficult to increase the number of pixel units under the condition of fixed display area size, which is not beneficial to resolution improvement.
Disclosure of Invention
The application discloses pixel drive circuit can solve the transistor quantity in the drive circuit more, leads to under the fixed condition of display area size, is difficult to increase the technical problem of the quantity of pixel unit.
In a first aspect, the present application provides a pixel driving circuit, where the pixel driving circuit includes a plurality of enable transistors and a plurality of driving sub-circuits, each enable transistor receives a first voltage signal and is electrically connected to the plurality of driving sub-circuits, the enable transistors are used for conducting under control of the enable signals to transmit the first voltage signal to corresponding pixel units through the driving sub-circuits, another end of each pixel unit is used for receiving a second voltage signal, and each pixel unit is used for operating under loading of the first voltage signal and the second voltage signal; the driving sub-circuits and the pixel units are arranged in an array form, and the driving sub-circuits, to which the enabling transistors are respectively electrically connected, are positioned in the same row.
By controlling a plurality of the driving sub-circuits simultaneously for each of the enable transistors, the purpose of reducing the number of transistors in the pixel driving circuit can be achieved, thereby enabling a design space to be saved for setting more pixel units.
Optionally, the driving sub-circuit includes a storage capacitor, a first transistor and a second transistor, where one end of the storage capacitor is used to receive the first voltage signal, and the other end of the storage capacitor is electrically connected to the gate of the first transistor; the source electrode of the first transistor is electrically connected with the drain electrode of the second transistor and one end of the pixel unit, and the drain electrode of the first transistor is electrically connected with the source electrode of the enabling transistor; the grid electrode of the second transistor is used for receiving a first scanning signal, and the source electrode of the second transistor is used for receiving a data signal.
Optionally, the driving sub-circuit further includes a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor, where a gate of the third transistor is configured to receive the first scan signal, a source of the third transistor is electrically connected to a drain of the fourth transistor and a source of the first transistor, and a drain of the third transistor is electrically connected to a drain of the fifth transistor; the grid electrode of the fourth transistor is used for receiving the enabling signal, and the source electrode of the fourth transistor is electrically connected with one end of the pixel unit and the drain electrode of the sixth transistor; the grid electrode of the fifth transistor is used for receiving a second scanning signal, and the source electrode of the fifth transistor is used for receiving a first initialization signal; the grid electrode of the sixth transistor is used for receiving the first scanning signal, and the source electrode of the sixth transistor is used for receiving a second initialization signal.
Optionally, the pixel driving circuit has a reset phase, and when the pixel driving circuit is in the reset phase, the fifth transistor is turned on under the control of the second scan signal to transmit the first initialization signal to one end of the storage capacitor.
Optionally, the pixel driving circuit has a charging phase, and when the pixel driving circuit is in the charging phase, the second transistor and the third transistor are turned on under the control of the first scan signal, so that the data signal is transmitted to one end of the storage capacitor; the sixth transistor is turned on under the control of the first scan signal to transmit the second initialization signal to one end of the pixel unit.
Optionally, the pixel driving circuit has a light emitting stage, when the pixel driving circuit is in the light emitting stage, the enable transistor and the fourth transistor are turned on under the control of the enable signal, and the first transistor controls a current value flowing through the pixel unit according to a voltage value of one end of the storage capacitor electrically connected to a gate thereof.
Optionally, the pixel unit includes a first sub-pixel, a second sub-pixel and a third sub-pixel, and each of the enable transistors is electrically connected to the driving sub-circuits correspondingly and electrically connected to the first sub-pixel, the second sub-pixel and the third sub-pixel, respectively.
Optionally, the first sub-pixel, the second sub-pixel and the third sub-pixel are respectively a red color pixel, a green color pixel and a blue color pixel.
In a second aspect, the present application further provides a display panel, where the display panel has a display area and a non-display area surrounding the display area, and a pixel unit and a pixel driving circuit according to the first aspect are disposed in the display area.
In a third aspect, the present application further provides an electronic device, where the electronic device includes a housing and the display panel according to the second aspect, and the housing is used to carry the display panel.
Drawings
For a clearer description of the technical solutions in the embodiments of the present application, the drawings that are needed in the embodiments will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic diagram of a pixel driving circuit according to an embodiment of the present application.
Fig. 2 is a schematic signal waveform provided in an embodiment of the present application.
Fig. 3 is a schematic diagram of a current flow of a pixel driving circuit according to an embodiment of the present disclosure.
Fig. 4 is a schematic diagram illustrating a current flow of a pixel driving circuit according to another embodiment of the present disclosure.
Fig. 5 is a schematic diagram illustrating a current flow of a pixel driving circuit according to another embodiment of the present disclosure.
Fig. 6 is a schematic top view of a display panel according to an embodiment of the disclosure.
Fig. 7 is a schematic top view of an electronic device according to an embodiment of the present application.
Reference numerals illustrate: an enable signal-Em, a first voltage signal-ELVDD, a second voltage signal-ELVSS, a first Scan signal-Scan 1, a second Scan signal-Scan 2, a first initialization signal-Vint 1, a second initialization signal-Vint 2, a Data signal-Data, a pixel driving circuit-1, an enable transistor-T1, a driving sub-circuit-11, a storage capacitor-C, a first transistor-T2, a second transistor-T3, a third transistor-T4, a fourth transistor-T5, a fifth transistor-T6, a sixth transistor-T7, a gate-g, a source-s, a drain-d, a reset stage-M1, a charging stage-M2, a light emitting stage-M3, a display panel-2, a pixel unit-21, a first sub-pixel-211, a second sub-pixel-212, a third sub-pixel-213, a display area-22, a non-display area-23, an electronic device-3, and a housing-31.
Detailed Description
The following description of the embodiments of the present application will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all, of the embodiments of the present application. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present disclosure.
Referring to fig. 1, fig. 1 is a schematic diagram of a pixel driving circuit according to an embodiment of the present application. The pixel driving circuit 1 includes a plurality of enable transistors T1 and a plurality of driving sub-circuits 11, each of the enable transistors T1 receives a first voltage signal ELVDD and is electrically connected to the plurality of driving sub-circuits 11, the enable transistors T1 are used for being turned on under the control of an enable signal Em to transmit the first voltage signal ELVDD to the corresponding pixel units 21 through the driving sub-circuits 11, the other ends of the pixel units 21 are used for receiving a second voltage signal ELVSS, and the pixel units 21 are used for operating under the loading of the first voltage signal ELVDD and the second voltage signal ELVSS; the driving sub-circuits 11 and the pixel units 21 are arranged in an array, and the driving sub-circuits 11 to which each of the enable transistors T1 is electrically connected are located in the same row.
It should be noted that, the pixel units 21 may be Organic Light-Emitting Semiconductors (OLEDs), the pixel units 21 generally include red color pixels, green color pixels, and blue color pixels, and the driving sub-circuit 11 is further configured to receive a Data signal Data, and control the magnitude of a current flowing through each of the pixel units 21 according to the received Data signal Data, so as to realize display of a picture.
In the present embodiment, when the pixel unit 21 starts to emit light and when it ends to emit light, the on of the enable transistor T1 is controlled by the enable signal Em. For example, when the enable signal Em controls the enable transistor T1 to be turned on, a current flows through the pixel unit 21 under the loading of the first voltage signal ELVDD and the second voltage signal ELVSS, and the pixel unit 21 emits light; on the contrary, when the enable signal Em controls the enable transistor T1 to be turned off, no current flows through the pixel unit 21, and the pixel unit 21 does not emit light. For the different driving sub-circuits 11, the enabling transistor T1 transmits the first voltage signal ELVDD to one end of the pixel unit 21 through the driving sub-circuit 11 under the control of the enabling signal Em, so that the different driving sub-circuits 11 can share one enabling transistor T1 for controlling, thereby reducing the number of transistors used by the pixel driving circuit 1, and in case that the size of the display area is fixed, more space can be released for increasing the number of the pixel unit 21, thereby improving the display resolution.
It will be appreciated that for all the enable transistors T1 in a row, the gate g control signal of the enable transistor T1 is the enable signal Em, and the drain d voltage of the enable transistor T1 is the first voltage signal ELVDD, because the driving sub-circuits 11 located in the same row can be compatible with one of the enable transistors T1.
Specifically, for the driving sub-circuits 11 in a row, at most one of the enabling transistors T1 may be electrically connected at the same time, and if the number of the pixel units 21 and the driving sub-circuits 11 in a row is x, it is understood that the number of the enabling transistors T1 used is reduced by 3x-1 of the enabling transistors T1 with respect to each of the enabling transistors T1 electrically connected to 1 of the driving sub-circuits 11.
It will be appreciated that in the present embodiment, by simultaneously controlling a plurality of the driving sub-circuits 11 per the enable transistor T1, the purpose of reducing the number of transistors in the pixel driving circuit 1 can be achieved, so that a design space can be saved for providing more pixel units 21.
In one possible implementation, referring to fig. 1 again, the driving sub-circuit 11 includes a storage capacitor C, a first transistor T2 and a second transistor T3, wherein one end of the storage capacitor C is used for receiving the first voltage signal ELVDD, and the other end of the storage capacitor C is electrically connected to the gate g of the first transistor T2; the source s of the first transistor T2 is electrically connected to the drain d of the second transistor T3 and one end of the pixel unit 21, and the drain d of the first transistor T2 is electrically connected to the source s of the enable transistor T1; the gate g of the second transistor T3 is configured to receive the first Scan signal Scan1, and the source s of the second transistor T3 is configured to receive the Data signal Data.
Specifically, the second transistor T3 is turned on under the control of the first Scan signal Scan1, so that the Data signal Data is transmitted to one end of the storage capacitor C through the second transistor T3 to charge the storage capacitor C. One end of the storage capacitor C is configured to receive the Data signal Data, and since the gate g of the first transistor T2 is electrically connected to one end of the storage capacitor C, under the loading of the voltage value of one end of the storage capacitor C, the opening degree of the channel between the source s and the drain d of the first transistor T2 can be controlled, so as to control the magnitude of the current flowing through the first transistor T2, so as to control the light emitting brightness of the pixel unit 21.
It is understood that as long as the driving sub-circuit 11 includes therein the first transistor T2 for controlling the magnitude of the current flowing through the pixel unit 21 and the second transistor T3 for controlling the Data signal Data to charge one end of the storage capacitor C, the enable transistor T1 is capable of controlling the driving sub-circuit 11 according to the enable signal Em, the pixel driving circuit 1 may be electrically connected to a plurality of the driving sub-circuits 11 through the enable transistor T1, respectively, for the purpose of reducing the number of transistors, in other words, the pixel driving circuit 1 may be an nTmC circuit in which n represents the number of thin film transistors in the pixel driving circuit 1 and m represents the number of capacitors in the pixel driving circuit 1, and according to the above, n is greater than or equal to 3, that is, includes the enable transistor T1, the first transistor T2 and the second transistor T3.
For example, in one possible implementation, referring to fig. 1 again, the driving sub-circuit 11 further includes a third transistor T4, a fourth transistor T5, a fifth transistor T6 and a sixth transistor T7, the gate g of the third transistor T4 is configured to receive the first Scan signal Scan1, the source s of the third transistor T4 is electrically connected to the drain d of the fourth transistor T5 and the source s of the first transistor T2, and the drain d of the third transistor T4 is electrically connected to the drain d of the fifth transistor T6; a gate g of the fourth transistor T5 is configured to receive the enable signal Em, and a source s of the fourth transistor T5 is electrically connected to one end of the pixel unit 21 and a drain d of the sixth transistor T7; the gate g of the fifth transistor T6 is configured to receive the second Scan signal Scan2, and the source s of the fifth transistor T6 is configured to receive the first initialization signal Vint1; the gate g of the sixth transistor T7 is configured to receive the first Scan signal Scan1, and the source s of the sixth transistor T7 is configured to receive the second initialization signal Vint2.
Specifically, as shown in fig. 1, the third transistor T4 is turned on under the control of the first Scan signal Scan1, and is used for compensating the threshold voltage of the first transistor T2; the fourth transistor T5 is turned on under the control of the enable signal Em, so that the current flowing through the first transistor T2 is transmitted to the pixel unit 21 through the fourth transistor T5, and the current flows through the pixel unit 21 to operate; the fifth transistor T6 is turned on under the control of the second Scan signal Scan2, so as to transmit the first initialization signal Vint1 to one end of the storage capacitor C, so as to initialize a voltage value of one end of the storage capacitor C; the sixth transistor T7 is turned on under the control of the second Scan signal Scan2, so that the second initialization signal Vint2 is transmitted to one end of the pixel unit 21 for initializing the voltage value of one end of the pixel unit 21.
In this embodiment, the drain d of the second transistor T3 is electrically connected to one side of the pixel unit 21 through the third transistor T4, so that it is avoided that the Data signal Data affects the voltage value at the other end of the storage capacitor C through the enable transistor T1 when the enable transistor T1 is turned on. It will be appreciated that the enable signal Em controls the enable transistor T1 and the fourth transistor T5 to be turned on, so that the pixel unit 21 operates under the loading of the first voltage signal ELVDD and the second voltage signal ELVSS, and thus, the plurality of driving sub-circuits 11 may be electrically connected through the enable transistor T1, respectively, to achieve the purpose of reducing the number of transistors. While the fourth transistor T5 is on the line where current flows through the pixel units 21, since the value of the current flowing through each of the pixel units 21 may be different, the fourth transistor T5 is not compatible with a plurality of different pixel units 21.
It will be appreciated that in other possible embodiments, the circuit design in the driving sub-circuit 11 is not limited as long as it is satisfied that at least the enabling transistor T1, the first transistor T2 and the second transistor T3 are included in the pixel driving circuit 1.
In one possible embodiment, please refer to fig. 2 and fig. 3 together, fig. 2 is a schematic diagram of signal waveforms provided in an embodiment of the present application; fig. 3 is a schematic diagram of a current flow of a pixel driving circuit according to an embodiment of the present disclosure. The pixel driving circuit 1 has a reset stage M1, and when the pixel driving circuit 1 is in the reset stage M1, the fifth transistor T6 is turned on under the control of the second Scan signal Scan2 to transmit the first initialization signal Vint1 to one end of the storage capacitor C.
Specifically, as shown in fig. 3, the "X" symbol represents that the transistor is turned off, and a dotted arrow is used to indicate the flow direction of the current. The fifth transistor T6 is turned on under the control of the second Scan signal Scan2, and transmits the first initialization signal Vint1 to one end of the storage capacitor C, and the other end of the storage capacitor C receives the first voltage signal ELVDD, so that the voltage value of the other end of the storage capacitor C is unchanged, thereby initializing the storage capacitor C.
It will be appreciated that, since the first transistor T2 controls the opening degree between the source s and the drain d according to the voltage value of the one end of the storage capacitor C, so as to control the magnitude of the current flowing through the first transistor T2, the Data signal Data needs to be initialized before charging the one end of the storage capacitor C, so that the voltage existing at the one end of the storage capacitor C affects the voltage value of the one end of the storage capacitor C, and thus affects the magnitude of the current flowing through the pixel unit 21.
In this embodiment, the enabling transistor T1, the second transistor T3, the third transistor T4, the fourth transistor T5, the fifth transistor T6 and the sixth transistor T7 are turned off under the control of corresponding control signals, and the turning on or off of the first transistor T2 has no effect on the reset phase M1.
In one possible embodiment, please refer to fig. 2 and fig. 4 together, fig. 4 is a schematic diagram illustrating a current flow of a pixel driving circuit according to another embodiment of the present application. The pixel driving circuit 1 has a charging stage M2, and when the pixel driving circuit 1 is in the charging stage M2, the second transistor T3 and the third transistor T4 are turned on under the control of the first Scan signal Scan1, so that the Data signal Data is transmitted to one end of the storage capacitor C; the sixth transistor T7 is turned on under the control of the first Scan signal Scan1 to transmit the second initialization signal Vint2 to one end of the pixel unit 21.
Specifically, as shown in fig. 4, the "X" symbol represents that the transistor is turned off, and a dotted arrow is used to indicate the flow direction of the current. The second transistor T3 and the third transistor T4 are turned on under the control of the first Scan signal Scan1, so that the Data signal Data is transmitted to one end of the storage capacitor C, and the other end of the storage capacitor C receives the first voltage signal ELVDD, so that the voltage value of the other end of the storage capacitor C is unchanged, thereby charging the storage capacitor C. In order to avoid that the voltage value at one end of the pixel unit 21 affects the magnitude of the current flowing through the pixel unit 21, before the enable transistor T1 controls the pixel unit 21 to emit light through the driving sub-circuit 11, the sixth transistor T7 is turned on under the control of the first Scan signal Scan1, and transmits the second initialization signal Vint2 to one end of the pixel unit 21, and the other end of the pixel unit 21 receives the second voltage signal ELVSS, so that the voltage value at the other end of the pixel unit 21 is unchanged, and the other end of the pixel unit 21 is initialized to ensure that the pixel unit 21 operates under the correct current driving.
In the present embodiment, the enabling transistor T1, the fourth transistor T5 and the fifth transistor T6 are turned off under the control of the corresponding control signals, and likewise, the turning on or off of the first transistor T2 has no effect on the charging stage M2.
In one possible embodiment, please refer to fig. 2 and fig. 5 together, fig. 5 is a schematic diagram illustrating a current flow of a pixel driving circuit according to another embodiment of the present application. The pixel driving circuit 1 has a light emitting stage M3, and when the pixel driving circuit 1 is in the light emitting stage M3, the enable transistor T1 and the fourth transistor T5 are turned on under the control of the enable signal Em, and the first transistor T2 controls a current value flowing through the pixel unit 21 according to a voltage value of one end of the storage capacitor C electrically connected to the gate g thereof.
Specifically, as shown in fig. 5, the "X" symbol represents that the transistor is turned off, and a dotted arrow is used to indicate the flow direction of the current. After the Data signal Data is the charge of one end of the storage capacitor C, the enable transistor T1 and the fourth transistor T5 are turned on under the control of the enable signal Em, so as to transmit the first voltage signal ELVDD to one side of the pixel unit 21, determine the magnitude of the current flowing through the first transistor T2 according to the turn-on degree of the first transistor T2, and finally determine the magnitude of the current flowing through the pixel unit 21, so as to control whether the pixel unit 21 emits light and emits brightness, thereby realizing the display of the picture.
In the present embodiment, the second transistor T3, the third transistor T4, the fifth transistor T6, and the sixth transistor T7 are turned off under the control of corresponding control signals.
In one possible embodiment, referring to fig. 1 again, the pixel unit 21 includes a first sub-pixel 211, a second sub-pixel 212 and a third sub-pixel 213, and each of the enable transistors T1 is electrically connected to the driving sub-circuit 11 correspondingly and electrically connected to the first sub-pixel 211, the second sub-pixel 212 and the third sub-pixel 213, respectively.
Since the enable transistor T1 is electrically connected to a plurality of the driving sub-circuits 11 at the same time, the first voltage signal ELVDD is simultaneously applied to the pixel cells 21 electrically connected to a plurality of the driving sub-circuits 11 through the enable transistor T1, and the enable transistor T1 is also required to receive a large current.
Specifically, each of the enable transistors T1 is electrically connected to the driving sub-circuits 11 corresponding to and electrically connected to the first sub-pixel 211, the second sub-pixel 212, and the third sub-pixel 213, respectively, in other words, each of the enable transistors T1 is electrically connected to three of the driving sub-circuits 11, respectively. If the number of the pixel units 21 and the driving sub-circuits 11 in a row is x, it can be understood that the number of the enable transistors T1 used is reduced by x-1 with respect to 1 of the driving sub-circuits 11 electrically connected to each of the enable transistors T1.
In the present embodiment, the first sub-pixel 211, the second sub-pixel 212, and the third sub-pixel 213 are respectively a red color pixel, a green color pixel, and a blue color pixel, and each of the enable transistors T1 respectively controls the first sub-pixel 211, the second sub-pixel 212, and the third sub-pixel 213 in the pixel unit 21, and since a single enable transistor T1 can individually control the red color pixel, the green color pixel, and the blue color pixel in a single pixel unit 21, that is, the three primary color pixels for displaying a picture, timing control for implementing picture display can be simplified.
Referring to fig. 6, fig. 6 is a schematic top view of a display panel according to an embodiment of the present application. The display panel 2 has a display area 22 and a non-display area 23 surrounding the display area 22, and the display area 22 is provided with the pixel units 21 and the pixel driving circuit 1 as described above. Specifically, the pixel driving circuit 1 is described above, and the description is omitted herein.
The display area 22 is used for displaying a picture, and the pixel driving circuit 1 and the pixel unit 21 are generally disposed in the display area 22 to realize a picture display function of the display panel 2. The display panel 2 generally further includes a Scan driving module, a Data driving module, etc. disposed in the non-display area 23, for generating the first Scan signal Scan1, the second Scan signal Scan2, the Data signal Data, etc., respectively.
It can be appreciated that in the present embodiment, by simultaneously controlling a plurality of the driving sub-circuits 11 by each of the enable transistors T1, the purpose of reducing the number of transistors in the pixel driving circuit 1 can be achieved, so that the design space can be saved for providing more pixel units 21, and the resolution of the display panel 2 can be improved.
The application further provides an electronic device 3, please refer to fig. 7, fig. 7 is a schematic top view of the electronic device according to an embodiment of the application. The electronic device 3 comprises a housing 31 and the display panel 2 as described above, the housing 31 being arranged to carry the display panel 2. Specifically, the display panel 2 is described above, and the description is omitted herein.
It should be noted that, in the embodiment of the present application, the electronic device 3 may be an electronic device 3 such as a television, a mobile phone, a smart phone, a tablet computer, an electronic reader, a portable device when worn, a notebook computer, etc., and may communicate with a data transfer server through the internet, where the data transfer server may be an instant messaging server, an SNS (Social Networking Services, social network service) server, etc., and the embodiment of the present application is not limited thereto.
It will be appreciated that in the present embodiment, by simultaneously controlling a plurality of the driving sub-circuits 11 by each of the enable transistors T1, the purpose of reducing the number of transistors in the pixel driving circuit 1 can be achieved, so that the design space can be saved for providing more pixel units 21, and the resolution of the electronic device 3 can be improved.
The principles and embodiments of the present application are described herein with specific examples applied thereto, the description of the above embodiments being merely for aiding in understanding of the core ideas of the present application; meanwhile, as those skilled in the art will have modifications in the specific embodiments and application scope in accordance with the ideas of the present application, the present description should not be construed as limiting the present application in view of the above.
Claims (10)
1. The pixel driving circuit is characterized by comprising a plurality of enabling transistors and a plurality of driving sub-circuits, wherein each enabling transistor is used for receiving a first voltage signal and is respectively and electrically connected with the driving sub-circuits, the enabling transistors are used for being conducted under the control of the enabling signals so as to transmit the first voltage signal to the corresponding pixel units through the driving sub-circuits, the other ends of the pixel units are used for receiving a second voltage signal, and the pixel units are used for working under the loading of the first voltage signal and the second voltage signal; the driving sub-circuits and the pixel units are arranged in an array form, and the driving sub-circuits, to which the enabling transistors are respectively electrically connected, are positioned in the same row.
2. The pixel driving circuit according to claim 1, wherein the driving sub-circuit comprises a storage capacitor, a first transistor and a second transistor, wherein one end of the storage capacitor is used for receiving the first voltage signal, and the other end of the storage capacitor is electrically connected with the gate of the first transistor; the source electrode of the first transistor is electrically connected with the drain electrode of the second transistor and one end of the pixel unit, and the drain electrode of the first transistor is electrically connected with the source electrode of the enabling transistor; the grid electrode of the second transistor is used for receiving a first scanning signal, and the source electrode of the second transistor is used for receiving a data signal.
3. The pixel driving circuit according to claim 2, wherein the driving sub-circuit further comprises a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor, a gate of the third transistor being configured to receive the first scan signal, a source of the third transistor being electrically connected to a drain of the fourth transistor and a source of the first transistor, a drain of the third transistor being electrically connected to a drain of the fifth transistor; the grid electrode of the fourth transistor is used for receiving the enabling signal, and the source electrode of the fourth transistor is electrically connected with one end of the pixel unit and the drain electrode of the sixth transistor; the grid electrode of the fifth transistor is used for receiving a second scanning signal, and the source electrode of the fifth transistor is used for receiving a first initialization signal; the grid electrode of the sixth transistor is used for receiving the first scanning signal, and the source electrode of the sixth transistor is used for receiving a second initialization signal.
4. A pixel driving circuit according to claim 3, wherein the pixel driving circuit has a reset phase, and the fifth transistor is turned on under control of the second scan signal to transmit the first initialization signal to one end of the storage capacitor when the pixel driving circuit is in the reset phase.
5. A pixel drive circuit as claimed in claim 3, wherein the pixel drive circuit has a charging phase, the second transistor and the third transistor being turned on under control of the first scan signal when the pixel drive circuit is in the charging phase so that the data signal is transmitted to one end of the storage capacitor; the sixth transistor is turned on under the control of the first scan signal to transmit the second initialization signal to one end of the pixel unit.
6. A pixel driving circuit according to claim 3, wherein the pixel driving circuit has a light emitting stage, and the enable transistor and the fourth transistor are turned on under control of the enable signal when the pixel driving circuit is in the light emitting stage, and the first transistor controls a value of a current flowing through the pixel unit according to a voltage value of one end of the storage capacitor electrically connected to a gate thereof.
7. The pixel driving circuit of claim 1, wherein the pixel unit includes a first sub-pixel, a second sub-pixel, and a third sub-pixel, each of the enable transistors being electrically connected to the driving sub-circuits of the first sub-pixel, the second sub-pixel, and the third sub-pixel, respectively.
8. The pixel driving circuit of claim 7, wherein the first subpixel, the second subpixel, and the third subpixel are a red color pixel, a green color pixel, and a blue color pixel, respectively.
9. A display panel, characterized in that the display panel has a display area and a non-display area surrounding the display area, and the display area is provided with a pixel unit and a pixel driving circuit according to any one of claims 1-8.
10. An electronic device comprising a housing and the display panel of claim 9, wherein the housing is configured to carry the display panel.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310092593.8A CN116013202A (en) | 2023-01-30 | 2023-01-30 | Pixel driving circuit, display panel and electronic equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310092593.8A CN116013202A (en) | 2023-01-30 | 2023-01-30 | Pixel driving circuit, display panel and electronic equipment |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN116013202A true CN116013202A (en) | 2023-04-25 |
Family
ID=86029966
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202310092593.8A Pending CN116013202A (en) | 2023-01-30 | 2023-01-30 | Pixel driving circuit, display panel and electronic equipment |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN116013202A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116434703A (en) * | 2023-04-27 | 2023-07-14 | 惠科股份有限公司 | Pixel driving circuit, compensation method thereof and display panel |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070126671A1 (en) * | 2005-12-02 | 2007-06-07 | Komiya Naoaki | Organic light emitting display device and driving method thereof |
| CN106531084A (en) * | 2017-01-05 | 2017-03-22 | 上海天马有机发光显示技术有限公司 | Organic light emitting display panel and driving method thereof, and organic light emitting display apparatus |
| CN107103878A (en) * | 2017-05-26 | 2017-08-29 | 上海天马有机发光显示技术有限公司 | Array base palte, its driving method, organic electroluminescence display panel and display device |
| CN108417178A (en) * | 2018-03-13 | 2018-08-17 | 京东方科技集团股份有限公司 | Array substrate, its driving method, electroluminescence display panel and display device |
| CN108596083A (en) * | 2018-04-23 | 2018-09-28 | 上海天马有机发光显示技术有限公司 | A kind of display panel and display device |
| CN115050323A (en) * | 2022-06-29 | 2022-09-13 | 惠科股份有限公司 | Pixel array, display panel and display device |
-
2023
- 2023-01-30 CN CN202310092593.8A patent/CN116013202A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070126671A1 (en) * | 2005-12-02 | 2007-06-07 | Komiya Naoaki | Organic light emitting display device and driving method thereof |
| CN106531084A (en) * | 2017-01-05 | 2017-03-22 | 上海天马有机发光显示技术有限公司 | Organic light emitting display panel and driving method thereof, and organic light emitting display apparatus |
| CN107103878A (en) * | 2017-05-26 | 2017-08-29 | 上海天马有机发光显示技术有限公司 | Array base palte, its driving method, organic electroluminescence display panel and display device |
| CN108417178A (en) * | 2018-03-13 | 2018-08-17 | 京东方科技集团股份有限公司 | Array substrate, its driving method, electroluminescence display panel and display device |
| CN108596083A (en) * | 2018-04-23 | 2018-09-28 | 上海天马有机发光显示技术有限公司 | A kind of display panel and display device |
| CN115050323A (en) * | 2022-06-29 | 2022-09-13 | 惠科股份有限公司 | Pixel array, display panel and display device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116434703A (en) * | 2023-04-27 | 2023-07-14 | 惠科股份有限公司 | Pixel driving circuit, compensation method thereof and display panel |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US11837162B2 (en) | Pixel circuit and driving method thereof, display panel | |
| US10565918B2 (en) | OLED pixel arrangement structure having pixel unit of four sub-pixels configured for improving display resolution | |
| US11049458B1 (en) | Pixel driving circuit, driving method and organic light emitting display panel | |
| EP3690871A1 (en) | Pixel circuit and driving method thereof, and display device | |
| US10290260B2 (en) | Pixel circuit having third drive circuit connected to first drive circuit and second drive circuit respectively, display panel and driving method | |
| CN109712565B (en) | Pixel circuit, driving method thereof and electroluminescent display panel | |
| US11315475B2 (en) | Pixel driving circuit, driving method thereof, and display device | |
| US11238803B2 (en) | Pixel circuit and method for driving the same, and display panel | |
| US8922472B2 (en) | Level shifter circuit, scanning circuit, display device and electronic equipment | |
| CN112233621B (en) | Pixel driving circuit, display panel and electronic equipment | |
| US20190051246A1 (en) | Display device, electronic device, and toggling circuit | |
| CN110288950B (en) | Pixel array, array substrate and display device | |
| CN106847190B (en) | Pixel charging circuit, driving method thereof and organic light emitting display device | |
| WO2021057653A1 (en) | Pixel drive circuit and drive method therefor, display panel and display apparatus | |
| US11170701B2 (en) | Driving circuit, driving method thereof, display panel and display device | |
| CN116013202A (en) | Pixel driving circuit, display panel and electronic equipment | |
| US20220139337A1 (en) | Pixel circuit and display panel | |
| CN113658554B (en) | Pixel driving circuit, pixel driving method and display device | |
| CN111312162B (en) | Pixel circuit, display device and driving method of pixel circuit | |
| US20240005872A1 (en) | Pixel array and display panel | |
| US11798477B1 (en) | Pixel circuit, display panel, and display apparatus | |
| EP3244389A1 (en) | Power circuit, array substrate and display device | |
| CN111883060B (en) | Display panel and display device | |
| CN113394258A (en) | Display panel and display device | |
| CN219626302U (en) | Pixel driving circuit, display panel and display device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |