CN116631325A

CN116631325A - Display panel, driving method thereof and display device

Info

Publication number: CN116631325A
Application number: CN202310569142.9A
Authority: CN
Inventors: 李伟明; 敦栋梁; 李孝文; 周舒
Original assignee: Hubei Changjiang New Display Industry Innovation Center Co Ltd
Current assignee: Hubei Changjiang New Display Industry Innovation Center Co Ltd
Priority date: 2023-05-17
Filing date: 2023-05-17
Publication date: 2023-08-22

Abstract

The invention discloses a display panel, a driving method thereof and a display device, wherein a display area of the display panel comprises a plurality of pixel circuits which are arranged in an array; in the same pixel circuit, the driving module comprises a driving transistor; the reset module and the node control module are electrically connected to the first node; the grid electrodes of the driving transistors in the node control module and the driving module are electrically connected to the second node; when the display mode of the display panel is the first mode, the conduction period of the reset module of the pixel circuit in the high-frequency display area is T11, and the conduction period of the node control module of the pixel circuit in the high-frequency display area is T12; the conduction period of the reset module of the pixel circuit in the low-frequency display area is T21, and the conduction period of the node control module of the pixel circuit in the low-frequency display area is T22; wherein T21> T11, and/or T22> T12. According to the technical scheme, the display panel can realize the functions of partial area high-frequency display and partial area low-frequency display, and the application range of the display panel is enlarged.

Description

Display panel, driving method thereof and display device

Technical Field

The present invention relates to the field of display technologies, and in particular, to a display panel, a driving method thereof, and a display device.

Background

With the development of display technology, there is an increasing demand for display panels, for example, when the display panels display dynamic images such as video and games, the refresh frequency of the display images needs to be high to prevent flicker, while in static display images such as web page text browsing, the refresh frequency of the display images needs to be low to reduce power consumption.

Therefore, when the display surface of the display panel has both a dynamic picture and a static picture, how to enable the display panel to realize a partial area high-frequency display and a partial area low-frequency display so as to meet the display requirements of different application occasions becomes a technical problem to be solved.

Disclosure of Invention

The invention provides a display panel, a driving method thereof and a display device, so that the display panel can realize the functions of partial area high-frequency display and partial area low-frequency display, and the positions of a high-frequency display area and a low-frequency display area can be divided arbitrarily, thereby reducing the power consumption of the display panel and expanding the application range of the display panel.

In a first aspect, an embodiment of the present invention provides a display panel, including: a display area; the display area comprises a plurality of pixel circuits which are arranged in an array manner, wherein each pixel circuit comprises a driving module, a resetting module, a node control module and a light-emitting element;

In the same pixel circuit, the driving module is used for providing driving current for the light-emitting element in a light-emitting stage; the driving module comprises a driving transistor; the reset module and the node control module are electrically connected to a first node; the reset module is used for being conducted in a reset phase so as to provide a reset signal for the first node; the node control module and the grid electrode of the driving transistor are electrically connected to a second node; the node control module is used for being conducted in the reset stage and the data writing stage, and controlling the signal of the first node to be transmitted to the second node;

when the display mode of the display panel is a first mode, the display panel comprises a high-frequency display area and a low-frequency display area; the conduction period of the reset module of the pixel circuit in the high-frequency display area is T11, and the conduction period of the node control module of the pixel circuit in the high-frequency display area is T12; the conduction period of the reset module of the pixel circuit in the low-frequency display area is T21, and the conduction period of the node control module of the pixel circuit in the low-frequency display area is T22;

Wherein T21> T11, and/or T22> T12.

In a second aspect, an embodiment of the present invention provides a driving method of a display panel, which is applicable to the display panel in the first aspect, where the driving method of the display panel includes:

acquiring a display mode and a display signal of the display panel;

when the display mode of the display panel is determined to be a first display mode, determining a high-frequency display area and a low-frequency display area of the display panel according to the display signals;

the on period of the reset module of the pixel circuit in the high-frequency display area is T11, and the on period of the node control module of the pixel circuit in the high-frequency display area is T12; the conduction period of the reset module of the pixel circuit in the low-frequency display area is T21, and the conduction period of the node control module of the pixel circuit in the low-frequency display area is T22; t21> T11, and/or T22> T12.

In a third aspect, an embodiment of the present invention provides a display device, including a display panel as described in the first aspect.

According to the scheme provided by the invention, the display area comprises a plurality of pixel circuits which are arranged in an array, and in the same pixel circuit, the reset module and the node control module are electrically connected to the first node, so that the reset module is conducted in a reset stage to provide a reset signal for the first node; the grid electrodes of the driving transistors of the node control module and the driving module are electrically connected to the second node, so that the node control module is conducted in a reset stage and a data writing stage, signals of the first node are controlled to be transmitted to the second node, and the driving module provides driving current for the light-emitting element according to the potential of the second node in a light-emitting stage, so that image display of the display panel is realized. When the display mode of the display panel 100 is the first mode, the display panel includes a high-frequency display area and a low-frequency display area, it can be understood that the on period of the reset module of the pixel circuit in the high-frequency display area and the on period of the node control module are both less than or equal to the time of one frame of display screen of the high-frequency display area, and the on period of the reset module of the pixel circuit in the low-frequency display area and the on period of the node control module are both less than or equal to the time of one frame of display screen of the low-frequency display area, and because the refresh frequency of the display screen of the high-frequency display area is greater than the refresh frequency of the display screen of the low-frequency display area, the on period of the reset module of the pixel circuit in the high-frequency display area is less than or equal to the on period of the reset module of the pixel circuit in the low-frequency display area, and the on period of the pixel circuit node control module in the high-frequency display area is less than or equal to the on period of the node control module of the pixel circuit in the low-frequency display area. Setting the conduction period of the reset module of the pixel circuit in the high-frequency display area as T11, and setting the conduction period of the node control module of the pixel circuit in the high-frequency display area as T12; the on period of the reset module of the pixel circuit in the low-frequency display area is T21, and the on period of the node control module of the pixel circuit in the low-frequency display area is T22, so that T21 is greater than T11, and/or T22 is greater than T12, the display panel can realize the functions of partial area high-frequency display and partial area low-frequency display, and the positions of the high-frequency display area and the low-frequency display area can be divided arbitrarily, so that the power consumption of the display panel is reduced, and the application range of the display panel is enlarged.

It should be understood that the description in this section is not intended to identify key or critical features of the embodiments of the invention or to delineate the scope of the invention. Other features of the present invention will become apparent from the description that follows.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions of the prior art, a brief description will be given below of the drawings required for the embodiments or the description of the prior art, and it is obvious that although the drawings in the following description are specific embodiments of the present invention, it is obvious to those skilled in the art that the basic concepts of the device structure, the driving method and the manufacturing method, which are disclosed and suggested according to the various embodiments of the present invention, are extended and extended to other structures and drawings, and it is needless to say that these should be within the scope of the claims of the present invention.

Fig. 1 is a schematic structural diagram of a display panel according to an embodiment of the present invention;

fig. 2 is a schematic structural diagram of a pixel circuit according to an embodiment of the present invention;

fig. 3 is a schematic structural diagram of another display panel according to an embodiment of the present invention;

FIG. 4 is a timing diagram of driving a display panel according to an embodiment of the present invention;

Fig. 5 is a schematic structural diagram of another display panel according to an embodiment of the present invention;

FIG. 6 is a timing diagram of driving a display panel according to another embodiment of the present invention;

fig. 7 is a schematic partial structure of another display panel according to an embodiment of the invention;

FIG. 8 is a timing diagram of driving a display panel according to another embodiment of the present invention;

fig. 9 is a schematic structural diagram of another display panel according to an embodiment of the present invention;

fig. 10 is a schematic structural diagram of a first pixel circuit according to an embodiment of the present invention;

fig. 11 is a schematic structural diagram of a second pixel circuit according to an embodiment of the present invention;

FIG. 12 is a timing diagram of driving a display panel according to another embodiment of the present invention;

FIG. 13 is a timing diagram of driving a display panel according to another embodiment of the present invention;

fig. 14 is a schematic structural diagram of another first pixel circuit according to an embodiment of the present invention;

fig. 15 is a schematic structural diagram of another second pixel circuit according to an embodiment of the present invention;

fig. 16 is a schematic structural diagram of another display panel according to an embodiment of the present invention;

fig. 17 is a schematic structural diagram of a first pixel circuit according to another embodiment of the present invention;

Fig. 18 is a schematic structural diagram of a second pixel circuit according to an embodiment of the present invention;

fig. 19 is a driving timing diagram of a second pixel circuit according to an embodiment of the present invention;

FIG. 20 is a timing diagram of driving a display panel according to another embodiment of the present invention;

fig. 21 is a schematic structural diagram of another display panel according to an embodiment of the present invention;

fig. 22 is a schematic structural diagram of a first pixel circuit according to an embodiment of the present invention;

fig. 23 is a schematic structural diagram of a second pixel circuit according to an embodiment of the present invention;

FIG. 24 is a timing chart of driving a second pixel circuit according to another embodiment of the present invention

FIG. 25 is a schematic diagram of a shift register according to an embodiment of the present invention;

fig. 26 is a schematic structural diagram of a shift register unit according to an embodiment of the present invention;

FIG. 27 is a schematic diagram of another shift register according to an embodiment of the present invention;

FIG. 28 is a timing diagram of a shift register according to an embodiment of the present invention;

FIG. 29 is a timing diagram illustrating another embodiment of a shift register according to the present invention;

fig. 30 is a flowchart of a driving method of a display panel according to an embodiment of the present invention;

Fig. 31 is a schematic structural diagram of a display device according to an embodiment of the invention.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the present invention more apparent, the technical solutions of the present invention will be clearly and completely described by means of implementation examples with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, not all embodiments. All other embodiments obtained by those skilled in the art based on the basic concepts disclosed and suggested by the embodiments of the present invention are within the scope of the present invention.

Fig. 1 is a schematic structural diagram of a display panel according to an embodiment of the present invention, and fig. 2 is a schematic structural diagram of a pixel circuit according to an embodiment of the present invention, where, as shown in fig. 1 and fig. 2, a display panel 100 includes: a display area AA; the display area AA includes a plurality of pixel circuits 10 arranged in an array, and the pixel circuits 10 include a driving module 11, a reset module 12, a node control module 13, and a light emitting element 14.

In the same pixel circuit 10, the driving module 11 is used for providing driving current for the light emitting element 14 in the light emitting stage; the driving module 11 includes a driving transistor T1; the reset module 12 and the node control module 13 are electrically connected to the first node N1; the reset module 12 is configured to be turned on during a reset phase to provide a reset signal to the first node N1; the node control module 13 and the gate of the driving transistor T1 are electrically connected to the second node N2; the node control module 13 is configured to be turned on during the reset phase and the data writing phase, and control the signal of the first node N1 to be transmitted to the second node N2.

When the display mode of the display panel 100 is the first mode, the display panel 100 includes a high frequency display area AA1 and a low frequency display area AA2; the conduction period of the reset module 12 of the pixel circuit 10 in the high-frequency display area AA1 is T11, and the conduction period of the node control module 13 of the pixel circuit 10 in the high-frequency display area AA1 is T12; the conduction period of the reset module 12 of the pixel circuit 10 in the low-frequency display area AA2 is T21, and the conduction period of the node control module 13 of the pixel circuit 10 in the low-frequency display area AA2 is T22; wherein T21> T11, and/or T22> T12.

It will be appreciated that the pixel circuit 10 may further include a data writing module 15, a threshold compensation module 16, and a light emitting control module 17, which are not specifically limited herein, and may be set according to actual requirements.

With continued reference to fig. 2, the light emitting elements 14 may include one or more of a red light emitting element, a green light emitting element, a blue light emitting element, a white light emitting element, a yellow light emitting element, a cyan light emitting element, and a magenta light emitting element, which are not limited herein. The light emitting element may be a light emitting diode including, but not limited to, an Organic Light Emitting Diode (OLED), a sub-millimeter light emitting diode (Mini LED), or a Micro light emitting diode (Micro LED), etc.

Specifically, in the same pixel circuit 10, the driving transistor T1 of the driving module 11 may be an N-channel transistor or a P-channel transistor, which is not limited herein. When the display panel is in normal high-frequency refresh display, one complete driving period of the pixel circuit 10 includes a reset phase, a data writing phase and a light emitting phase, and in the reset phase, the reset module 12 and the node control module 13 are both in a conducting state, and a reset signal is written into the second node N2 through the conducting reset module 12 and node control module 13. In the data writing stage, the reset module 12 is turned off, at this time, the reset signal is not written into the first node N1, and the node control module 13 is turned on, and the data signal can be written into the second node N2, i.e. into the gate of the driving transistor T1, through the turned-on node control module 13. In the light emitting stage, the driving transistor T1 generates a driving current by the first fixed level signal PVDD and the potential of the second node N2, and supplies the driving current to the light emitting element 14, and drives the light emitting element 14 to emit light, thereby realizing image display of the display panel 100.

With continued reference to fig. 1, when the display mode of the display panel 100 is the first mode, the display area AA of the display panel 100 may be divided into a high-frequency display area AA1 and a low-frequency display area AA2, where the refresh frequency of the high-frequency display area AA1 is different from the refresh frequency of the low-frequency display area AA2, that is, the refresh frequency of the high-frequency display area AA1 is greater than the refresh frequency of the low-frequency display area AA2, and the duration of one frame of the low-frequency display area AA2 at the lower refresh frequency is greater than the display time of one frame of the high-frequency display area AA1 at the higher refresh frequency. The pixel circuit 10 located in the high frequency display area AA1 has one complete driving period (i.e., reset phase, data writing phase and light emitting phase) for each frame of display. The display screen of the low frequency display area AA2 may continuously display the standby screen without continuously refreshing the display screen of the low frequency display area AA2, so that the low frequency display area AA2 may have a longer display driving period, and a frame of display screen time of the low frequency display area AA2 may include a data writing frame and at least one holding frame, wherein the data writing frame may include a complete driving period of the pixel circuit 10, a duration of one holding frame may be the same as a duration of the data writing frame, and the holding frame may include only a lighting period, so that the low frequency display area AA2 may maintain the same display screen for a long period, that is, the low frequency display area AA2 may not perform screen switching for a longer period of time, thereby reducing power consumption caused by screen switching.

The display area AA of the display panel 100 may include a high-frequency display area AA1 and a low-frequency display area AA2, and the relative positional relationship between the high-frequency display area AA1 and the low-frequency display area AA2 may be set according to practical requirements, which is not particularly limited herein, and fig. 1 is only exemplary and not limited thereto. In addition, the shapes and sizes of the high frequency display area AA1 and the low frequency display area AA2 may be set according to actual demands.

Specifically, the display screen of the high-frequency display area AA1 is continuously refreshed, the pixel circuit 10 located in the high-frequency display area AA1 is turned on in the reset phase, the reset module 12 and the node control module 13 are both turned on, so that the reset signal can be written into the first node N1 and the second node N2 in sequence, in the data writing phase, the node control module 13 is turned on, so that the data signal can be transmitted to the second node N2 through the turned-on node control module 13, so that the driving transistor T1 can generate the driving current according to the data signal rewritten into the second node N2, and thus, the turn-on period T11 of the reset module 12 and the turn-on period T12 of the node control module 13 need to be the same as the refresh period of the display screen of the high-frequency display area AA 1. However, since the display screen of the low frequency display area AA2 may continuously display the standby screen, the hold frame of one frame of the display screen of the low frequency display area AA2 may only include a lighting phase, that is, in the hold frame, the reset module 12 and the node control module 13 of the pixel circuit 10 may not need to be turned on to avoid resetting or changing the potential of the second node N2, so as to ensure that the potential of the second node N2 is unchanged to maintain the display screen unchanged, so that the on period T21 of the reset module 12 and the on period T22 of the node control module 13 are the same as the refresh period of the display screen of the low frequency display area AA2, that is, T21> T11 and T22> T12 are satisfied to avoid refreshing the potential of the second node N2, and affect the display screen of the low frequency display area AA 2.

In addition, the on period of the reset module 12 of the pixel circuit 10 in the high-frequency display area AA1 may be the same as the on period of the reset module 12 of the pixel circuit 10 in the low-frequency display area AA2, that is, t11=t21, at this time, the pixel circuit 10 in the low-frequency display area AA2 only needs to control the node control module 13 to be turned off in the reset phase and the data writing phase of the holding frame, so that the potential of the second node N2 of the pixel circuit 10 in the low-frequency display area AA2 can be kept unchanged, so that the display picture in the low-frequency display area AA2 is kept unchanged, at this time, T22> T12, so that the display area AA of the display panel 100 can realize the frequency division display with different refresh frequencies. In the same principle, the on period of the node control module 13 of the pixel circuit 10 in the high-frequency display area AA1 may be the same as the on period of the node control module 13 of the pixel circuit 10 in the low-frequency display area AA2, that is, t12=t22, at this time, the pixel circuit 10 in the low-frequency display area AA2 only needs to control the reset module 12 to be turned off in the reset phase of the retention frame, and needs to control the path of the data signal written into the first node N1 to be turned off in the data writing phase, for example, control the threshold compensation module 16 and/or the data writing module 15 to be turned off, so that the potential of the second node N2 is also ensured to be unchanged, so that the display frame of the low-frequency display area AA2 is kept unchanged, at this time, T21> T11, and thus the display area AA of the display panel 100 can realize the frequency division display with different refresh frequencies.

It can be understood that, in the pixel circuit 10, the on period of the reset module 12 and the node control module 13 is less than or equal to the time of displaying a frame, i.e. when the frame is switched, the on period of the reset module 12 and the node control module 13 is recalculated, i.e. the on period of the previous frame and the time of the on period of the next frame do not overlap. In this way, the on period T11 of the reset module 12 and the on period T12 of the node control module 13 of the pixel circuit 10 in the high-frequency display area AA1 are both smaller than or equal to the time of displaying the pictures in one frame of the high-frequency display area AA1, and the on period T21 of the reset module 12 and the on period T22 of the node control module 13 of the pixel circuit 10 in the low-frequency display area AA2 are both smaller than or equal to the time of displaying the pictures in one frame of the low-frequency display area AA2, and since the refresh frequency of the pictures displayed in the high-frequency display area AA1 is greater than the refresh frequency of the pictures displayed in the low-frequency display area AA2, i.e. the number of the pictures switched in the high-frequency display area AA1 is greater than the number of the pictures switched in the low-frequency display area AA2, the on period T11 of the reset module 12 of the pixel circuit 10 in the high-frequency display area AA1 is not greater than the case of the on period T21 of the reset module 12 of the pixel circuit 10 in the low-frequency display area AA2, and the on period T12 of the node control module 13 of the pixel circuit 10 in the high-frequency display area AA1 is not greater than the case of the node control module 13 in the low-frequency display area AA 2.

In this way, when the display mode of the display panel 100 is the first mode, the display area AA of the display panel 100 can be arbitrarily divided into the high-frequency display area AA1 and the low-frequency display area AA2 by making T21> T11 and/or T22> T12, so that the display panel 100 can realize the function of partial area low-frequency display, and the power consumption of the display panel 100 can be reduced, thereby expanding the application range of the display panel 100.

In this embodiment, by setting that the display area includes a plurality of pixel circuits arranged in an array, in the same pixel circuit, the reset module and the node control module are electrically connected to the first node, so that the reset module is turned on in a reset phase to provide a reset signal to the first node; the grid electrodes of the driving transistors of the node control module and the driving module are electrically connected to the second node, so that the node control module is conducted in a reset stage and a data writing stage, signals of the first node are controlled to be transmitted to the second node, and the driving module provides driving current for the light-emitting element according to the potential of the second node in a light-emitting stage, so that image display of the display panel is realized. When the display mode of the display panel 100 is the first mode, the display panel includes a high-frequency display area and a low-frequency display area, it can be understood that the on period of the reset module of the pixel circuit in the high-frequency display area and the on period of the node control module are both less than or equal to the time of one frame of display screen of the high-frequency display area, and the on period of the reset module of the pixel circuit in the low-frequency display area and the on period of the node control module are both less than or equal to the time of one frame of display screen of the low-frequency display area, and because the refresh frequency of the display screen of the high-frequency display area is greater than the refresh frequency of the display screen of the low-frequency display area, the on period of the reset module of the pixel circuit in the high-frequency display area is less than or equal to the on period of the reset module of the pixel circuit in the low-frequency display area, and the on period of the pixel circuit node control module in the high-frequency display area is less than or equal to the on period of the node control module of the pixel circuit in the low-frequency display area. Setting the conduction period of the reset module of the pixel circuit in the high-frequency display area as T11, and setting the conduction period of the node control module of the pixel circuit in the high-frequency display area as T12; the on period of the reset module of the pixel circuit in the low-frequency display area is T21, and the on period of the node control module of the pixel circuit in the low-frequency display area is T22, so that T21 is greater than T11, and/or T22 is greater than T12, the display panel can realize the functions of partial area high-frequency display and partial area low-frequency display, and the positions of the high-frequency display area and the low-frequency display area can be divided arbitrarily, so that the power consumption of the display panel is reduced, and the application range of the display panel is enlarged.

Optionally, fig. 3 is a schematic structural diagram of another display panel according to an embodiment of the present invention, and referring to fig. 2 and 3 in combination, a non-display area NA located at one side of the display area AA; the display area AA includes a plurality of first driving signal lines 20, and the non-display area NA includes a first shift register 30; the plurality of pixel circuits 10 constitute a plurality of pixel circuit groups 110; each pixel circuit group 110 includes at least one column of pixel circuits 10; the first shift register 30 includes a plurality of first shift register units 31 disposed in cascade, and a signal output terminal of each stage of the first shift register units 31 is electrically connected to the reset module 12 of at least part of the pixel circuits 10 located in the same row; the first shift register unit 31 is configured to output a first scan signal S1 for controlling the reset module 12 to be turned on or off; each first driving signal line 20 is electrically connected to the node control module 13 of each pixel circuit 10 in the same pixel circuit group 110; the first driving signal line 20 is used for transmitting a first driving signal D for controlling the node control module 13 to be turned on or off.

With continued reference to fig. 3, the first shift register 30 includes a plurality of first shift register units 31 disposed in cascade, it is understood that, in the same shift register 30, a signal input terminal of the first shift register unit 31 of the first stage receives a start pulse signal, so that the start pulse signal can control a signal output by the first shift register unit 31 of the first stage; the signal input end of each of the remaining first shift register units 31 except the first shift register unit 31 of the first stage is electrically connected to the signal output end of the first shift register unit 31 of the previous stage, so that the signal output by the signal output end of the first shift register unit 31 of the previous stage can control the signal output by the signal output end of the first shift register unit 31 of the next stage.

Since the on periods of the reset modules 12 of the pixel circuits 10 in the high-frequency display area AA1 and the low-frequency display area AA2 may be different, the periods of the enable levels of the first scan signals S1 received by the reset modules 12 of the pixel circuits 10 in the high-frequency display area AA1 and the low-frequency display area AA2 may be different, so that the pixel circuits 10 in the high-frequency display area AA1 and the pixel circuits in the low-frequency display area AA2 may be respectively connected to different first shift registers 30, so as to realize that at least one row of pixel circuits 10 in the low-frequency display area AA2 may be displayed at a low frequency, while the rest of pixel circuits 10 may be displayed at a high frequency, but is not limited thereto. The signal output end of the first shift register unit 31 in the first shift register 30, which is electrically connected to the reset module 12 of the pixel circuit 10 in the low-frequency display area AA2, may be adjusted to not output a signal, so that a part of the rows of the pixel circuit 10 may realize low-frequency display.

The specific number and the working manner of the first shift register 30 are not limited, and may be set according to actual requirements, so that only the first scan signal S1 output by the first shift register unit 31 of the first shift register 30 is required to control at least one row of pixel circuits 10 to perform low-frequency display, and the rest of pixel circuits 10 may perform high-frequency display, so as to realize that the high-frequency display area AA1 and the low-frequency display area AA2 may be arranged along the column direction Y.

With continued reference to fig. 3, the number of columns of the pixel circuits 10 in the plurality of pixel circuit groups 110 may be the same or different, and not limited to this, and may be set according to practical requirements, and fig. 3 exemplarily shows that the display panel 100 includes m pixel circuit groups 110, and a portion of the pixel circuit groups 110 includes two columns of the pixel circuits 10, but not limited to this, each pixel circuit group 110 is electrically connected to one first driving line 20, and the received first driving signals D are D1 to Dm, respectively.

The first driving signal line 20 may be electrically connected to a driving chip, and the driving chip provides the first driving signal D to the first driving signal line 20 and transmits the first driving signal D to the node control module 13 of the pixel circuits 10 of one pixel circuit group 110 to control on or off of the node control module 13. In this way, the turn-on period of the node control module 13 may be controlled by controlling the period of the first driving signal D provided by each first driving signal line 20 as the enabling level, so that different pixel circuit groups 110 in the display panel 100 display images at different refresh frequencies, and thus, the turn-on period of the node control module 13 of the pixel circuit 10 in the high-frequency display area AA1 and the low-frequency display area AA2 is controlled differently by transmitting the first driving signal D to the node control module 13 of the pixel circuit 10 in each pixel circuit group 110 through the plurality of first driving signal lines 20, so that at least one pixel circuit group 110 can perform high-frequency display, and the rest of pixel circuit groups 110 perform low-frequency display, thereby realizing that the high-frequency display area AA1 and the low-frequency display area AA2 can be arranged along the row direction X.

Alternatively, with continued reference to fig. 3, the high-frequency display area AA1 and the low-frequency display area AA2 are arranged along the column direction Y of the pixel circuit 10; when the display mode of the display panel 100 is the first mode, T21> T11, and T22> T12.

Specifically, since the high-frequency display area AA1 and the low-frequency display area AA2 are arranged along the column direction Y of the pixel circuits 10, that is, the high-frequency display area AA1 includes at least one row of pixel circuits 10, and the rest of pixel circuits 10 are located in the low-frequency display area AA2, the on period T11 of the reset module 12 of at least one row of pixel circuits 10 located in the high-frequency display area AA1 is equal to the period of refreshing the picture of the high-frequency display area AA1, so as to ensure that the pixel circuits 10 located in the high-frequency display area AA1 have a complete driving period in a frame of display picture, thereby realizing high-frequency display. The reset module 12 of the pixel circuit 10 in the low frequency display area AA2 needs to be turned off in the holding frame of the display frame to avoid resetting the potential of the second node N2, so that the on period T21 of the reset module 12 of the pixel circuit 10 in the low frequency display area AA2 is greater than the on period T11 of the reset module 12 of the pixel circuit 10 in the high frequency display area AA1, i.e. T21> T11.

Further, with continued reference to fig. 3, since the pixel circuits 10 located in the high-frequency display area AA1 are further electrically connected to the first driving signal lines 20, the first driving signal D provided by the first driving signal lines 20 needs to control the node control modules 13 of the pixel circuits 10 to be turned on in both the reset phase and the data writing phase, so that the on period T21 of the node control modules 13 of at least one row of the pixel circuits 10 located in the high-frequency display area AA1 is equal to the period of the frame refresh of the high-frequency display area AA1, so as to ensure that the pixel circuits 10 located in the high-frequency display area AA1 have a complete driving period in a frame display frame of the high-frequency display area AA1, thereby implementing high-frequency display. The node control module 13 of the pixel circuit 10 in the low frequency display area AA2 needs to be turned off in a frame of the display frame, so that the potential of the second node N2 is kept unchanged, and the display frame is kept unchanged, so that the turn-on period T22 of the node control module 13 of the pixel circuit 10 in the low frequency display area AA2 is greater than the turn-on period T12 of the node control module 13 of the pixel circuit 10 in the high frequency display area AA1, i.e., T22> T12.

In this way, when the high-frequency display area AA1 and the low-frequency display area AA2 are arranged along the column direction Y of the pixel circuit 10 and the display mode of the display panel 100 is the first mode, T21> T11 and T22> T12 need to be satisfied, so that the display panel 100 can realize the frequency division display along the column direction Y, and power consumption is reduced. It should be noted that the high-frequency display area AA1 may be one or more, and the low-frequency display area AA2 may be one or more, and the specific arrangement manner may be set according to the actual requirement, which is not limited herein. Fig. 3 is merely exemplary, but is not limited thereto.

Optionally, fig. 4 is a driving timing chart of a display panel according to an embodiment of the present invention, and referring to fig. 3 and 4, a frame time of the low frequency display area AA2 includes a data writing frame t1 and at least one holding frame t2; the data writing frame t1 includes a first non-light-emitting period t10 and a light-emitting period t20; the first non-light emitting stage t10 includes a reset stage t11 and a data writing stage t12; the hold frame t2 includes a second non-light-emitting period t30 and a light-emitting period t20; the second non-light-emitting stage t30 is not provided with a reset stage and a data writing stage; at least part of the holding frame t2 is the first holding frame t201. In the data writing frame t1, the first shift register units 31 of each stage sequentially output the enable level of the first scan signal S1 for controlling the reset module 12 to be turned on; the first driving signal line 20 transmits an enable level of the first driving signals D (i.e., D1 to Dm) turned on by the control node control module 13. In the first holding frame t201, each of the first shift register units 31 electrically connected to the reset module 12 of the pixel circuit 10 in the high-frequency display area AA1 sequentially outputs the enable level of the first scan signal S1, and each of the first shift register units 31 electrically connected to the reset module 12 of the pixel circuit 10 in the low-frequency display area AA2 outputs the disable level of the first scan signal S1; the first driving signal line 20 electrically connected to the node control module 13 of the pixel circuit 10 in the high frequency display area AA1 transmits the enable level of the first driving signal D (i.e., D1 to Dm), and the first driving signal line 20 electrically connected to the node control module 13 of the pixel circuit 10 in the low frequency display area AA2 transmits the disable level of the first driving signal D (i.e., D1 to Dm).

In the second non-light-emitting stage t30, the reset stage and the data writing stage are not set, which can be understood that in the second non-light-emitting stage t30, the potential of the second node N2 of the pixel circuit 10 is not reset and a new data signal is written, that is, the potential of the second node N2 of the pixel circuit 10 remains unchanged, and the scan signal electrically connected to the data writing module 15 or the threshold compensation module 16 of the pixel circuit 10 is not necessarily a non-enable level, which can be specifically designed according to practical situations and is not specifically limited herein.

It will be appreciated that the level of the enable and disable levels are dependent on the type of transistor they control, and in embodiments of the invention the level of the enable and disable levels may be defined as desired. For convenience of description, embodiments of the present invention will be described by taking a signal with an enable level being a low level and a signal with a disable level being a high level as an example, unless otherwise specified.

Normally, a high level signal and a low level signal which is continuous with the high level signal form a pulse period, and the on period T11 of the reset module 12 of the pixel circuit 10 in the high frequency display area AA1 is the time between two adjacent enable levels of the first scan signal S1 outputted from the first shift register unit 31 which is electrically connected to the reset module 12 of the pixel circuit 10 in the high frequency display area AA 1. The on period T21 of the reset module 12 of the pixel circuit 10 in the low frequency display area AA2 is the time between two adjacent enable levels of the first scan signal S1 output by the first shift register unit 31 electrically connected to the reset module 12 of the pixel circuit 10 in the low frequency display area AA 2. Similarly, the on period T12 of the node control module 13 of the pixel circuit 10 in the high-frequency display area AA1 is the time between two adjacent enable levels of the first driving signal D output by the first driving signal line 20 electrically connected to the node control module 13 of the pixel circuit 10 in the high-frequency display area AA1, and if the node control module 13 of the pixel circuit 10 in the high-frequency display area AA1 is always on, the on period T12 of the node control module 13 of the pixel circuit 10 in the high-frequency display area AA1 is equal to the time of one frame of display screen in the high-frequency display area AA 1. The on period T22 of the node control module 13 of the pixel circuit 10 in the low frequency display area AA2 is the time between two adjacent enable levels of the first driving signal D outputted from the first driving signal line 20 electrically connected to the node control module 13 of the pixel circuit 10 in the low frequency display area AA 2.

Illustratively, taking an example that the kth line pixel circuit 10 is located in the high frequency display area AA1 and the k+1th line pixel circuit 10 is located in the low frequency display area AA2, k is an integer greater than or equal to 1, fig. 4 exemplarily shows a driving timing chart of the kth line pixel circuit 10 and the k+1th line pixel circuit 10.

With continued reference to fig. 2, 3 and 4, in the data writing frame t1, the k-th row pixel circuit 10 and the k+1th row pixel circuit 10 each have one complete driving period, i.e., include a reset phase t11, a data writing phase t12 and a light emitting phase t20. In the reset stage T11, the first shift register units 31 sequentially output the enable level (i.e., the low level signal) of the first scan signal S1 controlling the on of the reset module 12, so that the reset module 12 of the kth row of pixel circuits 10 and the reset module 12 of the kth+1th row of pixel circuits 10 can be turned on according to the received enable level of the first scan signal S1 to write the reset signal into the first node N1, and meanwhile, the first driving signals D (D1-Dm) transmitted by the first driving signal line 20 keep the enable level (i.e., the low level signal), so that the node control modules 13 of the kth row of pixel circuits 10 and the kth+1th row of pixel circuits 10 can be turned on, and further, the reset signal is transmitted from the first node N1 to the second node N2 to reset the gate of the driving transistor T1. In the data writing stage t12, the enable level (i.e., the low level signal) of the third scan signal S3 controls the data signal writing path to be turned on so that the data signal can be written to the second node N2. In the light emitting stage T20, the driving transistor T1 generates a driving current by the first fixed level signal PVDD and the potential of the second node N2, supplies the driving current to the light emitting element 14, and drives the light emitting element 14 to emit light, thereby realizing image display of the display panel 100.

In the first holding frame t201, the pixel circuits 10 in the high-frequency display area AA1 still have a complete driving period, referring to fig. 4, each of the first shift register units 31 electrically connected to the reset module 12 of the kth line of pixel circuits 10 sequentially outputs the enable level of the first scan signal S1, and meanwhile, the first driving signals D (i.e., D1 to Dm) transmitted by the first driving signal line 20 electrically connected to the node control module 13 of the kth line of pixel circuits 10 are the enable level, and it can be understood that the driving timing of the kth line of pixel circuits 10 in the data writing frame t1 and the holding frame t2 is the same, so that the pixel circuits 10 in the high-frequency display area AA1 still perform image display at a higher refresh frequency. The first shift register units 31 electrically connected to the reset module 12 of the pixel circuit 10 in the low-frequency display area AA2 all output the non-enable level (i.e., the high level signal) of the first scan signal S1, so that the reset module 12 of the pixel circuit 10 in the low-frequency display area AA2 is disconnected, and meanwhile, the first driving signals D (i.e., D1-Dm) transmitted by the first driving signal line 20 electrically connected to the node control module 13 of the pixel circuit 10 in the low-frequency display area AA2 are at the non-enable level, so that the node control module 13 is also in the disconnected state, and the second node N2 of the pixel circuit 10 is ensured to be kept unchanged all the time, and further, the display screen of the low-frequency display area AA2 is kept unchanged, so that the display panel 100 can realize frequency division display along the column direction Y, and power consumption is reduced.

It should be noted that, since the node control module 13 of the pixel circuit 10 in the low-frequency display area AA2 is in the off state in the first holding frame t201, the third scan signal S3 may output an enabling level or a non-enabling level, which is not limited herein, and may be set according to the actual requirement. The third scan signal S3 in fig. 4 is only exemplarily shown, but is not limited thereto.

For convenience of detailed explanation of the scheme, referring to fig. 2 and 4 in combination, fig. 2 illustrates only an exemplary structure of the pixel circuit 10, the light emission control module includes a first light emission control transistor T2 and a second light emission control transistor T3, and gates of the first light emission control transistor T2 and the second light emission control transistor T3 are electrically connected to a light emission control signal terminal for controlling the light emission control module 17 to be turned on or off according to a light emission control signal Emit provided from the light emission control signal terminal, and specific structures of the pixel circuit 10 include, but are not limited thereto. The emission control signal Emit is at a non-enable level (high level signal) in the first non-emission phase t10, controls the emission control module 17 to be turned off, and the emission control signal Emit is at an enable level (low level signal) in the emission phase t20, controls the emission control module 17 to be turned on. The third scan signal S3 is only an exemplary signal indicating the data writing stage t12, and the on signal of the data writing path of the pixel circuit 10 may be a signal for controlling the on of the threshold compensation module 16 and the data writing module 15, but is not limited thereto, fig. 4 is only an exemplary signal, and specific signals for switching on or off the threshold compensation module 16 and the data writing module 15 may be the same signal or different signals, and may be set according to actual requirements. In the case where no special explanation is provided, in the holding frame t2, the following description will take the same output case of the first scanning signal S1 as an example of the third scanning signal S3 controlling the pixel circuit 10 in the low-frequency display area AA2, for example, if the first scanning signal S1 is at the disable level in the reset phase t11 of the holding frame t2, the third scanning signal S3 is at the disable level in the data writing phase t12, and if the first scanning signal S1 is at the enable level in the reset phase t11 of the holding frame t2, the third scanning signal S3 is at the enable level in the data writing phase t 12.

Alternatively, fig. 5 is a schematic structural diagram of another display panel according to an embodiment of the present invention, as shown in fig. 5, the high-frequency display area AA1 and the low-frequency display area AA2 are arranged along the row direction X of the pixel circuit 10; when the display mode of the display panel 100 is the first mode, t21=t11 and T22> T12.

Specifically, the high-frequency display area AA1 and the low-frequency display area AA2 are arranged along the row direction X of the pixel circuits 10, that is, the high-frequency display area AA1 includes at least one pixel circuit group 110, and the rest of the pixel circuit groups 110 are located in the low-frequency display area AA2, because the signal output end of each stage of the first shift register unit 31 is electrically connected to the reset module 12 of at least part of the pixel circuits 10 located in the same row, and the pixel circuits 10 in the high-frequency display area AA1 need to have a complete driving period in each frame of display image, the on period T11 of the reset module 12 of the pixel circuits 10 in the high-frequency display area AA1 is the same as the on period T21 of the reset module 12 of the pixel circuits 10 in the low-frequency display area AA2, that is, t11=t21, so as to ensure normal image display in the high-frequency display area AA 1.

However, the display frame needs to be maintained in the low frequency display area AA2, and since the on period T21 of the reset module 12 of the pixel circuit 10 in the low frequency display area AA2 is the same as the on period T11 of the reset module 12 of the pixel circuit 10 in the high frequency display area AA1, it is necessary to ensure that the node control module 13 of the pixel circuit 10 in the low frequency display area AA2 is turned off in both the reset phase and the data writing phase, so as to avoid the potential change of the second node N2, and ensure that the display frame is maintained unchanged, so that the on period T22 of the node control module 13 of the pixel circuit 10 in the low frequency display area AA2 is greater than the on period T12 of the node control module 13 of the pixel circuit 10 in the high frequency display area AA1, that is, i.e., T22> T12.

In this way, when the high-frequency display area AA1 and the low-frequency display area AA2 are arranged along the row direction X of the pixel circuit 10 and the display mode of the display panel 100 is the first mode, t21=t11 needs to be satisfied, and T22> T12, so that the display panel 100 can realize the frequency division display along the row direction X, and power consumption is reduced. It should be noted that the high-frequency display area AA1 may be one or more, and the low-frequency display area AA2 may be one or more, and the specific arrangement manner may be set according to the actual requirement, which is not limited herein. Fig. 5 is merely exemplary, but is not limited thereto.

Optionally, fig. 6 is a driving timing chart of another display panel according to an embodiment of the present invention, and referring to fig. 5 and 6, a frame time of the low frequency display area AA2 includes a data writing frame t1 and at least one holding frame t2; the data writing frame t1 includes a first non-light-emitting period t10 and a light-emitting period t20; the first non-light emitting stage t10 includes a reset stage t11 and a data writing stage t12; the hold frame t2 includes a second non-light-emitting period t30 and a light-emitting period t20; the second non-light-emitting stage t30 is not provided with a reset stage and a data writing stage; at least part of the holding frame t2 is the first holding frame t201. In the data writing frame t1, the first shift register units 31 of each stage sequentially output the enable level of the first scan signal S1 for controlling the reset module 12 to be turned on; the first driving signal line 20 transmits an enable level of the first driving signals D (i.e., D1 to Dm) turned on by the control node control module 13. In the first holding frame t201, the first shift register units 31 of each stage sequentially output the enable level of the first scan signal S1; the first driving signal line 20 electrically connected to the node control module 13 of the pixel circuit 10 in the high frequency display area AA1 transmits an enable level of the first driving signal D, and the first driving signal line 20 electrically connected to the node control module 13 of the pixel circuit 10 in the low frequency display area AA2 transmits a disable level of the first driving signal D.

By way of example, fig. 6 exemplarily shows a driving timing chart of the jth column pixel circuit 10 and the jth+1th column pixel circuit 10, taking an example that the kth row jth column pixel circuit 10 is located in the high-frequency display area AA1 and the kth row jth+1th column pixel circuit 10 is located in the low-frequency display area AA2, both k and j being integers greater than or equal to 1.

With continued reference to fig. 2, 5 and 6, in the data writing frame t1, the j-th column pixel circuit 10 and the j+1th column pixel circuit 10 each have a complete driving cycle, i.e., include the reset phase t11, the data writing phase t12 and the light emitting phase t20, and the detailed operation will not be described herein.

In the first holding frame T201, the first shift register units 31 sequentially output the enable level (i.e., the low level signal) of the first scan signal S1, so that the first scan signal S1 received by the reset module 12 of the pixel circuit 10 in the kth row and the jth column and the (j+1) th column is identical, that is, the on period T11 of the reset module 12 of the pixel circuit 10 in the high frequency display area AA1 is identical to the on period T21 of the reset module 12 of the pixel circuit 10 in the low frequency display area AA 2. Meanwhile, the node control module 13 of the jth column of pixel circuits 10 in the high-frequency display area AA1 needs to be kept on in the holding frame t2, so that the first driving signal Dj transmitted by the first driving signal line 20 electrically connected to the node control module 13 of the jth column of pixel circuits 10 is kept at the enabling level (i.e. the low level signal), thereby ensuring that the pixel circuits 10 in the high-frequency display area AA1 still perform image display at a higher refresh frequency. The j+1th row of the pixel circuits 10 in the low frequency display area AA2 needs to maintain the current display frame unchanged, at this time, the first driving signal dj+1 transmitted by the first driving signal line 20 electrically connected to the node control module 13 of the pixel circuits 10 in the low frequency display area AA2 is at a non-enabling level (i.e., a high level signal), so as to ensure that the potential of the second node N2 remains unchanged, thereby maintaining the display frame of the low frequency display area AA2 unchanged, and thus, the display panel 100 can realize frequency division display along the row direction X and reduce power consumption.

Optionally, fig. 7 is a schematic diagram of a partial structure of a display panel according to another embodiment of the present invention, as shown in fig. 7, the low-frequency display area AA2 includes a first low-frequency display area AA21 and a second low-frequency display area AA22; the first low-frequency display area AA21 and the high-frequency display area AA1 are arranged along the column direction Y of the pixel circuit 10, and the second low-frequency display area AA22 and the high-frequency display area AA1 are arranged along the row direction X of the pixel circuit 10. The turn-on period of the reset module 12 of the pixel circuit 10 in the first low-frequency display area AA21 is T211, the turn-on period of the reset module 12 of the pixel circuit 10 in the second low-frequency display area AA22 is T212, the turn-on period of the node control module 13 of the pixel circuit 10 in the first low-frequency display area AA21 is T221, and the turn-on period of the node control module 13 of the pixel circuit 10 in the second low-frequency display area AA22 is T222; when the display mode of the display panel 100 is the first mode, T211> T11, t212=t11, T221> T12, and T222> T12.

Specifically, the first low-frequency display area AA21 and the high-frequency display area AA1 are arranged along the column direction Y of the pixel circuit 10, that is, the pixel circuit 10 in the high-frequency display area AA1 has a complete driving period in one frame of display picture, and the reset module 12 of the pixel circuit 10 in the first low-frequency display area AA21 needs to be disconnected in a holding frame of the display picture so as to avoid resetting the potential of the second node N2, so that the on period T211 of the reset module 12 of the pixel circuit 10 in the first low-frequency display area AA21 is greater than the on period T11, that is, T211> T11, of the reset module 12 of the pixel circuit 10 in the high-frequency display area AA1, and meanwhile, the on period T221 of the node control module 13 of the pixel circuit 10 in the first low-frequency display area AA21 is greater than the on period T11, that is T221> T12 of the node control module 13 of the pixel circuit 10 in the high-frequency display area AA1, so as to ensure that the high-frequency display area AA1 always performs display with high refresh rate, and the first low-frequency display area AA is kept in the holding frame so as not to refresh the display picture with low power consumption.

The second low-frequency display area AA22 and the high-frequency display area AA1 are arranged along the row direction X of the pixel circuits 10, and since the signal output end of the first shift register unit 31 of each stage is electrically connected to the reset module 12 of at least part of the pixel circuits 10 located in the same row, and the pixel circuits 10 in the high-frequency display area AA1 need to have a complete driving period in each frame of display picture, the on period T11 of the reset module 12 of the pixel circuits 10 in the high-frequency display area AA1 is the same as the on period T212 of the reset module 12 of the pixel circuits 10 in the second low-frequency display area AA22, that is, t212=t11, so that normal picture display in the high-frequency display area AA1 is ensured. The second low frequency display area AA22 needs to maintain the display frame unchanged, at this time, the node control module 13 of the pixel circuit 10 in the second low frequency display area AA22 is turned off to avoid the potential change of the second node N2, so as to ensure that the display frame is maintained unchanged, so that the on period T222 of the node control module 13 of the pixel circuit 10 in the second low frequency display area AA22 is greater than the on period T12, i.e., T222> T12, of the node control module 13 of the pixel circuit 10 in the high frequency display area AA1, so as to ensure that the high frequency display area AA1 always performs the frame display at a high refresh rate, and the second low frequency display area AA22 maintains the display frame unchanged to perform the frame display at a lower refresh rate, so as to reduce the power consumption of the display panel.

In this way, when the first low-frequency display area AA21 and the high-frequency display area AA1 are arranged along the column direction Y of the pixel circuit 10, the second low-frequency display area AA22 and the high-frequency display area AA1 are arranged along the row direction X of the pixel circuit 10, and the display mode of the display panel 100 is the first mode, T211> T11, t212=t11, T221> T12, and T222> T12 need to be satisfied, so that the display panel 100 can realize the frequency division display along the column direction Y and the X direction at the same time, and power consumption is reduced.

It should be noted that the number of the high-frequency display areas AA1 may be one or more, and the number of the first low-frequency display areas AA21 and the second low-frequency display areas AA22 may be one or more, which is not particularly limited, and may be set according to actual requirements. In addition, the refreshing of the display images of the first low frequency display area AA21 and the second low frequency display area AA22 may be the same or different, and is not particularly limited herein, and may be set according to actual requirements.

Optionally, fig. 8 is a driving timing chart of a display panel according to another embodiment of the present invention, and referring to fig. 7 and 8, a frame time of the low frequency display area AA2 includes a data writing frame t1 and at least one holding frame t2; the data writing frame t1 includes a first non-light-emitting period t10 and a light-emitting period t20; the first non-light emitting stage t10 includes a reset stage t11 and a data writing stage t12; the hold frame t2 includes a second non-light-emitting period t30 and a light-emitting period t20; the second non-light-emitting stage t30 is not provided with a reset stage and a data writing stage; at least part of the holding frame t2 is the first holding frame t201. In the data writing frame t1, the first shift register units 31 of each stage sequentially output the enable level of the first scan signal S1 for controlling the reset module 12 to be turned on; the first driving signal line 20 transmits an enable level of the first driving signals D (i.e., D1 to Dm) turned on by the control node control module 13. In the first holding frame t201, each of the first shift register units 31 electrically connected to the reset module 12 of the pixel circuit 10 in the second low-frequency display AA22 and the high-frequency display area AA1 sequentially outputs the enable level of the first scan signal S1, and each of the first shift register units 31 electrically connected to the reset module 12 of the pixel circuit 10 in the first low-frequency display area AA21 outputs the disable level of the first scan signal S1; the first driving signal line 20 electrically connected to the node control module 13 of the pixel circuit 10 in the high frequency display area AA1 transmits an enable level of the first driving signal D, and the first driving signal line 20 electrically connected to the node control module 13 of the pixel circuit 10 in the first and second low frequency display areas AA21 and AA22 transmits a disable level of the first driving signal D.

Illustratively, taking the example that the kth row and the jth column of the pixel circuits 10 are located in the high-frequency display area AA1, the kth row and the jth+1th column of the pixel circuits 10 are located in the second low-frequency display area AA22, the kth+1th row of the pixel circuits 10 are located in the first low-frequency display area AA21, and k and j are integers greater than or equal to 1.

With continued reference to fig. 2, 7 and 8, in the data writing frame t1, each pixel circuit 10 in the display area AA has a complete driving period, i.e. includes a reset phase t11, a data writing phase t12 and a light emitting phase t20, and the specific operation is not described in detail herein, and reference is made to the foregoing description.

In the first holding frame T201, each of the first shift register units 31 electrically connected to the reset modules 12 of the pixel circuits 10 in the second low-frequency display area AA22 and the high-frequency display area AA1 sequentially outputs the enable level (i.e., the low level signal) of the first scan signal S1, so that the first scan signal S1 received by the reset modules 12 of the pixel circuits 10 in the kth row and the jth column and the jth+1st column are identical, i.e., the on period T11 of the reset modules 12 of the pixel circuits 10 in the high-frequency display area AA1 is identical to the on period T212 of the reset modules 12 of the pixel circuits 10 in the second low-frequency display area AA 22. Meanwhile, the node control module 13 of the j-th column pixel circuit 10 located in the high-frequency display area AA1 needs to be kept on in the holding frame t2, so that the first driving signal Dj transmitted by the first driving signal line 20 electrically connected to the node control module 13 of the j-th column pixel circuit 10 is kept at an enabling level (i.e., a low level signal), ensuring that the pixel circuit 10 located in the high-frequency display area AA1 still performs image display at a higher refresh frequency, while the second low-frequency display area AA22 needs to maintain the current display screen unchanged, and the potential of the second node N2 of the j+1th column pixel circuit 10 located in the second low-frequency display area AA22 needs to be kept unchanged, at this time, the first driving signal dj+1 transmitted by the first driving signal line 20 electrically connected to the node control module 13 of the pixel circuit 10 in the second low-frequency display area AA22 is at a non-enabling level (i.e., a high level signal), so as to ensure that the potential of the second node N2 remains unchanged, thereby enabling the display screen of the second low-frequency display area AA22 to maintain the current display screen unchanged, and thus enabling the display area AA 100 to be reduced in the direction of the high-frequency display area AA 2. Further, each of the first shift register units 31 electrically connected to the reset module 12 of the pixel circuit 10 in the first low-frequency display area AA21 outputs a non-enable level (i.e., a high level signal) of the first scan signal S1, so that the reset module 12 of the pixel circuit 10 located in the first low-frequency display area AA21 is disconnected, and meanwhile, the first driving signals D (i.e., D1 to Dm) transmitted by the first driving signal line 20 electrically connected to the node control module 13 of the pixel circuit 10 in the first low-frequency display area AA21 are at the non-enable level, so that the node control module 13 is also in the disconnected state, and the second node N2 of the pixel circuit 10 is ensured to be kept unchanged all the time, so that the display screen of the first low-frequency display area AA21 and the high-frequency display area AA1 of the display panel 100 are kept unchanged, and thus the first low-frequency display area AA21 and the high-frequency display area AA1 can realize frequency division display along the column direction Y, and power consumption is reduced.

Optionally, fig. 9 is a schematic structural diagram of another display panel provided by the embodiment of the present invention, fig. 10 is a schematic structural diagram of a first pixel circuit provided by the embodiment of the present invention, fig. 11 is a schematic structural diagram of a second pixel circuit provided by the embodiment of the present invention, and as shown in fig. 9, fig. 10 and fig. 11, the reset module 12 includes a first control end C1 and a second control end C2; the first control terminal C1 of the reset module 12 is electrically connected to the signal output terminal of the first shift register unit 31. At least part of the pixel circuits 10 in the low-frequency display area AA2 are first pixel circuits 101, and at least part of the pixel circuits 10 in the high-frequency display area AA1 are second pixel circuits 102; the first control terminal C1 of the reset module 12 in the second pixel circuit 102 is electrically connected to the second control terminal C2.

The display area AA includes a second driving signal line 40, where the second driving signal line 40 is electrically connected to the second control terminal C2 of the reset module 12 in each first pixel circuit 101; the second driving signal line 40 is used for transmitting a second driving signal Cref; the reset module 12 of the first pixel circuit 101 is configured to be turned on when the received first driving signal Cref and the first scanning signal S1 are both at the enable level.

Illustratively, taking the arrangement of the low-frequency display area AA2 and the high-frequency display area AA1 in the column direction Y, the first pixel circuits 101 are arranged at least one row of the second pixel circuits 102 at intervals as an example, fig. 9 exemplarily shows that both the first pixel circuits 101 and the second pixel circuits 102 are included in the high-frequency display area AA1 and the low-frequency display area 102.

With continued reference to fig. 9, when the display panel 100 implements the frequency division display, the conduction period of the reset module 12 of the pixel circuit 10 in the low-frequency display area AA2 is smaller than the conduction period of the reset module 12 of the pixel circuit 10 in the high-frequency display area AA1, so that the reset module 12 of the pixel circuit 10 may further include a first control terminal C1 and a second control terminal C2, and the pixel circuit 10 in the high-frequency display area AA1 may be set to be the second pixel circuit 102, and referring to fig. 11, the first control terminal C1 and the second control terminal C2 of the reset module 12 of the second pixel circuit 102 may be electrically connected to the same signal terminal, that is, all electrically connected to the signal output terminal of the first shift register unit 31, so as to receive the first scan signal S1 transmitted by the first shift register unit 31, at this time, the first scan signal S1 is kept at the enabling level in the reset stage of the second pixel circuit 102, so as to control the reset module 12 to be turned on, and ensure normal operation of the second pixel circuit 102. For the pixel circuit 10 of the low frequency display area AA2, referring to fig. 10, the first control terminal C1 of the reset module 12 of the first pixel circuit 101 is electrically connected to the signal output terminal of the first shift register unit 31 to receive the first scan signal S1 transmitted by the first shift register unit 31, and the second control terminal C2 is electrically connected to the second drive signal line 40, so that the first pixel circuit 101 is turned on only when the first drive signal Cref and the first scan signal S1 are both at the enable level for data writing frames, and the normal operation of the first pixel circuit 101 is ensured, while during the reset phase of the frame, the reset module 12 of the pixel circuit 10 is controlled to be turned off by the second drive signal Cref transmitted by the second drive signal line 40 as the disable level for avoiding resetting the potential of the second node N2.

In this way, by setting at least a portion of the pixel circuits 10 in the low-frequency display area AA2 as the first pixel circuit 101, the second driving signal line 40 transmits the second driving signal Cref to the reset module 12 of the first pixel circuit 101, so as to control the on period of the reset module 12 in the first pixel circuit 101, so that the on period of the reset module 12 of the pixel circuits 10 in the low-frequency display area AA2 is smaller than the on period of the reset module 12 of the pixel circuits 10 in the high-frequency display area AA1, thereby enabling the display panel 100 to realize the frequency division display along the column direction Y.

It should be noted that, the pixel circuits 10 in the low-frequency display area AA2 may be the first pixel circuits 101, or a part of the pixel circuits 10 may be the first pixel circuits 101, and a part of the pixel circuits 10 may be the second pixel circuits 102, which may be set according to actual requirements, so that, when the second pixel circuits 102 in the low-frequency display area AA2 operate in the reset phase, the reset module 12 may be controlled to be turned off by adjusting the first scan signal S1 output by the first shift register unit 31 electrically connected to the reset module 12 of the second pixel circuits 102 to be a non-enable level, so as to ensure that the potential of the second node N2 is prevented from being reset. Similarly, the pixel circuits 10 in the high-frequency display area AA1 may be the second pixel circuits 102, or may be part of the pixel circuits 10 are the first pixel circuits 101, and part of the pixel circuits 10 are the second pixel circuits 102, so, since the pixel circuits 10 in the high-frequency display area AA1 have a complete driving period in a frame of display picture, the second driving signal Cref transmitted by the second driving signal line 40 electrically connected to the reset module 12 of the first pixel circuit 101 in the high-frequency display area AA1 can be controlled to be always kept at the enable level, so as to ensure that the reset module 12 of the first pixel circuit 101 in the high-frequency display area AA1 can be turned on under the control of the enable level of the first scanning signal S1 in the reset phase.

Optionally, with continued reference to fig. 10, the reset module 12 includes a first reset transistor T4 and a second reset transistor T5; in the same reset module 12, a first end of the first reset transistor T4 is electrically connected to the reset signal end, a second end of the first reset transistor T4 is electrically connected to a first end of the second reset transistor T5, and a second end of the second reset transistor T5 is electrically connected to the first node N1; one of the first control terminal C1 and the second control terminal C2 of the reset module 12 is electrically connected to the gate of the first reset transistor T4, and the other is electrically connected to the gate of the second reset transistor T5.

Specifically, the first reset transistor T4 and the second reset transistor T5 may be P-channel transistors, or N-channel transistors, and the types of the first reset transistor T4 and the second reset transistor T5 may be the same or different, which is not particularly limited, and may be set according to actual requirements.

It will be appreciated that the level of the enable and disable levels is dependent on the type of transistor it controls, for example when the transistor is a P-channel transistor, the enable level is a low signal and the disable level is a high signal; and when the transistor is an N-channel transistor, the enabling level is a high level signal, and the disabling level is a low level signal. In the embodiment of the invention, the high and low of the enabling level and the non-enabling level can be limited according to actual needs. For convenience of description, embodiments of the present invention will be described by taking a signal with an enable level being a low level and a signal with a disable level being a high level as an example, unless otherwise specified.

Optionally, fig. 12 is a driving timing chart of a display panel according to another embodiment of the present invention, and referring to fig. 9 and 12, a frame time of the low frequency display area AA2 includes a data writing frame t1 and at least one holding frame t2; the data writing frame t1 includes a first non-light-emitting period t10 and a light-emitting period t20; the first non-light emitting stage t10 includes a reset stage t11 and a data writing stage t12; the hold frame t2 includes a second non-light-emitting period t30 and a light-emitting period t20; the second non-light-emitting stage t30 is not provided with a reset stage and a data writing stage; at least part of the holding frame t2 is the first holding frame t201.

In the data writing frame t1, the first shift register units 31 of each stage sequentially output the enable level of the first scan signal S1 for controlling the reset module 12 to be turned on; the second driving signal line 40 transmits an enable level of a second driving signal Cref controlling the reset module 12 to be turned on; the first driving signal line 20 transmits an enable level of the first driving signals D (i.e., D1 to Dm) turned on by the control node control module 12;

in the first holding frame t201, the second driving signal line 40 electrically connected to the reset module 12 of the first pixel circuit 101 in the low frequency display area AA2 transmits the non-enable level of the second driving signal Cref, the first driving signal line 20 electrically connected to the node control module 13 of the second pixel circuit 102 in the high frequency display area AA1 transmits the enable level of the first driving signal D, the first driving signal line 20 electrically connected to the node control module 13 of the pixel circuit 10 in the low frequency display area AA2 transmits the non-enable level of the first driving signal D, and the first shift register unit 31 electrically connected to at least the reset module 12 of the second pixel circuit 102 in the high frequency display area AA1 sequentially outputs the enable level of the first scanning signal S1 controlling the on of the reset module 12.

For example, taking an example that the kth line pixel circuit 10 is located in the high frequency display area AA1, and the kth line pixel circuit 10 is the second pixel circuit 102, the k+1th line pixel circuit 10 is located in the low frequency display area AA2, and the k+1th line pixel circuit 10 is the first pixel circuit 101, k is an integer greater than or equal to 1, fig. 12 exemplarily shows a driving timing chart of the kth line second pixel circuit 102 and the k+1th line first pixel circuit 101.

With continued reference to fig. 9 to 12, in the data writing frame t1, each pixel circuit 10 in the display area AA has a complete driving period, i.e. includes a reset phase t11, a data writing phase t12 and a light emitting phase t20, and the specific operation is not described in detail herein, and reference is made to the foregoing description. In addition, since the first pixel circuit 101 located in the low frequency display area AA2 is further electrically connected to the second driving signal line 40, the second driving signal Cref transmitted by the second driving signal line 40 and controlling the on of the reset module 12 is set to the enable level (i.e. the low level signal), so as to ensure that the first pixel circuit 101 can be turned on in the reset stage t11, and further ensure the normal operation of the first pixel circuit 101.

In the first holding frame t201, each of the first shift register units 31 electrically connected to the reset module 12 of the kth row of the second pixel circuits 102 sequentially outputs the enable level (i.e., the low level signal) of the first scan signal S1, and meanwhile, the first driving signals D (i.e., the D1 to Dm) transmitted by the first driving signal line 20 electrically connected to the node control module 13 of the kth row of the second pixel circuits 102 are the enable level (i.e., the low level signal), so as to ensure that the second pixel circuits 102 located in the high frequency display area AA1 still perform image display at a higher refresh frequency. The low-frequency display area AA2 needs to maintain the current display screen unchanged, and the potential of the second node N2 of the k+1th row of the first pixel circuits 101 in the low-frequency display area AA2 needs to be kept unchanged, that is, the reset module 12 of the first pixel circuits 101 needs to be controlled to be disconnected in the reset phase t11 and the holding phase t12, at this time, the second driving signal Cref transmitted by the second driving signal line 40 electrically connected to the reset module 12 of the first pixel circuits 101 of the low-frequency display area AA2D is at a non-enabling level (i.e., a high level signal), the reset module 12 can be controlled to be disconnected, and the non-enabling level (i.e., a high level signal) of the first driving signal D (i.e., D1-Dm) transmitted by the first driving signal line 20 electrically connected to the node control module 13 of the pixel circuits 10 in the low-frequency display area AA2 needs to be ensured that the potential of the second node N2 of the first pixel circuits 101 is kept unchanged in the reset phase t11 and the data writing phase t12, so that the display screen of the low-frequency display area AA2 is maintained unchanged. In this way, the high-frequency display area AA1 and the low-frequency display area AA2 of the display panel 100 can realize frequency division display along the row direction X, reducing power consumption.

Optionally, in the first holding frame t201, each of the first shift register units 31 electrically connected to the reset module 12 of each of the pixel circuits 10 in the low frequency display area AA2 sequentially outputs the enable level of the first scan signal S1, and the enable level of the first scan signal S1 output by each of the first shift register units 31 of the first shift register 30 is sequentially shifted; alternatively, in the first holding frame t201, each of the first shift register units 31 electrically connected to the reset module 12 of each of the pixel circuits 10 in the low frequency display area AA2 outputs the disable level of the first scan signal S1.

It can be understood that, in the first holding frame t201, when the second driving signal Cref transmitted by the second driving signal line 40 by the reset module 12 of the first pixel circuit 10 in the low-frequency display area AA2 is at the non-enabled level, the reset module 12 of the first pixel circuit 10 can be controlled to be turned off, and at this time, the first scan signal S1 transmitted by the first shift register unit 31 electrically connected to the reset module 12 of each pixel circuit 10 in the low-frequency display area AA2 can be at the non-enabled level or the enabled level, which is not limited herein, and can be set according to the actual requirement, whether the first scan signal S1 is at the enabled level or not, and the reset module 12 of the first pixel circuit 101 is in the turned-off state.

With continued reference to fig. 12, fig. 2 shows that each of the first shift register units 31 electrically connected to the reset module 12 of each of the pixel circuits 10 in the low frequency display area AA2 sequentially outputs the enable level (i.e., the low level signal) of the first scan signal S1, and the enable level of the first scan signal S1 outputted by each of the first shift register units 31 of the first shift register 30 is sequentially shifted.

Fig. 13 is a driving timing chart of a display panel according to another embodiment of the present invention, and as shown in fig. 13, unlike fig. 12, fig. 13 shows that in a first holding frame t201, each of the first shift register units 31 electrically connected to the reset module 12 of each of the pixel circuits 10 in the low frequency display area AA2 outputs a disable level (i.e., a high level signal) of the first scan signal S1.

In addition, since the non-enable level (i.e., the high level signal) of the first driving signal D (i.e., D1 to Dm) transmitted by the first driving signal line 20 electrically connected to the node control module 13 of the pixel circuit 10 in the low frequency display area AA2 is at the first holding frame t201, the third scan signal S3 may output the enable level (i.e., the low level signal) or the non-enable level (i.e., the high level signal), which is not particularly limited herein, and may be set according to actual requirements. The third scan signal S3 in fig. 12 and 13 is only exemplarily shown, but is not limited thereto.

Optionally, as shown with continued reference to fig. 2, 10 and 11, the pixel circuit 10 further includes a data writing module 15 and a threshold compensation module 16; the data writing module 15 is electrically connected with the first pole of the driving transistor T1, and the threshold compensating module 16 is electrically connected between the second pole of the driving transistor T1 and the second node N2; the data writing module 15 is configured to write a data voltage to the first node N1 during a data writing phase; the threshold compensation module 16 is used for compensating the threshold voltage of the driving transistor T1 to the first node N1 during the data writing phase.

Specifically, the complete driving period of the pixel circuit 10 includes a reset phase, a data writing phase, and a light emitting phase. In the reset phase, the reset module 12 and the node control module 13 are in a conducting state, and a reset signal is sequentially written into the first node N1 and the second node N2 through the conducting reset module 12 and the node control module 13. In the data writing stage, the reset module 12 is turned off, the node control module 13 is turned on continuously, at this time, the reset signal is not written into the first node N1 any more, meanwhile, the data writing module 15 and the threshold compensation module 16 are turned on, the data signal provided by the data writing module 15 is written into the first node N1 through the driving transistor T1 and the threshold compensation module 16 in sequence, and is transmitted to the second node N2 through the turned-on node control module 13, so that the potential written into the second node N1 is the data signal after the threshold compensation. In the light emitting stage, the data writing module 15 and the threshold compensation module 16 may be turned off, and the driving transistor T1 generates a driving current under the action of the first fixed level signal PVDD and the potential of the second node N2, and supplies the driving current to the light emitting element 14, so as to drive the light emitting element 14 to emit light, thereby implementing the image display of the display panel 100.

Fig. 14 is a schematic structural diagram of another first pixel circuit provided by the present invention, fig. 15 is a schematic structural diagram of another second pixel circuit provided by the present invention, as shown in fig. 14 and 15, a node control module 13 in the first pixel circuit 101 and the second pixel circuit 102 includes a node control transistor T6, a data writing module 15 includes a data writing transistor T7, a threshold compensation module 16 includes a threshold compensation transistor T8, a first end of the node control transistor T6 is electrically connected to a first node N1, a second end of the node control transistor T6 is electrically connected to a second node N1, a gate of the node control transistor T6 is electrically connected to a first driving signal line 20, and the first driving signal D transmitted by the first driving signal line 20 is turned on or off. The first end of the Data writing transistor T7 is electrically connected to the Data writing end, the Data writing end is used for providing a Data writing signal Data, the second end of the Data writing transistor T7 is electrically connected to the first pole of the driving transistor T1, the gate of the Data writing transistor T7 is electrically connected to the third scanning signal end, and the Data writing transistor T7 is used for being turned on or off according to a third scanning signal S3 transmitted by the third scanning signal end. The first end of the threshold compensation transistor T8 is electrically connected to the second pole of the driving transistor T1, the second end of the threshold compensation transistor T8 is electrically connected to the first node N1, and the gate of the threshold compensation transistor is electrically connected to the third scan signal terminal, so as to be turned on or off according to the third scan signal S3 transmitted by the third scan signal terminal. The threshold compensation transistor T8 may be a double gate transistor, but is not limited thereto, and may be set according to actual requirements, and fig. 14 and 15 are only exemplary.

Further, with continued reference to fig. 14 and 15, the first pixel circuit 101 and the second pixel circuit 102 may further include a storage capacitor C and an anode reset mode 18. The first electrode plate of the storage capacitor C is electrically connected to the first electrode of the driving transistor T1, and the second electrode plate of the storage capacitor C is electrically connected to the second node N2, so as to apply the potential written into the second node N2. The anode reset module 18 includes an anode reset transistor T9, where a first end of the anode reset transistor T9 is electrically connected to an anode reset signal end, a second end of the anode reset transistor T9 is electrically connected to an anode of the light emitting element 14, and a gate of the anode reset transistor T9 is electrically connected to a fourth scan signal end, so as to turn on or off according to a fourth scan signal S4 provided by the fourth scan signal end, and write an anode reset signal Vref1 provided by the anode reset signal end into the anode of the light emitting element 14 when the anode reset transistor T9 is turned on, so as to avoid an influence of a voltage signal written in a previous frame, and improve a display effect of the display panel 100.

Optionally, fig. 16 is a schematic structural diagram of a display panel according to an embodiment of the present invention, fig. 17 is a schematic structural diagram of a first pixel circuit according to an embodiment of the present invention, fig. 18 is a schematic structural diagram of a second pixel circuit according to an embodiment of the present invention, and in combination with the first shift register units 31 of each stage shown in fig. 17 and 18, a signal output end of the first shift register unit 31 of the i-th stage is electrically connected to the threshold compensation module 16 of the i-th row pixel circuit 10 and a first control end C1 of the reset module 12 of the i+1th row pixel circuit 10 respectively; wherein i is a positive integer; the first scan signal S1 is also used to control the threshold compensation module 16 to be turned on or off.

Specifically, in the data writing stage, the threshold compensation module 16 of the ith row of pixel circuits 10 can output the enabling level of the first scanning signal S1 according to the signal output end of the ith stage of first shift register unit 31 to be turned on, meanwhile, because the enabling level of the first scanning signal S1 output by the signal output end of the ith stage of first shift register unit 31 is also transmitted to the first control end C1 of the reset module 12 of the ith+1 row of pixel circuits 10, when the ith+1 row of pixel circuits 10 are the second pixel circuits 102, the reset module 12 of the ith+1 row of second pixel circuits 102 can be enabled to be turned on, so that the reset module 12 of the ith+1 row of second pixel circuits 102 can write the reset signal Vref into the first node N1. When the i+1 row of the pixel circuits 10 is the second pixel circuit 102, if the second driving signal Cref transmitted by the second driving signal line 40 is the enabling level, the reset module 12 of the i+1 row of the second pixel circuit 102 is enabled to conduct under the simultaneous effect of the enabling level of the second driving signal Cref and the enabling level of the first scanning signal S1 outputted by the i-th stage first shift register unit 31, so that the reset module 12 of the i+1 row of the second pixel circuit 102 can write the reset signal Vref into the first node N1. In this way, by arranging the first shift register units 31 at each stage, the signal output end of the first shift register unit 31 at the i-th stage is electrically connected to the threshold compensation module 16 of the i-th row of pixel circuits 10 and the first control end C1 of the reset module 12 of the i+1-th row of pixel circuits 10, respectively, so that the threshold compensation module 16 of the i-th row of pixel circuits 10 and the first control end C1 of the reset module 12 of the i+1-th row of pixel circuits 10 are driven by the same scanning signal, which is beneficial to simplifying the circuit layout.

Taking the driving timing of the ith row of the second pixel circuits 102 and the (i+1) th row of the second pixel circuits 102 in the data writing frame t1 as an example, fig. 19 is a driving timing diagram of a second pixel circuit according to an embodiment of the present invention, and referring to fig. 16, 18 and 19, the data writing frame t1 includes a first non-light-emitting stage t10 and a light-emitting stage t20, and the first non-light-emitting stage t10 includes a reset stage t11 and a data writing stage t12.

When the ith row of second pixel circuits 102 operates in the Data writing stage t12, the first scan signal S1 (i) output by the signal output end of the ith stage of shift register unit 31 is an enable level (i.e., a low level signal), the threshold compensation module 16 is controlled to be turned on, and the enable level (i.e., a low level signal) of the first drive signal D (i.e., D1 (i) -Dm (i)) transmitted by the first drive signal line 20 controls the node control module 13 of the ith row of second pixel circuits 102 to be turned on, so that the Data signal Data provided by the Data writing module 15 can be written into the second node of the ith row of second pixel circuits 102. Meanwhile, the first control terminal C1 of the reset module 12 of the i+1 row second pixel circuit 102 electrically connected to the signal output terminal of the i-th stage shift register unit 31 receives the enable level (i.e., the low level signal) of the first scan signal S1 (i), so that the enable level (i.e., the low level signal) of the first scan signal S1 (i) can control the reset module 12 of the i+1 row second pixel circuit 102 to be turned on, and since the first driving signals D (i) to Dm (i)) transmitted by the first driving signal line 20 are the enable level (i.e., the low level signal), the node control module 13 of the i+1 row second pixel circuit 102 can be simultaneously controlled to be turned on, so that the reset signal Vref provided by the reset module 16 of the i+1 row second pixel circuit 102 can simultaneously reset the potential of the second node NN2 of the i+1 row second pixel circuit 102 when the i row second pixel circuit 102 is operated in the data writing stage t12.

Alternatively, fig. 20 is a driving timing chart of a display panel according to another embodiment of the present invention, referring to fig. 16 and 20 in combination, when the i-th row pixel circuit 10 is located in the high frequency display area AA1 and the i+1th row pixel circuit 10 is located in the low frequency display area AA2, the i+1th row pixel circuit AA2 is the first pixel circuit 101; the other pixel circuits 10 except the first pixel circuit 101 in the low frequency display area AA2 are the second pixel circuits 102. At the first holding frame t201, the start time of the non-enable level of the second driving signal Cref is located before the start time of the enable level of the first scanning signal S1 output by the i-th stage first shift register unit 31 and is located after the end time of the enable level of the first scanning signal S1 output by the i-1-th stage first shift register unit 31; wherein i is a positive integer greater than or equal to 2.

By way of example, taking the high-frequency display area AA1 and the low-frequency display area AA2 arranged along the column direction Y as an example, with continued reference to fig. 16, 17, 18 and 20, the other pixel circuits 10 in the low-frequency display area AA2 except for the first pixel circuit 101 are all the second pixel circuits 102, and the pixel circuits 10 in the high-frequency display area AA1 are all the second pixel circuits 102. In the first holding frame t201, the ith row of second pixel circuits 102 electrically connected to the ith first shift register unit 31 are located in the high-frequency display area AA1 and still have a complete driving period, and when the ith row of second pixel circuits 102 enter the reset stage t11, the enable level (i.e., the low level signal) of the first scan signal S1 (i.e., S1 (i-1)) output by the ith-1 stage first shift register unit 31 controls the reset module 12 of the ith row of second pixel circuits 102 to be turned on, so as to ensure that the ith row of second pixel circuits 102 can reset the second node N2 in the reset stage t 11. When the ith row of second pixel circuits 102 enters the data writing stage t12, the enable level (i.e., the low level signal) of the first scan signal S1 (i.e., S1 (i)) output by the ith stage of first shift register unit 31 is turned on while controlling the threshold compensation module 16 of the ith row of second pixel circuits 102, and the enable level (i.e., the low level signal) of the first scan signal S1 (i.e., S1 (i)) is transmitted to the first control terminal C1 of the reset module 12 of the ith+1 row of first pixel circuits 101, since the ith+1 row of first pixel circuits 101 is located in the low frequency display area AA2, the reset module 12 of the ith+1 row of first pixel circuits 101 can be still turned off by controlling the second drive signal Cref transmitted by the second drive signal line 40 electrically connected to the reset module 12 of the ith+1 row of first pixel circuits 101 to the disable level (i.e., the high level signal), so that the reset module 12 of the ith+1 row of first pixel circuits 101 is prevented from resetting the second node N2 of the ith+1 row of first pixel circuits 101, and the second node n+1 row of first pixel circuits is prevented from being kept unchanged from being in the low frequency display area AA 2.

Further, the first pixel circuit 101 may be further disposed in the high-frequency display area AA1, where the setting may be performed according to practical requirements, for example, the i-th row pixel circuit 10 is set as the first pixel circuit 101, so that, by setting the starting time of the second driving signal Cref transmitted by the second driving signal line 40 electrically connected to the reset module 12 of the i+1th row first pixel circuit 101 in the high-frequency display area to be the non-enabling level (i.e. the high-level signal) before the starting time of the enabling level (i.e. the low-level signal) of the first scanning signal S1 output by the i-th first shift register unit 31 and after the ending time of the enabling level of the first scanning signal S1 output by the i-1 th first shift register unit 31, it is ensured that the potential of the second node N2 of the i+1th row first pixel circuit 101 is not reset, and that the reset module 12 of the i-th row pixel circuit 10 can be normal in the reset stage t11, so that the second node N2 of the i-th row pixel circuit 10 can be reset to be well, and the high-frequency display area AA can be enlarged, thereby realizing good frequency division effect of the display area AA 2.

Further, with continued reference to fig. 17, 18 and 20, in the first holding frame t201, since the i+1th row first pixel circuit 101 does not include the data writing stage t12 in the second non-light emitting stage t30, it is necessary to make the first scan signal S1 (i.e., S1 (i+1)) output from the signal output terminal of the i+1th stage first shift register unit 31 electrically connected to the threshold compensation module 16 of the i+1th row first pixel circuit 101 be a non-enable level (i.e., a high level signal) to ensure that the potential of the second node N2 remains unchanged, thereby ensuring that the display screen of the low frequency display area AA2 remains unchanged.

Optionally, fig. 21 is a schematic structural diagram of a further display panel provided in the embodiment of the present invention, fig. 22 is a schematic structural diagram of a further first pixel circuit provided in the embodiment of the present invention, fig. 23 is a schematic structural diagram of a further second pixel circuit provided in the embodiment of the present invention, and, referring to fig. 21 to 23, the non-display area NA further includes a second shift register 50, where the second shift register 50 includes a plurality of second shift register units 51 disposed in cascade connection, and enable levels of the second scan signals S2 output by signal output ends of the second shift register units 51 at each stage are sequentially shifted. The signal output end of each stage of the second shift register unit 51 is electrically connected with the data writing module 15 of at least part of the pixel circuits 10 located in the same row; wherein, at least in the data writing frame t1, in the same pixel circuit 10, the enabling level time of the first scan signal S1 overlaps with the enabling level time of the second scan signal S2.

Specifically, the first shift register 30 and the second shift register 50 may be located on the same side of the display area AA or on two sides of the display area AA, which is not particularly limited in this embodiment, and may be set according to actual requirements, and fig. 21 is only exemplary and not limited thereto.

Taking the ith row of pixel circuits 10 as the second pixel circuits 102 and being located in the low-frequency display area AA2 as an example, fig. 24 is a driving timing diagram of another second pixel circuit according to an embodiment of the present invention, and referring to fig. 21, 23 and 24, a frame time of the low-frequency display area AA2 includes a data writing frame t1 and at least one holding frame t2; the data writing frame t1 includes a first non-light-emitting period t10 and a light-emitting period t20; the first non-light emitting stage t10 includes a reset stage t11 and a data writing stage t12; the hold frame t2 includes a second non-light-emitting period t30 and a light-emitting period t20; the second non-light-emitting stage t30 is not provided with a reset stage and a data writing stage; at least part of the holding frame t2 is the first holding frame t201.

In the data writing frame T1, the ith row of second pixel circuits 102 has a complete driving period, where in the data writing stage T12, the first scan signal S1 (i)) output from the signal output end of the ith stage of first shift register unit 31 is an enable level (i.e., a low level signal) to control the threshold compensation module 16 to be turned on, and the second scan signal S2 output from the signal output end of the ith stage of second shift register unit 51 is also an enable level (i.e., a low level signal) to control the data writing module 15 to be turned on, at this time, the first driving signal D transmitted by the first driving signal line 20 is also an enable level (i.e., a low level signal), so that the data signal can be written to the second node N2 sequentially through the turned on data writing module 15, the driving transistor T1, the threshold compensation module 16 and the node control module 13, thereby ensuring the normal light emitting display of the second pixel circuits 102 in the light emitting stage T20. In the first holding frame t201, since the first driving signal D output by the first driving signal line 20 is at a non-enabling level (i.e., a high level signal), the node control module 13 of the ith row of second pixel circuits 102 is turned off, and the ith stage of first scanning signal S1 is at a non-enabling level (i.e., a high level signal), so that the threshold compensation module 16 of the ith row of second pixel circuits 102 is turned off, the ii row of second pixel circuits 102 does not have a reset phase and a data writing phase in the non-light-emitting phase t30, that is, the potential of the second node N2 is not reset and written with a data signal, so that the potential of the second node N2 is ensured to be unchanged, and the display screen of the low frequency display area AA2 is maintained unchanged.

With continued reference to fig. 24, since the enabling level of the second scan signal S2 output by the signal output end of the second shift register unit 51 of each stage is sequentially shifted, so that in the first holding frame T201, the i-th row second scan signal S2 is still at the enabling level (i.e., the low level signal) in the Data writing stage T12, the Data writing module 15 of the i-th row second pixel circuit 102 can be controlled to be turned on in this stage, so that the Data signal Data is written into the first pole of the driving transistor T1, thus, the potential of the first pole of the driving transistor T1 can be reset at high frequency, the voltage difference of the first poles of the driving transistor T1 in the first non-light-emitting stage T10 and the second non-light-emitting stage T30 can be reduced, the bias voltages of the driving transistor T1 in the two periods tend to be consistent, so that not only the problem of the trailing shadow when the picture is switched under low frequency driving is improved, but also the difference of the luminance rising at the initial stage in the Data writing frame T1 and the holding frame T2 is reduced, and the flicker phenomenon of the picture under low frequency and low-level display is effectively improved.

Optionally, with continued reference to fig. 22 and 23, the signal output end of each stage of the second shift register unit 51 may be further electrically connected to the anode reset module 18 of at least part of the pixel circuits 10 located in the same row, or the signal output end of the ith stage of the second shift register unit 51 may be electrically connected to the data writing module of the ith row of the pixel circuits 10 and to the anode reset module 18 of the (i+1) th row of the pixel circuits 10, so that the second scan signal S2 output by the signal output end of each stage of the second shift register unit 51 may further control the anode reset module 18 to be turned on or off, and control the anode reset module 18 to be turned on when the second scan signal S2 is at an enable level (i.e., a low level signal), so that the anode reset signal Vref1 may be written to the anode of the light emitting element 14, thereby avoiding the influence of the voltage signal written in the previous frame and improving the display effect of the display panel 100.

Optionally, fig. 25 is a schematic diagram of a shift register according to an embodiment of the present invention, as shown in fig. 25, a first shift register unit 31 in a first shift register 30 and a second shift register unit 51 in a second shift register 50 are the same shift register unit 60; the shift register unit 60 includes a first signal output terminal OUT1 and a second signal output terminal OUT2, the first signal output terminal OUT1 being a signal output terminal of the first shift register unit 31, and the second signal output terminal OUT2 being a signal output terminal of the second shift register unit 50.

For example, fig. 25 shows a schematic configuration of the first to fourth stage shift register units 60 to 60 (i.e., ASG1, ASG2, ASG3, and ASG 4), wherein the input terminal IN of the first stage shift register unit 60 is electrically connected to the start pulse signal line Stv that transmits the start pulse signal Stv. The first signal output terminal OUT1 of the shift register unit 60 is a signal output terminal of the first shift register unit 31, the second signal output terminal OUT2 is a signal output terminal of the second shift register unit 50, such that the first signal output terminals OUT1 of the first to fourth stage shift register units 60 to 60 each output the first scan signal S1 (i.e., S11, S12, S13 and S14), and the second signal output terminals OUT2 of the first to fourth stage shift register units 60 to 60 each output the second scan signal S2 (i.e., S21, S22, S23 and S24). In this way, by setting the first shift register unit 31 in the first shift register 30 and the second shift register unit 51 in the second shift register 50 to be the same shift register unit 60, the number of shift registers can be reduced, which is beneficial to simplifying the circuit structure and further beneficial to the design of the narrow frame of the display panel 100.

It should be noted that, since the enable level of the second scan signal S2 output from the signal output terminal (i.e., the second output terminal OUT 2) of each stage of the second shift register unit 51 is sequentially shifted, the signal input terminal IN of each stage of the shift register units from the second stage of the shift register unit 60 to the fourth stage of the shift register unit 60 is electrically connected to the second signal output terminal OUT2 of the shift register unit of the previous stage thereof, so as to ensure the normal operation of the shift register.

Optionally, fig. 26 is a schematic structural diagram of a shift register unit according to an embodiment of the present invention, as shown IN fig. 26, the shift register unit 60 includes a first clock terminal SCK, a second clock terminal SCKB, a third clock terminal RCK, a first level terminal VGL, a second level terminal VGH, a signal input terminal IN, a first signal output terminal OUT1, a second signal output terminal OUT2, a first control module 61, a second control module 62, a mutual control module 63, a first output module 64, and a second output module 65.

The same shift register unit 60:

the first control module 61, the first output module 64 and the second output module 65 are electrically connected to the third node N3; the first control module 61 is further electrically connected to the first clock terminal SCK and the signal input terminal IN, respectively; the first control module 61 is configured to control the potential of the third node N3 IN response to the first clock signal Sck of the first clock terminal SCK and the input signal Vin of the signal input terminal IN.

The second control module 62 is electrically connected to the fourth node N4 with the first output module OUT1 and the second output module OU 2; the second control module 62 is further electrically connected to the first clock terminal SCK and the first level terminal VGL, respectively; the second control module 62 is configured to control the potential of the fourth node N4 in response to the first clock signal Sck of the first clock terminal SCK and the first level signal VGL of the first level terminal VGL.

The mutual control module 63 is electrically connected with the third node N3, the fourth node N4, the first clock terminal SCK, the second clock terminal SCKB and the second level terminal VGH, respectively; the mutual control module 63 is configured to control the potential of the fourth node N4 in response to the potentials of the first clock signal Sck of the first clock terminal SCK and the third node N3, and control the potential of the third node N3 in response to the second clock signal SCKB of the second clock terminal SCKB, the second level signal VGH of the second level terminal VGH and the potential of the fourth node N4.

The first output module 64 is also electrically connected to the third clock terminal RCK, the second level terminal VGH, and the first signal output terminal OUT1, respectively; the first output module 64 is configured to control a time when the first signal output terminal OUT1 outputs the third clock signal Rck of the third clock terminal RCK under the control of the potential of the third node N3, and to control a time when the first signal output terminal OUT1 outputs the second level signal VGH of the second level terminal VGH under the control of the potential of the fourth node N4.

The second output module 65 is further electrically connected to the second clock terminal SCKB, the second level terminal VGH, and the second signal output terminal OUT2, respectively; the second output module 65 is configured to control a time when the second signal output terminal OUT2 outputs the second clock signal SCKB of the second clock terminal SCKB under the control of the potential of the third node N3, and to control a time when the second signal output terminal OUT2 outputs the second level signal VGH of the second level terminal VGH under the control of the potential of the fourth node N4.

It should be understood that the electrical connection mentioned in this embodiment may be a direct connection, for example, the first control module 61 is electrically connected to the first clock terminal SCK, or the first control module 61 may be directly electrically connected to the first clock terminal SCK; alternatively, the electrical connection may be an intermediate connection with another element, for example, the first control module 61 may be electrically connected to the first clock terminal SCK, and the first control module 61 may be electrically connected to the first clock terminal SCK through a resistor, a capacitor, an inductor, a switch, or the like. On the premise that the core invention point of the embodiment of the present invention can be realized, the definition of the electrical connection in the embodiment of the present invention is not particularly limited.

For example, with continued reference to fig. 26, the first control module 61 includes a first input transistor T1 and a first voltage stabilizing transistor T2, the gate of the first input transistor T1 is electrically connected to the first clock terminal SCK, the first pole of the first input transistor T1 is electrically connected to the signal input terminal IN, and the second pole of the first input transistor T1 is electrically connected to the third node N3. IN this way, the first clock signal Sck of the first clock terminal SCK can control the first input transistor T1 to be turned on or off, and transmit the input signal Vin of the signal input terminal IN to the third node N3 when the first input transistor T1 is IN the on state. The third node N3 may include a first sub-node N31 and a second sub-node N32, where the gate of the first voltage stabilizing transistor T2 is electrically connected to the first level end VGL, the first pole of the first voltage stabilizing transistor T2 is electrically connected to the first sub-node N31, the second pole of the first voltage stabilizing transistor T2 is electrically connected to the second sub-node N32, and the first voltage stabilizing transistor T2 is in a conducting state under the control of the first level signal VGL of the first level end VGL, so that the potential of the original third node N3 can be shared between the first sub-node N31 and the second sub-node N32, so as to avoid the third node N3 from changing to affect the operation of the shift register circuit 10. In this way, by providing the first voltage stabilizing transistor T2, when the potential of one of the first sub-node N31 and the second sub-node N32 is abnormal, a device electrically connected to the other node can be protected.

The second control module 62 may include a third transistor T3, a gate of the third transistor T3 is electrically connected to the first clock terminal SCK, a first pole of the third transistor T3 is electrically connected to the first level terminal VGL, and a second pole of the third transistor T3 is electrically connected to the fourth node N4. In this way, the first clock signal Sck of the first clock terminal SCK can control the third transistor T3 to be turned on or off, and transmit the first level signal VGL of the first level terminal VGL to the fourth node N4 when the third transistor T3 is in the on state.

The intermodulation module 63 may include a fourth transistor T4, a fifth transistor T5, and a sixth transistor T6, where a gate of the fourth transistor T4 is electrically connected to the third node N3, a first pole of the fourth transistor T4 is electrically connected to the first clock terminal SCK, and a second pole of the fourth transistor T4 is electrically connected to the fourth node N4, so that a potential of the third node N3 may control the third transistor T3 to be turned on or off, and transmit the first clock signal Sck of the first clock terminal SCK to the fourth node N4 when the fourth transistor T4 is in an on state. The gate of the fifth transistor T5 is electrically connected to the fourth node N4, the first pole of the fifth transistor T5 is electrically connected to the second level terminal VGH, the second pole of the fifth transistor T5 is electrically connected to the first pole of the sixth transistor T6, the gate of the sixth transistor T6 is electrically connected to the second clock terminal SCKB, the second pole of the sixth transistor T6 is electrically connected to the third node N3, so that the potential of the fourth node N4 can control the fifth transistor T5 to be turned on or off, the second clock signal SCKB of the second clock terminal SCKB can control the sixth transistor T6 to be turned on or off, and the second level signal VGH of the second level terminal VGH is transmitted to the third node N3 when both the fifth transistor T5 and the sixth transistor T6 are in the on state.

The first output module 64 includes a first output transistor T11 and a second output transistor T12; the gate of the first output transistor T11 is electrically connected to the third node N3, the first pole of the first output transistor T11 is electrically connected to the third clock terminal RCK, and the second pole of the first output transistor T11 is electrically connected to the first signal output terminal OUT 1; the gate of the second output transistor T12 is electrically connected to the fourth node N4, the first pole of the second output transistor T12 is electrically connected to the second level terminal VGH, and the second pole of the second output transistor T2 is electrically connected to the first signal output terminal OUT 1.

It is understood that the first output module 64 further includes a first capacitor C1 electrically connected between the first signal output terminal OUT1 and the third node N3, and a second capacitor C2 electrically connected between the second level terminal VGH and the fourth node N4, so as to store the potentials of the third node N3 and the fourth node N4, respectively, and maintain the stability of the potentials of the third node N3 and the fourth node N4.

The second output module 65 includes a third output transistor T21 and a fourth output transistor T22; the gate of the third output transistor T21 is electrically connected to the third node N3, the first pole of the third output transistor T21 is electrically connected to the second clock terminal SCKB, and the second pole of the third output transistor T21 is electrically connected to the second signal output terminal OUT 2; the gate of the fourth output transistor T22 is electrically connected to the fourth node N4, the first pole of the fourth output transistor T22 is electrically connected to the second level terminal VGH, and the second pole of the fourth output transistor T22 is electrically connected to the second signal output terminal OUT 2.

It can be appreciated that the second output module 65 further includes a third capacitor C3 electrically connected between the second signal output terminal OUT1 and the third node N3, and a fourth capacitor C4 electrically connected between the second level terminal VGH and the fourth node N4, so as to store the potentials of the third node N3 and the fourth node N4, respectively, and maintain the stability of the potentials of the third node N3 and the fourth node N4.

It should be noted that fig. 26 is a schematic diagram illustrating the structure of the shift register unit 60, where the structures of the first control module 61, the second control module 62, and the mutual control module 63 include, but are not limited to, those illustrated in fig. 26. In addition, the types of transistors in each module may be P-channel transistors or N-channel transistors, which is not particularly limited in this embodiment of the present invention, and fig. 26 is only an exemplary schematic structure diagram showing each transistor as a P-channel transistor, but not limited thereto, and those skilled in the art can design the transistor according to the requirements, which is not particularly limited in this embodiment of the present invention. For convenience of description, the following will take the P-channel transistors as examples of each transistor in the shift register unit 60, and the technical solution of the embodiment of the present invention will be described in an exemplary manner.

Optionally, fig. 27 is a schematic structural diagram of another shift register according to an embodiment of the present invention, as shown IN fig. 27, IN each stage of shift register units 60, a signal input terminal IN of the i+1th stage of shift register unit 60 is electrically connected to a second signal output terminal OUT2 of the i stage of shift register unit 60; the signal input terminal IN of the first stage shift register unit 60 receives the start pulse signal Stv; wherein i is a positive integer. The first clock signal Sck received by the i-th shift register unit 60 is multiplexed into the second clock signal Sckb received by the i+1-th shift register unit 60; and/or, the second clock signal Sckb received by the i-th stage shift register unit 60 is multiplexed to the first clock signal Sck received by the i+1-th stage shift register unit 60.

It will be appreciated that each stage of shift register unit 60 comprises a first clock terminal SCK, a second clock terminal SCKB and a third clock terminal RCK, i.e. each stage of shift register unit 60 requires three clock signals, so that the whole shift register requires a plurality of clock signals, which increases the number of signal terminals in the driving chip providing clock signals to each shift register unit 60 in the shift register, which is disadvantageous for low cost of the driving chip. Meanwhile, in order to ensure that the clock signal transmission processes are not mutually affected, clock signal transmission lines with corresponding intervals and widths are required to be arranged for respectively transmitting different clock signals, so that the frame size of the display panel is increased, and the narrow frame of the display panel is not utilized.

For example, fig. 27 shows a schematic diagram of the structures of the first stage shift register unit 60 to the fourth stage shift register unit 60 (i.e., ASG1, ASG2, ASG3, and ASG 4), the signal input terminal IN of the first stage shift register unit 60 receives the start pulse signal Stv, and the signal input terminal IN of each stage shift register unit from the second stage shift register unit 60 to the fourth stage shift register unit 60 is electrically connected to the second signal output terminal OUT2 of the shift register unit of the previous stage. In the first stage shift register unit 60, the first clock terminal SCK is electrically connected to the first clock signal line L1 for transmitting the first clock signal Sck, the second clock terminal SCKB is electrically connected to the second clock signal line L2 for transmitting the second clock signal SCKB, and the third clock terminal RCK is electrically connected to the fourth clock signal line L4 for transmitting the third clock signal Rck.

Since the time of the enable level of the first clock signal Sck and the time of the enable level of the second clock signal Sckb do not overlap, the first clock signal Sck of the previous stage shift register unit 60 can be multiplexed into the second clock signal Sckb of the next stage shift register unit 60 in the adjacent two stages shift register units 60, and the number of clock signals provided to each stage shift register unit 60 in the shift register can be reduced. Alternatively, the second clock signal Sckb of the shift register unit 60 of the previous stage is multiplexed to the first clock signal Sck of the shift register unit 60 of the next stage, which is also advantageous in reducing the number of clock signals supplied to the shift register units 60 of each stage in the shift register. Fig. 27 exemplarily shows a schematic structural diagram of the first clock signal Sck received by the i-th stage shift register unit 60 multiplexed to the second clock signal Sckb received by the i+1-th stage shift register unit 60, and the second clock signal Sckb received by the i-th stage shift register unit 60 multiplexed to the first clock signal Sck received by the i+1-th stage shift register unit 60, but is not limited thereto. Taking i=1 as an example, the first clock terminal SCK of the first stage shift register unit 60 and the second clock terminal SCKB of the second stage shift register unit 60 are electrically connected to the first clock signal line L1, and the second clock terminal SCKB of the first stage shift register unit 60 and the first clock terminal SCK of the second stage shift register unit 60 are electrically connected to the second clock signal line L2. In this way, the number of signal terminals in the driving chip for supplying the clock signal to each stage of shift register unit 60 in the shift register is advantageously reduced, which is advantageous in low cost of the driving chip. Meanwhile, when the number of clock signals supplied to each stage of the shift register unit 60 in the shift register is reduced, it is advantageous to reduce the number of signal lines for transmitting the clock signals, thereby facilitating a narrow bezel of the display panel 100.

Alternatively, with continued reference to fig. 18, the first clock signal Sck received by the i-th stage shift register unit 60 is multiplexed into the first clock signal Sck received by the i+2-th stage shift register unit 60; the second clock signal Sckb received by the i-th stage shift register unit 60 is multiplexed to the second clock signal Sckb received by the i+2-th stage shift register unit 60.

The first clock signal Sck received by the i-th stage shift register unit 60 is multiplexed into the first clock signal Sck received by the i+2-th stage shift register unit 60, that is, the first clock terminal SCK of the i-th stage shift register unit 60 and the first clock terminal SCK of the i+2-th stage shift register unit 60 are electrically connected to the same clock signal line, so as to reduce the number of clock signal lines for transmitting the first clock signal Sck to the respective stages of shift register units 60. Similarly, the second clock signal Sckb received by the i-th stage shift register unit 60 is multiplexed into the second clock signal Sckb received by the i+2-th stage shift register unit 60, that is, the second clock terminal Sckb of the i-th stage shift register unit 60 and the second clock terminal Sckb of the i+2-th stage shift register unit 60 may be electrically connected to the same clock signal line, so as to reduce the number of clock signal lines for transmitting the second clock signal Sckb to the respective stages of shift register units 60. In this way, the number of signal terminals in the driving chip for supplying the clock signal to each stage of the shift register unit 60 in the shift register can be reduced, the structure is simplified and the cost is reduced, and at the same time, the number of signal lines for transmitting the clock signal can be reduced, thereby facilitating a narrow bezel of the display panel.

Alternatively, with continued reference to fig. 27, the time of the active pulse of the third clock signal Rck received by the i-th stage shift register unit 60 does not overlap with the time of the active pulse of the third clock signal Rck received by the i+1-th stage shift register unit 60.

It will be appreciated that, in general, a high level signal and a low level signal that is continuous therewith form a pulse period, the time of the active pulse of the third clock signal Rck received by the i-th stage shift register unit 60 and the time of the active pulse of the third clock signal Rck received by the i+1th stage shift register unit 60 do not overlap, that is, the enable level (e.g., low level signal) of the third clock signal Rck received by the i-th stage shift register unit 60 and the enable level (e.g., low level signal) of the third clock signal Rck received by the i+1th stage shift register unit 60 do not overlap. In this way, when the third clock signal Rck received by the i-th shift register unit 60 is a low-level signal, the third clock signal Rck received by the i-th shift register unit 60 is a high-level signal, whereas when the third clock signal Rck received by the i-th shift register unit 60 is a high-level signal, the third clock signal Rck received by the i-th shift register unit 60 is a low-level signal. In this way, it is ensured that the adjacent two stages of shift register units 60 can normally operate, and the third clock terminal RCK of the i-th stage shift register unit 60 and the third clock terminal RCK of the i+1th stage shift register unit 60 can be electrically connected to different signal lines, respectively, and fig. 27 exemplarily shows that the third clock terminal RCK of the first stage shift register unit 60 is electrically connected to the fourth clock signal line L4, and the third clock terminal RCK of the second stage shift register unit 60 is electrically connected to the third clock signal line L3, but is not limited thereto.

Optionally, fig. 28 is a driving timing chart of a shift register according to an embodiment of the present invention, and each driving cycle of the shift register includes a first stage t01 and a second stage t02, where a time of the first stage t01 overlaps a time of a data writing frame t1, and a time of the second stage t02 overlaps a time of a holding frame t2, as shown in fig. 26, 27 and 28. At least in the first stage t01, the third clock signal Rck received by the i-th stage shift register unit 60 is identical to the second clock signal Sckb received by the i-th stage shift register unit 60 and/or the third clock signal Rck received by the i-th stage shift register unit 60 is identical to the first clock signal Sck received by the i+1-th stage shift register unit 60.

Referring to fig. 27, fig. 27 shows that the second clock terminal SCKB of the i-th stage shift register unit 60 is electrically connected to the second clock signal line L2 and the third clock terminal RCK is electrically connected to the fourth clock signal line L4, and the second clock terminal SCKB of the i+1th stage shift register unit 60 is electrically connected to the first clock signal line L1 and the third clock terminal RCK is electrically connected to the third clock signal line L3, wherein i is a positive integer. In the first stage t01, the shift register unit 60 at each stage operates in the data writing frame t1, the third clock signal Rck received by the shift register unit 60 at the i-th stage is identical to the second clock signal Sckb received by the shift register unit 60 at the i-th stage, the clock signal transmitted by the first clock signal line L1 is identical to the clock signal transmitted by the third clock signal line L3, and the clock signal transmitted by the second clock signal line L2 is identical to the clock signal transmitted by the fourth clock signal line L4, so that, when the shift register unit 60 operates in the first stage t01, the first clock signal line L1 and the third clock signal line L3 can be made to be supplied with signals by the same signal terminal in the driving chip, and the second clock signal line L2 and the fourth clock signal line L4 can be supplied with signals by the same signal terminal in the driving chip, so that power consumption can be reduced. In addition, when the second clock signal Sckb received by the i-th stage shift register unit 60 is multiplexed to the first clock signal Sck received by the i+1th stage shift register unit 60, the third clock signal Rck received by the i-th stage shift register unit 60 may also be the same as the first clock signal Sck received by the i+1th stage shift register unit 60.

With continued reference to fig. 26 to 28, when the first clock signal Sck received by the shift register unit 60 is low, the second clock signal Sckb is high, and the third clock signal Rck is high, both the first input transistor T1 and the first voltage stabilizing transistor T2 are turned on, the signal input terminal IN of the shift register unit 60 writes the enable level (i.e., the low level signal) output by the received previous stage shift register unit 60 into the third node N3, so that the potential of the third node N3 is low, while the third transistor T3 is turned on, so that the first level signal VGL (i.e., the low level signal) of the first level terminal VGL is transmitted to the fourth node N4, and the fourth transistor T3 IN the inter-control module 63 is turned on under the control of the potential of the third node N3, so that the first clock signal Sck is transmitted to the fourth node N4 to maintain the potential of the fourth node N4 at the low level, and the fifth transistor T5 IN the inter-control module 63 is turned on under the control of the sixth node N4 at the high potential of the third node N6, so that the potential of the fourth transistor T6 IN the inter-control module 63 is maintained at the low level. As such, the first output transistor T11 and the second output transistor T12 in the first output module 64, and the third output transistor T21 and the fourth output transistor T22 in the second output module 65 are both turned on under the potential control of the low level of the third node N3 and the fourth node N4, respectively, when the high level of the third clock signal Rck is the same as the second level signal VGH (i.e., the high level signal) of the second level terminal VGH, and the high level of the second clock signal Sckb is the same as the second level signal VGH (i.e., the high level signal) of the second level terminal VGH, so that the first scan signal S1 output by the first signal output terminal OUT1 is the disable level (i.e., the high level signal) and the second scan signal S2 output by the second signal output terminal OUT2 is the disable level (i.e., the high level signal).

Similarly, when the first clock signal Sck received by the shift register unit 60 is at a high level, the second clock signal Sckb is at a low level, and the third clock signal Rck is at a low level, the first input transistor T1 is turned off, the input signal Vin of the signal input terminal IN cannot be transmitted to the third node N3, such that the potential of the third node N3 is maintained at a low level, and the third transistor T3 is turned off, and the first level signal VGL (i.e., a low level signal) of the first level terminal VGL cannot be transmitted to the fourth node N4. At this time, the fourth transistor T4 of the inter-control module 63 is turned on under the control of the potential of the third node N3, so that the high level of the first clock signal Sck is transmitted to the fourth node N4, and further, the fifth transistor T5 of the inter-control module 63 is turned off under the control of the potential of the fourth node N4, so that the second level signal VGH (i.e., the high level signal) of the second level terminal VGH cannot be transmitted to the third node N3, so as to ensure that the potential of the third node N3 is continuously stabilized at the low level. In this way, the first output transistor T11 in the first output module 64 is turned on under the control of the potential of the third node N3, and the second output transistor T12 is turned off under the control of the potential of the fourth node N4, so that the first scan signal S1 output by the first signal output terminal OUT1 is a low level signal of the third clock signal Rck. Meanwhile, the third output transistor T21 in the second output module 65 is turned on under the control of the potential of the third node N3, and the fourth output transistor T22 is turned off under the control of the potential of the fourth node N4, so that the second scan signal S2 output by the second signal output terminal OUT2 is a low level signal of the second clock signal Sckb.

Based on the above-described operation principle of the shift register unit 60, the transistors in the shift register unit 60 of each stage are exemplified by the P-channel transistors arranged in the column direction Y in the high-frequency display area AA1 and the low-frequency display area AA 2.

With continued reference to fig. 21 to 23 and fig. 26 to 28, in the first stage t01, each of the shift register units 60 operates in the data writing frame t1, each of the first clock signal Sck, the second clock signal Sckb and the third clock signal Rck includes a plurality of active pulses, the time of the active pulse of the first clock signal Sck and the time of the active pulse of the second clock signal Sckb do not overlap each other, the time of the active pulse of the second clock signal Sckb and the time of the active pulse of the third clock signal Rck overlap each other, so that when the first clock signal Sck is at a high level, the second clock signal Sckb is at a low level and the third clock signal Rck is at a low level, the first output module 64 can be controlled to transmit the third clock signal Rck to the first signal output terminal OUT1, and the second output module 65 transmits the second clock signal Sckb to the second signal output terminal OUT2, so that the first level signal S1 output by the first signal output terminal OUT1 of the shift register unit and the second signal S2 can be sequentially shifted by the time of the second level and the second signal S2. Fig. 28 exemplarily shows timings of the first level signal S1 (i) and the second scan signal S2 (i) output from the i-th stage shift register unit 60 electrically connected to the i-th row pixel circuit 10, and the first level signal S1 (i+n) and the second scan signal S2 (i+n) output from the i+n-th stage shift register unit 60 electrically connected to the i+n-th row pixel circuit 10.

In the second stage T02, the shift register units 60 at each stage operate in the holding frame T2, and the first clock signal Sck and the second clock signal Sckb may still include a plurality of effective pulses, so that the second level signal S2 output by the second signal output terminal OUT2 is sequentially shifted, so as to reset the potential of the first pole of the driving transistor T1 of the pixel circuit 10 at a high frequency, reduce the voltage difference between the first poles of the driving transistors T1 of the data writing frame T1 and the holding frame T2, and improve the ghost problem. Since the ith row of pixel circuits 10 is located in the high-frequency display area AA1, i.e., the ith row of pixel circuits 10 still needs to have a completed driving period, i.e., the first scan signal S1 received in the reset phase is at the enable level (i.e., the low level signal), at this time, the received third clock signal Rck of the ith stage of shift register units 60 electrically connected to the ith row of pixel circuits 10 needs to be at the low level to ensure that the first scan signal S1 (i.e., S1 (i)) output from the first signal output terminal OUT1 of the ith stage of shift register units 60 is at the enable level. However, for the i+n-th row pixel circuit 10 located in the low frequency display area AA2, since the threshold compensation module 16 of the i+n-th row pixel circuit 10 is turned off at the holding frame t2 to avoid affecting the stability of the potential of the second node N2 of the pixel circuit 10, i.e., to control the first scan signal S1 outputted from the first signal output terminal OUT1 of the i+n-th shift register unit 60 electrically connected to the threshold compensation module 16 of the i+n-th row pixel circuit 10 to be at the disable level (i.e., the high level signal), at this time, the received third clock signal Rck of the i+n-th shift register unit 60 electrically connected to the i+n-th row pixel circuit 10 needs to be at the high level to ensure that the first scan signal S1 outputted from the first signal output terminal OUT1 of the i+n-th shift register unit 60 (i+n) is at the disable level.

In this way, by setting the first signal output terminal OUT1 of the first output module 64 of the shift register unit 60 to output the first scan signal S1, and the second signal output terminal OUT2 of the second output module 65D to output the second scan signal S2, the number of shift registers can be reduced, which is beneficial to the design of the narrow frame of the display panel. When the potential of the third node N3 of the shift register unit 60 is the enabling potential, the first scan signal S1 output by the first signal output terminal OUT1 of the first output module 64 is the third clock signal Rck, the second scan signal S2 output by the second signal output terminal OUT2 of the second output module 65 is the second clock signal Sckb, and further, the pixel circuit 10 of the low-frequency display area AA2 can maintain the current display screen unchanged in the holding frame t2 by controlling the second clock signal Sckb received by the shift register unit 60 electrically connected to the pixel circuit 10 of the low-frequency display area AA2 to be at the non-enabling level, thereby realizing the high-frequency and low-frequency partition display of the display panel 100.

It should be noted that, according to the different division manners of the high-frequency display area AA1 and the low-frequency display area AA2 in the display panel 100, the timings of the second scan signals S2 output by the shift register units 60 at different levels may also be different, and the embodiments of the present invention are described above and set according to practical situations, and are not described in detail herein, but fig. 28 is an exemplary illustration and not limited thereto. For example, when the high frequency display area AA1 and the low frequency display area AA2 are arranged in the row direction X, the i-th row pixel circuit 10 is located in the high frequency display area AA1, the i+n-th row pixel circuit 10 is located in the low frequency display area AA2, i and n are both positive integers, and fig. 29 shows another driving timing chart of the shift register, and the i-th row pixel circuit of the low frequency display area AA 2. The i-th row of pixel circuits 10 is located in the high-frequency display area AA1, the i+n-th row of pixel circuits 10 is located in the low-frequency display area AA2, i and n are both positive integers, fig. 29 shows another driving timing diagram of the shift register, and unlike fig. 28, in the second stage t02, the first scanning signal S1 still keeps shifting in sequence, so that the pixel circuits 10 located in the high-frequency display area AA1 in the same row of pixel circuits 10 keep working normally, and further, the picture of the high-frequency display area AA1 is displayed normally, and the specific working process is not repeated herein, and can be described above. In the holding frame t2, the pixel circuit 10 of the low frequency display area AA2 may control the potential of the second node N2 of the pixel circuit 10 of the low frequency display area AA2 to be unchanged by controlling the first driving signal D transmitted by the first driving signal line 20 electrically connected to the node control module 13 of the pixel circuit 10 of the low frequency display area AA2 to be a non-enabling level (i.e., a high level signal), so as to realize that the display screen of the low frequency display area AA2 is maintained unchanged.

Based on the same inventive concept, the embodiment of the present invention further provides a driving method of a display panel, which is applicable to the display panel 100 provided in any of the embodiments described above, and fig. 30 is a flowchart of a driving method of a display panel provided in the embodiment of the present invention, where, as shown in fig. 30, the driving method of a display panel includes:

s101, acquiring a display mode and a display signal of a display panel.

The display modes may include a high-frequency display mode, a low-frequency display mode, or a part of high-frequency display and a part of low-frequency display, and the display modes of different display panels may be identified by corresponding control signals, which are not particularly limited herein.

The display signals corresponding to the high-frequency display mode and the low-frequency display mode are different, and it can be understood that the refresh frequency of the display picture corresponding to the high-frequency display mode is greater than the refresh frequency of the display picture corresponding to the low-frequency display mode, so that the display signals can be represented by the refresh frequency of the display picture, which is not particularly limited herein and can be set according to actual requirements.

S102, when the display mode of the display panel is determined to be the first display mode, a high-frequency display area and a low-frequency display area of the display panel are determined according to the display signals.

In this embodiment, the driving chip in the display panel may acquire a display mode and a display signal of the display panel, and determine whether the display panel is in a first display mode according to the display mode, where the first display mode indicates that the display panel includes a high-frequency display area and a low-frequency display area, and when determining that the display mode of the display panel is the first display mode, may further determine specific positions of the high-frequency display area and the low-frequency display area of the display panel according to the display signal. It can be understood that, the on period of the reset module of the pixel circuit in the high-frequency display area and the on period of the node control module are both less than or equal to the time of one frame of display screen of the high-frequency display area, the on period of the reset module of the pixel circuit in the low-frequency display area and the on period of the node control module are both less than or equal to the time of one frame of display screen of the low-frequency display area, and the refresh frequency of the display screen of the high-frequency display area is greater than the refresh frequency of the display screen of the low-frequency display area, so that the on period of the reset module of the pixel circuit in the high-frequency display area is less than or equal to the on period of the reset module of the pixel circuit in the low-frequency display area, and the on period of the node control module of the pixel circuit in the high-frequency display area is less than or equal to the on period of the node control module of the pixel circuit in the low-frequency display area. Setting the conduction period of the reset module of the pixel circuit in the high-frequency display area as T11, and setting the conduction period of the node control module of the pixel circuit in the high-frequency display area as T12; the on period of the reset module of the pixel circuit in the low-frequency display area is T21, and the on period of the node control module of the pixel circuit in the low-frequency display area is T22, so that T21 is greater than T11, and/or T22 is greater than T12, the display panel can realize the functions of partial area high-frequency display and partial area low-frequency display, and the positions of the high-frequency display area and the low-frequency display area can be divided arbitrarily, so that the power consumption of the display panel is reduced, and the application range of the display panel is enlarged.

Based on the same inventive concept, the embodiment of the present invention further provides a display device, and fig. 31 is a schematic structural diagram of the display device provided by the embodiment of the present invention, as shown in fig. 31, the display device 200 includes the display panel 100 provided by any embodiment of the present invention, and the display device 200 provided by the embodiment of the present invention may be a mobile phone or any electronic product with a display function, including but not limited to the following categories: television, notebook computer, desktop display, tablet computer, digital camera, smart bracelet, smart glasses, vehicle-mounted display, medical equipment, industrial control equipment, touch interactive terminal, etc., which are not particularly limited in this embodiment of the invention.

Note that the above is only a preferred embodiment of the present invention and the technical principle applied. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, and that various obvious changes, rearrangements, combinations, and substitutions can be made by those skilled in the art without departing from the scope of the invention. Therefore, while the invention has been described in connection with the above embodiments, the invention is not limited to the embodiments, but may be embodied in many other equivalent forms without departing from the spirit or scope of the invention, which is set forth in the following claims.

Claims

1. A display panel, comprising: a display area; the display area comprises a plurality of pixel circuits which are arranged in an array manner, wherein each pixel circuit comprises a driving module, a resetting module, a node control module and a light-emitting element;

Wherein T21> T11, and/or T22> T12.

2. The display panel of claim 1, further comprising: a non-display area located at one side of the display area; the display area comprises a plurality of first driving signal lines, and the non-display area comprises a first shift register;

the pixel circuits form a plurality of pixel circuit groups; each pixel circuit group comprises at least one column of the pixel circuits;

the first shift register comprises a plurality of first shift register units which are arranged in cascade, and the signal output end of each stage of the first shift register unit is electrically connected with the reset module of at least part of the pixel circuits positioned in the same row; the first shift register unit is used for outputting a first scanning signal for controlling the on or off of the reset module;

each first driving signal line is electrically connected with a node control module of each pixel circuit in the same pixel circuit group; the first driving signal line is used for transmitting a first driving signal for controlling the node control module to be switched on or switched off.

3. The display panel according to claim 2, wherein the high-frequency display region and the low-frequency display region are arranged in a column direction of the pixel circuit;

When the display mode of the display panel is the first mode, T21> T11, and T22> T12.

4. A display panel according to claim 3, wherein one frame picture time of the low frequency display region includes a data writing frame and at least one holding frame; the data writing frame comprises a first non-light-emitting stage and a light-emitting stage; the first non-light-emitting stage includes the reset stage and the data writing stage; the hold frame includes a second non-light-emitting phase and the light-emitting phase; the second non-light-emitting stage does not set the reset stage and the data writing stage; at least part of the holding frames are first holding frames;

in the data writing frame, each stage of the first shift register unit sequentially outputs the enabling level of the first scanning signal for controlling the conduction of the reset module; the first driving signal line transmits an enabling level of the first driving signal for controlling the node control module to be conducted;

in the first holding frame, each of the first shift register units electrically connected to the reset module of the pixel circuit in the high-frequency display area sequentially outputs an enable level of the first scan signal, and each of the first shift register units electrically connected to the reset module of the pixel circuit in the low-frequency display area outputs a disable level of the first scan signal; the first driving signal line electrically connected to the node control module of the pixel circuit in the high frequency display region transmits an enable level of the first driving signal, and the first driving signal line electrically connected to the node control module of the pixel circuit in the low frequency display region transmits a disable level of the first driving signal.

5. The display panel according to claim 2, wherein the high-frequency display region and the low-frequency display region are arranged in a row direction of the pixel circuit;

when the display mode of the display panel is the first mode, t21=t11 and T22> T12.

6. The display panel according to claim 5, wherein a frame time of the low frequency display region includes a data writing frame and at least one holding frame; the data writing frame comprises a first non-light-emitting stage and a light-emitting stage; the first non-light-emitting stage includes the reset stage and the data writing stage; the hold frame includes a second non-light-emitting phase and the light-emitting phase; the second non-light-emitting stage does not set the reset stage and the data writing stage; at least part of the holding frames are first holding frames;

in the first holding frame, the first shift register unit of each stage sequentially outputs the enable level of the first scanning signal; the first driving signal line electrically connected to the node control module of the pixel circuit in the high frequency display region transmits an enable level of the first driving signal, and the first driving signal line electrically connected to the node control module of the pixel circuit in the low frequency display region transmits a disable level of the first driving signal.

7. The display panel of claim 2, wherein the low frequency display region comprises a first low frequency display region and a second low frequency display region; the first low-frequency display area and the high-frequency display area are arranged along the column direction of the pixel circuit, and the second low-frequency display area and the high-frequency display area are arranged along the row direction of the pixel circuit;

the conduction period of the reset module of the pixel circuit in the first low-frequency display area is T211, the conduction period of the reset module of the pixel circuit in the second low-frequency display area is T212, the conduction period of the node control module of the pixel circuit in the first low-frequency display area is T221, and the conduction period of the node control module of the pixel circuit in the second low-frequency display area is T222;

when the display mode of the display panel is the first mode, T211> T11, t212=t11, T221> T12 and T222> T12.

8. The display panel according to claim 7, wherein a frame time of the low frequency display region includes a data writing frame and at least one holding frame; the data writing frame comprises a first non-light-emitting stage and a light-emitting stage; the first non-light-emitting stage includes the reset stage and the data writing stage; the hold frame includes a second non-light-emitting phase and the light-emitting phase; the second non-light-emitting stage does not set the reset stage and the data writing stage; at least part of the holding frames are first holding frames;

in the first hold frame, each of the first shift register units electrically connected to the reset module of the pixel circuit in the second low-frequency display and the high-frequency display area sequentially outputs an enable level of the first scan signal, and each of the first shift register units electrically connected to the reset module of the pixel circuit in the first low-frequency display area outputs a disable level of the first scan signal; the first driving signal line electrically connected to the node control module of the pixel circuit in the high frequency display region transmits an enable level of the first driving signal, and the first driving signal line electrically connected to the node control module of the pixel circuit in the first low frequency display region and the second low frequency display region transmits a disable level of the first driving signal.

9. The display panel of claim 2, wherein the reset modules each comprise a first control terminal and a second control terminal; the first control end of the reset module is electrically connected with the signal output end of the first shift register unit;

At least part of the pixel circuits in the low-frequency display area are first pixel circuits, and at least part of the pixel circuits in the high-frequency display area are second pixel circuits; the first control end of the reset module in the second pixel circuit is electrically connected with the second control end;

the display area comprises a second driving signal line, and the second driving signal line is electrically connected with the second control end of the reset module in each first pixel circuit; the second driving signal line is used for transmitting a second driving signal; the reset module of the first pixel circuit is used for being conducted when the received first driving signal and the first scanning signal are both in an enabling level.

10. The display panel of claim 9, wherein the reset module comprises a first reset transistor and a second reset transistor;

in the same reset module, a first end of the first reset transistor is electrically connected with a reset signal end, a second end of the first reset transistor is electrically connected with a first end of the second reset transistor, and a second end of the second reset transistor is electrically connected with the first node; one of the first control end and the second control end of the reset module is electrically connected with the grid electrode of the first reset transistor, and the other is electrically connected with the grid electrode of the second reset transistor.

11. The display panel according to claim 9, wherein a frame time of the low frequency display region includes a data writing frame and at least one holding frame; the data writing frame comprises a first non-light-emitting stage and a light-emitting stage; the first non-light-emitting stage includes the reset stage and the data writing stage; the hold frame includes a second non-light-emitting phase and the light-emitting phase; the second non-light-emitting stage does not set the reset stage and the data writing stage; at least part of the holding frames are first holding frames in the data writing frames, and each stage of the first shift register unit sequentially outputs the enabling level of the first scanning signal for controlling the reset module to be conducted; the second driving signal line transmits an enabling level of the second driving signal for controlling the reset module to be conducted; the first driving signal line transmits an enabling level of the first driving signal for controlling the node control module to be conducted;

in the first hold frame, the second driving signal line electrically connected to the reset module of the first pixel circuit in the low frequency display region transmits a non-enable level of the second driving signal, the first driving signal line electrically connected to the node control module of the second pixel circuit in the high frequency display region transmits an enable level of the first driving signal, the first driving signal line electrically connected to the node control module of the pixel circuit in the low frequency display region transmits a non-enable level of the first driving signal, and the first shift register unit electrically connected to at least the reset module of the second pixel circuit in the high frequency display region sequentially outputs an enable level of the first scanning signal controlling the turn-on of the reset module.

12. The display panel according to claim 11, wherein in the first holding frame, each of the first shift register units electrically connected to the reset module of each of the pixel circuits in the low frequency display region sequentially outputs an enable level of the first scan signal, and the enable level of the first scan signal output by each of the first shift register units of the first shift register is sequentially shifted; or,

in the first hold frame, each of the first shift register units electrically connected to the reset module of each of the pixel circuits in the low frequency display region outputs a disable level of the first scan signal.

13. The display panel of claim 11, wherein the pixel circuit further comprises a data writing module and a threshold compensation module;

the data writing module is electrically connected with the first pole of the driving transistor, and the threshold compensation module is electrically connected between the second pole of the driving transistor and the second node;

the data writing module is used for writing data voltage to the first node in the data writing stage;

the threshold compensation module is used for compensating the threshold voltage of the driving transistor to the first node in the data writing stage.

14. The display panel according to claim 13, wherein in each stage of the first shift register unit, a signal output terminal of the i-th stage of the first shift register unit is electrically connected to the threshold compensation module of the i-th row of the pixel circuits and a first control terminal of the reset module of the i+1-th row of the pixel circuits, respectively; wherein i is a positive integer;

the first scanning signal is also used for controlling the threshold compensation module to be switched on or off.

15. The display panel according to claim 14, wherein when the i-th row of the pixel circuits is located in the high-frequency display region, the i+1-th row of the pixel circuits is located in the low-frequency display region, the i+1-th row of the pixel circuits is the first pixel circuit; the other pixel circuits except the first pixel circuit in the low-frequency display area are all the second pixel circuits;

the start time of the non-enabling level of the second driving signal is positioned before the start time of the enabling level of the first scanning signal output by the first shift register unit of the ith stage and is positioned after the end time of the enabling level of the first scanning signal output by the first shift register unit of the ith-1 stage in the first holding frame; wherein i is a positive integer greater than or equal to 2.

16. The display panel according to claim 14, wherein the non-display area further comprises a second shift register, the second shift register comprises a plurality of second shift register units arranged in cascade, and enable levels of second scan signals output from signal output terminals of the second shift register units of each stage are sequentially shifted;

the signal output end of each stage of the second shift register unit is electrically connected with the data writing module of at least part of the pixel circuits positioned in the same row;

wherein at least in the data writing frame, in the same pixel circuit, the enable level time of the first scan signal overlaps with the enable level time of the second scan signal.

17. The display panel of claim 16, wherein the first shift register unit in the first shift register and the second shift register unit in the second shift register are the same shift register unit;

the shift register unit comprises a first signal output end and a second signal output end, wherein the first signal output end is the signal output end of the first shift register unit, and the second signal output end is the signal output end of the second shift register unit.

18. The display panel of claim 17, wherein the shift register unit comprises a first clock terminal, a second clock terminal, a third clock terminal, a first level terminal, a second level terminal, a signal input terminal, a first signal output terminal, a second signal output terminal, a first control module, a second control module, a mutual control module, a first output module, and a second output module;

in the same shift register unit:

the first control module, the first output module and the second output module are electrically connected to a third node; the first control module is also electrically connected with the first clock end and the signal input end respectively; the first control module is used for responding to a first clock signal of the first clock end and an input signal of the signal input end and controlling the potential of the third node;

the second control module, the first output module and the second output module are electrically connected to a fourth node; the second control module is also electrically connected with the first clock end and the first level end respectively; the second control module is used for responding to a first clock signal of the first clock end and a first level signal of the first level end and controlling the potential of the fourth node;

The mutual control module is electrically connected with the third node, the fourth node, the first clock end, the second clock end and the second level end respectively; the mutual control module is used for responding to the first clock signal of the first clock end and the potential of the third node, controlling the potential of the fourth node, and responding to the second clock signal of the second clock end, the second level signal of the second level end and the potential of the fourth node, and controlling the potential of the third node;

the first output module is also respectively and electrically connected with the third clock end, the second level end and the first signal output end; the first output module is used for controlling the time of the first signal output end to output the third clock signal of the third clock end under the control of the potential of the third node, and controlling the time of the first signal output end to output the second level signal of the second level end under the control of the potential of the fourth node;

the second output module is also respectively and electrically connected with the second clock end, the second level end and the second signal output end; the second output module is used for controlling the time of the second signal output end to output the second clock signal of the second clock end under the control of the potential of the third node, and controlling the time of the second signal output end to output the second level signal of the second level end under the control of the potential of the fourth node.

19. The display panel according to claim 18, wherein, among the shift register units of each stage, a signal input terminal of the (i+1) -th stage of the shift register unit is electrically connected to a second signal output terminal of the (i) -th stage of the shift register unit; the signal input end of the first stage of the shift register unit receives a start pulse signal; wherein i is a positive integer;

multiplexing the first clock signal received by the i-th stage of the shift register unit into the second clock signal received by the i+1-th stage of the shift register unit; and/or multiplexing the second clock signal received by the i-th stage of the shift register unit into the first clock signal received by the i+1-th stage of the shift register unit.

20. The display panel according to claim 19, wherein the first clock signal received by the i-th stage of the shift register unit is multiplexed into the first clock signal received by the i+2-th stage of the shift register unit;

the second clock signal received by the i-th stage of the shift register unit is multiplexed into the second clock signal received by the i+2-th stage of the shift register unit.

21. The display panel according to claim 19, wherein each driving period of the shift register includes a first phase and a second phase, a time of the first phase overlapping a time of the data writing frame, and a time of the second phase overlapping a time of the holding frame;

At least in the first stage, the third clock signal received by the i-th stage of the shift register unit is the same as the second clock signal received by the i-th stage of the shift register unit, and/or the third clock signal received by the i-th stage of the shift register unit is the same as the first clock signal received by the i+1-th stage of the shift register unit.

22. A driving method of a display panel, which is applicable to the display panel of any one of claims 1 to 21, comprising:

acquiring a display mode and a display signal of the display panel;

23. A display device comprising the display panel according to any one of claims 1-21.