CN113012634A

CN113012634A - Pixel circuit, driving method thereof and display device

Info

Publication number: CN113012634A
Application number: CN202110244164.9A
Authority: CN
Inventors: 陈亮; 刘冬妮; 肖丽; 郑皓亮; 韩承佑; 玄明花; 赵蛟; 陈昊
Original assignee: BOE Technology Group Co Ltd
Current assignee: BOE Technology Group Co Ltd
Priority date: 2021-03-05
Filing date: 2021-03-05
Publication date: 2021-06-22

Abstract

A pixel circuit, a driving method thereof and a display device are provided, wherein the pixel circuit comprises: the current control sub-circuit is used for receiving a display data signal and a light-emitting control signal, controlling whether a driving current is generated or not according to the light-emitting control signal, and controlling the current intensity of the generated driving current according to the display data signal; the gray scale control sub-circuit is used for receiving the mode control signal and the generated driving current, and driving the light-emitting element at a first time length when the mode control signal is in a first display mode; when the mode control signal is in the second display mode, the light emitting element is driven for a second duration, at least one of the first duration and the second duration being comprised of a plurality of pulse periods. According to the display device, the light-emitting elements are driven in different time lengths according to different display modes, and at least one of the different time lengths is composed of a plurality of pulse time intervals, so that the light-emitting time can be dispersed in a light-emitting stage during low gray scale, and the flicker phenomenon occurring in the low gray scale is avoided.

Description

Pixel circuit, driving method thereof and display device

Technical Field

The embodiment of the disclosure relates to but is not limited to the technical field of display, and in particular relates to a pixel circuit, a driving method thereof and a display device.

Background

Micro Light Emitting Diode (Micro LED) technology is to integrate a Micro-sized LED array on one chip with high density to realize thinning, miniaturization and matrixing of LEDs, the distance between pixels can reach micron level, and each pixel can address and emit Light individually. Micro LED display panels are gradually developing towards display panels used by consumer terminals due to their characteristics of low driving voltage, long life, wide temperature resistance, etc.

The Micro LED is electrically connected to the pixel circuit to drive the Micro LED to emit light. In a related pixel circuit, the gray scale is usually adjusted through current and light emitting time, but the gray scale is adjusted through the current, so that the efficiency of the low gray scale is reduced due to the low current density corresponding to the low gray scale, and along with the change of the current density, the color coordinate of the Micro LED changes, namely, the Micro LED has color cast when the gray scale changes; the gray scale is adjusted by reducing the light emitting time, and if the light emitting time is concentrated at one section, the flicker (flicker) is easily caused, and the display effect of the display panel is further influenced.

Disclosure of Invention

The embodiment of the disclosure provides a pixel circuit, a driving method thereof and a display device, which can improve the display effect of a display panel.

The disclosed embodiment provides a pixel circuit, including: a current control sub-circuit, a gray scale control sub-circuit, and a light emitting element, wherein: the current control sub-circuit is used for receiving a display data signal and a light-emitting control signal, controlling whether to generate a driving current according to the light-emitting control signal, and controlling the current intensity of the generated driving current according to the display data signal; the gray scale control sub-circuit is used for receiving a mode control signal and a driving current generated by the current control sub-circuit, and when the mode control signal is in a first display mode, the light-emitting element is driven for a first time; and when the mode control signal is in a second display mode, driving the light-emitting element for a second duration, wherein at least one of the first duration and the second duration is composed of a plurality of pulse periods.

In some exemplary embodiments, the gray scale control sub-circuit includes: a mode control sub-circuit, an inverter sub-circuit, and a third emission control sub-circuit, wherein: the mode control sub-circuit is respectively connected with a first control signal end, a mode control signal end and a second node and is used for writing a signal of the mode control signal end into the second node under the control of the first control signal end; the inverter subcircuit is respectively connected with a light-emitting control signal end, a pulse control signal end, a first node and the second node, and is used for writing a signal of the light-emitting control signal end or a signal of the pulse control signal end into the first node under the control of a signal of the second node; the third light-emitting control sub-circuit is respectively connected to the first node, the current control sub-circuit and the light-emitting element, and is configured to receive a driving current of the current control sub-circuit, and control a time for the driving current to flow through the light-emitting element under control of a signal of the first node.

In some exemplary embodiments, the first control signal terminal is a first scan signal terminal, the third light emission control sub-circuit includes an eighth transistor, the inverter sub-circuit includes a ninth transistor and a tenth transistor, the mode control sub-circuit includes an eleventh transistor and a second capacitor, wherein: a control electrode of the eighth transistor is connected to the first node, a first electrode of the eighth transistor is connected to a third node, and a second electrode of the eighth transistor is connected to an anode terminal of the light-emitting element; a control electrode of the ninth transistor is connected with the second node, a first electrode of the ninth transistor is connected with the light-emitting control signal end, and a second electrode of the ninth transistor is connected with the first node; a control electrode of the tenth transistor is connected to the second node, a first electrode of the tenth transistor is connected to the pulse control signal terminal, and a second electrode of the tenth transistor is connected to the first node; a control electrode of the eleventh transistor is connected to the first scan signal terminal, a first electrode of the eleventh transistor is connected to the mode control signal terminal, and a second electrode of the eleventh transistor is connected to the second node; one end of the second capacitor is connected with the second node, and the other end of the second capacitor is connected with the initial voltage end; the ninth transistor is a P-type transistor, and the tenth transistor is an N-type transistor; or, the ninth transistor is an N-type transistor, and the tenth transistor is a P-type transistor.

In some exemplary embodiments, the current control sub-circuit includes a driving sub-circuit, a writing sub-circuit, a compensation sub-circuit, a resetting sub-circuit, a first light emission control sub-circuit, and a second light emission control sub-circuit, wherein: the driving sub-circuit is respectively connected with a fourth node, a fifth node and a sixth node and is used for providing driving current for the sixth node under the control of signals of the fourth node and the fifth node; the write-in sub-circuit is respectively connected with a first scanning signal terminal, a display data signal terminal and a fifth node, and is used for writing the signal of the display data signal terminal into the fifth node under the control of the signal of the first scanning signal terminal; the compensation sub-circuit is respectively connected with a first voltage end, the first scanning signal end, a fourth node and a sixth node, and is used for compensating the fourth node under the control of a signal of the first scanning signal end and a signal of the first voltage end; the reset sub-circuit is respectively connected with a reset control signal end, an initial voltage end, a fourth node and an anode end of the light-emitting element, and is used for writing a signal of the initial voltage end into the fourth node and the anode end of the light-emitting element under the control of a signal of the reset control signal end; the first light-emitting control sub-circuit is respectively connected with a first voltage end, a light-emitting control signal end and a fifth node and is used for providing a signal of the first voltage end to the fifth node under the control of a signal of the light-emitting control signal end; the second light-emitting control sub-circuit is respectively connected with a light-emitting control signal end, a third node and a sixth node, and is used for allowing a driving current to pass between the sixth node and the third node under the control of a signal of the light-emitting control signal end.

In some exemplary embodiments, the reset sub-circuit includes a first transistor and a seventh transistor, the compensation sub-circuit includes a second transistor and a first capacitor, the driving sub-circuit includes a third transistor, the write sub-circuit includes a fourth transistor, the first emission control sub-circuit includes a fifth transistor, the second emission control sub-circuit includes a sixth transistor, wherein: a control electrode of the first transistor is connected with a reset control signal end, a first electrode of the first transistor is connected with an initial voltage end, and a second electrode of the first transistor is connected with a fourth node; a control electrode of the second transistor is connected with a first scanning signal end, a first electrode of the second transistor is connected with a fourth node, and a second electrode of the second transistor is connected with a sixth node; a control electrode of the third transistor is connected with a fourth node, a first electrode of the third transistor is connected with a fifth node, and a second electrode of the third transistor is connected with a sixth node; one end of the first capacitor is connected with the fourth node, and the other end of the first capacitor is connected with the first voltage end; a control electrode of the fourth transistor is connected with a first scanning signal end, a first electrode of the fourth transistor is connected with a display data signal end, and a second electrode of the fourth transistor is connected with a fifth node; a control electrode of the fifth transistor is connected with a light-emitting control signal end, a first electrode of the fifth transistor is connected with a first voltage end, and a second electrode of the fifth transistor is connected with a fifth node; a control electrode of the sixth transistor is connected with the light-emitting control signal end, a first electrode of the sixth transistor is connected with a sixth node, and a second electrode of the sixth transistor is connected with a third node; a control electrode of the seventh transistor is connected with a reset control signal end, a first electrode of the seventh transistor is connected with an initial voltage end, and a second electrode of the seventh transistor is connected with an anode end of the light-emitting element.

In some exemplary embodiments, the first control signal terminal is a reset control signal terminal, the third light emission control sub-circuit includes an eighth transistor, the inverter sub-circuit includes a ninth transistor and a tenth transistor, the mode control sub-circuit includes an eleventh transistor and a second capacitor, wherein: a control electrode of the eighth transistor is connected to the first node, a first electrode of the eighth transistor is connected to a sixth node, and a second electrode of the eighth transistor is connected to an anode terminal of the light-emitting element; a control electrode of the ninth transistor is connected with the second node, a first electrode of the ninth transistor is connected with the light-emitting control signal end, and a second electrode of the ninth transistor is connected with the first node; a control electrode of the tenth transistor is connected to the second node, a first electrode of the tenth transistor is connected to the pulse control signal terminal, and a second electrode of the tenth transistor is connected to the first node; a control electrode of the eleventh transistor is connected with the reset control signal end, a first electrode of the eleventh transistor is connected with the mode control signal end, and a second electrode of the eleventh transistor is connected with the second node; one end of the second capacitor is connected with the second node, and the other end of the second capacitor is connected with the initial voltage end; the ninth transistor is a P-type transistor, and the tenth transistor is an N-type transistor; or, the ninth transistor is an N-type transistor, and the tenth transistor is a P-type transistor.

In some exemplary embodiments, the current control sub-circuit includes a driving sub-circuit, a writing sub-circuit, a compensation sub-circuit, a resetting sub-circuit, and a first light emitting control sub-circuit, wherein: the driving sub-circuit is respectively connected with a fourth node, a fifth node and a sixth node and is used for providing driving current for the sixth node under the control of signals of the fourth node and the fifth node; the write-in sub-circuit is respectively connected with a first scanning signal terminal, a display data signal terminal and a fifth node, and is used for writing the signal of the display data signal terminal into the fifth node under the control of the signal of the first scanning signal terminal; the compensation sub-circuit is respectively connected with a first voltage end, the first scanning signal end, a fourth node and a sixth node, and is used for compensating the fourth node under the control of a signal of the first scanning signal end and a signal of the first voltage end; the reset sub-circuit is respectively connected with a reset control signal end, an initial voltage end, a fourth node and an anode end of the light-emitting element, and is used for writing a signal of the initial voltage end into the fourth node and the anode end of the light-emitting element under the control of a signal of the reset control signal end; the first light-emitting control sub-circuit is respectively connected with a first voltage end, a light-emitting control signal end and a fifth node, and is used for providing a signal of the first voltage end for the fifth node under the control of a signal of the light-emitting control signal end.

In some exemplary embodiments, the reset sub-circuit includes a first transistor and a seventh transistor, the compensation sub-circuit includes a second transistor and a first capacitor, the driving sub-circuit includes a third transistor, the write sub-circuit includes a fourth transistor, and the first light emission control sub-circuit includes a fifth transistor, wherein: a control electrode of the first transistor is connected with a reset control signal end, a first electrode of the first transistor is connected with an initial voltage end, and a second electrode of the first transistor is connected with a fourth node; a control electrode of the second transistor is connected with a first scanning signal end, a first electrode of the second transistor is connected with a fourth node, and a second electrode of the second transistor is connected with a sixth node; a control electrode of the third transistor is connected with a fourth node, a first electrode of the third transistor is connected with a fifth node, and a second electrode of the third transistor is connected with a sixth node; one end of the first capacitor is connected with the fourth node, and the other end of the first capacitor is connected with the first voltage end; a control electrode of the fourth transistor is connected with a first scanning signal end, a first electrode of the fourth transistor is connected with a display data signal end, and a second electrode of the fourth transistor is connected with a fifth node; a control electrode of the fifth transistor is connected with a light-emitting control signal end, a first electrode of the fifth transistor is connected with a first voltage end, and a second electrode of the fifth transistor is connected with a fifth node; a control electrode of the seventh transistor is connected with a reset control signal end, a first electrode of the seventh transistor is connected with an initial voltage end, and a second electrode of the seventh transistor is connected with an anode end of the light-emitting element.

The embodiment of the present disclosure also provides a display device, including: a pixel circuit as claimed in any one of the above.

The embodiment of the present disclosure further provides a driving method of a pixel circuit, for driving the pixel circuit as described in any one of the above, where the pixel circuit has a plurality of scanning periods, and in one scanning period, the driving method includes: the current control sub-circuit receives the display data signal and the light-emitting control signal, controls whether to generate the driving current according to the light-emitting control signal, and controls the current intensity of the generated driving current according to the display data signal; the gray scale control sub-circuit receives a mode control signal and a driving current generated by the current control sub-circuit, and drives the light-emitting element for a first time when the mode control signal is in a first display mode; when the mode control signal is in a second display mode, the light emitting element is driven for a second duration, at least one of the first duration and the second duration being comprised of a plurality of pulse periods.

According to the pixel circuit, the driving method thereof and the display device, the light-emitting elements are driven in different time lengths according to different display modes, and at least one of the different time lengths is composed of a plurality of pulse time periods, so that the light-emitting time can be dispersed in the whole light-emitting stage in the low gray scale display mode, the image flicker phenomenon in the low gray scale display mode is avoided, and the display effect of the display device in high and low gray scales is improved. In addition, the pixel circuit has less occupied space due to the fact that the number of transistors in the pixel circuit is small, and therefore pixel resolution of the display device is improved.

Additional features and advantages of the disclosure will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by the practice of the disclosure. Other advantages of the disclosure may be realized and attained by the instrumentalities and combinations particularly pointed out in the specification and the drawings.

Drawings

The accompanying drawings are included to provide an understanding of the disclosed embodiments and are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the examples serve to explain the principles of the disclosure and not to limit the disclosure.

Fig. 1 is a schematic structural diagram of a pixel circuit according to an embodiment of the disclosure;

fig. 2 is a second schematic structural diagram of a pixel circuit according to an embodiment of the disclosure;

fig. 3 is a third schematic structural diagram of a pixel circuit according to an embodiment of the disclosure;

fig. 4 is an equivalent circuit diagram of a pixel circuit provided in an embodiment of the present disclosure;

FIG. 5 is a timing diagram illustrating the operation of the pixel circuit shown in FIG. 4 during a scan period;

fig. 6 is a fourth schematic structural diagram of a pixel circuit according to an embodiment of the disclosure;

fig. 7 is a second equivalent circuit diagram of a pixel circuit according to an embodiment of the disclosure;

FIG. 8 is a timing diagram illustrating the operation of the pixel circuit shown in FIG. 7 during a scan period;

fig. 9 is a flowchart illustrating a driving method of a pixel circuit according to an embodiment of the disclosure.

Description of reference numerals:

EM-light emission control signal terminal; DataI-display data signal terminal;

VDD-first voltage terminal; VSS — second voltage terminal;

DataT-mode control signal terminal; Reset-Reset control signal terminal;

N1-N6-nodes; C1-C2-capacitance;

GateA-scanning signal terminal; T1-T11-transistor;

EL-light emitting element; vinit-initial voltage terminal;

control-a first Control signal terminal; hf represents the pulse control signal terminal.

Detailed Description

To make the objects, technical solutions and advantages of the present disclosure more apparent, embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. It should be noted that, in the present disclosure, the embodiments and features of the embodiments may be arbitrarily combined with each other without conflict.

Unless otherwise defined, technical or scientific terms used in the disclosure of the embodiments of the present disclosure should have the ordinary meaning as understood by those having ordinary skill in the art to which the present disclosure belongs. The use of "first," "second," and similar terms in the embodiments of the disclosure is not intended to indicate any order, quantity, or importance, but rather to distinguish one element from another. The word "comprising" or "comprises", and the like, means that the element or item preceding the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items.

It will be appreciated by those skilled in the art that the transistors employed in all embodiments of the present disclosure may be thin film transistors or field effect transistors or other devices of the same characteristics. Preferably, the thin film transistor used in the embodiment of the present disclosure may be an oxide semiconductor transistor. Since the source and drain of the transistor used herein are symmetrical, the source and drain may be interchanged. In the embodiment of the present disclosure, in order to distinguish two electrodes of a transistor except for a gate, one of the electrodes is referred to as a first electrode, the other electrode is referred to as a second electrode, the first electrode may be a source or a drain, and the second electrode may be a drain or a source.

The embodiment of the present disclosure provides a pixel circuit, and fig. 1 is a schematic structural diagram of the pixel circuit according to the embodiment of the present disclosure, and as shown in fig. 1, the pixel circuit according to the embodiment of the present disclosure includes: a current control sub-circuit, a gray scale control sub-circuit, and a light emitting element.

The current control sub-circuit is respectively connected with the first voltage end VDD, the display data signal end DataI and the light-emitting control signal end EM, and is used for receiving the display data signal of the display data signal end DataI and the light-emitting control signal of the light-emitting control signal end EM, controlling whether to generate the driving current according to the light-emitting control signal, and controlling the current intensity of the generated driving current according to the display data signal.

The gray scale control sub-circuit is respectively connected with the mode control signal end DataT, the light-emitting control signal end EM and the pulse control signal end Hf, and is used for receiving the driving current of the current control sub-circuit and the mode control signal of the mode control signal end DataT, and driving the light-emitting element with a first time length when the mode control signal is in a first display mode; when the mode control signal is in the second display mode, the light emitting element is driven for a second duration, and at least one of the first duration and the second duration is comprised of a plurality of pulse periods.

According to the pixel circuit provided by the embodiment of the disclosure, the light emitting elements are driven in different time lengths according to different display modes, and at least one of the different time lengths is composed of a plurality of pulse time periods, so that in the low gray scale display mode, the light emitting time can be dispersed in the whole light emitting stage, the image flicker phenomenon occurring in the low gray scale display mode is avoided, and the display effect of the display device in high and low gray scales is improved.

The pixel circuit of the embodiment of the present disclosure can be implemented by various schemes. The following description will be made by taking two display modes (one is a high gray scale display mode, and the other is a low gray scale display mode) as an example, the pixel circuit of the embodiment of the disclosure is also applicable to three or more display modes, and the gray scale range corresponding to each display mode can be set according to actual situations, which is not limited by the disclosure.

In some exemplary embodiments, as shown in fig. 2, the gray scale control sub-circuit provided by the embodiments of the present disclosure includes: a mode control sub-circuit, an inverter sub-circuit, and a third emission control sub-circuit.

The mode Control sub-circuit is respectively connected to the first Control signal terminal Control, the mode Control signal terminal DataT, and the second node N2, and is configured to write the mode Control signal of the mode Control signal terminal DataT into the second node N2 under the Control of the first Control signal terminal Control.

The inverter sub-circuit is respectively connected to the emission control signal terminal EM, the pulse control signal terminal Hf, the first node N1 and the second node N2, and is configured to write the emission control signal of the emission control signal terminal EM or the pulse control signal of the pulse control signal terminal Hf into the first node N1 under the control of the signal of the second node N2.

The third light-emitting control sub-circuit is respectively connected with the first node N1, the current control sub-circuit and the light-emitting element, and is used for receiving the driving current of the current control sub-circuit and controlling the time for the driving current to flow through the light-emitting element under the control of the signal of the first node N1.

In some exemplary embodiments, as shown in fig. 3, the first Control signal terminal Control may be the first scan signal terminal GateA.

In some exemplary embodiments, as shown in fig. 3, the current control sub-circuit includes: the drive sub-circuit, the write sub-circuit, the compensation sub-circuit, the reset sub-circuit, the first light-emitting control sub-circuit and the second light-emitting control sub-circuit.

The driving sub-circuit is respectively connected with the fourth node N4, the fifth node N5 and the sixth node N6, and is used for supplying a driving current to the sixth node N6 under the control of signals of the fourth node N4 and the fifth node N5; the write-in sub-circuit is respectively connected to the first scan signal terminal GateA, the display data signal terminal DataI, and the fifth node N5, and is configured to write the display data signal of the display data signal terminal DataI into the fifth node N5 under the control of the first scan signal terminal GateA; the compensation sub-circuit is respectively connected with the first voltage end VDD, the first scanning signal end GateA, the fourth node N4 and the sixth node N6, and is used for compensating the fourth node N4 under the control of the first scanning signal end GateA and the first voltage signal of the first voltage end VDD; the Reset sub-circuit is respectively connected with the Reset control signal terminal Reset, the initial voltage terminal Vinit, the fourth node N4 and the anode terminal of the light emitting element, and is used for writing the initial voltage signal of the initial voltage terminal Vinit into the fourth node N4 and the anode terminal of the light emitting element under the control of the Reset control signal terminal Reset; the first light-emitting control sub-circuit is respectively connected with the first voltage terminal VDD, the light-emitting control signal terminal EM and the fifth node N5, and is configured to provide the first voltage signal of the first voltage terminal VDD to the fifth node N5 under the control of the light-emitting control signal terminal EM; the second light-emission control sub-circuit is connected to the light-emission control signal terminal EM, the third node N3 and the sixth node N6, respectively, for allowing the driving current to pass between the sixth node N6 and the third node N3 under the control of the light-emission control signal terminal EM.

In some exemplary embodiments, as shown in fig. 4, the reset sub-circuit includes a first transistor T1 and a seventh transistor T7, the compensation sub-circuit includes a second transistor T2 and a first capacitor C1, the driving sub-circuit includes a third transistor T3, the write sub-circuit includes a fourth transistor T4, the first light emission control sub-circuit includes a fifth transistor T5, and the second light emission control sub-circuit includes a sixth transistor T6.

A control electrode of the first transistor T1 is connected to the Reset control signal terminal Reset, a first electrode of the first transistor T1 is connected to the initial voltage terminal Vinit, and a second electrode of the first transistor T1 is connected to the fourth node N4; a control electrode of the second transistor T2 is connected to the first scan signal terminal GateA, a first electrode of the second transistor T2 is connected to the fourth node N4, and a second electrode of the second transistor T2 is connected to the sixth node N6; one end of the first capacitor C1 is connected to the fourth node N4, and the other end of the first capacitor C1 is connected to the first voltage terminal VDD; a control electrode of the third transistor T3 is connected to the fourth node N4, a first electrode of the third transistor T3 is connected to the fifth node N5, and a second electrode of the third transistor T3 is connected to the sixth node N6; a control electrode of the fourth transistor T4 is connected to the first scan signal terminal GateA, a first electrode of the fourth transistor T4 is connected to the display data signal terminal DataI, and a second electrode of the fourth transistor T4 is connected to the fifth node N5; a control electrode of the fifth transistor T5 is connected to the emission control signal terminal EM, a first electrode of the fifth transistor T5 is connected to the first voltage terminal VDD, and a second electrode of the fifth transistor T5 is connected to the fifth node N5; a control electrode of the sixth transistor T6 is connected to the emission control signal terminal EM, a first electrode of the sixth transistor T6 is connected to the sixth node N6, and a second electrode of the sixth transistor T6 is connected to the third node N3; a control electrode of the seventh transistor T7 is connected to the Reset control signal terminal Reset, a first electrode of the seventh transistor T7 is connected to the initial voltage terminal Vinit, and a second electrode of the seventh transistor T7 is connected to the anode terminal of the light emitting element EL.

In some exemplary embodiments, as shown in fig. 4, the third light emission control sub-circuit includes an eighth transistor T8, the inverter sub-circuit includes a ninth transistor T9 and a tenth transistor T10, and the mode control sub-circuit includes an eleventh transistor T11 and a second capacitor C2.

A control electrode of the eighth transistor T8 is connected to the first node N1, a first electrode of the eighth transistor T8 is connected to the third node N3, and a second electrode of the eighth transistor T8 is connected to the anode terminal of the light emitting element EL; a control electrode of the ninth transistor T9 is connected to the second node N2, a first electrode of the ninth transistor T9 is connected to the emission control signal terminal EM, and a second electrode of the ninth transistor T9 is connected to the first node N1; a control electrode of the tenth transistor T10 is connected to the second node N2, a first electrode of the tenth transistor T10 is connected to the pulse control signal terminal Hf, and a second electrode of the tenth transistor T10 is connected to the first node N1; a control electrode of the eleventh transistor T11 is connected to the first scan signal terminal GateA, a first electrode of the eleventh transistor T11 is connected to the mode control signal terminal DataT, and a second electrode of the eleventh transistor T11 is connected to the second node N2; one end of the second capacitor C2 is connected to the second node N2, and the other end of the second capacitor C2 is connected to the initial voltage terminal Vinit.

One exemplary structure of the current control sub-circuit and the gray scale control sub-circuit is shown in fig. 4. It is easily understood by those skilled in the art that the implementation of the current control sub-circuit and the gray scale control sub-circuit is not limited thereto as long as their respective functions can be implemented.

As shown in fig. 4, in the pixel circuit provided in the embodiment of the present disclosure, the current control sub-circuit includes: the driving sub-circuit includes a third transistor T3, the compensation sub-circuit includes a second transistor T2 and a first capacitor C1, the reset sub-circuit includes a first transistor T1 and a seventh transistor T7, the writing sub-circuit includes a fourth transistor T4, the first light emission control sub-circuit includes a fifth transistor T5, the second light emission control sub-circuit includes a sixth transistor T6, the mode control sub-circuit includes an eleventh transistor T11 and a second capacitor C2, the inverter sub-circuit includes a ninth transistor T9 and a tenth transistor T10, and the third light emission control sub-circuit includes an eighth transistor T8.

A control electrode of the third transistor T3 is connected to the fourth node N4, a first electrode of the third transistor T3 is connected to the fifth node N5, and a second electrode of the third transistor T3 is connected to the sixth node N6; a control electrode of the second transistor T2 is connected to the first scan signal terminal GateA, a first electrode of the second transistor T2 is connected to the fourth node N4, and a second electrode of the second transistor T2 is connected to the sixth node N6; one end of the first capacitor C1 is connected to the fourth node N4, and the other end of the first capacitor C1 is connected to the first voltage terminal VDD; a control electrode of the first transistor T1 is connected to a Reset control signal terminal Reset, a first electrode of the first transistor T1 is connected to an initial voltage terminal Vinit, and a second electrode of the first transistor T1 is connected to a fourth node N4; a control electrode of the seventh transistor T7 is connected to the Reset control signal terminal Reset, a first electrode of the seventh transistor T7 is connected to the initial voltage terminal Vinit, and a second electrode of the seventh transistor T7 is connected to the anode terminal of the light emitting element EL; a control electrode of the fourth transistor T4 is connected to the first scan signal terminal GateA, a first electrode of the fourth transistor T4 is connected to the display data signal terminal DataI, and a second electrode of the fourth transistor T4 is connected to the fifth node N5; a control electrode of the fifth transistor T5 is connected to the emission control signal terminal EM, a first electrode of the fifth transistor T5 is connected to the first voltage terminal VDD, and a second electrode of the fifth transistor T5 is connected to the fifth node N5; a control electrode of the sixth transistor T6 is connected to the emission control signal terminal EM, a first electrode of the sixth transistor T6 is connected to the sixth node N6, and a second electrode of the sixth transistor T6 is connected to the third node N3; a control electrode of the eleventh transistor T11 is connected to the first scan signal terminal GateA, a first electrode of the eleventh transistor T11 is connected to the mode control signal terminal DataT, and a second electrode of the eleventh transistor T11 is connected to the second node N2; one end of the second capacitor C2 is connected to the second node N2, and the other end of the second capacitor C2 is connected to the initial voltage terminal Vinit; a control electrode of the ninth transistor T9 is connected to the second node N2, a first electrode of the ninth transistor T9 is connected to the emission control signal terminal EM, and a second electrode of the ninth transistor T9 is connected to the first node N1; a control electrode of the tenth transistor T10 is connected to the second node N2, a first electrode of the tenth transistor T10 is connected to the pulse control signal terminal Hf, and a second electrode of the tenth transistor T10 is connected to the first node N1; a control electrode of the eighth transistor T8 is connected to the first node N1, a first electrode of the eighth transistor T8 is connected to the third node N3, and a second electrode of the eighth transistor T8 is connected to the anode terminal of the light emitting element EL.

An exemplary structure of the driving sub-circuit, the writing sub-circuit, the compensation sub-circuit, the reset sub-circuit, the first light emission control sub-circuit, the second light emission control sub-circuit, the mode control sub-circuit, the inverter sub-circuit, and the third light emission control sub-circuit is shown in fig. 4. It is easily understood by those skilled in the art that the implementation of the above sub-circuits is not limited thereto as long as the respective functions thereof can be realized. Because the number of transistors in the pixel circuit is smaller, the occupied space of the pixel circuit is smaller, and therefore the pixel resolution of the display device is improved.

In some exemplary embodiments, the Light Emitting elements EL (including the first Light Emitting element EL1 to the nth Light Emitting element ELN) may be micro Light Emitting diodes, or may be sub-millimeter Light Emitting diodes (Mini LEDs), Organic Light Emitting Diodes (OLEDs), and other types of Light Emitting diodes. In practical applications, the structure of the light emitting element EL needs to be designed and determined according to practical application environments, and is not limited herein. In the following, the light-emitting element EL is described as an example of a micro light-emitting diode.

In some exemplary embodiments, the first to ninth transistors T1 to T9 and the eleventh transistor T11 are all first type transistors, the first type transistors include N type transistors or P type transistors, the tenth transistor T10 is a second type transistor, the second type transistor includes P type transistors or N type transistors, and the second type transistor is different from the first type transistor in transistor type, that is, when the first type transistor is an N type transistor, the second type transistor is a P type transistor, and when the first type transistor is a P type transistor, the second type transistor is an N type transistor.

In some exemplary embodiments, considering that the leakage current of the low temperature polysilicon thin film transistor is small, all transistors of the embodiments of the present disclosure may be low temperature polysilicon thin film transistors, and the thin film transistor may be a bottom gate thin film transistor or a top gate thin film transistor, as long as the switching function is achieved.

In some exemplary embodiments, the first capacitor C1 to the second capacitor C2 may be a liquid crystal capacitor formed by a pixel electrode and a common electrode, or may be an equivalent capacitor formed by a liquid crystal capacitor formed by a pixel electrode and a common electrode and a storage capacitor, which is not limited by the disclosure.

In some exemplary embodiments, the pulse control signal of the pulse control signal terminal Hf may be generated by a driving chip (IC).

In this embodiment, the pulse control signal of the pulse control signal terminal Hf may be generated by a driving chip (IC), and in full screen synchronization, the mode control signal of the mode control signal terminal DataT is read in during the compensation phase, and the switching states of the ninth transistor T9 and the tenth transistor T10 are determined, and since a low-level pulse of the pulse control signal terminal Hf may occur during the compensation phase (i.e., the second phase T2 described later), the sixth transistor T6 (i.e., the second emission control sub-circuit) must be provided, and remain turned off during the compensation phase.

Fig. 5 is an operation timing diagram of the pixel circuit shown in fig. 4, wherein VH is high, VL1 is first low, and VL2 is second low, in this embodiment, the gray-scale control sub-circuit transmits the mode control signal to the inverter sub-circuit to determine the on-off time of the third light-emitting control sub-circuit while the current control sub-circuit completes the threshold voltage compensation. The technical solution of the embodiment of the present disclosure is further explained by the working process of the pixel circuit.

Taking the first to ninth transistors T1 to T9 and the eleventh transistor T11 of the pixel circuit provided in the embodiment of the present disclosure as P-type transistors and the tenth transistor T10 as N-type transistors as an example, the operation of one pixel circuit in one frame period will be described with reference to the pixel circuit shown in fig. 4 and the operation timing diagram shown in fig. 5. As shown in fig. 4, the pixel circuit provided by the embodiment of the present disclosure includes 11 transistor units (T1-T11), 2 capacitor units (C1-C2), and 3 voltage terminals (VDD, VSS, Vinit), wherein the first voltage terminal VDD continuously provides a high level signal, the second voltage terminal VSS continuously provides a low level signal, and the initial voltage terminal Vinit provides an initial voltage signal. The working process comprises the following steps:

in a first phase T1, i.e., a Reset phase, the Reset control signal terminal Reset is pulled low, the first transistor T1 and the seventh transistor T7 are turned on, and the gate of the third transistor T3, one end of the first capacitor C1 (i.e., the fourth node N4) and the anode end of the light emitting element EL are Reset to the initial voltage of the initial voltage terminal Vinit; at this time, the light emission control signal terminal EM is at a high level, and the fifth transistor T5 and the sixth transistor T6 remain turned off;

a second stage T2, namely a threshold voltage compensation and display data reading stage, in which the GateA voltage at the first scan signal terminal is pulled low, the fourth transistor T4, the third transistor T3 and the second transistor T2 are turned on, the display data signal at the display data signal terminal DataI is inputted, and the display data signal and the threshold voltage (VdataI + Vth) are stored on the first capacitor C1; meanwhile, the eleventh transistor T11 is turned on, the mode control signal of the mode control signal terminal DataT is input, and the mode control signal VdataT is stored in the second capacitor C2, the mode control signal VdataT is a high level signal or a low level signal, only any one of the ninth transistor T9 and the tenth transistor T10 can be turned on at the same time, when the tenth transistor T10 is turned on, the ninth transistor T9 is turned off, the pulse control signal of the pulse control signal terminal Hf is input to the gate of the eighth transistor T8 (i.e., the first node N1), and when the ninth transistor T9 is turned on, the tenth transistor T10 is turned off, the light emission control signal of the light emission control signal terminal EM is input to the gate of the eighth transistor T8 (i.e., the first node N1);

in the third stage T3, i.e., the light emitting stage, a low level signal is input to the light emitting control signal terminal EM, the fifth transistor T5 and the sixth transistor T6 are turned on, the light emitting duration of the light emitting element EL is determined by the operating state of the eighth transistor T8, when the display mode is the high gray scale mode, the gate of the eighth transistor T8 is connected to the signal of the light emitting control signal terminal EM, and when the display mode is the low gray scale mode, the gate of the eighth transistor T8 is connected to the pulse control signal of the pulse control signal terminal Hf, so that two different display modes of high gray scale and low gray scale are implemented.

By integrating the above steps, when the display sub-pixel displays the low gray scale, the pulse control signal of the pulse control signal terminal Hf can be used to disperse the light emitting time of the light emitting element EL in the whole light emitting stage (in this embodiment, when the pulse control signal is at low level, the light emitting element EL emits light) within one frame time, so as to reduce the flicker phenomenon in the low gray scale mode; when the display sub-pixel displays high gray scale, the light-emitting element EL can continuously emit light in the whole light-emitting stage through the light-emitting control signal of the light-emitting control signal end EM in one frame time.

In other exemplary embodiments, as shown in fig. 6, the first Control signal terminal Control may also be a Reset Control signal terminal Reset.

In other exemplary embodiments, as shown in fig. 6, the current control sub-circuit may include: the drive sub-circuit, the write sub-circuit, the compensation sub-circuit, the reset sub-circuit and the first light-emitting control sub-circuit.

The driving sub-circuit is respectively connected with the fourth node N4, the fifth node N5 and the sixth node N6, and is used for supplying a driving current to the sixth node N6 under the control of signals of the fourth node N4 and the fifth node N5; the write-in sub-circuit is respectively connected to the first scan signal terminal GateA, the display data signal terminal DataI, and the fifth node N5, and is configured to write the display data signal of the display data signal terminal DataI into the fifth node N5 under the control of the first scan signal terminal GateA; the compensation sub-circuit is respectively connected with the first voltage end VDD, the first scanning signal end GateA, the fourth node N4 and the sixth node N6, and is used for compensating the fourth node N4 under the control of the first scanning signal end GateA and the first voltage signal of the first voltage end VDD; the Reset sub-circuit is respectively connected with the Reset control signal terminal Reset, the initial voltage terminal Vinit, the fourth node N4 and the anode terminal of the light emitting element, and is used for writing the initial voltage signal of the initial voltage terminal Vinit into the fourth node N4 and the anode terminal of the light emitting element under the control of the Reset control signal terminal Reset; the first light-emitting control sub-circuit is respectively connected to the first voltage terminal VDD, the light-emitting control signal terminal EM, and the fifth node N5, and is configured to provide the first voltage signal of the first voltage terminal VDD to the fifth node N5 under the control of the light-emitting control signal terminal EM.

In some exemplary embodiments, as shown in fig. 7, the driving sub-circuit includes a third transistor T3, the compensating sub-circuit includes a second transistor T2 and a first capacitor C1, the resetting sub-circuit includes a first transistor T1 and a seventh transistor T7, the writing sub-circuit includes a fourth transistor T4, and the first light-emitting control sub-circuit includes a fifth transistor T5.

A control electrode of the third transistor T3 is connected to the fourth node N4, a first electrode of the third transistor T3 is connected to the fifth node N5, and a second electrode of the third transistor T3 is connected to the sixth node N6; a control electrode of the second transistor T2 is connected to the first scan signal terminal GateA, a first electrode of the second transistor T2 is connected to the fourth node N4, and a second electrode of the second transistor T2 is connected to the sixth node N6; one end of the first capacitor C1 is connected to the fourth node N4, and the other end of the first capacitor C1 is connected to the first voltage terminal VDD; a control electrode of the first transistor T1 is connected to a Reset control signal terminal Reset, a first electrode of the first transistor T1 is connected to an initial voltage terminal Vinit, and a second electrode of the first transistor T1 is connected to a fourth node N4; a control electrode of the seventh transistor T7 is connected to the Reset control signal terminal Reset, a first electrode of the seventh transistor T7 is connected to the initial voltage terminal Vinit, and a second electrode of the seventh transistor T7 is connected to the anode terminal of the light emitting element EL; a control electrode of the fourth transistor T4 is connected to the first scan signal terminal GateA, a first electrode of the fourth transistor T4 is connected to the display data signal terminal DataI, and a second electrode of the fourth transistor T4 is connected to the fifth node N5; a control electrode of the fifth transistor T5 is connected to the emission control signal terminal EM, a first electrode of the fifth transistor T5 is connected to the first voltage terminal VDD, and a second electrode of the fifth transistor T5 is connected to the fifth node N5.

In some exemplary embodiments, as shown in fig. 7, the mode control sub-circuit includes an eleventh transistor T11 and a second capacitor C2, the inverter sub-circuit includes a ninth transistor T9 and a tenth transistor T10, and the third light emission control sub-circuit includes an eighth transistor T8.

A control electrode of the eleventh transistor T11 is connected to the Reset control signal terminal Reset, a first electrode of the eleventh transistor T11 is connected to the mode control signal terminal DataT, and a second electrode of the eleventh transistor T11 is connected to the second node N2; one end of the second capacitor C2 is connected to the second node N2, and the other end of the second capacitor C2 is connected to the initial voltage terminal Vinit; a control electrode of the ninth transistor T9 is connected to the second node N2, a first electrode of the ninth transistor T9 is connected to the emission control signal terminal EM, and a second electrode of the ninth transistor T9 is connected to the first node N1; a control electrode of the tenth transistor T10 is connected to the second node N2, a first electrode of the tenth transistor T10 is connected to the pulse control signal terminal Hf, and a second electrode of the tenth transistor T10 is connected to the first node N1; a control electrode of the eighth transistor T8 is connected to the first node N1, a first electrode of the eighth transistor T8 is connected to the sixth node N6, and a second electrode of the eighth transistor T8 is connected to the anode terminal of the light emitting element EL.

Another exemplary structure of the current control sub-circuit and the gray scale control sub-circuit is shown in fig. 7. It is easily understood by those skilled in the art that the implementation of the current control sub-circuit and the gray scale control sub-circuit is not limited thereto as long as their respective functions can be implemented.

As shown in fig. 7, in the pixel circuit provided in this embodiment, the current control sub-circuit includes: the gray scale control sub-circuit comprises a mode control sub-circuit, an inverter sub-circuit and a third light emitting control sub-circuit, the driving sub-circuit comprises a third transistor T3, the compensation sub-circuit comprises a second transistor T2 and a first capacitor C1, the reset sub-circuit comprises a first transistor T1 and a seventh transistor T7, the writing sub-circuit comprises a fourth transistor T4, the first light emitting control sub-circuit comprises a fifth transistor T5, the mode control sub-circuit comprises an eleventh transistor T11 and a second capacitor C2, the inverter sub-circuit comprises a ninth transistor T9 and a tenth transistor T10, and the third light emitting control sub-circuit comprises an eighth transistor T8.

A control electrode of the third transistor T3 is connected to the fourth node N4, a first electrode of the third transistor T3 is connected to the fifth node N5, and a second electrode of the third transistor T3 is connected to the sixth node N6; a control electrode of the second transistor T2 is connected to the first scan signal terminal GateA, a first electrode of the second transistor T2 is connected to the fourth node N4, and a second electrode of the second transistor T2 is connected to the sixth node N6; one end of the first capacitor C1 is connected to the fourth node N4, and the other end of the first capacitor C1 is connected to the first voltage terminal VDD; a control electrode of the first transistor T1 is connected to a Reset control signal terminal Reset, a first electrode of the first transistor T1 is connected to an initial voltage terminal Vinit, and a second electrode of the first transistor T1 is connected to a fourth node N4; a control electrode of the seventh transistor T7 is connected to the Reset control signal terminal Reset, a first electrode of the seventh transistor T7 is connected to the initial voltage terminal Vinit, and a second electrode of the seventh transistor T7 is connected to the anode terminal of the light emitting element EL; a control electrode of the fourth transistor T4 is connected to the first scan signal terminal GateA, a first electrode of the fourth transistor T4 is connected to the display data signal terminal DataI, and a second electrode of the fourth transistor T4 is connected to the fifth node N5; a control electrode of the fifth transistor T5 is connected to the emission control signal terminal EM, a first electrode of the fifth transistor T5 is connected to the first voltage terminal VDD, and a second electrode of the fifth transistor T5 is connected to the fifth node N5; a control electrode of the eleventh transistor T11 is connected to the Reset control signal terminal Reset, a first electrode of the eleventh transistor T11 is connected to the mode control signal terminal DataT, and a second electrode of the eleventh transistor T11 is connected to the second node N2; one end of the second capacitor C2 is connected to the second node N2, and the other end of the second capacitor C2 is connected to the initial voltage terminal Vinit; a control electrode of the ninth transistor T9 is connected to the second node N2, a first electrode of the ninth transistor T9 is connected to the emission control signal terminal EM, and a second electrode of the ninth transistor T9 is connected to the first node N1; a control electrode of the tenth transistor T10 is connected to the second node N2, a first electrode of the tenth transistor T10 is connected to the pulse control signal terminal Hf, and a second electrode of the tenth transistor T10 is connected to the first node N1; a control electrode of the eighth transistor T8 is connected to the first node N1, a first electrode of the eighth transistor T8 is connected to the sixth node N6, and a second electrode of the eighth transistor T8 is connected to the anode terminal of the light emitting element EL.

Because the number of transistors in the pixel circuit is smaller, the occupied space of the pixel circuit is smaller, and therefore the pixel resolution of the display device is improved.

In some exemplary embodiments, the pulse control signal of the pulse control signal terminal Hf may be generated by a shift register unit and shifted row by row.

In the present embodiment, the mode control signal of the mode control signal terminal DataT is read in at a timing advanced by one horizontal scan period (1H period), that is, the mode control signal of the mode control signal terminal DataT is read in at the reset stage (that is, the first stage T1 'described later) to determine the switching states of the ninth transistor T9 and the tenth transistor T10, regardless of whether the tenth transistor T10 is turned on or the ninth transistor T9 is turned on, and the gate of the eighth transistor T8 is at a high level and remains turned off at the first stage T1', and thus, the sixth transistor T6 (that is, the second light emission control sub-circuit) may be cancelled, and the pulse control signal of the pulse control signal terminal Hf is generated by the shift register unit, thereby improving the load capacity of the pulse control signal.

The pixel circuit provided by the embodiment of the disclosure can disperse the light emitting time in the whole light emitting stage in the low gray scale display mode, thereby avoiding the image flicker phenomenon in the low gray scale display mode, and improving the display effect of the display device under the high and low gray scales.

In some exemplary embodiments, the first to fifth transistors T1 to T5, the seventh to ninth transistors T7 to T9, and the eleventh transistor T11 are all first type transistors, the first type transistors include N-type transistors or P-type transistors, the tenth transistor T10 is a second type transistor, the second type transistors include P-type transistors or N-type transistors, and the second type transistors are different from the first type transistors in transistor type, that is, when the first type transistors are N-type transistors, the second type transistors are P-type transistors, and when the first type transistors are P-type transistors, the second type transistors are N-type transistors.

The technical solution of the embodiment of the present disclosure is further explained by the working process of the pixel circuit. Here, taking the pixel circuit in which the first to fifth transistors T1 to T5, the seventh to ninth transistors T7 to T9, and the eleventh transistor T11 are all P-type transistors, and the tenth transistor T10 is an N-type transistor as an example, the operation of one pixel circuit in one frame period is described with reference to the pixel circuit shown in fig. 7 and the operation timing chart shown in fig. 8. As shown in fig. 7, the pixel circuit provided by the embodiment of the present disclosure includes 10 transistor units (T1-T5, T7-T11), 2 capacitor units (C1-C2), and 3 voltage terminals (VDD, VSS, Vinit), wherein the first voltage terminal VDD continuously provides a high level signal, the second voltage terminal VSS continuously provides a low level signal, and the initial voltage terminal Vinit provides an initial voltage signal. The working process comprises the following steps:

the first stage T1', that is, the Reset stage, the Reset control signal terminal Reset is pulled low, the first transistor T1 and the seventh transistor T7 are turned on, the gate of the third transistor T3 and one terminal of the first capacitor C1 (that is, the fourth node N4) and the anode terminal of the light emitting element EL are Reset to the initial voltage of the initial voltage terminal Vinit, and at the same time, the eleventh transistor T11 is turned on, the mode control signal of the mode control signal terminal DataT is input, and the mode control signal VdataT is stored on the second capacitor C2, the mode control signal VdataT is a high level signal or a low level signal, only any one of the ninth transistor T9 and the tenth transistor T10 can be turned on at the same time, when the tenth transistor T10 is turned on, the ninth transistor T9 is turned off, the gate of the eighth transistor T8 (that is, the first node N1) is input as the pulse control signal of the pulse control signal terminal Hf, and when the ninth transistor T9 is turned on, the tenth transistor T10 is turned off, and the gate (i.e., the first node N1) of the eighth transistor T8 is inputted with the emission control signal of the emission control signal terminal EM, in this embodiment, no matter the pulse control signal of the pulse control signal terminal Hf or the emission control signal of the emission control signal terminal EM, in the stage T1 and the subsequent stage T2, the pulse control signal and the emission control signal are continuous high level signals, so the eighth transistor T8 is kept off, and the normal operation of the reset operation in the stage T1, the threshold voltage compensation in the stage T2, and the display data reading operation are ensured. At this time, the emission control signal terminal EM is at a high level, and the fifth transistor T5 and the sixth transistor T6 remain turned off.

The second phase T2', i.e., the threshold voltage compensation and display data reading phase, when the GateA voltage at the first scan signal terminal is pulled low, the fourth transistor T4, the third transistor T3 and the second transistor T2 are turned on, the display data signal at the display data signal terminal DataI is inputted, and the display data signal and the threshold voltage (VdataI + Vth) are stored on the first capacitor C1.

In the third stage T3', i.e., the light emitting stage, the light emitting control signal terminal EM inputs a low level signal, the fifth transistor T5 is turned on, the light emitting duration of the light emitting element EL is determined by the operating state of the eighth transistor T8, when the display mode is the high gray scale mode, the gate of the eighth transistor T8 is connected to the light emitting control signal provided by the light emitting control signal terminal EM, and the light emitting control signal provides the operating voltage for the gate of the eighth transistor T8 in the light emitting stage; when the display mode is the low gray scale mode, the gate of the eighth transistor T8 is connected to the pulse control signal provided by the pulse control signal terminal Hf, the pulse control signal is composed of a plurality of pulse periods in the light emitting stage, and the gate of the eighth transistor T8 is provided with the operating voltage only in the pulse periods. Thus, by controlling whether the gate of the eighth transistor T8 is connected to the emission control signal provided by the emission control signal terminal EM or the pulse control signal provided by the pulse control signal terminal Hf, two different display modes of high and low gray levels can be realized.

Illustratively, the pulse control signal is a high-frequency pulse signal, for example, the frequency of the pulse control signal is between 3000Hz and 60000Hz, and may be 3000Hz or 60000Hz, for example. For example, the frequency of the reset control signal and the frequency of the first scan signal take values between 60Hz and 120Hz, and may be, for example, 60Hz or 120 Hz. For example, the frame frequency of the display panel is 60Hz, that is, the display panel can display 60 frames of images within 1s, and the display time of each frame of image is equal. Thus, in the case of a high frequency signal with a pulse control signal of 3000Hz, in one image frame, if the light emitting element is to emit low gray scale luminance, the element to be driven can receive about 50 active periods of the high frequency signal during the light emitting phase.

The embodiment of the present disclosure further provides a display device, where the display device includes a plurality of sub-pixels arranged in an array, and each sub-pixel includes the pixel circuit described in any one of the foregoing embodiments. The display device of the embodiment of the present disclosure may be: any product or component with a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like.

In a column of sub-pixels, for at least two adjacent sub-pixels, the first scan signal terminal in the sub-pixel in the previous row is electrically connected to the first reset control signal terminal in the sub-pixel in the next row.

The embodiment of the present disclosure further provides a driving method of a pixel circuit, which is used for driving the pixel circuit as described above, where the pixel circuit has a plurality of scanning periods, and in one scanning period, as shown in fig. 9, the driving method includes steps 100 to 200.

Step 100, the current control sub-circuit receives the display data signal and the light-emitting control signal, controls whether to generate the driving current according to the light-emitting control signal, and controls the current intensity of the generated driving current according to the display data signal.

In some exemplary embodiments, the current control sub-circuit includes a driving sub-circuit, a writing sub-circuit, a compensation sub-circuit, a resetting sub-circuit, and a first light emitting control sub-circuit, and step 100 may include:

the reset sub-circuit writes a signal of an initial voltage end into a fourth node and an anode end of the light-emitting element under the control of a signal of a reset control signal end;

the write-in sub-circuit writes a signal of a display data signal end into the fifth node under the control of a signal of the first scanning signal end; the compensation sub-circuit compensates the fourth node under the control of the signal of the first scanning signal end and the signal of the first voltage end;

the first light-emitting control sub-circuit provides a signal of a first voltage end to the fifth node under the control of a signal of a light-emitting control signal end; the driving sub-circuit supplies a driving current to the sixth node under the control of signals of the fourth node and the fifth node.

In further exemplary embodiments, the current control sub-circuit includes a driving sub-circuit, a writing sub-circuit, a compensation sub-circuit, a resetting sub-circuit, a first light emission control sub-circuit, and a second light emission control sub-circuit, and step 100 may include:

the first light-emitting control sub-circuit provides a signal of a first voltage end to the fifth node under the control of a signal of a light-emitting control signal end; the driving sub-circuit provides driving current to the sixth node under the control of signals of the fourth node and the fifth node; the second light emission control sub-circuit allows the driving current to pass between the sixth node and the third node under the control of a signal of the light emission control signal terminal.

Step 200, the gray scale control sub-circuit receives a mode control signal and a driving current generated by the current control sub-circuit, and when the mode control signal is in a first display mode, the light-emitting element is driven for a first time; when the mode control signal is in a second display mode, the light emitting element is driven for a second duration, at least one of the first duration and the second duration being comprised of a plurality of pulse periods.

In some exemplary embodiments, the gray scale control sub-circuit includes: a mode control sub-circuit, an inverter sub-circuit, and a third emission control sub-circuit, step 200 comprising:

the mode control sub-circuit writes a signal of the mode control signal end into the second node under the control of the first control signal end;

the inverter sub-circuit writes a signal of a light-emitting control signal end or a signal of a pulse control signal end into the first node under the control of a signal of the second node;

the third light-emitting control sub-circuit receives the driving current of the current control sub-circuit and controls the time for which the driving current flows through the light-emitting element under the control of the signal of the first node.

In some exemplary embodiments, the first control signal terminal may be a first scan signal terminal or a reset control signal terminal.

According to the pixel circuit, the driving method thereof and the display device, the light-emitting elements are driven in different time lengths according to different display modes, and at least one of the different time lengths is composed of a plurality of pulse time periods, so that the light-emitting time can be dispersed in the whole light-emitting stage in the low gray scale display mode, the image flicker phenomenon in the low gray scale display mode is avoided, and the display effect of the display device in high and low gray scales is improved.

The following points need to be explained:

the drawings of the embodiments of the disclosure only relate to the structures related to the embodiments of the disclosure, and other structures can refer to common designs.

Without conflict, features of embodiments of the present disclosure, i.e., embodiments, may be combined with each other to arrive at new embodiments.

Although the embodiments disclosed in the present disclosure are described above, the descriptions are only for the convenience of understanding the present disclosure, and are not intended to limit the present disclosure. It will be understood by those skilled in the art of the present disclosure that various changes in form and details may be made therein without departing from the spirit and scope of the disclosure, and that the scope of the disclosure is to be limited only by the terms of the appended claims.

Claims

1. A pixel circuit, comprising: a current control sub-circuit, a gray scale control sub-circuit, and a light emitting element, wherein:

the current control sub-circuit is used for receiving a display data signal and a light-emitting control signal, controlling whether to generate a driving current according to the light-emitting control signal, and controlling the current intensity of the generated driving current according to the display data signal;

the gray scale control sub-circuit is used for receiving a mode control signal and a driving current generated by the current control sub-circuit, and when the mode control signal is in a first display mode, the light-emitting element is driven for a first time; and when the mode control signal is in a second display mode, driving the light-emitting element for a second duration, wherein at least one of the first duration and the second duration is composed of a plurality of pulse periods.

2. The pixel circuit according to claim 1, wherein the gray scale control sub-circuit comprises: a mode control sub-circuit, an inverter sub-circuit, and a third emission control sub-circuit, wherein:

the mode control sub-circuit is respectively connected with a first control signal end, a mode control signal end and a second node and is used for writing a signal of the mode control signal end into the second node under the control of the first control signal end;

the inverter subcircuit is respectively connected with a light-emitting control signal end, a pulse control signal end, a first node and the second node, and is used for writing a signal of the light-emitting control signal end or a signal of the pulse control signal end into the first node under the control of a signal of the second node;

the third light-emitting control sub-circuit is respectively connected to the first node, the current control sub-circuit and the light-emitting element, and is configured to receive a driving current of the current control sub-circuit, and control a time for the driving current to flow through the light-emitting element under control of a signal of the first node.

3. The pixel circuit according to claim 2, wherein the first control signal terminal is a first scan signal terminal, the third emission control sub-circuit comprises an eighth transistor, the inverter sub-circuit comprises a ninth transistor and a tenth transistor, and the mode control sub-circuit comprises an eleventh transistor and a second capacitor, wherein:

a control electrode of the eighth transistor is connected to the first node, a first electrode of the eighth transistor is connected to a third node, and a second electrode of the eighth transistor is connected to an anode terminal of the light-emitting element;

a control electrode of the ninth transistor is connected with the second node, a first electrode of the ninth transistor is connected with the light-emitting control signal end, and a second electrode of the ninth transistor is connected with the first node;

a control electrode of the tenth transistor is connected to the second node, a first electrode of the tenth transistor is connected to the pulse control signal terminal, and a second electrode of the tenth transistor is connected to the first node;

a control electrode of the eleventh transistor is connected to the first scan signal terminal, a first electrode of the eleventh transistor is connected to the mode control signal terminal, and a second electrode of the eleventh transistor is connected to the second node;

one end of the second capacitor is connected with the second node, and the other end of the second capacitor is connected with the initial voltage end;

the ninth transistor is a P-type transistor, and the tenth transistor is an N-type transistor; or, the ninth transistor is an N-type transistor, and the tenth transistor is a P-type transistor.

4. The pixel circuit according to claim 3, wherein the current control sub-circuit comprises a driving sub-circuit, a writing sub-circuit, a compensation sub-circuit, a resetting sub-circuit, a first emission control sub-circuit, and a second emission control sub-circuit, wherein:

the driving sub-circuit is respectively connected with a fourth node, a fifth node and a sixth node and is used for providing driving current for the sixth node under the control of signals of the fourth node and the fifth node;

the write-in sub-circuit is respectively connected with a first scanning signal terminal, a display data signal terminal and a fifth node, and is used for writing the signal of the display data signal terminal into the fifth node under the control of the signal of the first scanning signal terminal;

the compensation sub-circuit is respectively connected with a first voltage end, the first scanning signal end, a fourth node and a sixth node, and is used for compensating the fourth node under the control of a signal of the first scanning signal end and a signal of the first voltage end;

the reset sub-circuit is respectively connected with a reset control signal end, an initial voltage end, a fourth node and an anode end of the light-emitting element, and is used for writing a signal of the initial voltage end into the fourth node and the anode end of the light-emitting element under the control of a signal of the reset control signal end;

the first light-emitting control sub-circuit is respectively connected with a first voltage end, a light-emitting control signal end and a fifth node and is used for providing a signal of the first voltage end to the fifth node under the control of a signal of the light-emitting control signal end;

the second light-emitting control sub-circuit is respectively connected with a light-emitting control signal end, a third node and a sixth node, and is used for allowing a driving current to pass between the sixth node and the third node under the control of a signal of the light-emitting control signal end.

5. The pixel circuit according to claim 4, wherein the reset sub-circuit comprises a first transistor and a seventh transistor, the compensation sub-circuit comprises a second transistor and a first capacitor, the driving sub-circuit comprises a third transistor, the write sub-circuit comprises a fourth transistor, the first emission control sub-circuit comprises a fifth transistor, and the second emission control sub-circuit comprises a sixth transistor, wherein:

a control electrode of the first transistor is connected with a reset control signal end, a first electrode of the first transistor is connected with an initial voltage end, and a second electrode of the first transistor is connected with a fourth node;

a control electrode of the second transistor is connected with a first scanning signal end, a first electrode of the second transistor is connected with a fourth node, and a second electrode of the second transistor is connected with a sixth node;

a control electrode of the third transistor is connected with a fourth node, a first electrode of the third transistor is connected with a fifth node, and a second electrode of the third transistor is connected with a sixth node;

one end of the first capacitor is connected with the fourth node, and the other end of the first capacitor is connected with the first voltage end;

a control electrode of the fourth transistor is connected with a first scanning signal end, a first electrode of the fourth transistor is connected with a display data signal end, and a second electrode of the fourth transistor is connected with a fifth node;

a control electrode of the fifth transistor is connected with a light-emitting control signal end, a first electrode of the fifth transistor is connected with a first voltage end, and a second electrode of the fifth transistor is connected with a fifth node;

a control electrode of the sixth transistor is connected with the light-emitting control signal end, a first electrode of the sixth transistor is connected with a sixth node, and a second electrode of the sixth transistor is connected with a third node;

a control electrode of the seventh transistor is connected with a reset control signal end, a first electrode of the seventh transistor is connected with an initial voltage end, and a second electrode of the seventh transistor is connected with an anode end of the light-emitting element.

6. The pixel circuit according to claim 2, wherein the first control signal terminal is a reset control signal terminal, the third emission control sub-circuit comprises an eighth transistor, the inverter sub-circuit comprises a ninth transistor and a tenth transistor, and the mode control sub-circuit comprises an eleventh transistor and a second capacitor, wherein:

a control electrode of the eighth transistor is connected to the first node, a first electrode of the eighth transistor is connected to a sixth node, and a second electrode of the eighth transistor is connected to an anode terminal of the light-emitting element;

a control electrode of the eleventh transistor is connected with the reset control signal end, a first electrode of the eleventh transistor is connected with the mode control signal end, and a second electrode of the eleventh transistor is connected with the second node;

7. The pixel circuit of claim 6, wherein the current control sub-circuit comprises a drive sub-circuit, a write sub-circuit, a compensation sub-circuit, a reset sub-circuit, and a first light emitting control sub-circuit, wherein:

the first light-emitting control sub-circuit is respectively connected with a first voltage end, a light-emitting control signal end and a fifth node, and is used for providing a signal of the first voltage end for the fifth node under the control of a signal of the light-emitting control signal end.

8. The pixel circuit of claim 7, wherein the reset sub-circuit comprises a first transistor and a seventh transistor, wherein the compensation sub-circuit comprises a second transistor and a first capacitor, wherein the drive sub-circuit comprises a third transistor, wherein the write sub-circuit comprises a fourth transistor, wherein the first emission control sub-circuit comprises a fifth transistor, and wherein:

9. A display device comprising the pixel circuit according to any one of claims 1 to 8.

10. A driving method for driving the pixel circuit according to any one of claims 1 to 8, the pixel circuit having a plurality of scanning periods, the driving method comprising, during one scanning period:

the current control sub-circuit receives the display data signal and the light-emitting control signal, controls whether to generate the driving current according to the light-emitting control signal, and controls the current intensity of the generated driving current according to the display data signal;

the gray scale control sub-circuit receives a mode control signal and a driving current generated by the current control sub-circuit, and drives the light-emitting element for a first time when the mode control signal is in a first display mode; when the mode control signal is in a second display mode, the light emitting element is driven for a second duration, at least one of the first duration and the second duration being comprised of a plurality of pulse periods.