CN112992071A

CN112992071A - Pixel circuit, driving method thereof and display device

Info

Publication number: CN112992071A
Application number: CN202110436670.8A
Authority: CN
Inventors: 曹席磊
Original assignee: BOE Technology Group Co Ltd; Chengdu BOE Optoelectronics Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Chengdu BOE Optoelectronics Technology Co Ltd
Priority date: 2021-04-22
Filing date: 2021-04-22
Publication date: 2021-06-18

Abstract

The embodiment of the disclosure provides a pixel circuit, a driving method thereof and a display device. The pixel circuit includes: the data writing circuit is configured to write a signal of the data signal terminal into the first node and store the signal of the data signal terminal under control of a signal of the first scan signal terminal, and write a signal of the first power supply terminal into the second node to place the driving circuit in a biased state; the driving circuit is configured to supply a signal of a first power source terminal to a third node to which a first electrode of the light emitting element is connected under control of a signal of the data signal terminal; the node control circuit includes: a first node control sub-circuit and a second node control sub-circuit, the first node control sub-circuit being configured to control a connection state between the third node and the fourth node under control of a signal of the second scan signal terminal; the second node control sub-circuit is configured to control a connection state between the first node and the fourth node under control of a signal of the third scan signal terminal.

Description

Pixel circuit, driving method thereof and display device

Technical Field

The embodiment of the disclosure relates to but is not limited to the technical field of display, and in particular relates to a pixel circuit, a driving method thereof and a display device.

Background

The Organic Light-Emitting Diode (OLED) display device has the advantages of thin thickness, Light weight, wide viewing angle, active Light emission, continuously adjustable Light emission color, low cost, high response speed, low driving voltage, wide working temperature range, simple production process, flexible display and the like, and is more and more widely applied to the display fields of mobile phones, tablet computers, digital cameras and the like. The pixel circuit design is the core technical content of the OLED display device, and has important research significance.

With the increasing demand for display diversification of display devices, increasing screen utilization rate is a new development demand, and at present, power consumption is reduced mainly by reducing the refresh frequency of the screen to meet the demand under some displays, but when the driving mode of some pixel circuits is low-frequency driving, the light emitting elements are easy to flicker when emitting light, so that the display effect is poor.

Disclosure of Invention

The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

In a first aspect, an embodiment of the present disclosure provides a pixel circuit, including: a driving circuit, a data writing circuit, and a node control circuit, wherein,

the data writing circuit is connected with a first scanning signal terminal, a data signal terminal, a first light-emitting signal terminal, a first power supply terminal, a first node and a second node, and is configured to write a signal of the data signal terminal into the first node and store the signal of the data signal terminal under the control of a signal of the first scanning signal terminal; further configured to write a signal of a first power supply terminal into the second node under control of a signal of the first light-emitting signal terminal to place the driving circuit in a biased state;

the driving circuit, connected to the first node, the second node and a third node, configured to supply a signal of the first power source terminal to the third node under the control of a signal of the data signal terminal, a first electrode of a light emitting element being connected to the third node;

the node control circuit includes: a first node control sub-circuit and a second node control sub-circuit, wherein the first node control sub-circuit is connected to a second scan signal terminal, the third node and a fourth node, and configured to control a connection state between the third node and the fourth node under the control of a signal of the second scan signal terminal; the second node control sub-circuit is connected with a third scanning signal terminal, the first node and the fourth node, and is configured to control a connection state between the first node and the fourth node under the control of a signal of the third scanning signal terminal.

In a second aspect, an embodiment of the present disclosure provides a display device, including: the pixel circuit described in the above embodiments.

In a third aspect, an embodiment of the present disclosure provides a driving method for a pixel circuit, where the driving method is applied to the pixel circuit in the above embodiment, and the driving method includes:

in the data writing compensation stage, a first node control sub-circuit is controlled to be started through a signal of a second scanning signal end, a second node control sub-circuit is controlled to be started through a signal of a third scanning signal end, and a data writing circuit is controlled to write a signal of a data signal end into a first node through the first node control sub-circuit and the second node control sub-circuit and store the signal of the data signal end through a signal of a first scanning signal end;

in the hysteresis regulation stage, the data writing circuit is controlled by the signal of the first light-emitting signal end to write the signal of the first power end into the second node so as to enable the driving circuit to be in a bias state;

in a light emitting stage, the first node control sub-circuit is controlled to be turned off by a signal of the second scan signal terminal, the second node control sub-circuit is controlled to be turned off by a signal of the third scan signal terminal, and the driving circuit is controlled by a signal of the data signal terminal to provide a signal of a first power terminal to the first electrode of the light emitting element so as to drive the light emitting element to emit light.

According to the pixel circuit, the driving method thereof and the display device provided by the embodiment of the disclosure, when the pixel circuit is in a low-frequency driving mode, the problem of electric leakage of the first node can be reduced through the first node control sub-circuit, so that when the light-emitting element emits light, the phenomenon of light-emitting flicker caused by reduction of the light-emitting brightness of the light-emitting element can be reduced. Furthermore, the driving circuit can be in a bias state before the light-emitting stage by writing the signal of the first power supply terminal into the second node, and the driving circuit can drive the light-emitting element to emit light by starting writing the signal of the data signal terminal from the bias state in the light-emitting stage, so that the light-emitting flicker phenomenon caused by the hysteresis phenomenon of the driving circuit can be avoided when the light-emitting element emits light. Therefore, the pixel circuit provided by the embodiment of the disclosure can avoid the phenomenon of light-emitting flicker of the light-emitting element during low-frequency driving, thereby improving the display effect.

Additional features and advantages of the disclosure will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by the practice of the disclosure. Other advantages of the disclosure may be realized and attained by the instrumentalities and combinations particularly pointed out in the specification and the drawings.

Other aspects will be apparent upon reading and understanding the attached drawings and detailed description.

Drawings

The accompanying drawings are included to provide an understanding of the disclosed embodiments and are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the examples serve to explain the principles of the disclosure and not to limit the disclosure. The shapes and sizes of the various elements in the drawings are not to be considered as true proportions, but are merely intended to illustrate the present disclosure.

Fig. 1 is a schematic structural diagram of a 7T1C pixel circuit;

fig. 2 is a circuit schematic diagram of a pixel circuit provided in an exemplary embodiment of the present disclosure;

fig. 3 is another circuit schematic diagram of a pixel circuit provided by an exemplary embodiment of the present disclosure;

FIG. 4 is an equivalent circuit diagram of the pixel circuit shown in FIG. 2;

FIG. 5 is a signal timing diagram of a pixel circuit in an exemplary embodiment of the disclosure;

FIG. 6 is a circuit diagram of the pixel circuit shown in FIG. 4 in a first stage S1;

FIG. 7 is a circuit diagram illustrating the pixel circuit shown in FIG. 4 in the second stage S2;

FIG. 8 is a circuit diagram illustrating the pixel circuit of FIG. 4 in the first sub-phase S31 of the third phase S3;

FIG. 9 is a circuit diagram illustrating the pixel circuit of FIG. 4 in the second sub-phase S32 of the third phase S3;

fig. 10 is a circuit diagram of the pixel circuit shown in fig. 4 in a fourth stage S4;

fig. 11 is a flowchart illustrating a driving method of a pixel circuit in an exemplary embodiment of the present disclosure.

Detailed Description

Various embodiments are described herein, but the description is intended to be exemplary, rather than limiting and many more embodiments and implementations are possible within the scope of the embodiments described herein. Although many possible combinations of features are shown in the drawings and discussed in the exemplary embodiments, many other combinations of the disclosed features are possible. Any feature or element of any embodiment may be used in combination with or instead of any other feature or element in any other embodiment, unless expressly limited otherwise.

In describing representative embodiments, the specification may have presented a method or process as a particular sequence of steps. However, to the extent that the method or process does not rely on the particular order of steps herein, the method or process should not be limited to the particular sequence of steps. Other orders of steps are possible as will be understood by those of ordinary skill in the art. Therefore, the particular order of the steps set forth in the specification should not be construed as limitations on the claims. Further, the claims directed to the method or process should not be limited to the performance of their steps in the order written, and one skilled in the art can readily appreciate that the sequences may be varied and still remain within the spirit and scope of the embodiments of the present disclosure.

In the drawings, the size of each component, the thickness of a layer, or a region may be exaggerated for clarity. Therefore, one mode of the present disclosure is not necessarily limited to the dimensions, and the shape and size of each component in the drawings do not reflect a true scale. Further, the drawings schematically show ideal examples, and one embodiment of the present disclosure is not limited to the shapes, numerical values, and the like shown in the drawings.

The ordinal numbers such as "first", "second", "third", and the like in the present specification are provided for avoiding confusion among the constituent elements, and are not limited in number.

In this specification, for convenience, terms indicating orientation or positional relationship such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like are used to explain positional relationship of constituent elements with reference to the drawings, only for convenience of description and simplification of description, and do not indicate or imply that a device or element referred to has a specific orientation, is configured and operated in a specific orientation, and thus, is not to be construed as limiting the present disclosure. The positional relationship of the constituent elements is appropriately changed according to the direction in which each constituent element is described. Therefore, the words described in the specification are not limited to the words described in the specification, and may be replaced as appropriate.

In this specification, the terms "mounted," "connected," and "connected" are to be construed broadly unless otherwise specifically indicated and limited. For example, it may be a fixed connection, or a removable connection, or an integral connection; can be a mechanical connection, or an electrical connection; either directly or indirectly through intervening components, or both may be interconnected. The meaning of the above terms in the present disclosure can be understood by those of ordinary skill in the art as appropriate.

In this specification, "electrically connected" includes a case where constituent elements are connected together by an element having some kind of electrical action. The "element having a certain electric function" is not particularly limited as long as it can transmit and receive an electric signal between connected components. The "element having some kind of electric function" may be, for example, an electrode, a wiring, a switching element such as a transistor, or another functional element such as a resistor, an inductor, or a capacitor.

In this specification, a transistor refers to an element including at least three terminals, i.e., a gate electrode (which may also be referred to as a gate or a control electrode), a drain electrode (which may also be referred to as a drain electrode terminal, a drain region, or a drain), and a source electrode (which may also be referred to as a source electrode terminal, a source region, or a source). The transistor has a channel region between a drain electrode and a source electrode, and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, a channel region refers to a region where current mainly flows.

In this specification, in order to distinguish two poles of a transistor except for a gate electrode, one of them is directly described as a first pole, and the other is a second pole, where the first pole may be a drain electrode and the second pole may be a source electrode, or the first pole may be a source electrode and the second pole may be a drain electrode. In the case of using transistors of opposite polarities, or in the case of changing the direction of current flow during circuit operation, the functions of the "source electrode" and the "drain electrode" may be interchanged. Therefore, in this specification, "source electrode" and "drain electrode" may be exchanged with each other.

The transistors in the embodiments of the present disclosure may be Thin Film Transistors (TFTs) or Field Effect Transistors (FETs), or other devices with the same characteristics. For example, the thin film transistor used in the embodiments of the present disclosure may include, but is not limited to, an Oxide thin film transistor (Oxide TFT), a Low Temperature polysilicon thin film transistor (LTPS TFT), or the like. For example, the thin film transistor may be a thin film transistor of a bottom gate structure or a thin film transistor of a top gate structure as long as a switching function can be achieved. Here, the embodiment of the present disclosure does not limit this.

Fig. 1 is a schematic structural diagram of a 7T1C pixel circuit, and as shown in fig. 1, the 7T1C pixel circuit includes: 7 transistors (first to seventh transistors T1 to T7), 1 storage capacitor Cst, and 7 signal input terminals (a DATA signal terminal DATA, a first Scan signal terminal Scan1, a second Scan signal terminal Scan2, a first light emitting signal terminal EM1, an initialization signal terminal INIT, a first power supply terminal VDD, and a second power supply terminal VSS). The first terminal of the storage capacitor Cst is connected to the first power terminal VDD, the second terminal of the storage capacitor Cst is connected to the first node N1, that is, the second terminal of the storage capacitor Cst is connected to the control electrode of the third transistor T3. A control electrode of the first transistor T1 is connected to the second Scan signal terminal Scan2, a first electrode of the first transistor T1 is connected to the first node N1, and a second electrode of the first transistor is connected to the initial signal terminal INIT. A control electrode of the second transistor T2 is connected to the first Scan signal terminal Scan1, a first electrode of the second transistor T2 is connected to the first node N1, and a second electrode of the second transistor T2 is connected to the third node N3. A control electrode of the third transistor T3 is coupled to the first node N1, that is, a control electrode of the third transistor T3 is coupled to the second terminal of the storage capacitor Cst, a first electrode of the third transistor T3 is coupled to the second node N2, and a second electrode of the third transistor T3 is coupled to the third node N3. A control electrode of the fourth transistor T4 is connected to the first Scan signal terminal Scan1, a first electrode of the fourth transistor T4 is connected to the second node N2, and a second electrode of the fourth transistor T4 is connected to the DATA signal terminal DATA. A control electrode of the fifth transistor T5 is connected to the first light-emitting signal terminal EM1, a first electrode of the fifth transistor T5 is connected to the first power source terminal VDD, and a second electrode of the fifth transistor T5 is connected to the second node N2. A control electrode of the sixth transistor T6 is connected to the first light emitting signal terminal EM1, a first electrode of the sixth transistor T6 is connected to the third node N3, and a second electrode of the sixth transistor T6 is connected to the first electrode of the light emitting element L. A control electrode of the seventh transistor T7 is connected to the first Scan signal terminal Scan1, a first electrode of the seventh transistor T7 is connected to the first electrode of the light emitting element L, and a second electrode of the seventh transistor T7 is connected to the initial signal terminal INIT. The second electrode of the light emitting element L is connected to a second power source terminal VSS.

As a result of research by the inventors of the present disclosure, in the conventional pixel circuit shown in fig. 1, on one hand, the potential of the first node N1 is simultaneously influenced by the first transistor T1 and the second transistor T2, so that the potential of the first node N1 is influenced by the potential changes of the initial signal terminal INIT and the third node N3. The third transistor T3 determines the amount of driving current flowing between the first power source terminal VDD and the second power source terminal VSS according to the potential difference between the control electrode and the first electrode thereof, and since the control electrode of the third transistor T3 is connected to the first node N1, the potential change of the first node N1 affects the display luminance of the light emitting element L. In the actual working process, the transistors cannot be completely guaranteed to be turned off without loss, and particularly when the driving mode of the pixel circuit is switched to low-frequency driving, the first transistor T1 and the second transistor T2 are easily turned off without complete shutdown, so that a leakage situation occurs, and therefore, the potential of the first node N1 is easily changed, the problem of leakage of the first node N1 is easily caused, the luminance of the light-emitting element L is reduced, and further, the light-emitting element L is easily flickered when emitting light, and the display effect is reduced. On the other hand, when the driving method of the pixel circuit is switched to the low frequency driving, due to the hysteresis effect of the third transistor T3, the light emitting element L is easy to flicker when emitting light, and the display effect is reduced.

Fig. 2 is a circuit schematic diagram of a pixel circuit provided in an exemplary embodiment of the present disclosure, and as shown in fig. 2, the pixel circuit provided in an embodiment of the present disclosure may include: a drive circuit 21, a data write circuit 22, and a node control circuit 23; wherein,

a DATA write circuit 22 connected to the first Scan signal terminal Scan1, the DATA signal terminal DATA, the first light emitting signal terminal EM1, the first power terminal VDD, the first node N1, and the second node N2, and configured to write a signal of the DATA signal terminal DATA into the first node N1 and store a signal of the DATA signal terminal DATA under the control of a signal of the first Scan signal terminal Scan 1; is further configured to write a signal of the first power source terminal VDD into the second node N2 under the control of the signal of the first light emitting signal terminal EM1 to put the driving circuit 21 in a biased state;

a driving circuit 21 connected to the first, second, and third nodes N1, N2, and N3, and configured to supply a signal of a first power source terminal VDD to the third node N3 under the control of a signal of a DATA signal terminal DATA, a first electrode (e.g., anode) of the light emitting element L being connected to the third node N3; a second electrode (e.g., cathode) of the light emitting element L is connected to a second power source terminal VSS.

The node control circuit 23 may include: a first node control sub-circuit 231 and a second node control sub-circuit 232; the first node control sub-circuit 231 is connected to the second Scan signal terminal Scan2, the third node N3 and the fourth node N4, and configured to control a connection state between the third node N3 and the fourth node N4 under the control of a signal of the second Scan signal terminal Scan 2; the second node control sub-circuit 232 is connected to the third Scan signal terminal Scan3, the first node N1 and the fourth node N4, and configured to control a connection state between the first node N1 and the fourth node N4 under the control of a signal of the third Scan signal terminal Scan 3.

In this way, the pixel circuit provided in the embodiment of the present disclosure can reduce the leakage problem of the first node N1 through the first node control sub-circuit 231 when the pixel circuit is in the low frequency driving mode, so that when the light emitting element L emits light, the light emitting flicker phenomenon caused by the reduction of the light emitting luminance of the light emitting element L can be reduced. Further, by writing the signal of the first power source terminal VDD into the second node N2, the driving circuit 21 can be biased before the light emitting period, and the driving circuit 21 can drive the light emitting element L to emit light by starting writing the signal of the DATA signal terminal DATA from the biased state during the light emitting period, so that the light emitting flicker phenomenon caused by the hysteresis phenomenon of the driving circuit 21 can be avoided when the light emitting element L emits light. Therefore, the pixel circuit provided in the embodiment of the present disclosure can avoid the light-emitting flicker phenomenon of the light-emitting element L during low-frequency driving, thereby improving the display effect.

In an exemplary embodiment, as shown in fig. 2, the data writing circuit 22 may include: an input sub-circuit 221, a voltage control sub-circuit 222, and a memory sub-circuit 223, wherein,

an input sub-circuit 221 connected to the first Scan signal terminal Scan1, the DATA signal terminal DATA, and the second node N2, and configured to write a signal of the DATA signal terminal DATA into the second node N2 under the control of a signal of the first Scan signal terminal Scan 1;

a voltage control sub-circuit 222 connected to the first light-emitting signal terminal EM1, the first power terminal VDD, and the second node N2, and configured to write a signal of the first power terminal VDD into the second node N2 under the control of a signal of the first light-emitting signal terminal EM1 to bias the driving circuit 21;

the memory sub-circuit 223, connected to the first power terminal VDD and the first node N1, is configured to store a signal of the DATA signal terminal DATA.

In an exemplary embodiment, as shown in fig. 2, the pixel circuit may further include: reset circuit 24, reset circuit 24 may include: a first transmission sub-circuit 241 and a second transmission sub-circuit 242. Wherein,

a first transmission sub-circuit 241 connected to the second emission signal terminal EM2, the initial signal terminal INIT, and the fourth node N4, and configured to provide a signal of the initial signal terminal INIT to the fourth node N4 under the control of a signal of the second emission signal terminal EM 2;

a second transmission sub-circuit 242 connected to the second emission signal terminal EM2, the third node N3, and the first pole of the light emitting element L, and configured to supply a signal of the third node N3 to the first pole of the light emitting element L under the control of a signal of the second emission signal terminal EM 2;

a first pole of the light emitting element L is connected to the third node N3 through the second transmitting sub-circuit 242, and a second pole of the light emitting element L is connected to the second power source terminal VSS.

Thus, the pixel circuit provided by the embodiment of the present disclosure, in the initialization stage before the driving circuit 21 drives the light emitting element L to emit light, the first node control sub-circuit 231 may be controlled to be turned on by a signal of the second Scan signal terminal Scan2 and the second node control sub-circuit 232 may be controlled to be turned on by a signal of the third Scan signal terminal Scan3, and thus, the first transmission sub-circuit 241 may be controlled by a signal of the second emission signal terminal EM2, the signal of the initial signal terminal INIT is supplied to the first node N1 through the second node control sub-circuit 232, to initialize the data writing circuit 22 and the driving circuit 21, and the reset circuit 24 can be controlled by the signal of the second emission signal terminal EM2 to supply the signal of the initialization signal terminal INIT to the first pole of the light emitting element L through the first node control sub-circuit 231 to initialize the light emitting element L, so that the display effect can be made better.

In an exemplary embodiment, as shown in fig. 3, the reset circuit 24 may further include: a voltage regulation sub-circuit 243, wherein the first transmission sub-circuit 241 may be connected with the initial signal terminal INIT through the voltage regulation sub-circuit 243; the voltage adjusting sub-circuit 243, connected to the second emission signal terminal EM2 and the initial signal terminal INIT, is configured to adjust a voltage of a signal output from the initial signal terminal INIT to the first transmission sub-circuit 241 under the control of a signal of the second emission signal terminal EM2 to adjust a potential of the fourth node N4. In this way, when the light emitting element L emits light, the voltage of the signal output from the initial signal terminal INIT to the first transmission sub-circuit 241 is adjusted by the voltage adjusting sub-circuit 243, so that the potential of the fourth node N4 can be adjusted, the relative potential of the first node N1 can be adjusted, the leakage problem of the first node N1 can be reduced, and thus, the phenomenon of light emitting flicker caused by the reduction of the light emitting brightness of the light emitting element L can be reduced, and the display effect can be better.

In one exemplary embodiment, the voltage regulation subcircuit may include: and a control end of the variable resistor is connected with the second light-emitting signal end EM2, a first end of the variable resistor is connected with the first transmission sub-circuit 241, and a second end of the variable resistor is connected with the initial signal end INIT. Here, the resistance value of the variable resistor may be controlled to be changed by the second emission signal terminal EM 2. Therefore, the embodiment of the present disclosure can dynamically adjust the voltage of the signal output from the initial signal terminal INIT to the first transmission sub-circuit 241 by using the variable resistor, and can adjust the potential of the fourth node, thereby adjusting the relative potential of the first node N1, further changing the voltage difference between two electrodes of the light emitting element L, adjusting the light emitting brightness of the light emitting element L, avoiding the light emitting flicker phenomenon of the light emitting element when emitting light, and making the display effect better.

Fig. 4 is an equivalent circuit diagram of the pixel circuit shown in fig. 2. The pixel circuit provided by the exemplary embodiment of the present disclosure is explained below with reference to the circuit configuration shown in fig. 4. The types of transistors in fig. 4 are exemplary, and should not be construed as limiting embodiments of the present disclosure.

In an exemplary embodiment, as shown in fig. 4, the driving circuit 21 may include: a third transistor T3, a control electrode of the third transistor T3 is connected to the first node N1, a first electrode of the third transistor T3 is connected to the second node N2, and a second electrode of the third transistor T3 is connected to the third node N3.

In an exemplary embodiment, as shown in fig. 4, the first node control sub-circuit 231 may include: a control electrode of the second transistor T2, a control electrode of the second transistor T2 is connected to the second Scan signal terminal Scan2, a first electrode of the second transistor T2 is connected to the fourth node N4, and a second electrode of the second transistor T2 is connected to the third node N3.

In an exemplary embodiment, as shown in fig. 4, the second node control sub-circuit 232 may include: a control electrode of the seventh transistor T7, the seventh transistor T7 is connected to the third Scan signal terminal Scan3, a first electrode of the seventh transistor T7 is connected to the first node N1, and a second electrode of the seventh transistor T7 is connected to the fourth node N4.

In an exemplary embodiment, as shown in fig. 4, the first transmitting sub-circuit 241 may include: a first transistor T1, a control electrode of the first transistor T1 is connected to the second light-emitting signal terminal EM2, a first electrode of the first transistor T1 is connected to the fourth node N4, and a second electrode of the first transistor T1 is connected to the initial signal terminal INIT.

In an exemplary embodiment, as shown in fig. 4, the second transmitting sub-circuit 242 may include: a sixth transistor T6, a control electrode of the sixth transistor T6 is connected to the second emission signal terminal EM2, a first electrode of the sixth transistor T6 is connected to the third node N3, and a second electrode of the sixth transistor T6T6 is connected to the first electrode of the light emitting element L.

In an exemplary embodiment, as shown in fig. 4, the input sub-circuit 221 may include: a fourth transistor T4, a control electrode of the fourth transistor T4 being connected to the first Scan signal terminal Scan1, a first electrode of the fourth transistor T4 being connected to the second node N2, and a second electrode of the fourth transistor T4 being connected to the DATA signal terminal DATA; the fourth transistor T4 is configured to write the signal of the DATA signal terminal DATA into the second node N2 under the control of the signal of the first Scan signal terminal Scan 1.

In an exemplary embodiment, as shown in fig. 4, the voltage control sub-circuit 222 may include: a fifth transistor T5, a control electrode of the fifth transistor T5 being connected to the first light-emitting signal terminal EM1, a first electrode of the fifth transistor T5 being connected to the first power terminal VDD, and a second electrode of the fifth transistor T5 being connected to the second node N2; and a fifth transistor T5 configured to write the signal of the first power source terminal VDD into the second node N2 under the control of the signal of the first light emitting signal terminal EM1 to bias the driving circuit 21 (e.g., the driving circuit 21 may include the third transistor T3).

In an exemplary embodiment, as shown in FIG. 4, the storage subcircuit 223 may include: a first terminal of the storage capacitor Cst is connected to the first power terminal VDD, and a second terminal of the storage capacitor Cst is connected to the first node N1.

In an exemplary embodiment, the storage capacitor Cst may be a capacitor device manufactured by a process, for example, a capacitor device is realized by manufacturing a special capacitor electrode, and a plurality of capacitor electrodes of the capacitor may be realized by a metal layer, a semiconductor layer (e.g., doped polysilicon), and the like. Alternatively, the storage capacitor Cst may be a parasitic capacitor between a plurality of devices, and may be implemented by the transistor itself and other devices or lines. Alternatively, the storage capacitor Cst may be a liquid crystal capacitor formed by the pixel electrode and the common electrode. Alternatively, the storage capacitor Cst may be an equivalent capacitor formed by a liquid crystal capacitor formed by the pixel electrode and the common electrode and the storage capacitor. The connection method of the storage capacitor Cst includes, but is not limited to, the above-described method, and may be other suitable connection methods as long as the level of the corresponding node can be stored. Here, the exemplary embodiments of the present disclosure do not limit this.

In one exemplary embodiment, the light emitting element L may include: any one of an organic light emitting diode OLED, a quantum dot light emitting diode, and an inorganic light emitting diode. For example, the Light Emitting element L may be a micron-sized Light Emitting element, such as a Micro Light-Emitting Diode (Micro LED), a sub-millimeter Light-Emitting Diode (Mini LED), or a Micro organic Light-Emitting Diode (Micro OLED), which is not limited in the embodiment of the disclosure. For example, taking the light emitting element L as an organic electroluminescent diode (OLED) as an example, the light emitting element may include: a first electrode (e.g., as an anode), an organic light emitting layer, and a second electrode (e.g., as a cathode) are stacked.

In an exemplary embodiment, the types of the first to seventh transistors T1 to T7 may be the same, or the types of the first to seventh transistors T1 to T7 may not be the same. For example, the first to seventh transistors T1 to T7 may be P-type transistors, or the first to seventh transistors T1 to T7 may be N-type transistors, so that the same type of transistors used in the pixel circuit can simplify the process flow, reduce the process difficulty, and improve the yield of the product. For example, the first to seventh transistors T1 to T7 may include P-type transistors and N-type transistors. For example, the first to seventh transistors T1 to T7 may include an oxide thin film transistor and a low temperature polysilicon thin film transistor.

In an exemplary embodiment, taking as an example that the first to seventh transistors T1 to T7 may include P-type transistors and N-type transistors, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 may each be a P-type transistor, and the seventh transistor T7 may be an N-type transistor, wherein the P-type transistor is turned on when a control electrode is a low-level signal and turned off when a control electrode is a high-level signal; the N-type transistor is turned on when the control signal is a high level signal and turned off when the control signal is a low level signal.

In an exemplary embodiment, taking as an example that the first to seventh transistors T1 to T7 may include an oxide thin film transistor and a low temperature polysilicon thin film transistor, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 may each be a low temperature polysilicon thin film transistor, and the seventh transistor T7 may be an oxide thin film transistor.

In an exemplary embodiment, the type of the sixth transistor T6 and the type of the first transistor T1 may be the same, or the type of the sixth transistor T6 and the type of the first transistor T1 may not be the same. For example, the sixth transistor T6 and the first transistor T1 may be both P-type transistors, or the sixth transistor T6 and the first transistor T1 may be both N-type transistors. For example, the sixth transistor T6 may be a low temperature polysilicon thin film transistor, and the first transistor T1 may be an oxide thin film transistor.

In an exemplary embodiment, the type of the seventh transistor T7 and the type of the second transistor T2 may not be the same, or the type of the seventh transistor T7 and the type of the second transistor T2 may not be the same. For example, the seventh transistor T7 may be an N-type transistor, and the second transistor T2 may be a P-type transistor. For example, the seventh transistor T7 may be an oxide thin film transistor, and the second transistor T2 may be a low temperature polysilicon thin film transistor.

In one exemplary embodiment, the pixel circuit may be a Low Temperature Polycrystalline Oxide (LTPO) pixel circuit.

In an exemplary embodiment, taking the pixel circuit as an LTPO pixel circuit as an example, the seventh transistor T7 may be an Oxide thin film transistor (Oxide TFT), and the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 may be low temperature polysilicon thin film transistors (LTPS TFTs). In this way, the leakage problem of the first node N1 caused by the seventh transistor T7 can be avoided, and then, when the light emitting element L emits light, the luminance of the light emitting element can be prevented from being reduced due to the leakage problem of the first node N1, and thus, the flicker phenomenon of light emission caused by the reduction of the luminance of the light emitting element L can be prevented. Also, only the seventh transistor T7 may be provided, one transistor being an oxide thin film transistor, and the process complexity may be reduced as compared to the pixel circuit shown in fig. 1.

In an exemplary embodiment, taking the pixel circuit as an LTPO pixel circuit as an example, the first transistor T1 may be an oxide thin film transistor. Thus, the leakage problem of the fourth node N4 can be avoided, and the leakage problem of the first node N1 can be reduced.

In an exemplary embodiment, taking the pixel circuit as an LTPO pixel circuit as an example, the second transistor T2 may be an oxide thin film transistor. Thus, the leakage problem of the fourth node N4 can be avoided, and the leakage problem of the first node N1 can be reduced.

In one exemplary embodiment, the first power source terminal VDD may provide a high level signal.

In one exemplary embodiment, the second power source terminal VSS may provide a low-level signal. For example, the second power source terminal VSS may supply a zero voltage or a ground voltage.

In an exemplary embodiment, the initial signal terminal INIT may provide a reset voltage signal, where the reset voltage signal may be a zero voltage or a ground voltage, or may be other fixed levels, such as a low voltage, and the like, which is not limited in this disclosure.

In an exemplary embodiment, the first node N1, the second node N2, the third node N3, and the fourth node N4 do not represent components that must actually exist, but rather represent junctions of related electrical connections in the circuit diagram.

In an exemplary embodiment, as shown in fig. 4, a pixel circuit provided in an exemplary embodiment of the present disclosure may include: the 7 transistors (the first transistor T1 to the seventh transistor T7), the 1 storage capacitor Cst, and the 9 signal input terminals (the DATA signal terminal DATA, the first Scan signal terminal Scan1, the second Scan signal terminal Scan2, the third Scan signal terminal Scan3, the first light-emitting signal terminal EM1, the second light-emitting signal terminal EM2, the initialization signal terminal INIT, the first power supply terminal VDD, and the second power supply terminal VSS), the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 are P-type transistors, and the seventh transistor T7 is an N-type transistor. As shown in fig. 4, a first terminal of the storage capacitor Cst is connected to the first power terminal VDD, and a second terminal of the storage capacitor Cst is connected to the first node N1 (i.e., the second terminal of the storage capacitor Cst is connected to the control electrode of the third transistor T3). A control electrode of the first transistor T1 is connected to the second emission signal terminal EM2, a first electrode of the first transistor T1 is connected to the fourth node N4, and a second electrode of the first transistor is connected to the initial signal terminal INIT. A control electrode of the second transistor T2 is connected to the second Scan signal terminal Scan2, a first electrode of the second transistor T2 is connected to the fourth node N4 (i.e., a first electrode of the second transistor T2 is connected to a second electrode of the seventh transistor T7), and a second electrode of the second transistor T2 is connected to the third node N3. A control electrode of the third transistor T3 is coupled to the first node N1 (i.e., the control electrode of the third transistor T3 is coupled to the second terminal of the storage capacitor Cst), a first electrode of the third transistor T3 is coupled to the second node N2, and a second electrode of the third transistor T3 is coupled to the third node N3. A control electrode of the fourth transistor T4 is connected to the first Scan signal terminal Scan1, a first electrode of the fourth transistor T4 is connected to the second node N2, and a second electrode of the fourth transistor T4 is connected to the DATA signal terminal DATA. A control electrode of the fifth transistor T5 is connected to the first light-emitting signal terminal EM1, a first electrode of the fifth transistor T5 is connected to the first power source terminal VDD, and a second electrode of the fifth transistor T5 is connected to the second node N2. A control electrode of the sixth transistor T6 is connected to the second light emitting signal terminal EM2, a first electrode of the sixth transistor T6 is connected to the third node N3, and a second electrode of the sixth transistor T6 is connected to the first electrode of the light emitting element L. A control electrode of the seventh transistor T7 is connected to the third Scan signal terminal Scan3, a first electrode of the seventh transistor T7 is connected to the first node N1 (i.e., the first electrode of the seventh transistor T7 is connected to the second end of the storage capacitor Cst), and a second electrode of the seventh transistor T7 is connected to the fourth node N4 (i.e., the second electrode of the seventh transistor T7 is connected to the first electrode of the second transistor T2). The second electrode of the light emitting element L is connected to a second power source terminal VSS.

The pixel circuit provided by the exemplary embodiment of the present disclosure is explained below by referring to the circuit configuration shown in fig. 4 through the operation process of the pixel circuit.

Fig. 5 is a signal timing diagram of a pixel circuit in an exemplary embodiment of the present disclosure. Wherein the high and low of the potential of the signal timing diagram shown in fig. 5 are only schematic and do not represent the real potential value or relative proportion, the low level signal corresponds to the on signal of the P-type transistor and the high level signal corresponds to the off signal of the P-type transistor corresponding to the embodiment of the present disclosure. As shown in fig. 5, the working process of the pixel circuit provided by the exemplary embodiment of the disclosure may include four stages, namely, a first stage S1, a second stage S2, a third stage S3 and a fourth stage S4, the third stage S3 may include a first sub-stage S31 and a second sub-stage S32, and timing waveforms of a plurality of control signals (including timing waveforms of signals of the first Scan signal terminal Scan1, the second Scan signal terminal Scan2, the third Scan signal terminal Scan3, the first light emitting signal terminal EM1 and the second light emitting signal terminal EM 2) in each stage are shown in fig. 5.

Fig. 6 to 10 are circuit schematic diagrams of the pixel circuit shown in fig. 4 corresponding to four stages in fig. 5, respectively. Fig. 6 is a circuit diagram of the pixel circuit shown in fig. 4 in the first stage S1, fig. 7 is a circuit diagram of the pixel circuit shown in fig. 4 in the second stage S2, fig. 8 is a circuit diagram of the pixel circuit shown in fig. 4 in the first sub-stage S31 of the third stage S3, fig. 9 is a circuit diagram of the pixel circuit shown in fig. 4 in the second sub-stage S32 of the third stage S3, and fig. 10 is a circuit diagram of the pixel circuit shown in fig. 4 in the fourth stage S4. Here, in fig. 6 to 10, the transistors identified by a cross (x) each indicate an off state in the corresponding stage, the transistors identified by a circle (o) each indicate an on state in the corresponding stage, and the dotted line with an arrow indicates a current path of the pixel circuit in the corresponding stage (the direction of the arrow does not indicate a current direction). In addition, the signal timing charts shown in fig. 6 to 10 are schematic and may be determined according to actual situations. As shown in fig. 6 to 10, a pixel circuit according to an embodiment of the present disclosure includes: the 7 transistors (the first transistor T1 to the seventh transistor T7), the 1 storage capacitor Cst, and the 9 signal input terminals (the DATA signal terminal DATA, the first Scan signal terminal Scan1, the second Scan signal terminal Scan2, the third Scan signal terminal Scan3, the first light-emitting signal terminal EM1, the second light-emitting signal terminal EM2, the initialization signal terminal INIT, the first power supply terminal VDD, and the second power supply terminal VSS), the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 are P-type transistors, and the seventh transistor T7 is an N-type transistor.

In an exemplary embodiment, as shown in fig. 5, the operation process of the pixel circuit in the embodiment of the present disclosure may include the following stages:

the first stage S1 may be referred to as an initialization stage or a reset stage.

As shown in fig. 5, in the first stage S1, the signals of the first light emitting signal terminal EM1, the first Scan signal terminal Scan1 and the third Scan signal terminal Scan3 are high level signals, and the signals of the second light emitting signal terminal EM2 and the second Scan signal terminal Scan2 are low level signals.

As shown in fig. 6, in the first stage S1, since the signals of the first light emitting signal terminal EM1 and the first Scan signal terminal Scan1 are high level signals, the fourth transistor T4 and the fifth transistor T5 are turned off. Since the signals of the second light emitting signal terminal EM2 and the second Scan signal terminal Scan2 are low level signals, the first transistor T1, the second transistor T2, and the sixth transistor T6 are turned on. Since the signal of the third Scan signal terminal Scan3 is a high level signal, the seventh transistor T7 is turned on. In this way, the signal output from the initial signal terminal INIT may be sequentially written to the first node N1 and the control electrode of the third transistor T3 through the turned-on first transistor T1, the turned-on fourth node N4, and the turned-on seventh transistor T7, and the storage capacitor Cst is initialized (also referred to as reset) to erase the original data voltage in the storage capacitor Cst, so as to initialize the charge amount of the control electrode of the third transistor T3, and the signal of the initial signal terminal INIT may be written to the first electrode of the light emitting element L through the fourth node N4, the turned-on second transistor T2, the turned-on third node N3, and the turned-on sixth transistor T6, so as to initialize (reset) the first electrode of the light emitting element L, and clear the internal pre-stored voltage, thereby completing initialization and ensuring that the light emitting element L does not emit light.

Here, in the first stage S1, the potential at the first node N1 is the voltage Vinit of the signal of the initial signal terminal INIT, i.e., the initialization potential. The initialization voltage may be a low voltage (e.g., a ground voltage or a zero voltage), which is not limited in the embodiments of the disclosure.

The second stage S2 may be referred to as a data write compensation stage.

As shown in fig. 5, in the second stage S2, the signals of the first light-emitting signal terminal EM1, the second light-emitting signal terminal EM2 and the third Scan signal terminal Scan3 are high level signals, and the signals of the first Scan signal terminal Scan1 and the second Scan signal terminal Scan2 are low level signals.

As shown in fig. 7, in the second stage S2, since the signals of the first and second light-emitting signal terminals EM1 and EM2 are high-level signals, the fifth transistor T5, the first transistor T1 and the sixth transistor T6 are turned off. Since the signals of the first Scan signal terminal Scan1 and the second Scan signal terminal Scan2 are low level signals, the second transistor T2 and the fourth transistor T4 are turned on. Since the signal of the third Scan signal terminal Scan3 is a high level signal, the seventh transistor T7 is turned on. Since the potential at the first node N1 is the voltage Vinit of the signal at the initial signal terminal INIT after the first stage S1, the third transistor T3 is turned on at this stage. In this way, the signal output from the DATA signal terminal DATA may be sequentially written into the first node N1 through the turned-on fourth transistor T4, the turned-on second node N2, the turned-on third transistor T3, the turned-on third node N3, the turned-on second transistor T2, the turned-on fourth node N4, and the turned-on seventh transistor T7, and stored in the storage capacitor Cst.

Here, since the potential at the first node N1 is the voltage Vinit of the signal of the initial signal terminal INIT after the first phase S1 passes, Vgs ═ Vinit-Vdata, that is, Vgs < Vth, is satisfied for the third transistor T3 in the second phase S2, the third transistor T3 is turned on at this phase, and thus, the signal output from the DATA signal terminal DATA is written into the first node N1, so that the potential at the first node N1 becomes: vdata + Vth. Where Vgs represents a voltage difference between the gate and the second pole (e.g., source) of the third transistor T3, Vinit represents a voltage of a signal output from the initial signal terminal INIT, Vdata represents a voltage of a signal output from the DATA signal terminal DATA, and Vth represents a threshold voltage of the third transistor T3. Therefore, after the second stage S2, the voltage at the first node N1 (i.e., the second terminal of the storage capacitor Cst, i.e., the control electrode of the third transistor T3) is: vdata + Vth, that is, the sum of the voltage information Vdata of the signal output from the DATA signal terminal DATA and the threshold voltage of the third transistor T3 is stored in the storage capacitor Cst for controlling the third transistor T3 to turn on at a subsequent light emitting stage.

The third stage S3, which may be referred to as a hysteresis adjustment stage, may include a first sub-stage S31 and a second sub-stage S32.

As shown in fig. 5, in the first sub-phase S31, the signals of the first light emitting signal terminal EM1, the second light emitting signal terminal EM2 and the second Scan signal terminal Scan2 are high level signals, and the signals of the first Scan signal terminal Scan1 and the third Scan signal terminal Scan3 are low level signals.

As shown in fig. 8, in the first sub-stage S31, since the signals of the first light-emitting signal terminal EM1, the second light-emitting signal terminal EM2 and the second Scan signal terminal Scan2 are high level signals, the fifth transistor T5, the first transistor T1, the second transistor T2 and the sixth transistor T6 are turned off. Since the signal of the third Scan signal terminal Scan3 is a low level signal, the seventh transistor T7 is turned off. Since the signal of the first Scan signal terminal Scan1 is a low level signal, the fourth transistor T4 is turned on.

Here, in the first sub-stage S31, the fourth transistor T4 is turned on, which belongs to the shifting action of the waveform of the first Scan signal terminal Scan1 and does not affect the operating state of the pixel circuit.

As shown in fig. 5, in the second sub-stage S32, the signals of the second light emitting signal terminal EM2, the second Scan signal terminal Scan2 and the first Scan signal terminal Scan1 are high level signals, and the signals of the first light emitting signal terminal EM1 and the third Scan signal terminal Scan3 are low level signals.

As shown in fig. 9, in the second sub-stage S32, since the signals of the second emission signal terminal EM2, the second Scan signal terminal Scan2 and the first Scan signal terminal Scan1 are high level signals, the first transistor T1, the second transistor T2, the fourth transistor T4 and the sixth transistor T6 are turned off. Since the signal of the third Scan signal terminal Scan3 is a low level signal, the seventh transistor T7 is turned off. Since the signal of the first light emitting signal terminal EM1 is a low level signal, the fifth transistor T5 is turned on. Thus, the signal of the first power terminal VDD may be written into the second node N2 through the turned-on fifth transistor T5.

Here, since the potential at the first node N1 is Vdata + Vth after the second stage S2, then, in the second sub-stage S32, Vgs ═ Vn1-Vn3 ═ Vdata + Vth-Vdd, that is, Vgs < Vth, is satisfied for the third transistor T3, and thus, the third transistor T3 is placed in a biased state. In this way, by setting the third transistor T3 to be biased in the second sub-phase S32, and then driving the light emitting element to emit light in the fourth phase S4 (i.e., the light emitting phase) after the second sub-phase S32, the signal of the data signal terminal stored in the storage capacitor Cst is written into the third transistor T3 from the biased state when all the pixel circuits start emitting light to drive the light emitting element to emit light, so that short-term after image phenomenon caused by hysteresis of the TFT can be eliminated before all the pixel circuits start emitting light, flicker phenomenon can be reduced, and display effect can be improved. Where Vn1 denotes a potential at the first node N1, Vn3 denotes a potential at the third node N3, Vdata denotes a voltage of a signal output from the DATA signal terminal DATA, Vth denotes a threshold voltage of the third transistor T3, and Vdd denotes a voltage of a signal of the first power terminal Vdd.

The fourth stage S4 may be referred to as a lighting stage.

As shown in fig. 5, in the fourth stage S4, the signals of the second Scan signal terminal Scan2 and the first Scan signal terminal Scan1 are high level signals, and the signals of the first emission signal terminal EM1, the second emission signal terminal EM2 and the third Scan signal terminal Scan3 are low level signals.

As shown in fig. 10, in the fourth stage S4, since the signals of the second Scan signal terminal Scan2 and the first Scan signal terminal Scan1 are high level signals, the second transistor T2 and the fourth transistor T4 are turned off. Since the signals of the first and second light emitting signal terminals EM1 and EM2 are low level signals, the fifth transistor T5, the first transistor T1, and the sixth transistor T6 are turned on. Since the signal of the third Scan signal terminal Scan3 is a low level signal, the seventh transistor T7 is turned off. In this way, a signal (i.e., a power voltage) output from the first power terminal VDD may be written to the first electrode of the light emitting element L through the turned-on fifth transistor T5, the turned-on second node N2, the turned-on third transistor T3, the turned-on third node N3, and the turned-on sixth transistor T6 to supply a driving voltage to the first electrode of the light emitting element L, thereby driving the light emitting element L to emit light.

In an exemplary embodiment, in the fourth stage S4, when the first transistor T1 is in the on state of emitting light, the voltage of the signal at the dynamic initialization signal terminal INIT may be designed to adjust the relative potential of the first node N1, so as to change the voltage difference between the two poles of the light emitting device L, and further adjust the emitting brightness of the light emitting device L, thereby avoiding the phenomenon of light flicker when the light emitting device emits light. For example, as shown in fig. 3, in the fourth stage S4, the voltage of the signal output from the initial signal terminal INIT to the first transmission sub-circuit 241 may be adjusted by the voltage adjustment sub-circuit 243 to adjust the potential of the fourth node N4.

In an exemplary embodiment, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 may each be an N-type transistor, and the seventh transistor T7 may be a P-type transistor. At this time, the timing of the external signal for driving the pixel circuit of such a structure can be adjusted accordingly. For example, the timing of the third Scan signal terminal Scan3 is opposite to the corresponding signal timing shown in fig. 5 (i.e., the phase difference therebetween is 180 degrees), and the timing of the first Scan signal terminal Scan1, the second Scan signal terminal Scan2, the first light emitting signal terminal EM1, and the second light emitting signal terminal EM2 is opposite to the corresponding signal timing shown in fig. 5 (i.e., the phase difference therebetween is 180 degrees).

In an exemplary embodiment, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may each employ an N-type transistor. At this time, the timing of the external signal for driving the pixel circuit of such a structure can be adjusted accordingly. For example, the timings of the first Scan signal terminal Scan1, the second Scan signal terminal Scan2, the first light emitting signal terminal EM1 and the second light emitting signal terminal EM2 may coincide with the corresponding signal timings shown in fig. 5, and the timing of the third Scan signal terminal Scan3 is opposite to the corresponding signal timings shown in fig. 5 (i.e., the phase difference therebetween is 180 degrees).

Of course, the type of the thin film transistor used in the pixel circuit in the embodiment of the present disclosure is not limited to the implementation given above, and can be replaced by those skilled in the art according to the actual situation, and correspondingly, the timing sequence of the external signal of the pixel circuit can be adjusted by those skilled in the art according to the actual situation. Here, the embodiment of the present disclosure does not limit this.

The embodiment of the disclosure also provides a display device. The display device may include: the pixel circuit in one or more of the exemplary embodiments described above.

In an exemplary embodiment, the display device may further include: the display substrate, the pixel circuit can be disposed on the display substrate.

In an exemplary embodiment, the display device may include, but is not limited to, an LTPO display device.

In an exemplary embodiment, the Display device may include, but is not limited to, an OLED Display device or a Liquid Crystal Display (LCD) device, etc.

In an exemplary embodiment, the display device may be: any product or component with a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like. Here, the embodiment of the present disclosure does not limit the type of the display device. Other essential components of the display device are understood by those skilled in the art, and are not described herein nor should they be construed as limiting the present disclosure.

For technical details that are not disclosed in the embodiments of the display device disclosed in the present disclosure, those skilled in the art should understand with reference to the description in the embodiments of the pixel circuit disclosed in the present disclosure, and therefore, the detailed description is omitted here.

The embodiment of the disclosure also provides a driving method of the pixel circuit, which can be applied to the pixel circuit in one or more embodiments.

Fig. 11 is a flowchart illustrating a driving method of a pixel circuit in an exemplary embodiment of the disclosure, and as shown in fig. 11, the driving method may include:

step 111: in the data writing compensation stage, a first node control sub-circuit is controlled to be started through a signal of a second scanning signal end, a second node control sub-circuit is controlled to be started through a signal of a third scanning signal end, and a data writing circuit is controlled to write a signal of a data signal end into a first node through a first node control sub-circuit and a second node control sub-circuit and store the signal of the data signal end through a signal of a first scanning signal end;

step 112: in the hysteresis regulation stage, the data writing circuit is controlled by the signal of the first light-emitting signal end to write the signal of the first power end into the second node so as to enable the driving circuit to be in a bias state;

step 113: in the light-emitting stage, the first node control sub-circuit is controlled to be closed by a signal of the second scanning signal terminal, the second node control sub-circuit is controlled to be closed by a signal of the third scanning signal terminal, the driving circuit is controlled by a signal of the data signal terminal, and a signal of the first power supply terminal is provided for the first electrode of the light-emitting element so as to drive the light-emitting element to emit light.

In this way, according to the driving method of the pixel circuit provided by the embodiment of the present disclosure, when the pixel circuit is in the low-frequency driving mode, the problem of the leakage current of the first node can be reduced by providing the first node control sub-circuit, so that when the light emitting element L emits light, the phenomenon of light emitting flicker caused by the reduction of the light emitting brightness of the light emitting element L can be reduced. Furthermore, the driving circuit can be in a bias state in the hysteresis adjusting stage by writing the signal of the first power source terminal into the second node, so that the driving circuit can drive the light emitting element L to emit light by starting writing the signal of the data signal terminal from the bias state in the light emitting stage, and thus, the light emitting flicker phenomenon caused by the hysteresis phenomenon of the driving circuit can be avoided when the light emitting element L emits light. Further, the display effect can be improved.

In one exemplary embodiment, a pixel circuit includes: for example, before step 111, the driving method may further include: step 114: in the initialization stage, the first node control sub-circuit is controlled to be started by a signal of the second scanning signal terminal, the second node control sub-circuit is controlled to be started by a signal of the third scanning signal terminal, the reset circuit is controlled by a signal of the second light-emitting signal terminal, a signal of the initial signal terminal is provided for the first electrode of the light-emitting element through the first node control sub-circuit so as to initialize the first electrode of the light-emitting element, and a signal of the initial signal terminal is provided for the first node through the second node control sub-circuit so as to initialize the data writing circuit and the driving circuit.

In an exemplary embodiment, the reset circuit may further include: for example, the driving method may further include: step 115: in the light-emitting stage, the voltage of the signal output from the initial signal end to the first transmission sub-circuit is adjusted by the voltage adjusting sub-circuit controlled by the signal of the second light-emitting signal end so as to adjust the potential of the fourth node.

Therefore, according to the driving method of the pixel circuit provided by the embodiment of the disclosure, when the pixel circuit is in a low-frequency driving mode, in a light-emitting stage, the voltage of the signal output from the initial signal end to the first transmission sub-circuit is dynamically adjusted through the voltage adjustment sub-circuit, and the adjustment of the potential of the fourth node can be realized, so that the adjustment of the relative potential of the first node N1 can be realized, further, the voltage difference between two poles of the light-emitting element L can be changed, the adjustment of the light-emitting brightness of the light-emitting element L can be realized, the light-emitting flicker phenomenon of the light-emitting element during light emission can be avoided, and the display effect can be improved.

For technical details that are not disclosed in the embodiments of the driving method of the pixel circuit of the present disclosure, those skilled in the art should refer to the description in the embodiments of the pixel circuit of the present disclosure for understanding, and therefore, the description is omitted here.

Although the embodiments disclosed in the present disclosure are described above, the above description is only for the convenience of understanding the present disclosure, and is not intended to limit the present disclosure. It will be understood by those skilled in the art of the present disclosure that various changes in form and details may be made therein without departing from the spirit and scope of the disclosure, and that the scope of the disclosure is to be limited only by the terms of the appended claims.

Claims

1. A pixel circuit, comprising: a driving circuit, a data writing circuit, and a node control circuit, wherein,

2. The pixel circuit according to claim 1, further comprising: a reset circuit, the reset circuit comprising: a first transmission sub-circuit and a second transmission sub-circuit, wherein,

the first transmission sub-circuit is connected with a second light-emitting signal terminal, an initial signal terminal and the fourth node, and is configured to provide a signal of the initial signal terminal to the fourth node under the control of a signal of the second light-emitting signal terminal;

the second transmission sub-circuit is connected with the second light-emitting signal terminal, the third node and the first pole of the light-emitting element, and is configured to provide the signal of the third node to the first pole of the light-emitting element under the control of the signal of the second light-emitting signal terminal; the first pole of the light-emitting element is connected with the third node through the second transmission sub-circuit, and the second pole of the light-emitting element is connected with a second power supply end.

3. The pixel circuit according to claim 2, wherein the first transmission sub-circuit comprises: a first transistor, a control electrode of which is connected to the second light emitting signal terminal, a first electrode of which is connected to the fourth node, and a second electrode of which is connected to the initial signal terminal.

4. The pixel circuit according to claim 3, wherein the first transistor is an oxide thin film transistor.

5. The pixel circuit according to claim 3, wherein the second transmission sub-circuit comprises a sixth transistor, a control electrode of the sixth transistor is connected to the second light emitting signal terminal, a first electrode of the sixth transistor is connected to the third node, and a second electrode of the sixth transistor T6 is connected to the first electrode of the light emitting element.

6. The pixel circuit according to claim 5, wherein the type of the sixth transistor is the same as the type of the first transistor, or wherein the type of the sixth transistor is different from the type of the first transistor.

7. The pixel circuit according to claim 2, wherein the reset circuit further comprises: a voltage regulation sub-circuit, wherein,

the first transmission sub-circuit is connected with the initial signal end through the voltage regulation sub-circuit;

the voltage adjusting sub-circuit is connected with the second light-emitting signal end and configured to adjust the voltage of the signal output by the initial signal end to the first transmission sub-circuit under the control of the signal of the second light-emitting signal end.

8. The pixel circuit according to claim 2, wherein the first node control sub-circuit comprises: and a control electrode of the second transistor is connected with the second scanning signal end, a first electrode of the second transistor is connected with the fourth node, and a second electrode of the second transistor is connected with the third node.

9. The pixel circuit according to claim 8, wherein the second transistor is an oxide thin film transistor.

10. The pixel circuit of claim 8, wherein the second node control sub-circuit comprises: a seventh transistor, a control electrode of which is connected to the third scan signal terminal, a first electrode of which is connected to the first node, and a second electrode of which is connected to the fourth node.

11. The pixel circuit according to claim 10, wherein a type of the seventh transistor is different from a type of the second transistor, or wherein the type of the seventh transistor is the same as the type of the second transistor.

12. The pixel circuit according to claim 10, wherein the seventh transistor is an oxide thin film transistor.

13. The pixel circuit according to claim 1 or 8, wherein the driving circuit comprises: a third transistor having a control electrode coupled to the first node, a first electrode coupled to the second node, and a second electrode coupled to the third node.

14. The pixel circuit according to claim 1 or 8, wherein the data writing circuit comprises: a fourth transistor, a fifth transistor, and a storage capacitor, wherein,

a control electrode of the fourth transistor is connected with the first scanning signal end, a first electrode of the fourth transistor is connected with the second node, and a second electrode of the fourth transistor is connected with the data signal end; the fourth transistor configured to write a signal of the data signal terminal into the second node under control of a signal of the first scan signal terminal;

a control electrode of the fifth transistor is connected with the first light-emitting signal end, a first electrode of the fifth transistor is connected with the first power supply end, and a second electrode of the fifth transistor is connected with the second node; the fifth transistor is configured to write a signal of a first power supply terminal into the second node under control of a signal of the first light-emitting signal terminal to place the driving circuit in a biased state;

a first end of the storage capacitor is connected to the first power supply terminal, and a second end of the storage capacitor is connected to the first node.

15. A display device, comprising: a pixel circuit as claimed in any one of claims 1 to 14.

16. A driving method of a pixel circuit, applied to the pixel circuit according to claim 1, the driving method comprising:

17. The driving method according to claim 16, wherein the pixel circuit further comprises: a reset circuit, the reset circuit comprising: a first transmission sub-circuit connected to a second light-emitting signal terminal, an initial signal terminal, and the fourth node, and a second transmission sub-circuit connected to the second light-emitting signal terminal, the third node, and the first electrode of the light-emitting element;

before the data write compensation phase, the driving method further includes: in the initialization stage, the first node control sub-circuit is controlled to be started by a signal of a second scanning signal end, the second node control sub-circuit is controlled to be started by a signal of a third scanning signal end, the reset circuit is controlled by a signal of a second light-emitting signal end, a signal of an initial signal end is provided for the first pole of the light-emitting element through the first node control sub-circuit so as to initialize the light-emitting element, and the signal of the initial signal end is provided for the first node through the second node control sub-circuit so as to initialize the data writing circuit and the driving circuit.

18. The driving method according to claim 17, wherein the reset circuit further comprises: the first transmission sub-circuit is connected with the initial signal end through the voltage regulation sub-circuit;

the driving method further includes: and in the light-emitting stage, the voltage of the signal output from the initial signal end to the first transmission sub-circuit is adjusted by the voltage adjusting sub-circuit controlled by the signal of the second light-emitting signal end.