CN115050317A - Data driving circuit, display module and method for outputting driving signal - Google Patents
Data driving circuit, display module and method for outputting driving signal Download PDFInfo
- Publication number
- CN115050317A CN115050317A CN202210832800.4A CN202210832800A CN115050317A CN 115050317 A CN115050317 A CN 115050317A CN 202210832800 A CN202210832800 A CN 202210832800A CN 115050317 A CN115050317 A CN 115050317A
- Authority
- CN
- China
- Prior art keywords
- gray scale
- pulses
- gray
- data
- duration
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0275—Details of drivers for data electrodes, other than drivers for liquid crystal, plasma or OLED displays, not related to handling digital grey scale data or to communication of data to the pixels by means of a current
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/02—Improving the quality of display appearance
- G09G2320/0242—Compensation of deficiencies in the appearance of colours
Abstract
The embodiment of the application discloses a data driving circuit, which comprises a data processing unit, a gray clock generating unit and an output unit, wherein the data processing unit outputs a data clock signal to the gray clock generating unit and outputs a data signal for displaying an image to the output unit, the gray clock generating unit outputs a gray clock signal according to the data clock signal, the gray clock signal comprises a first gray area and a second gray area, and the duration of any one gray pulse in the first gray area is longer than that of any one gray pulse in the second gray area. The output unit is used for receiving the data signal to count the gray scale clock signal and correspondingly outputting a driving signal to drive the pixel unit to display the image. The color cast of the display panel is improved by controlling the duration of the gray pulse so as to improve the display effect. The application also discloses a display module comprising the data driving circuit and a method for outputting the driving signal of the data driving circuit.
Description
Technical Field
The present application relates to the field of display technologies, and in particular, to a data driving circuit, a display module, and a method for outputting a driving signal.
Background
The Mini-LED is an LED chip with the size of 100um, and compared with a common LED, the Mini-LED has higher unit area density and smaller light source unit size. Compared with a Liquid Crystal Display (LCD), the Mini-LED Display screen has a better Display effect, the response speed is improved by orders of magnitude, the screen can be thinner and lighter, and the power consumption is lower.
At present, in the process of displaying by using the Mini-LED, when the low brightness is displayed, the proportion of current flowing through the Mini-LED is small due to the existence of parasitic capacitance, so that the color cast phenomenon appears during the display.
Disclosure of Invention
In view of the above-mentioned deficiencies of the prior art, the present application provides a data driving circuit for effectively improving display color shift.
A data driving circuit includes a data processing unit outputting a data clock signal to a gray clock generating unit and outputting a data signal for displaying an image to an output unit, the data clock signal having a first pulse width duration which is the longest time a pixel unit performing image display receives the data signal in a frame image display duration, the gray clock generating unit outputting a gray clock signal according to the data clock signal, the gray clock signal including N consecutive gray pulses including a plurality of first gray pulses having a first duration and a plurality of second gray pulses having a second duration, the first duration being longer than the second duration, the output unit receiving the data signal, when a gray scale luminance corresponding to the data signal is less than or equal to a first threshold, counting the first gray pulses according to the gray scale brightness corresponding to the data signals to obtain a counting pulses, outputting driving signals according to the duration of the a counting pulses, counting the second gray pulses according to the gray scale brightness corresponding to the data signals to obtain b counting pulses when the gray scale brightness corresponding to the data signals is greater than a first threshold, outputting driving signals according to the duration of the b counting pulses, wherein the driving signals are used for driving the pixel units to display images, a is greater than 1 and less than or equal to N, and b is greater than 1 and less than or equal to N.
Optionally, the gray scale clock signal includes a first gray scale region and a second gray scale region, the first gray scale region includes 1 st to x th gray scale pulses, and the first gray scale pulse is any one of the 1 st to x th gray scale pulses; the second gray scale area comprises the (x + 1) -N gray scale pulses, and the second gray scale pulse is any one of the (x + 1) -N gray scale pulses; the duration of any one of the 1 st to x th gray scale pulses is longer than that of any one of the x +1 th to N th gray scale pulses, wherein the ith gray scale corresponds to i gray scale pulses, and i is more than or equal to 1 and less than or equal to N; when the gray scale brightness corresponding to the data signal is smaller than or equal to a first threshold value, counting the gray scale pulses in the first gray scale area according to the gray scale brightness corresponding to the data signal and obtaining a counting pulses, wherein a is more than or equal to 1 and less than or equal to x, and outputting a driving signal according to the duration of the a counting pulses; and when the gray scale brightness corresponding to the data signal is greater than the first threshold, counting the gray scale pulses in the second gray scale region according to the gray scale brightness corresponding to the data signal and obtaining b counting pulses, wherein x is greater than b and is less than or equal to N, and outputting a driving signal according to the duration of the b counting pulses.
Alternatively, the duration of each gray pulse in the first gray scale region is the same, and the duration of each gray pulse in the second gray scale region is the same.
Optionally, at least two gray scale pulses with different durations are included in the first gray scale region, and each gray scale pulse in the second gray scale region has the same duration.
Optionally, the number of gray scale pulses in the first gray scale region is less than or equal to the number of gray scale pulses in the second gray scale region.
Optionally, the gray scale clock generating module is configured to perform frequency division and/or frequency multiplication on the data clock signal to control a duration of a first pulse width in the data clock signal to correspond to the N gray scale pulses.
The application also discloses a method for outputting the driving signal by the data driving circuit, which comprises the steps of outputting a data clock signal to the gray scale clock generation unit and outputting a data signal for displaying an image to the output unit, wherein the data clock signal has a first pulse width duration, and the first pulse width duration is the longest time for receiving the data signal by a pixel unit executing image display in the display duration of a frame of image; outputting a gray scale clock signal according to the data clock signal, wherein the gray scale clock signal comprises N continuous gray scale pulses, the N continuous gray scale pulses comprise a plurality of first gray scale pulses with first duration and a plurality of second gray scale pulses with second duration, and the first duration is longer than the second duration; when the gray scale brightness corresponding to the data signal is smaller than or equal to a first threshold value, counting the first gray scale pulse according to the gray scale brightness corresponding to the data signal and obtaining a counting pulses, outputting a driving signal according to the duration of the a counting pulses, when the gray scale brightness corresponding to the data signal is larger than the first threshold value, counting the second gray scale pulse according to the gray scale brightness corresponding to the data signal and obtaining b counting pulses, and outputting the driving signal according to the duration of the b counting pulses, wherein the driving signal is used for driving the pixel unit to display an image, a is more than 1 and less than or equal to N, and b is more than 1 and less than or equal to N.
Alternatively, outputting a gray scale clock signal according to the data clock signal includes: applying a voltage corresponding to the standard white color to the pixel unit, determining a color coordinate corresponding to the current display color of the pixel unit according to the color gamut map, comparing the current color coordinate of the pixel unit with the color coordinate corresponding to the standard white color, adjusting the duration of the 1 st to x th gray scale pulses in the first gray scale region to control the pixel unit to display the standard white color, and acquiring the adjusted 1 st to x th gray scale pulses when the current color coordinate of the pixel unit is the color coordinate of the standard white color.
Alternatively, applying a voltage corresponding to a standard white color to the pixel cells in the display area includes applying a voltage corresponding to a standard red or a standard green or a standard blue color to the pixel cells in the display area.
Alternatively, the "outputting a gray scale clock signal according to the data clock signal" includes: controlling a pixel unit to display standard white, determining the standard charge amount flowing through the pixel unit, adjusting the duration of the 1 st to x gray scale pulses in the first gray scale area to control the charge amount flowing through the pixel unit to be the standard charge amount, and acquiring the adjusted 1 st to x gray scale pulses.
The application still discloses a display module assembly includes display control circuit, scanning drive circuit, display panel, luminescence controller and aforementioned data drive circuit, display control circuit receives former data signal according to external signal source to export source control signal and grid control signal respectively, data drive circuit basis source control signal with scanning drive circuit basis grid control signal cooperation luminescence controller control display panel carries out image display.
Optionally, the display panel is provided with a plurality of scan lines extending along the first direction, a plurality of data lines extending along the second direction F2, and pixel units are correspondingly arranged at intersections of the plurality of scan lines and the plurality of data lines, the pixel units are light emitting diodes, anodes of the light emitting diodes are connected with the scan lines to receive scan signals, and cathodes of the light emitting diodes are connected with the data lines to receive data signals.
Compared with the prior art, the data driving circuit disclosed by the application enables the duration of the first gray pulse to be increased to eliminate color cast of the display panel when the low gray is displayed by adjusting the duration of the gray pulse in the first gray area, effectively improves the color cast problem when the display panel displays the low gray, and improves the display effect.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a display device according to a first embodiment of the present application;
FIG. 2 is a schematic plan view of a display module shown in FIG. 1 according to a second embodiment of the present application;
FIG. 3 is a schematic diagram of the connection of the pixel unit in FIG. 2;
FIG. 4 is a block diagram of a data driving circuit shown in FIG. 2 according to a third embodiment of the present application;
FIG. 5 is a schematic diagram illustrating the frequency multiplication/division principle of the gray scale clock generation unit in FIG. 4;
FIG. 6 is a diagram of gray scale pulses in the gray scale clock signal of FIG. 4;
FIG. 7 is a schematic diagram of a standard color gamut;
FIG. 8 is a diagram illustrating gray scale pulses in a gray scale clock signal according to a fourth embodiment of the present disclosure;
fig. 9 is a method for outputting a driving signal according to a fifth embodiment of the present application.
Description of reference numerals: display device-100, display module-10, power supply module-20, support frame-30, Data drive circuit-11, scan drive circuit-12, display panel-13, pixel unit-15, display area-13 a, display control circuit-14, light emission controller-16, scan lines-G1-Gn, Data lines-S1-Sm, Data signal-Data, clock signal-CLK, horizontal synchronization signal-Hsyn, vertical synchronization signal-Vsyn, gate control signal-Cg, source control signal-Cs, Data processing unit-111, gray clock generating unit-112, output unit-113, Data clock signal-DCLK, first pulse width duration-H, gray clock signal-GCLK, original gray clock signal-GCLK _0, Pulse width-T, first gray scale region-GL, second gray scale region-GH.
Detailed Description
To facilitate an understanding of the present application, the present application will now be described more fully with reference to the accompanying drawings. Preferred embodiments of the present application are given in the accompanying drawings. This application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
The following description of the various embodiments refers to the accompanying drawings, which are included to illustrate specific embodiments that can be implemented by the application. The numbering of the components as such, e.g., "first", "second", etc., is used herein only to distinguish the objects as described, and does not have any sequential or technical meaning. The term "connected" and "coupled" as used herein includes both direct and indirect connections (couplings), unless otherwise specified. Directional phrases used in this application, such as, for example, "upper," "lower," "front," "rear," "left," "right," "inner," "outer," "side," and the like, refer only to the orientation of the appended drawings and are, therefore, used herein for better and clearer illustration and understanding of the application and are not intended to indicate or imply that the device or element so referred to must have a particular orientation, be constructed and operated in a particular orientation, and are therefore not to be considered limiting of the application.
In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as being fixedly connected, detachably connected, or integrally connected; may be a mechanical connection; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art. It should be noted that the terms "first", "second", and the like in the description and claims of the present application and in the drawings are used for distinguishing different objects and not for describing a particular order.
Furthermore, the terms "comprises," "comprising," "includes," "including," or "including," when used in this application, specify the presence of stated features, operations, elements, and/or the like, but do not limit one or more other features, operations, elements, and/or the like. Furthermore, the terms "comprises" or "comprising" indicate the presence of the respective features, numbers, steps, operations, elements, components or combinations thereof disclosed in the specification, but do not preclude the presence or addition of one or more other features, numbers, steps, operations, elements, components or combinations thereof, and are intended to cover non-exclusive inclusions. Furthermore, when describing embodiments of the present application, the use of "may" mean "one or more embodiments of the present application. Also, the term "exemplary" is intended to refer to an example or illustration.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
Referring to fig. 1, fig. 1 is a schematic structural diagram of a display device 100 according to a first embodiment of the present application. The display device 100 includes a display device 100, the display module 10 and the power module 20 are fixed on the supporting frame 30, and the power module 20 is disposed on the back of the display module 10 for providing a power voltage to the display module 10.
Referring to fig. 2, fig. 2 is a schematic plan layout structure of a display module 10 shown in fig. 1 according to a second embodiment of the present application.
As shown in fig. 2, the display module 10 further includes a data driving circuit 11, a scan driving circuit 12, a display panel 13, a display control circuit 14, and a light emission controller 16. The data driving circuit 11, the scan driving circuit 12, the display control circuit 14, and the light emission controller 16 are disposed in a non-display area of the display panel 13.
In the display region 13a of the display panel 13, a plurality of scanning lines (Gate lines) G1 to Gn extending in the first direction F1 and a plurality of data lines (Source lines) S1 to Sm extending in the second direction F2 are provided in a grid pattern. The first direction F1 and the second direction F2 are perpendicular to each other, and the plurality of scan lines G1-Gn, the plurality of data lines S1-Sm, and the scan lines G1-Gn and the data lines S1-Sm are insulated from each other.
The pixel cells 15 are provided at intersections of the plurality of scanning lines G1 to Gn and the data lines S1 to Sm. In this embodiment, the pixel units 15 are represented by P11-P1 m, P21-P2 m, … …, Pn 1-Pnm, respectively.
The scanning lines G1 to Gn are connected to the scanning driving circuit 12 and receive scanning signals from the scanning driving circuit 12, and the Data lines S1 to Sm are connected to the Data driving circuit 11 and receive Data signals Data stored and transmitted in a gray scale format supplied from the Data driving circuit 11.
The display control circuit 14 receives an original image signal indicating image information, a clock signal CLK for synchronization, a horizontal synchronization signal Hsyn, and a vertical synchronization signal Vsyn from an external signal source, and outputs a gate control signal Cg for controlling the scan drive circuit 12, a source control signal Cs for controlling the Data drive circuit 11, and a Data signal Data indicating image information. In this embodiment, the display control circuit 14 performs Data adjustment processing on the original Data signal to obtain a Data signal Data, and transmits the Data signal Data to the Data driving circuit 11.
The scan driving circuit 12 receives the gate control signal Cg outputted from the display control circuit 14, and outputs a scan signal to each of the scan lines G1 to Gn. The Data driving circuit 11 receives the source control signal Cs, the clock signal CLK, and the Data signal Data output from the display control circuit 14, and outputs driving signals for driving elements performing image display in the respective pixel cells 15 in the display panel 13 to the respective Data lines S1 to Sm. The light emission controller 16 is configured to apply light emission signals to the plurality of pixels to control the pixel unit 15 to emit light, so as to control the pixel unit 15 to display a corresponding image.
Referring to fig. 3, fig. 3 is a schematic connection diagram of the pixel unit 15 in fig. 2. As shown in fig. 3, the pixel unit 15 includes a light emitting diode, the anode of the light emitting diode is connected to the scan lines G1-Gn, the cathode of the light emitting diode is connected to the data lines S1-Sm, each scan line is provided with a P-type MOS transistor, when the gate of the P-type MOS transistor is at a low voltage potential, the source and the drain of the P-type MOS transistor are conducted, so that the light emitting diode connected to the scan line receives a corresponding scan signal, and the anode voltage is increased. The data driving circuit 11 may control the luminance of the led by Pulse Width Modulation (PWM), wherein the wider the Pulse width of the led, the higher the luminance.
Referring to fig. 4, fig. 4 is a block diagram illustrating a circuit of a data driving circuit shown in fig. 2 according to a third embodiment of the present application. As shown in fig. 4, the data driving circuit includes a data processing unit 111, a gradation clock generating unit 112, and an output unit 113. The Data processing unit 111 is configured to receive and store the Data clock signal DCLK and the Data signal Data, and respectively transmit the Data clock signal DCLK to the gray scale clock generating unit 112 and the Data signal Data to the output unit 113 after processing. The Data clock signal DCLK is used for controlling the output time sequence of the Data signal Data, and the Data clock signal has a first pulse width duration H, and in the duration of displaying the image of one frame, the first pulse width duration H is the longest time for the pixel unit performing image display to receive the Data signal Data.
The gray clock generating unit 112 is configured to receive the data clock signal DCLK and perform frequency multiplication/division processing on the data clock signal to generate a gray clock signal GCLK, which is used to control gray scales. The gray clock signal GCLK includes N consecutive gray pulses, where the N consecutive gray pulses include a plurality of first gray pulses having a first duration and a plurality of second gray pulses having a second duration, the first duration is longer than the second duration, the ith gray corresponds to the i gray pulses, i is greater than or equal to 1 and less than or equal to N, N may be 128, 256, and the like according to specific needs, and the application is not limited.
The output unit 113 is configured to receive the Data signal Data and the gray clock signal GCLK, count gray pulses in the gray clock signal GCLK, and generate an output waveform of a PWM signal corresponding to the Data signal Data according to a Data result, that is, a duration of the gray pulse corresponding to the Data signal Data, for controlling the pixel unit 15 to display an image.
Specifically, when the gray scale brightness corresponding to the Data signal Data is smaller than or equal to a first threshold, the first gray scale pulse is counted according to the gray scale brightness corresponding to the Data signal and a counting pulses are obtained, the driving signal is output according to the duration of the a counting pulses, when the gray scale brightness corresponding to the Data signal is larger than the first threshold, the second gray scale pulse is counted according to the gray scale brightness corresponding to the Data signal and b counting pulses are obtained, the driving signal is output according to the duration of the b counting pulses, the driving signal is used for driving the pixel unit to display an image, a is larger than 1 and smaller than or equal to N, and b is larger than 1 and smaller than or equal to N.
Referring to fig. 5, fig. 5 is a schematic diagram illustrating a frequency multiplication/division principle of the gray scale clock generating unit in fig. 4. As shown in fig. 5, the first pulse width H of the data clock signal DCLK is the time for scanning a row of pixel units, and is converted into the gray scale clock signal GCLK by the gray scale clock generating unit 112, and the gray scale clock signal GCLK converts the data clock signal DCLK with the first pulse width H into N gray scale pulses, wherein the ith gray scale corresponds to i gray scale pulses, and i is greater than or equal to 1 and less than or equal to N. One pulse width T includes one pulse, that is, one pulse width T represents gray 1, two pulse widths T represent gray 2, three pulse widths T represent gray 3, and so on, and the length of the pulse width T is controlled to control the gray displayed by the pixel unit 15. The gray level is determined by the number of the same pulse width T, and is independent of the starting time of the pulse width T, for example, the gray level 3 may be ended from the first pulse width T to the third pulse width T, or ended from the fourth pulse width T to the seventh pulse width T, that is, the pixel unit 15 displays the preset gray level, and selects the gray level clock GCLK starting at any time point to open the preset number of pulse widths T within the data clock signal DCLK with the duration of the first pulse width H.
Referring to fig. 6, fig. 6 is a schematic diagram of gray scale pulses in the gray scale clock signal of fig. 4. As shown in fig. 6, the gray clock signal GCLK includes N consecutive gray pulses including a plurality of first gray pulses having a first duration and a plurality of second gray pulses having a second duration, and the first duration is longer than the second duration. Specifically, the gray clock signal GCLK includes a first gray area GL including 1 st to x-th gray pulses, i.e., a plurality of first gray pulses, and a second gray area GH including x +1 th to N-th gray pulses, i.e., a plurality of second gray pulses, where a duration of any one of the 1 st to x-th gray pulses is longer than a duration of any one of the x +1 th to N-th gray pulses, where an i-th gray corresponds to i gray pulses, and i is greater than or equal to 1 and less than or equal to N. The number of gray scale pulses in the first gray scale region GL is less than or equal to the number of gray scale pulses in the second gray scale region GH.
When the gray-scale brightness corresponding to the Data signal Data is less than or equal to the first threshold, the gray-scale pulses in the first gray-scale region GL are counted according to the gray-scale brightness corresponding to the Data signal Data to obtain a count pulses, a is greater than or equal to 1 and less than or equal to x, and the driving signal is output according to the duration of the a count pulses.
When the gray scale brightness corresponding to the Data signal Data is larger than the first threshold, the gray scale pulses in the second gray scale region GH are counted according to the gray scale brightness corresponding to the Data signal Data to obtain b counting pulses, wherein x is larger than b and is smaller than or equal to N, and the driving signal is output according to the duration of the b counting pulses.
The first threshold is 32 when the first gray scale region GL includes 32 gray scales, and the first threshold is 64 when the first gray scale region GL includes 64 gray scales, that is, the first threshold is a boundary value between the first gray scale region GL and the second gray scale region GH.
The original gray clock signal GCLK _0 is an unadjusted gray clock signal, in which the duration of the gray pulses in the first gray area GL is the same, the duration of the gray pulses in the second gray area GH is the same, and the duration of the gray pulses in the first gray area GL is the same as that of the gray pulses in the second gray area GH.
Taking 8 bits as an example, in the data clock signal DCLK, the first pulse width H in the data clock signal DCLK corresponds to 256 gray scale pulses in the gray scale clock signal GCLK, the 256 gray scale pulses correspond to 256 gray scales, and one pulse width T includes one gray scale pulse. The first threshold is 64, that is, 0 to 63 grayscales are set as the first grayscale region GL, and 64 to 255 grayscales are set as the second grayscale region GH. The 64 gray scale pulses in the first gray scale region GL are the same, that is, the pulse widths Ta are the same, the 192 gray scale pulses in the second gray scale region GH are the same, that is, the pulse width Tb is the same, and the duration of one pulse width Ta in the first gray scale region GL is longer than that of one pulse width Tb in the second gray scale region GH, that is, the duration of one gray scale pulse in the first gray scale region GL is longer than that of one gray scale pulse in the second gray scale region GH. For example, one pulse width Ta in the first gray scale region GL may be set to 0.5ms, and one pulse width Tb in the second gray scale region GH may be set to 0.3ms, which may be other values, but the application is not limited thereto.
The pulse width settings of the first gray scale region GL and the second gray scale region GH are mainly adjusted according to the parasitic capacitance in the display panel 13, and due to the parasitic capacitance, the current actually flowing through the pixel unit 15, that is, the current of the light emitting diode, becomes small, so that the gray scale displayed by the pixel unit 15 does not reach the preset gray scale, and a color cast phenomenon occurs, because when the pixel unit 15 performs low gray scale display, the current flowing through the pixel unit 15 is small, and the color cast phenomenon mainly occurs when the pixel unit 15 performs low gray scale display. Therefore, the color shift phenomenon caused by the parasitic capacitance is cancelled by setting the duration of each pulse width Ta in the first gray scale region GL longer.
Specifically, the gray scale displayed by the pixel unit 15 can be ensured by controlling the amount of charge flowing through the pixel unit 15, the pixel unit 15 is not only controlled by the current, but also determined by the number of pulse widths T in the PWM signal, that is, the gray scale clock signal GCLK, and the influence of time on the luminance is linear. And the charge amount Q is equal to It, i.e., the charge amount flowing through the pixel unit 15 is equal to the current multiplied by time, so the relationship of the charge amount to time is also linear. The luminance displayed by the pixel unit 15 may be set to Lv ═ kQ, where k is a constant and Q denotes the total amount of electric charges flowing through the pixel unit 15. The constant k can be obtained by testing the parasitic capacitance in the display panel 13, that is, the constant k is obtained by obtaining the correspondence between the luminance Lv and the charge amount Q when no color cast occurs by debugging.
In one embodiment, the pulse width T of the gray clock signal GCLK may be set by determining whether the pixel unit 15 has color cast through a color gamut map. As shown in fig. 7, fig. 7 is a schematic diagram of a standard color gamut. The standard red color coordinates are (0.67,0.33), the standard green color coordinates are (0.21,0.71), the standard blue color coordinates are (0.14,0.08), and the standard white color coordinates are (0.33 ). By controlling the pixel unit 15, that is, the led, to display a corresponding standard color, the real display color of the pixel unit 15 corresponds to the color coordinate in the standard color gamut schematic diagram, and then by adjusting the duration of one pulse width Ta of the first gray scale region GL in the gray scale clock signal GCLK, when the color displayed by the pixel unit 15 after adjustment is the standard color, the pulse width at this time is the optimal pulse width.
For example, the pixel unit 15 is controlled to display a standard red color, i.e. the color coordinates in the corresponding color gamut map are (0.67,0.33), and the color displayed by the pixel unit 15 at this time has the color coordinates in the corresponding color gamut map of (0.67,0.25) which has a certain difference from the standard red color coordinates. Then, the pulse width Ta of the first gray area GL in the gray clock signal GCLK is adjusted, and if the pulse width Ta is 0.5ms, the pixel unit 15 displays a standard red color, i.e. the color coordinate is (0.67,0.33), and the pulse width at this time is 0.5ms, which is the required pulse width, so as to eliminate the color shift phenomenon caused by the parasitic capacitance. Of course, the pulse width in the second gray scale region GH can be modulated as described above to eliminate the color cast in the second gray scale region GH.
Referring to fig. 8, fig. 8 is a schematic diagram of gray scale clock signal pulses according to a fourth embodiment of the present application. As shown in fig. 8, the gray clock signal GCLK includes N consecutive gray pulses including a plurality of first gray pulses having a first duration and a plurality of second gray pulses having a second duration, and the first duration is longer than the second duration. The gray clock signal GCLK includes a first gray area GL and a second gray area GH, the first gray area GL includes 1 st to x-th gray pulses, i.e. a plurality of first gray pulses, the second gray area GH includes x +1 th to N-th gray pulses, i.e. a plurality of second gray pulses, the duration of any one of the 1 st to x-th gray pulses is longer than the duration of any one of the x +1 th to N-th gray pulses, wherein the i-th gray corresponds to i gray pulses, and i is greater than or equal to 1 and less than or equal to N.
At least two first gray scale pulses with different durations are included in the first gray scale region GL, and each of the gray scale pulses in the second gray scale region GH has the same duration. The number of gray scale pulses in the first gray scale region GL is less than or equal to the number of gray scale pulses in the second gray scale region GH.
The original gray clock signal GCLK _0 is an unadjusted gray clock signal, in which the duration of the gray pulses in the first gray area GL is the same, the duration of the gray pulses in the second gray area GH is the same, and the duration of the gray pulses in the first gray area GL is the same as that of the gray pulses in the second gray area GH.
Taking 8 bits as an example, in the data clock signal DCLK, the first pulse width H in the data clock signal DCLK corresponds to 256 gray scale pulses in the gray scale clock signal GCLK, the 256 gray scale pulses correspond to 256 gray scales, and one pulse width T includes one gray scale pulse. The first threshold is 64, that is, 0 to 63 grayscales are set as the first grayscale region GL, and 64 to 255 grayscales are set as the second grayscale region GH. The 64 pulse widths Ta in the first gray scale region GL are not identical and may be set to pulse widths of different time lengths, for example, a first pulse width Ta1 of a time length of 5ms, a second pulse width Ta2 of a time length of 6ms, and a third pulse width Ta3 of a time length of 7ms may be set among the 64 pulse widths Ta.
In an exemplary embodiment, the pulse width types may be set to other numbers according to needs, and the application is not limited.
The pulse widths of the first gray scale region GL and the second gray scale region GH are mainly adjusted according to the parasitic capacitance in the display panel 13.
Specifically, the gray scale displayed by the pixel unit 15 can be ensured by controlling the amount of charge flowing through the pixel unit 15, the pixel unit 15 is not only controlled by the current, but also determined by the number of pulse widths T in the PWM signal, that is, the gray scale clock signal GCLK, and the influence of time on the luminance is linear. The charge amount Q is equal to It, i.e., the charge amount flowing through the pixel unit 15 is equal to the current multiplied by the time, and thus the relationship between the charge amount and the time is also linear. The luminance displayed by the pixel unit 15 may be set to Lv ═ kQ, where k is a constant and Q denotes the total amount of electric charges flowing through the pixel unit 15. The constant k can be obtained by testing the parasitic capacitance in the display panel 13, that is, the constant k is obtained by obtaining the correspondence between the luminance Lv and the charge amount Q when no color cast occurs by debugging.
In one embodiment, the pulse width T of the gray clock signal GCLK may be set by determining whether the pixel unit 15 has color cast through a color gamut map. As shown in fig. 7, fig. 7 is a schematic diagram of a standard color gamut. The standard red color coordinates are (0.67,0.33), the standard green color coordinates are (0.21,0.71), the standard blue color coordinates are (0.14,0.08), and the standard white color coordinates are (0.33 ). By applying a voltage corresponding to a standard color, i.e., a standard red, a standard green or a standard blue, to the pixel unit 15, i.e., the light emitting diode, the real display color of the pixel unit 15 corresponds to the color coordinate in the standard color gamut diagram, and then by adjusting the duration of one pulse width Ta of the first gray scale region GL in the gray scale clock signal GCLK, when the display color of the pixel unit 15 after adjustment is the standard color, the pulse width T at this time is the optimal pulse width.
For example, the pixel unit 15 is controlled to display a standard red color, i.e. the color coordinates in the corresponding color gamut map are (0.67,0.33), and the color displayed by the pixel unit 15 at this time has the color coordinates in the corresponding color gamut map of (0.67,0.25) which has a certain difference from the standard red color coordinates. Then, the pulse width Ta of the first gray area GL in the gray clock signal GCLK is adjusted, and if the pulse width T is 0.5ms, the pixel unit 15 displays a standard red color, i.e. the color coordinate is (0.67,0.33), and the pulse width T at this time is 0.5ms, which is the required pulse width, thereby eliminating the color shift phenomenon caused by the parasitic capacitance.
Referring to fig. 9, fig. 9 is a method for outputting a driving signal according to a fifth embodiment of the present disclosure. As shown in fig. 9, the specific steps are as follows:
step S101, outputting a data clock signal to the gray scale clock generating unit and outputting a data signal for displaying an image to the output unit, where the data clock signal has a first pulse width duration, and the first pulse width duration is the longest time for a pixel unit performing image display to receive the data signal in a frame of image display duration.
Step S102, outputting a gray scale clock signal according to the data clock signal, wherein the gray scale clock signal includes N continuous gray scale pulses, the N continuous gray scale pulses include a plurality of first gray scale pulses with a first duration and a plurality of second gray scale pulses with a second duration, and the first duration is longer than the second duration.
The duration of the 1 st to x th gray scale pulses in the first gray scale region is adjusted according to the parasitic capacitance of the display panel 13, specifically: a voltage corresponding to standard white is applied to any number of pixel units 15, and a voltage corresponding to standard red, standard green, or standard blue may also be applied to control the pixel units 15 to display.
And determining the color coordinates corresponding to the current display color of the pixel unit according to the color gamut map. After the pixel unit 15 is applied with a voltage, the displayed color has a certain difference from the standard white due to the existence of the parasitic capacitance, and the color coordinate corresponding to the currently displayed color is determined by the color gamut map.
And comparing the current color coordinate of the pixel unit with the standard white color coordinate. And determining whether a difference exists between the color coordinate of the current display color and the standard white color coordinate according to the color gamut map, if so, indicating that the parasitic capacitance exists, and if not, indicating that no parasitic capacitance influence exists.
The duration of the 1 st to x-th gray scale pulses in the first gray scale region GL is adjusted to control the pixel unit to display the standard white color. Since the parasitic capacitance has a large influence on the low gray level displayed by the pixel unit, the pulse width of the first gray level region GL is mainly adjusted. According to the color gamut diagram, when the color coordinates of the pixel unit 15 are the standard white color coordinates (0.33 ), it is shown that the influence of the parasitic capacitance has been eliminated, and the pulse width T is the optimal pulse width.
The method can also display standard white for the control pixel unit, determine the standard charge amount flowing through the pixel unit, adjust the duration of the 1 st to x-th gray scale pulses in the first gray scale region to control the charge amount flowing through the pixel unit as the standard charge amount, and obtain the adjusted 1 st to x-th gray scale pulses.
Step S103, when the gray scale brightness corresponding to the data signal is smaller than or equal to a first threshold, counting the first gray scale pulse according to the gray scale brightness corresponding to the data signal and obtaining a counting pulses, outputting a driving signal according to the duration of the a counting pulses, when the gray scale brightness corresponding to the data signal is larger than the first threshold, counting the second gray scale pulse according to the gray scale brightness corresponding to the data signal and obtaining b counting pulses, and outputting the driving signal according to the duration of the b counting pulses, wherein the driving signal is used for driving the pixel unit to display an image, a is larger than 1 and smaller than or equal to N, and b is larger than 1 and smaller than or equal to N.
It is to be understood that the invention is not limited to the examples described above, but that modifications and variations may be effected thereto by those of ordinary skill in the art in light of the foregoing description, and that all such modifications and variations are intended to be within the scope of the invention as defined by the appended claims.
Claims (10)
1. A data driving circuit includes a data processing unit, a gray clock generating unit, and an output unit,
the data processing unit outputs a data clock signal to the gray scale clock generating unit, and simultaneously outputs a data signal for image display to the output unit, wherein the data clock signal has a first pulse width duration, and the first pulse width duration is the longest time for a pixel unit executing image display to receive the data signal in one frame of image display duration;
the gray clock generating unit outputs a gray clock signal according to the data clock signal, wherein the gray clock signal comprises N continuous gray pulses, the N continuous gray pulses comprise a plurality of first gray pulses with first duration and a plurality of second gray pulses with second duration, and the first duration is longer than the second duration;
the output unit is used for receiving the data signal, counting the first gray pulses according to the gray-scale brightness corresponding to the data signal and obtaining a counting pulses when the gray-scale brightness corresponding to the data signal is smaller than or equal to a first threshold, outputting driving signals according to the duration of the a counting pulses, counting the second gray pulses according to the gray-scale brightness corresponding to the data signal and obtaining b counting pulses when the gray-scale brightness corresponding to the data signal is larger than the first threshold, and outputting driving signals according to the duration of the b counting pulses, wherein the driving signals are used for driving the pixel unit to display images, a is larger than 1 and smaller than or equal to N, and b is larger than 1 and smaller than or equal to N.
2. The data driving circuit of claim 1,
the gray scale clock signal comprises a first gray scale area and a second gray scale area, the first gray scale area comprises 1 st to x-th gray scale pulses, and the first gray scale pulse is any one of the 1 st to x-th gray scale pulses;
the second gray scale region comprises the (x + 1) -N gray scale pulses, and the second gray scale pulse is any one of the (x + 1) -N gray scale pulses;
the duration of any one of the 1 st to x th gray scale pulses is longer than that of any one of the x +1 th to N th gray scale pulses, wherein the ith gray scale corresponds to the i gray scale pulses, and i is more than or equal to 1 and less than or equal to N;
when the gray scale brightness corresponding to the data signal is smaller than or equal to a first threshold value, counting the gray scale pulses in the first gray scale area according to the gray scale brightness corresponding to the data signal and obtaining a counting pulses, wherein a is greater than or equal to 1 and less than or equal to x, and outputting a driving signal according to the duration of the a counting pulses;
and when the gray scale brightness corresponding to the data signal is greater than a first threshold value, counting the gray scale pulses in the second gray scale region according to the gray scale brightness corresponding to the data signal and obtaining b counting pulses, wherein x is greater than b and is less than or equal to N, and outputting a driving signal according to the duration of the b counting pulses.
3. The data driving circuit according to claim 1 or 2, wherein a duration of each of the gray scale pulses in the first gray scale region is the same, and a duration of each of the gray scale pulses in the second gray scale region is the same.
4. The data driving circuit according to claim 1 or 2, wherein at least two gray scale pulses having different durations are included in the first gray scale region, and each of the gray scale pulses in the second gray scale region has the same duration.
5. The data driving circuit according to claim 1 or 2, wherein the number of gray scale pulses in the first gray scale region is less than or equal to the number of gray scale pulses in the second gray scale region.
6. A method of outputting a drive signal by a data driving circuit according to any of claims 1 to 5,
outputting a data clock signal to the gray clock generating unit and outputting a data signal for displaying an image to the output unit, wherein the data clock signal has a first pulse width duration, and the first pulse width duration is the longest time for a pixel unit performing image display to receive the data signal in one frame of image display duration;
outputting a gray scale clock signal according to the data clock signal, wherein the gray scale clock signal comprises N continuous gray scale pulses, the N continuous gray scale pulses comprise a plurality of first gray scale pulses with a first duration and a plurality of second gray scale pulses with a second duration, and the first duration is longer than the second duration;
when the gray scale brightness corresponding to the data signal is smaller than or equal to a first threshold, counting the first gray scale pulse according to the gray scale brightness corresponding to the data signal and obtaining a counting pulses, outputting a driving signal according to the duration of the a counting pulses, when the gray scale brightness corresponding to the data signal is larger than the first threshold, counting the second gray scale pulse according to the gray scale brightness corresponding to the data signal and obtaining b counting pulses, and outputting a driving signal according to the duration of the b counting pulses, wherein the driving signal is used for driving the pixel unit to display an image, a is larger than 1 and smaller than or equal to N, and b is larger than 1 and smaller than or equal to N.
7. The method of claim 6, wherein outputting a gray scale clock signal according to the data clock signal comprises:
applying a voltage corresponding to a standard white color to a pixel unit, determining a color coordinate corresponding to a current display color of the pixel unit according to a color gamut diagram, comparing the current color coordinate of the pixel unit with the color coordinate corresponding to the standard white color, adjusting the duration of 1 st to x gray scale pulses in the first gray scale region to control the pixel unit to display the standard white color, and acquiring the adjusted 1 st to x gray scale pulses when the current color coordinate of the pixel unit is the color coordinate of the standard white color.
8. The method of claim 6, wherein outputting a gray scale clock signal according to the data clock signal comprises:
controlling a pixel unit to display standard white, determining the standard charge amount flowing through the pixel unit, adjusting the duration of the 1 st to x gray scale pulses in the first gray scale area to control the charge amount flowing through the pixel unit to be the standard charge amount, and acquiring the adjusted 1 st to x gray scale pulses.
9. A display module, comprising a display control circuit, a scan driving circuit, a display panel, a light emitting controller and the data driving circuit as claimed in any one of claims 1 to 5, wherein the display control circuit receives an original data signal according to an external signal source and outputs a source control signal and a gate control signal respectively, and the data driving circuit cooperates with the light emitting controller to control the display panel to display images according to the source control signal and the scan driving circuit according to the gate control signal.
10. The display module as claimed in claim 9, wherein the display panel is provided with a plurality of scan lines extending along a first direction, a plurality of data lines extending along a second direction F2, and pixel units are disposed at intersections of the plurality of scan lines and the plurality of data lines, the pixel units are light emitting diodes, anodes of the light emitting diodes are connected to the scan lines to receive scan signals, and cathodes of the light emitting diodes are connected to the data lines to receive data signals.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210832800.4A CN115050317B (en) | 2022-07-15 | 2022-07-15 | Data driving circuit, display module and method for outputting driving signal |
| PCT/CN2022/132868 WO2024011807A1 (en) | 2022-07-15 | 2022-11-18 | Data driving circuit, display module, and method for outputting driving signal |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210832800.4A CN115050317B (en) | 2022-07-15 | 2022-07-15 | Data driving circuit, display module and method for outputting driving signal |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN115050317A true CN115050317A (en) | 2022-09-13 |
| CN115050317B CN115050317B (en) | 2023-03-21 |
Family
ID=83165843
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210832800.4A Active CN115050317B (en) | 2022-07-15 | 2022-07-15 | Data driving circuit, display module and method for outputting driving signal |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN115050317B (en) |
| WO (1) | WO2024011807A1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2024011807A1 (en) * | 2022-07-15 | 2024-01-18 | 惠科股份有限公司 | Data driving circuit, display module, and method for outputting driving signal |
Citations (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107016955A (en) * | 2017-04-07 | 2017-08-04 | 合肥集创微电子科技有限公司 | LED display and its driving method |
| CN110277052A (en) * | 2019-06-13 | 2019-09-24 | 华中科技大学 | Multirow sweeps the all-colour LED driving chip and driving method of high refresh rate |
| CN110853573A (en) * | 2019-11-29 | 2020-02-28 | 上海天马微电子有限公司 | Display device and driving method thereof |
| KR20200038741A (en) * | 2018-10-04 | 2020-04-14 | 삼성전자주식회사 | Display panel and driving method of the display panel |
| CN111477165A (en) * | 2020-05-13 | 2020-07-31 | 深圳市华星光电半导体显示技术有限公司 | Display device and driving method thereof |
| TWI701648B (en) * | 2019-08-06 | 2020-08-11 | 大陸商北京集創北方科技股份有限公司 | LED display drive circuit, LED drive current modulation method, and LED display |
| US20200394953A1 (en) * | 2019-06-17 | 2020-12-17 | Samsung Electronics Co., Ltd. | Display module and driving method thereof |
| US20210035493A1 (en) * | 2019-07-30 | 2021-02-04 | Innolux Corporation | Display device |
| CN112992041A (en) * | 2021-02-26 | 2021-06-18 | 合肥维信诺科技有限公司 | Display panel, driving method thereof and display device |
| CN113012634A (en) * | 2021-03-05 | 2021-06-22 | 京东方科技集团股份有限公司 | Pixel circuit, driving method thereof and display device |
| US20210343223A1 (en) * | 2019-06-05 | 2021-11-04 | Lg Display Co., Ltd. | Light emitting display device and method for driving same |
| CN113658551A (en) * | 2021-08-19 | 2021-11-16 | 深圳市华星光电半导体显示技术有限公司 | Pixel circuit driving method, pixel driving device and display device |
| CN113724640A (en) * | 2020-05-26 | 2021-11-30 | 京东方科技集团股份有限公司 | Pixel driving circuit, driving method thereof, display panel and display device |
| CN113948033A (en) * | 2020-07-15 | 2022-01-18 | 厦门凌阳华芯科技有限公司 | High-precision PWM driving method, device and medium for LED display screen |
| CN114155807A (en) * | 2021-12-09 | 2022-03-08 | 深圳市奥视微科技有限公司 | Pixel driving device and pixel driving method |
| CN114664234A (en) * | 2022-03-17 | 2022-06-24 | Tcl华星光电技术有限公司 | Hybrid driving method of display and hybrid driving module of display |
Family Cites Families (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000231360A (en) * | 1999-11-16 | 2000-08-22 | Canon Inc | Image forming device |
| CN110796985B (en) * | 2018-07-24 | 2022-03-11 | 群创光电股份有限公司 | Electronic device |
| CN111462705B (en) * | 2020-04-14 | 2021-09-24 | Tcl华星光电技术有限公司 | Display panel driving method and display device |
| CN113012624B (en) * | 2020-07-31 | 2022-04-29 | 重庆康佳光电技术研究院有限公司 | LED display device and driving method thereof |
| WO2022095044A1 (en) * | 2020-11-09 | 2022-05-12 | 京东方科技集团股份有限公司 | Display panel and driving method therefor, and display device |
| KR20220084785A (en) * | 2020-12-14 | 2022-06-21 | 주식회사 엘엑스세미콘 | Led display driving apparatus and led display device |
| CN112908264B (en) * | 2021-01-26 | 2022-04-12 | 厦门天马微电子有限公司 | Pixel driving circuit, driving method, display panel and display device |
| CN113674691B (en) * | 2021-08-30 | 2023-03-24 | 武汉华星光电半导体显示技术有限公司 | Display brightness adjusting method and adjusting device |
| CN115050317B (en) * | 2022-07-15 | 2023-03-21 | 惠科股份有限公司 | Data driving circuit, display module and method for outputting driving signal |
-
2022
- 2022-07-15 CN CN202210832800.4A patent/CN115050317B/en active Active
- 2022-11-18 WO PCT/CN2022/132868 patent/WO2024011807A1/en unknown
Patent Citations (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107016955A (en) * | 2017-04-07 | 2017-08-04 | 合肥集创微电子科技有限公司 | LED display and its driving method |
| KR20200038741A (en) * | 2018-10-04 | 2020-04-14 | 삼성전자주식회사 | Display panel and driving method of the display panel |
| US20210343223A1 (en) * | 2019-06-05 | 2021-11-04 | Lg Display Co., Ltd. | Light emitting display device and method for driving same |
| CN110277052A (en) * | 2019-06-13 | 2019-09-24 | 华中科技大学 | Multirow sweeps the all-colour LED driving chip and driving method of high refresh rate |
| US20200394953A1 (en) * | 2019-06-17 | 2020-12-17 | Samsung Electronics Co., Ltd. | Display module and driving method thereof |
| US20210035493A1 (en) * | 2019-07-30 | 2021-02-04 | Innolux Corporation | Display device |
| TWI701648B (en) * | 2019-08-06 | 2020-08-11 | 大陸商北京集創北方科技股份有限公司 | LED display drive circuit, LED drive current modulation method, and LED display |
| CN110853573A (en) * | 2019-11-29 | 2020-02-28 | 上海天马微电子有限公司 | Display device and driving method thereof |
| CN111477165A (en) * | 2020-05-13 | 2020-07-31 | 深圳市华星光电半导体显示技术有限公司 | Display device and driving method thereof |
| CN113724640A (en) * | 2020-05-26 | 2021-11-30 | 京东方科技集团股份有限公司 | Pixel driving circuit, driving method thereof, display panel and display device |
| CN113948033A (en) * | 2020-07-15 | 2022-01-18 | 厦门凌阳华芯科技有限公司 | High-precision PWM driving method, device and medium for LED display screen |
| CN112992041A (en) * | 2021-02-26 | 2021-06-18 | 合肥维信诺科技有限公司 | Display panel, driving method thereof and display device |
| CN113012634A (en) * | 2021-03-05 | 2021-06-22 | 京东方科技集团股份有限公司 | Pixel circuit, driving method thereof and display device |
| CN113658551A (en) * | 2021-08-19 | 2021-11-16 | 深圳市华星光电半导体显示技术有限公司 | Pixel circuit driving method, pixel driving device and display device |
| CN114155807A (en) * | 2021-12-09 | 2022-03-08 | 深圳市奥视微科技有限公司 | Pixel driving device and pixel driving method |
| CN114664234A (en) * | 2022-03-17 | 2022-06-24 | Tcl华星光电技术有限公司 | Hybrid driving method of display and hybrid driving module of display |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2024011807A1 (en) * | 2022-07-15 | 2024-01-18 | 惠科股份有限公司 | Data driving circuit, display module, and method for outputting driving signal |
Also Published As
| Publication number | Publication date |
|---|---|
| CN115050317B (en) | 2023-03-21 |
| WO2024011807A1 (en) | 2024-01-18 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US11043188B2 (en) | Driving method for pulse width and voltage hybrid modulation, driving device and display device | |
| CN101202017B (en) | Backlight brightness control for liquid crystal display panel | |
| US20070132674A1 (en) | Driving method of self-luminous type display unit, display control device of self-luminous type display unit, current output type drive circuit of self-luminous type display unit | |
| KR101493493B1 (en) | Backlight device and liquid crystal display device including the same | |
| US9520097B2 (en) | Display device with compensating backlight drive circuit and method for driving same | |
| US20060208974A1 (en) | Organic electroluminescent device, driving method thereof and electronic apparatus | |
| US20060125742A1 (en) | Liquid-crystal display device and method of driving liquid-crystal display device | |
| CN101320539A (en) | Display and method of driving the same | |
| US8416175B2 (en) | Liquid crystal display device and method for driving the same | |
| CN109961741A (en) | Organic light-emitting diode (OLED) display apparatus | |
| CN111883079B (en) | Driving method and circuit of display panel and display device | |
| CN102074182A (en) | Display device and driving method thereof | |
| KR101548845B1 (en) | Display device and driving method | |
| CN105741717A (en) | Display device | |
| JP2002366113A (en) | Liquid crystal driving device | |
| CN112216237A (en) | Display control method, time sequence control chip and display device | |
| CN112289246A (en) | Display device | |
| JP2007536594A (en) | Color display device | |
| US11361731B2 (en) | Display device and method of driving the same | |
| EP1530743B1 (en) | Liquid crystal display | |
| CN111341278A (en) | Overdrive processing method and overdrive device for image data | |
| CN115050317B (en) | Data driving circuit, display module and method for outputting driving signal | |
| KR20140119511A (en) | Organic light emitting display device and driving method thereof | |
| CN100362541C (en) | Drive controlling device for matrix displaying panel and drive controlling method | |
| CN100565638C (en) | The driving method of self-luminous display device, display control unit and current output type drive circuit thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |