CN112992041A - Display panel, driving method thereof and display device - Google Patents
Display panel, driving method thereof and display device Download PDFInfo
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
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- G—PHYSICS
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- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/02—Improving the quality of display appearance
- G09G2320/0233—Improving the luminance or brightness uniformity across the screen
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Abstract
The embodiment of the invention discloses a display panel, a driving method thereof and a display device, wherein the display panel comprises a pixel circuit and a data line connected with the pixel circuit; the frame display of the display panel includes a high gray scale display and a low gray scale display, the data lines are configured to transmit data voltages of the same magnitude to the pixel circuits for different gray scales at least at the low gray scale display, and the time periods for transmitting the data voltages are different. Compared with the prior art, the technical scheme provided by the embodiment of the invention is favorable for realizing the threshold compensation effect during low gray scale display, thereby being favorable for improving the bad phenomena of display unevenness and the like under low gray scale.
Description
Technical Field
The embodiment of the invention relates to the technical field of display, in particular to a display panel, a driving method thereof and a display device.
Background
With the continuous development of display technology, people have higher and higher requirements on display panels.
The display panel usually adopts the pixel circuit to provide stable light for the light emitting device, however, the performance of the pixel circuit in the prior art is not perfect, and when the display panel is under low gray scale display, the image quality is not uniform.
Disclosure of Invention
The embodiment of the invention provides a display panel, a driving method thereof and a display device, which are used for ensuring the display effect of the display panel in low gray scale.
In a first aspect, an embodiment of the present invention provides a display panel, including: the pixel circuit and the data line connected with the pixel circuit;
the frame display of the display panel includes a high gray scale display and a low gray scale display, the data lines are configured to transmit data voltages of the same magnitude to the pixel circuits for different gray scales at least at the low gray scale display, and the time periods for transmitting the data voltages are different.
Optionally, in the high gray scale display, the data lines are configured to transmit data voltages of different magnitudes to the pixel circuits for different gray scales, and the duration of transmitting the data voltages is the same.
Optionally, the gray levels of the low gray level display include gray levels of 0-32.
Optionally, at a first display gray scale, the data line is configured to transmit a first data voltage to the pixel circuit for a first period of time, and at a second display gray scale, the data line is configured to transmit a second data voltage to the pixel circuit for a second period of time, the first data voltage and the second data voltage having the same magnitude; the first display gray scale is larger than the second display gray scale, and the duration of the first time period is larger than the duration of the second time period.
Optionally, the pixel circuit comprises a driving transistor and a light emitting module;
the driving transistor is used for generating driving current according to the data voltage to drive the light emitting module to emit light; in the low gray scale display, the driving transistor operates in a saturation region.
Optionally, the pixel circuit includes: the transistor comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, a storage capacitor and a light emitting diode;
a gate of the second transistor is connected to a second scan signal line, a first pole of the second transistor is connected to the data line, a second pole of the second transistor is connected to a first pole of the first transistor, a second pole of the first transistor is connected to a first pole of the third transistor, and a second pole of the third transistor is connected to a gate of the first transistor;
a gate of the fourth transistor is connected to a first scanning signal line, a gate of the seventh transistor is connected to a third scanning signal line, a first pole of the fourth transistor and a first pole of the seventh transistor are both inputted with a reference voltage, and a second pole of the fourth transistor is connected to a gate of the first transistor;
a gate of the fifth transistor and a gate of the sixth transistor are both connected to a light emission control signal line, a first pole of the fifth transistor is connected to a first power line, a second pole of the fifth transistor is connected to the first pole of the first transistor, a first pole of the sixth transistor is connected to the second pole of the first transistor, a second pole of the sixth transistor is connected to an anode of the light emitting diode, a cathode of the light emitting diode is connected to a second power line, and a second pole of the seventh transistor is connected to the anode of the light emitting diode;
the storage capacitor is connected between the first power supply line and the gate of the first transistor.
Optionally, the turn-on time of the second transistor is greater than or equal to the transmission duration of the data voltage.
In a second aspect, an embodiment of the present invention further provides a driving method of a display panel, where the panel includes a pixel circuit and a data line connected to the pixel circuit, and frame display of the display panel includes high grayscale display and low grayscale display;
the driving method of the display panel includes:
at least in the low gray scale display, the same data voltage is transmitted to the pixel circuit through the data line for different gray scales, and the time length of transmitting the data voltage is different.
Optionally, at least in the low gray scale display, transmitting data voltages of the same magnitude to the pixel circuits through the data lines for different gray scales and transmitting the data voltages for different time periods includes:
transmitting a first data voltage to the data line for a first period of time at a first display gray scale, and transmitting a second data voltage to the pixel circuit for a second period of time at a second display gray scale; the first data voltage and the second data voltage have the same magnitude, the first display gray scale is larger than the second display gray scale, and the duration of the first time period is larger than the duration of the second time period.
In a third aspect, an embodiment of the present invention further provides a display device, including the display panel provided in any embodiment of the present invention, and the display device further includes a driving chip, where the driving chip is connected to the data line, and is configured to transmit a data voltage to the data line.
According to the technical scheme provided by the embodiment of the invention, the data lines are configured to be at least displayed in low gray scales, the data voltages with the same size are transmitted to the pixel circuit aiming at different gray scales, and the transmission duration of the data voltages is different, so that the display of different gray scales is realized. When the high gray scale is displayed, the data voltages with different sizes are transmitted to the pixel circuit according to different gray scales, the time length for transmitting the data voltages is the same, or the data voltages with the same size are transmitted, the time length for transmitting the data voltages is different, and different gray scale display under the high gray scale is realized. When the low gray scale is displayed, the same data voltage (the same as the data voltage under the high gray scale display) is transmitted to the pixel circuit aiming at different gray scales, and the different gray scale displays under the low gray scale are realized due to different time lengths of the data voltage transmission. Compared with the prior art, the technical scheme provided by the embodiment of the invention is favorable for realizing the threshold compensation effect during low gray scale display, thereby being favorable for improving the bad phenomena of display unevenness and the like under low gray scale and ensuring the display effect of the display panel during low gray scale.
Drawings
FIG. 1 is a schematic diagram of an output characteristic of a transistor;
FIG. 2 is a schematic diagram of a transfer characteristic of a transistor;
fig. 3 is a schematic structural diagram of a display panel according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of a pixel circuit according to an embodiment of the present invention;
fig. 5 is a schematic diagram of a driving timing sequence of a pixel circuit according to an embodiment of the invention;
FIG. 6 is a schematic diagram of a driving timing sequence of another pixel circuit according to an embodiment of the present invention;
FIG. 7 is a schematic diagram of a driving timing sequence of another pixel circuit according to an embodiment of the present invention;
fig. 8 is a schematic structural diagram of a display device according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.
As described in the background art, the conventional display panel has an uneven image quality when displaying in a low gray scale. The inventor researches and finds that the above problem occurs because the conventional pixel circuit realizes display with different brightness by writing data voltages of different magnitudes with a fixed writing time of the data voltage for different gray scales, but the threshold compensation effect is poor at the low gray scale. The pixel circuit generally includes a driving transistor and a light emitting diode, and the driving transistor is used for providing a driving current to the light emitting diode to drive the light emitting diode to emit light. FIG. 1 is a schematic diagram of an output characteristic curve of a transistor, FIG. 2 is a schematic diagram of a transfer characteristic curve of the transistor, referring to FIGS. 1 and 2, an operating region of the transistor can be divided into a non-saturation region, a saturation region breakdown region and a cut-off region when a gate-source voltage U of the transistor is higher than a threshold voltage UGSLess than the threshold voltage of the transistorThe transistor works in a cut-off region; when the gate-source voltage U of the transistorGSGreater than the threshold voltage of the transistor and having a drain-source voltage UDSWhen the current is low, the transistor works in a non-saturation region, and the transistor is used for switching; when the gate-source voltage U of the transistorGSGreater than the threshold voltage of the transistor and having a drain-source voltage UDSWhen the voltage is higher, the transistor works in a breakdown region; when drain-source voltage U of transistorDSIs higher than the pre-pinch-off voltage (critical voltage for making the transistor transition from non-saturation region to saturation region) and lower than the breakdown voltage, the transistor works in the saturation region, and at the moment, the gate-source voltage U is appliedGSAt fixed time, the driving current I output by the transistorDNot dependent on drain-source voltage UDSMay vary.
Because the threshold voltage Vth of the driving transistor is greatly influenced by the process, the same grid-source voltage U corresponds to different driving transistorsGSDifferent driving currents may also be generated, resulting in display unevenness of the display screen. The existing pixel circuit usually adopts a 7T1C architecture to compensate the threshold voltage Vth of the driving transistor to optimize the display non-uniformity. However, the pixel circuit architecture can only perform threshold compensation on the driving transistor working in the saturation region, and when the display panel is in low gray scale display, the gate voltage of the driving transistor is lower, so that the gate-source voltage U is enabled to be lowerGSDecrease, as can be seen from FIG. 2, when the gate-source voltage U is loweredGSWhen the threshold voltage is reduced, the working state of the driving transistor is gradually shifted from the saturation region to the cut-off region (non-saturation region), accordingly, the driving current of the cut-off region (non-saturation region) does not conform to the calculation formula of the driving current of the saturation region, and the threshold value compensation scheme based on the saturation region is not applicable, so that the compensation of the threshold voltage Vth of the driving transistor cannot be realized under the low gray scale display, and the problem of uneven low gray scale display occurs.
In view of the above problems, embodiments of the present invention provide a display panel to improve the display effect of the display panel in low gray scale. Fig. 3 is a schematic structural diagram of a display panel according to an embodiment of the present invention, and referring to fig. 3, the display panel according to the embodiment of the present invention includes: pixel circuits PX and data lines DL1-DLj connected to the pixel circuits PX; the frame display of the display panel includes a high gray scale display and a low gray scale display, the data lines DL1-DLj are configured to transmit the data voltage Vdata of the same magnitude to the pixel circuits PX for different gray scales at least at the low gray scale display, and the time period for transmitting the data voltage Vdata is different.
The data lines DL1-DLj are connected to the driver chip 101, and the driver chip 101 is used for providing data signals to the data lines DL 1-DLj; the gate driver 102 is connected to a plurality of gate control lines (GL1-GLk) for providing gate driving signals. The frame display of the display panel comprises high gray scale display and low gray scale display, and under the normal condition, the high gray scale display has higher brightness and larger corresponding drive current; the brightness of low gray scale display is lower, and the corresponding driving current is smaller. In the embodiment, different driving currents are obtained by fixing the size of the data voltage Vdata transmitted to the pixel circuit PX and adjusting the time length of the data voltage Vdata transmitted, so as to obtain different gray scale displays. Particularly, in the low gray scale display, the same data voltage Vdata is transmitted to the pixel circuit PX for different gray scales, and the time duration for transmitting the data voltage Vdata is different, for example, the larger the gray scale is, the longer the time duration for transmitting the data voltage Vdata is, so as to ensure that the display panel can display with normal brightness.
In this embodiment, the data voltage Vdata transmitted to the pixel circuit PX may be lower than the data voltage corresponding to the normal light-emitting luminance regardless of the high gray-scale display or the low gray-scale display.
Fig. 4 is a schematic structural diagram of a pixel circuit according to an embodiment of the present invention, and fig. 4 specifically shows a pixel circuit with a 7T1C architecture, of course, in other embodiments, the pixel circuit PX may also be another architecture with a threshold compensation function, which is not limited in this embodiment, and this embodiment only takes the pixel circuit shown in fig. 4 as an example for description. The pixel circuit PX includes: a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, a storage capacitor Cst, and a light emitting diode D; a gate of the second transistor T2 is connected to the second scan signal line, a first pole of the second transistor T2 is connected to the data line DLj, a second pole of the second transistor T2 is connected to a first pole of the first transistor T1, a second pole of the first transistor T1 is connected to a first pole of the third transistor T3, and a second pole of the third transistor T3 is connected to a gate of the first transistor T1; a gate of the fourth transistor T4 is connected to the first scan signal line, a gate of the seventh transistor T7 is connected to the third scan signal line, a first pole of the fourth transistor T4 and a first pole of the seventh transistor T7 are both inputted with the reference voltage Vref, and a second pole of the fourth transistor T4 is connected to a gate of the first transistor T1; a gate of the fifth transistor T5 and a gate of the sixth transistor T6 are both connected to a light emission control signal line, a first pole of the fifth transistor T5 is connected to a first power supply line, a second pole of the fifth transistor T5 is connected to a first pole of the first transistor T6, a first pole of the sixth transistor T6 is connected to a second pole of the first transistor T1, a second pole of the sixth transistor T6 is connected to an anode of the light emitting diode D, a cathode of the light emitting diode D is connected to a second power supply line, and a second pole of the seventh transistor T7 is connected to an anode of the light emitting diode D; the storage capacitor Cst is connected between the first power line and the gate of the first transistor T1.
Wherein the first to seventh transistors T1 to T7 may be N-type transistors or P-type transistors, fig. 4 exemplarily shows a case where all the transistors are N-type transistors,
the pixel circuit PX includes at least an initialization stage, a data writing stage, and a light emitting stage;
in the initialization stage, the fourth transistor T4 is turned on by the first Scan signal Scan1, the reference voltage VREF is written into the gate of the first transistor T1, and the potential of the gate of the first transistor T1 is initialized to the potential of the reference voltage VREF.
In the data writing phase, the second transistor T2 and the third transistor T3 are turned on by the second Scan signal Scan2, the data voltage Vdata on the data line DLj is written into the gate of the first transistor T1 and the end of the storage capacitor Cst connected to the gate of the first transistor T1 through the second transistor T2, and the threshold voltage compensation of the first transistor T1 is realized through the third transistor T3, at this time, the storage capacitor Cst maintains the potential of the gate of the first transistor T1 at Vdata + Vth, where Vth is the threshold voltage of the first transistor T1.
At the same time of the data writing phase, the seventh transistor T7 is turned on by the third Scan signal Scan3, and the reference voltage Vref is written to the anode of the light emitting diode D, so that the potential of the anode of the light emitting diode D is initialized.
In the light emitting phase, the light emitting control signal EM controls the fifth transistor T5 and the sixth transistor T6 to be turned on, the voltage ELVDD on the first power line is input to the anode of the light emitting diode D through the fifth transistor T5, the first transistor T1 and the sixth transistor T6, the voltage ELVSS on the second power line is input to the cathode of the light emitting diode D, the storage capacitor Cst maintains the potential of the gate of the first transistor T1 at Vdata + Vth, and the first transistor T1 generates the driving signal to drive the light emitting diode D to emit light.
The frame display of the display panel comprises a high gray scale display and a low gray scale display, and the high gray scale display and the low gray scale display both comprise the three stages (an initialization stage, a data writing stage and a light emitting stage). Fig. 5 is a schematic diagram of a driving timing sequence of a pixel circuit according to an embodiment of the invention, and with reference to fig. 4 and 5, an example of the pixel circuit PX is composed of N-type transistors, where t1 is a high gray scale display and t2 is a low gray scale display.
The high gray scale display t1 includes an initialization phase t11, a data writing phase t12 and a light emitting phase t 13.
In the initialization stage t11, the first Scan signal Scan1 is at a high level, the second Scan signal Scan is at a low level, the third Scan signal Scan3 is at a low level, and the emission control signal EM is at a low level. The second transistor T2 and the third transistor T3 are both in an off state under the control of the second Scan signal Scan2, the seventh transistor T7 is in an off state under the control of the third Scan signal Scan3, the fourth transistor T4 is turned on under the control of the first Scan signal Scan1, and the reference voltage Vref is written to the gate of the first transistor T1 (i.e., the gate of the driving transistor) to initialize the gate of the first transistor T1, so as to ensure that the display result of the previous frame does not affect the display of the current frame.
It should be noted that, in the initialization stage T11, the emission control signal EM is set to be high first and then low, which is set to drain the current, so as to ensure that the driving current generated by the first transistor T1 in the previous frame is completely released, so as not to affect the display of the current frame.
In the data writing phase t12, the first Scan signal Scan1 is at a low level, the second Scan signal Scan is at a high level, the third Scan signal Scan3 is at a high level, and the emission control signal EM is at a low level. The fourth transistor T4 is turned off under the control of the first Scan signal Scan1, the second transistor T2 and the third transistor T3 are turned on under the control of the second Scan signal Scan2, the data voltage Vdata is written into the gate of the first transistor T1, and the potential of the gate of the first transistor T1 is Vdata + Vth due to the compensation effect of the third transistor T3, wherein Vdata is data 1. Meanwhile, the seventh transistor T7 is turned on under the control of the third Scan signal Scan3, and writes the reference voltage Vref to the anode of the light emitting diode D, thereby initializing the anode potential of the light emitting diode D.
In the light emission period t13, the first Scan signal Scan1 is at a low level, the second Scan signal Scan is at a low level, the third Scan signal Scan3 is at a low level, and the light emission control signal EM is at a high level. The fourth transistor T4 is turned off under the control of the first Scan signal Scan1, the second transistor T2 and the third transistor T3 are turned off under the control of the second Scan signal Scan2, the fifth transistor T5 and the sixth transistor T6 are turned on under the control of the emission control signal EM, the voltage ELVDD on the first power line is written into the first pole of the first transistor T1 through the fifth transistor T5, and the first transistor T1 generates the driving current I since the voltage stored on the storage capacitor Cst is data1+ VthDAnd driving the light emitting diode D to emit light. At this stage, the current I is drivenDThe expression of (a) is as follows:
The low gray scale display t2 includes an initialization phase t21, a data writing phase t22 and a light emitting phase t 23.
In the initialization stage t21, the first Scan signal Scan1 is at a high level, the second Scan signal Scan is at a low level, the third Scan signal Scan3 is at a low level, and the emission control signal EM is at a low level. The second transistor T2 and the third transistor T3 are both in an off state under the control of the second Scan signal Scan2, the seventh transistor T7 is in an off state under the control of the third Scan signal Scan3, the fourth transistor T4 is turned on under the control of the first Scan signal Scan1, and the reference voltage Vref is written to the gate of the first transistor T1 (i.e., the gate of the driving transistor) to initialize the gate of the first transistor T1, so as to ensure that the display result of the previous frame does not affect the display of the current frame.
In the data writing phase t22, the first Scan signal Scan1 is at a low level, the second Scan signal Scan is at a high level, the third Scan signal Scan3 is at a high level, and the emission control signal EM is at a low level. The fourth transistor T4 is turned off under the control of the first Scan signal Scan1, the second transistor T2 and the third transistor T3 are turned on under the control of the second Scan signal Scan2, the data voltage Vdata is written into the gate of the first transistor T1, and due to the compensation effect of the third transistor T3, the potential of the gate of the first transistor T1 is Vdata + Vth, where Vdata is data2 and data1, and the transmission duration of the data2 is less than that of the data 1. Meanwhile, the seventh transistor T7 is turned on under the control of the third Scan signal Scan3, and writes the reference voltage Vref to the anode of the light emitting diode D, thereby initializing the anode potential of the light emitting diode D. Illustratively, as shown in fig. 5, in the low gray scale display, the data voltage Vdata transmitted to the pixel circuit PX is data2 for different gray scales, such as the first low gray scale display I and the second low gray scale display II, but the data voltage Vdata is transmitted for different time periods to ensure that different gray scales have different luminance displays.
In the light emitting period t23, the first Scan signal Scan1 is at a low level,the second Scan signal Scan is at a low level, the third Scan signal Scan3 is at a low level, and the emission control signal EM is at a high level. The fourth transistor T4 is turned off under the control of the first Scan signal Scan1, the second transistor T2 and the third transistor T3 are turned off under the control of the second Scan signal Scan2, the fifth transistor T5 and the sixth transistor T6 are turned on under the control of the emission control signal EM, the voltage ELVDD on the first power line is written into the first pole of the first transistor T1 through the fifth transistor T5, and the first transistor T1 generates the driving current I since the voltage stored on the storage capacitor Cst is data2+ VthDAnd driving the light emitting diode D to emit light. Since the voltage at the gate of the first transistor T1 is the same in the low gray level display and the high gray level display, the driving current I is set at this stageDIt can still be represented by the following expression:
in summary, in the technical solution provided by the embodiment of the present invention, the data lines are configured to be at least displayed in the low gray scale, the data voltages with the same size are transmitted to the pixel circuit according to different gray scales, and the transmission durations of the data voltages are different, so as to realize different gray scale display. When the high gray scale is displayed, the data voltages with different sizes are transmitted to the pixel circuit according to different gray scales, the time length for transmitting the data voltages is the same, or the data voltages with the same size are transmitted, the time length for transmitting the data voltages is different, and different gray scale display under the high gray scale is realized. When the low gray scale is displayed, the same data voltage (the same as the data voltage under the high gray scale display) is transmitted to the pixel circuit aiming at different gray scales, and the different gray scale displays under the low gray scale are realized due to different time lengths of the data voltage transmission. Compared with the prior art, the technical scheme provided by the embodiment of the invention is favorable for realizing the threshold compensation effect during low gray scale display, thereby being favorable for improving the bad phenomena of display unevenness and the like under low gray scale and ensuring the display effect of the display panel during low gray scale.
As a preferred implementation of the embodiment of the present invention, in the high gray scale display, the data line DLj is configured to transmit the data voltage Vdata of the same magnitude to the pixel circuit PX for different gray scales, and the time duration for transmitting the data voltage Vdata is different; in the low gray scale display, the data line DLj is configured to transmit the data voltage Vdata of the same magnitude to the pixel circuit PX for different gray scales, and the time period for transmitting the data voltage Vdata is different. That is, in the high gray scale display and the low gray scale display, the data voltage transmitted to the pixel circuit PX has the same magnitude, and the duration of transmitting the data voltage is adjusted according to the specific gray scale, thereby realizing different luminance displays. For a detailed description, please refer to the above description of the low gray scale display, which is not repeated herein.
Of course, in other embodiments, in the high gray scale display, the data line DLj is configured to transmit the data voltage Vdata of different sizes to the pixel circuit PX for different gray scales, and the time duration for transmitting the data voltage Vdata is the same. Fig. 6 is a schematic diagram of a driving timing sequence of another pixel circuit according to an embodiment of the present invention, and referring to fig. 4 and 6, a frame display of the display panel includes a high gray scale display t1 and a low gray scale display t2, and the low gray scale display t2 is the same as the driving process of the above embodiment, and is not repeated herein.
In the high gray scale display t1, during the initialization period t11, the first Scan signal Scan1 is at a high level, the second Scan signal Scan is at a low level, the third Scan signal Scan3 is at a low level, and the emission control signal EM is at a low level. The second transistor T2 and the third transistor T3 are both in an off state under the control of the second Scan signal Scan2, the seventh transistor T7 is in an off state under the control of the third Scan signal Scan3, the fourth transistor T4 is turned on under the control of the first Scan signal Scan1, and the reference voltage Vref is written to the gate of the first transistor T1 (i.e., the gate of the driving transistor) to initialize the gate of the first transistor T1, so as to ensure that the display result of the previous frame does not affect the display of the current frame.
In the data writing phase t12, the first Scan signal Scan1 is at a low level, the second Scan signal Scan is at a high level, the third Scan signal Scan3 is at a high level, and the emission control signal EM is at a low level. The fourth transistor T4 is turned off under the control of the first Scan signal Scan1, the second transistor T2 and the third transistor T3 are turned on under the control of the second Scan signal Scan2, the data voltage Vdata is written into the gate of the first transistor T1, and the potential of the gate of the first transistor T1 is Vdata + Vth due to the compensation effect of the third transistor T3, wherein Vdata is data 1. Meanwhile, the seventh transistor T7 is turned on under the control of the third Scan signal Scan3, and writes the reference voltage Vref to the anode of the light emitting diode D, thereby initializing the potential of the light emitting diode D. At this stage, the data line DLj is configured to transmit the data voltage Vdata of different sizes to the pixel circuit PX for different gray scales, and the time periods for transmitting the data voltage Vdata are the same. Exemplarily, the high gray scale display is divided into a first high gray scale display III and a second high gray scale display IV, the first high gray scale display III may be a 255 gray scale, the second high gray scale display IV may be a 190 gray scale, the first high gray scale display III and the second high gray scale display IV transmit the data voltage Vdata to the pixel circuit PX for the same time period, but the data voltage Vdata has different magnitudes, data1 > data 1', thereby realizing that different driving currents are obtained according to different data voltages Vdata under the high gray scale, and further realizing different gray scale display.
In the light emission period t13, the first Scan signal Scan1 is at a low level, the second Scan signal Scan is at a low level, the third Scan signal Scan3 is at a low level, and the light emission control signal EM is at a high level. The fourth transistor T4 is turned off under the control of the first Scan signal Scan1, the second transistor T2 and the third transistor T3 are turned off under the control of the second Scan signal Scan2, the fifth transistor T5 and the sixth transistor T6 are turned on under the control of the emission control signal EM, the voltage ELVDD on the first power line is written into the first pole of the first transistor T1 through the fifth transistor T5, and the first transistor T1 generates the driving current ID to drive the light emitting diode D to emit light since the voltage stored on the storage capacitor Cst is data1+ Vth.
Fig. 7 is a schematic diagram of a driving timing sequence of another pixel circuit according to an embodiment of the invention. Referring to fig. 4-7, the first transistor T1 is a driving transistor, the light emitting diode D is the light emitting module 308, and the first transistor T1 is used for generating a driving current according to the data voltage Vdata to drive the light emitting diode D to emit light. At the first display gray scale, the data line DLj is configured to transmit the first data voltage data1 to the pixel circuit PX for a first time period ta, and at the second display gray scale, the data line DLj is configured to transmit the second data voltage data2 to the pixel circuit PX for a second time period tb, the first data voltage data1 and the second data voltage data2 having the same magnitude; the first display gray scale is larger than the second display gray scale, and the duration of the first time period ta is larger than the duration of the second time period tb.
In this embodiment, the first display gray scale and the second display gray scale may be a high gray scale and a low gray scale, and may be both the high gray scale and the low gray scale. In the present embodiment, only the first display gray scale is a high gray scale, and the second display gray scale is a low gray scale, which are similar to the driving process of the present embodiment.
The high gray scale display and the low gray scale display both include an initialization phase, a data writing phase and a light emitting phase, wherein the initialization phase and the light emitting phase are described in detail in the above embodiments and are not described herein again.
The high gray scale and the low gray scale can be defined by gray scale values, for example, when the gray scale values are greater than a preset gray scale, the display panel is considered to be in high gray scale display; when the gray scale value is less than or equal to the predetermined gray scale, the display panel is considered to be in the low gray scale display mode, and in the present embodiment, the first transistor T1 only needs to be operated in the saturation region when the low gray scale display mode is ensured. In this embodiment, the gray scale of the low gray scale display may be 0-32 gray scale, and the gray scale greater than 32 gray scale may be high gray scale. In the data writing stage, when the display panel is in the high gray level display, the voltage of the gate of the first transistor T1 is larger, i.e. the gate-source voltage V of the first transistor T1GSThe first transistor T1 is operated in a saturation region, where the data voltage Vdata transmitted to the pixel circuit PX is data1 and the duration of the data voltage Vdata is ta, when the display panel is in a low gray scale display, the data voltage Vdata transmitted to the pixel circuit PX is data2, and since the data1 is data2, the first transistor T1 is also operated in the saturation region in the low gray scale display, so that the threshold voltage compensation scheme in the high gray scale display is also applicable to the low gray scale display, thereby eliminating the threshold voltage in the low gray scale displayThe influence of the value voltage on the driving current causes the problem of non-uniform display. However, since the high gray scale and the low gray scale have different brightness, in order to ensure that both the high gray scale and the low gray scale can be normally displayed, the duration of the data voltage Vdata transmitted during the low gray scale display is correspondingly reduced, that is, the on-time of the first transistor M1 is reduced, and when the data voltage Vdata is written into the gate of the first transistor T1 by using the high voltage, the writing duration of the data voltage Vdata is determined according to the relationship between the gray scale-brightness-voltage, so as to realize the normal display of the low gray scale. For example, in a normal case, during low gray scale display, the data voltage Vdata corresponding to the display luminance is written into the gate of the first transistor T1 for a fixed charging time, and the first transistor T1 generates a corresponding driving current to drive the light emitting diode D to emit light with a set luminance. If the voltage value of the data voltage Vdata written into the gate of the first transistor T1 is increased, since it takes a certain time to write the data voltage Vdata, more data voltage Vdata is written into the gate of the first transistor T1 within the same charging time, that is, the driving current generated by the first transistor T1 is increased, and the light-emitting brightness of the corresponding light-emitting diode D is also changed and is no longer the set brightness. Therefore, in order to ensure that the led D still emits light with the set brightness, the writing time of the data voltage Vdata (i.e. the charging time to the gate of the first transistor T1) needs to be reduced to ensure that the driving current generated by the gate of the first transistor T1 in the set time is just the driving current corresponding to the required set brightness, so as to ensure the normal display of the low gray scale display under the higher data voltage.
According to the technical scheme provided by the embodiment, the amplitude of the data voltage written into the grid electrode of the first transistor under the low-gray-scale display is adjusted, so that the first transistor is ensured to be in a saturation region, and further, the threshold voltage compensation under the low-gray-scale display can be realized, so that the display unevenness is improved. The gray scale brightness under different gray scales is controlled by adjusting the writing time of the data voltage so as to ensure that the different gray scales can be normally displayed.
With continued reference to fig. 4 and 7, the turn-on time of the second transistor T2 is greater than or equal to the transmission duration of the data voltage Vdata. In the low gray scale display, since the writing time of the data voltage data2 is shorter than that of the data voltage data1 in the high gray scale display, but the turn-on time of the second transistor T2 is not reduced correspondingly, it can be ensured that the data voltage data2 can be written into the gate of the first transistor T1 sufficiently in the low gray scale display.
The embodiment of the invention also provides a driving method of the display panel, and the driving method is suitable for the display panel provided by any embodiment of the invention. The driving method of the display panel comprises the following steps:
at least in the low gray scale display, the same data voltage is transmitted to the pixel circuit through the data line for different gray scales, and the time length of transmitting the data voltage is different.
The driving method of the display panel specifically comprises the following steps: transmitting a first data voltage to the data line at a first display gray scale for a first period of time, and transmitting a second data voltage to the pixel circuit at a second display gray scale for a second period of time; the first data voltage and the second data voltage have the same magnitude, the first display gray scale is larger than the second display gray scale, and the duration of the first time period is larger than the duration of the second time period.
With reference to fig. 4-7, in the present embodiment, the first display gray scale and the second display gray scale may be a high gray scale and a low gray scale, and may also be both high gray scales or both low gray scales. In the present embodiment, only the first display gray scale is a high gray scale, and the second display gray scale is a low gray scale, which are similar to the driving process of the present embodiment.
The high gray scale display and the low gray scale display both include an initialization phase, a data writing phase and a light emitting phase, wherein the initialization phase and the light emitting phase are described in detail in the above embodiments and are not described herein again.
In this embodiment, the gray scale of the low gray scale display may be 0-32 gray scale, and the gray scale greater than 32 gray scale may be high gray scale. In the data writing stage, when the display panel is in a high gray scale display, because the voltage of the gate of the first transistor T1 is large, that is, the gate-source voltage VGS of the first transistor T1 is large, the first transistor T1 operates in a saturation region, at this time, the data voltage Vdata transmitted to the pixel circuit PX is data1, and the duration of the data voltage Vdata transmitted is ta, when the display panel is in a low gray scale display, the data voltage Vdata transmitted to the pixel circuit PX is data2, and because the data1 is data2, at the time of the low gray scale display, the first transistor T1 also operates in the saturation region, so that the threshold voltage compensation scheme under the high gray scale display is also applicable to the low gray scale display, thereby eliminating the influence of the threshold voltage on the driving current at the time of the low gray scale display, which causes the problem of display non-uniformity. However, since the high gray scale and the low gray scale have different brightness, in order to ensure that both the high gray scale and the low gray scale can be normally displayed, the duration of the data voltage Vdata transmitted during the low gray scale display is correspondingly reduced, that is, the on-time of the first transistor M1 is reduced, and when the data voltage Vdata is written into the gate of the first transistor T1 by using the high voltage, the writing duration of the data voltage Vdata is determined according to the relationship between the gray scale-brightness-voltage, so as to realize the normal display of the low gray scale. For example, in a normal case, during low gray scale display, the data voltage Vdata corresponding to the display luminance is written into the gate of the first transistor T1 for a fixed charging time, and the first transistor T1 generates a corresponding driving current to drive the light emitting diode D to emit light with a set luminance. If the voltage value of the data voltage Vdata written into the gate of the first transistor T1 is increased, since it takes a certain time to write the data voltage Vdata, more data voltage Vdata is written into the gate of the first transistor T1 within the same charging time, that is, the driving current generated by the first transistor T1 is increased, and the light-emitting brightness of the corresponding light-emitting diode D is also changed and is no longer the set brightness. Therefore, in order to ensure that the led D still emits light with the set brightness, the writing time of the data voltage Vdata (i.e. the charging time to the gate of the first transistor T1) needs to be reduced to ensure that the driving current generated by the gate of the first transistor T1 in the set time is just the driving current corresponding to the required set brightness, so as to ensure the normal display of the low gray scale display under the higher data voltage.
Fig. 8 is a schematic structural diagram of a display device according to an embodiment of the present invention, and referring to fig. 8, the display device 100 includes a display panel according to any embodiment of the present invention, and the display device 100 further includes a driving chip (not shown) connected to the data lines DL1-DLj for transmitting data voltages to the data lines DL 1-DLj. Since the display device provided in the embodiment of the present invention includes the display panel provided in any embodiment of the present invention, the display device also has the beneficial effects described in any embodiment of the present invention, and details are not described herein again.
It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.
Claims (10)
1. A display panel, comprising: the pixel circuit and the data line connected with the pixel circuit;
the frame display of the display panel includes a high gray scale display and a low gray scale display, the data lines are configured to transmit data voltages of the same magnitude to the pixel circuits for different gray scales at least at the low gray scale display, and the time periods for transmitting the data voltages are different.
2. The display panel according to claim 1, wherein in the high gray scale display, the data lines are configured to transmit data voltages of different magnitudes to the pixel circuits for different gray scales, and wherein the data voltages are transmitted for the same period of time.
3. The display panel of claim 1, wherein the low gray level display gray levels comprise gray levels from 0 to 32.
4. The display panel according to claim 1, wherein the data line is configured to transmit a first data voltage to the pixel circuit for a first period of time at a first display gray scale, and configured to transmit a second data voltage to the pixel circuit for a second period of time at a second display gray scale, the first data voltage and the second data voltage having the same magnitude; the first display gray scale is larger than the second display gray scale, and the duration of the first time period is larger than the duration of the second time period.
5. The display panel according to claim 1, wherein the pixel circuit includes a driving transistor and a light emitting module;
the driving transistor is used for generating driving current according to the data voltage to drive the light emitting module to emit light; in the low gray scale display, the driving transistor operates in a saturation region.
6. The display panel according to claim 1, wherein the pixel circuit comprises: the transistor comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, a storage capacitor and a light emitting diode;
a gate of the second transistor is connected to a second scan signal line, a first pole of the second transistor is connected to the data line, a second pole of the second transistor is connected to a first pole of the first transistor, a second pole of the first transistor is connected to a first pole of the third transistor, and a second pole of the third transistor is connected to a gate of the first transistor;
a gate of the fourth transistor is connected to a first scanning signal line, a gate of the seventh transistor is connected to a third scanning signal line, a first pole of the fourth transistor and a first pole of the seventh transistor are both inputted with a reference voltage, and a second pole of the fourth transistor is connected to a gate of the first transistor;
a gate of the fifth transistor and a gate of the sixth transistor are both connected to a light emission control signal line, a first pole of the fifth transistor is connected to a first power line, a second pole of the fifth transistor is connected to the first pole of the first transistor, a first pole of the sixth transistor is connected to the second pole of the first transistor, a second pole of the sixth transistor is connected to an anode of the light emitting diode, a cathode of the light emitting diode is connected to a second power line, and a second pole of the seventh transistor is connected to the anode of the light emitting diode;
the storage capacitor is connected between the first power supply line and the gate of the first transistor.
7. The display panel according to claim 6, wherein an on time of the second transistor is greater than or equal to a transmission period of the data voltage.
8. The driving method of a display panel, characterized by, the said panel includes the pixel circuit and connects to the data link of the said pixel circuit, the frame display of the said display panel includes high gray-scale display and low gray-scale display;
the driving method of the display panel includes:
at least in the low gray scale display, the same data voltage is transmitted to the pixel circuit through the data line for different gray scales, and the time length of transmitting the data voltage is different.
9. The method for driving a display panel according to claim 8, wherein at least in a low gray scale display, data voltages of the same magnitude are transmitted to the pixel circuits through the data lines for different gray scales and the periods of time for transmitting the data voltages are different, comprising:
transmitting a first data voltage to the data line for a first period of time at a first display gray scale, and transmitting a second data voltage to the pixel circuit for a second period of time at a second display gray scale; the first data voltage and the second data voltage have the same magnitude, the first display gray scale is larger than the second display gray scale, and the duration of the first time period is larger than the duration of the second time period.
10. A display device characterized by comprising the display panel according to any one of claims 1 to 7; the display device further comprises a driving chip, wherein the driving chip is connected with the data line and used for transmitting data voltage to the data line.
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