CN113593481A - Display panel and driving method thereof - Google Patents
Display panel and driving method thereof Download PDFInfo
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- CN113593481A CN113593481A CN202110867839.5A CN202110867839A CN113593481A CN 113593481 A CN113593481 A CN 113593481A CN 202110867839 A CN202110867839 A CN 202110867839A CN 113593481 A CN113593481 A CN 113593481A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
- G09G3/3258—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the voltage across the light-emitting element
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/02—Improving the quality of display appearance
- G09G2320/0233—Improving the luminance or brightness uniformity across the screen
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- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
The embodiment of the invention discloses a display panel and a driving method thereof, wherein the display panel comprises a pixel circuit and a driving signal wire connected with the pixel circuit; in a first refresh frequency phase, the driving signal line is configured to transmit a first driving signal to the pixel circuit when displaying a target display gray scale; in the second refreshing frequency stage, the driving signal line is configured to transmit a second driving signal to the pixel circuit when the target display gray scale is displayed, so that the brightness of the display panel is consistent when the same display gray scale is displayed in different refreshing frequency stages; the first driving signal is different from the second driving signal, and the first refresh frequency is less than the second refresh frequency. The technical scheme provided by the embodiment of the invention can ensure that the brightness of the display panel is consistent when the same display gray scale is displayed at different refreshing frequency stages, thereby being beneficial to improving the display effect when the display panel shares the same set of gamma debugging data at different refreshing frequencies.
Description
Technical Field
The embodiment of the invention relates to the technical field of display, in particular to a display panel and a driving method thereof.
Background
Organic Light-Emitting diodes (OLEDs) have the advantages of low power consumption, self-Light emission, low cost, fast response speed, and the like, and are widely used in display panels.
At present, when a display panel is displayed in different application scenes, different refresh frequencies are adopted for displaying, but the display panel in the prior art has brightness difference under different refresh frequencies, which affects the display effect.
Disclosure of Invention
The embodiment of the invention provides a display panel and a driving method thereof, which are used for improving the brightness difference of the display panel under different refreshing frequencies and improving the display effect.
In a first aspect, an embodiment of the present invention provides a display panel, including a pixel circuit and a driving signal line connected to the pixel circuit;
in a first refresh frequency phase, the driving signal line is configured to transmit a first driving signal to the pixel circuit when a target display gray scale is displayed;
in a second refresh frequency stage, the driving signal line is configured to transmit a second driving signal to the pixel circuit when the target display gray scale is displayed, so that the brightness of the display panel is consistent when the same display gray scale is displayed in different refresh frequency stages; wherein the first drive signal is different from the second drive signal, and the first refresh frequency is less than the second refresh frequency.
Optionally, the pixel circuit includes a driving transistor, a storage capacitor, a first switching transistor, and a second switching transistor, and the driving signal line includes a first scanning signal line and a second scanning signal line;
a gate of the first switching transistor is connected to the first scan signal line, a first pole of the first switching transistor is connected to the gate of the driving transistor, and a second pole of the first switching transistor is connected to the second pole of the driving transistor; the grid electrode of the second switching transistor is connected with the second scanning signal line, the first pole of the second switching transistor is connected with the grid electrode of the driving transistor, and the second pole of the second switching transistor is connected with an initialization voltage; the storage capacitor is connected between the grid electrode of the driving transistor and a first power line, and the driving transistor is connected between the first power line and a second power line;
the first drive signal and the second drive signal each include an off voltage for turning off the first switching transistor and the second switching transistor; the turn-off voltage corresponding to the first driving signal is greater than the turn-off voltage corresponding to the second driving signal.
Optionally, the turn-off voltage corresponding to the first driving signal and the turn-off voltage corresponding to the second driving signal satisfy:
VGf1＝(A*VGf2+BVth)*VD，
wherein, VGf1For the turn-off voltage, V, corresponding to the first drive signalGf2The second driving signal is the corresponding turn-off voltage, Vth is the threshold voltage of the first switch transistor or the second switch transistor, VDA and B are constants for the voltage corresponding to the first pole of the first switch transistor or the second switch transistor connected to the gate of the drive transistor.
Optionally, the pixel circuit includes a driving transistor, a storage capacitor, a first switching transistor, and a second switching transistor, the driving signal line includes a reset signal line, and the display panel further includes a first scanning signal line and a second scanning signal line;
a gate of the first switching transistor is connected to the first scan signal line, a first pole of the first switching transistor is connected to the gate of the driving transistor, and a second pole of the first switching transistor is connected to the second pole of the driving transistor; a gate of the second switching transistor is connected to the second scanning signal line, a first pole of the second switching transistor is connected to the gate of the driving transistor, and a second pole of the second switching transistor is connected to the reset signal line; the storage capacitor is connected between the grid electrode of the driving transistor and a first power line, and the driving transistor is connected between the first power line and a second power line;
in the first refresh frequency phase and the second refresh frequency phase, the reset signal line is configured to jump an initialization voltage transmitted to the second switching transistor from a low level to a high level in a non-active area between two adjacent display frames, and jump the initialization voltage from a high level to a low level in an active area.
Alternatively, the initialization voltage transmitted to the reset signal line in the non-active area between two adjacent display frames is a positive voltage.
Optionally, the pixel circuit includes a driving transistor, a storage capacitor, and a third switching transistor, and the driving signal line includes a third scanning signal line; the display panel further comprises a data line;
a gate of the third switching transistor is connected to the third scanning signal line, a first electrode of the third switching transistor is connected to the data line, and a second electrode of the third switching transistor is connected to the first electrode of the driving transistor; the storage capacitor is connected between the grid electrode of the driving transistor and a first power line, the first pole of the driving transistor is connected with the first power line, and the second pole of the driving transistor is connected with a second power line;
the first driving signal and the second driving signal transmitted on the third scanning signal line each include a turn-on voltage for turning on the third switching transistor;
when the target display gray scale is a high gray scale, in a display frame, the duration of the starting voltage corresponding to the first driving signal is less than the duration of the starting voltage corresponding to the second driving signal.
Optionally, when the target display gray scale is a low gray scale, in a display frame, a duration of the turn-on voltage corresponding to the first driving signal is greater than a duration of the turn-on voltage corresponding to the second driving signal.
Optionally, the pixel circuit includes a driving transistor, a storage capacitor, a first switching transistor, and a second switching transistor, the driving signal line includes a reset signal line, and the display panel further includes a first scanning signal line and a second scanning signal line;
a gate of the first switching transistor is connected to the first scan signal line, a first pole of the first switching transistor is connected to the gate of the driving transistor, and a second pole of the first switching transistor is connected to the second pole of the driving transistor; a gate of the second switching transistor is connected to the second scanning signal line, a first pole of the second switching transistor is connected to the gate of the driving transistor, and a second pole of the second switching transistor is connected to the reset signal line; the storage capacitor is connected between the grid electrode of the driving transistor and a first power line, the first pole of the driving transistor is connected with the first power line, and the second pole of the driving transistor is connected with a second power line;
when the target display gray scale is a high gray scale, the initialization voltage corresponding to the first driving signal is smaller than the initialization voltage corresponding to the second driving signal.
Optionally, when the target display gray scale is a low gray scale, the initialization voltage corresponding to the first driving signal is greater than the initialization voltage corresponding to the second driving signal.
In a second aspect, an embodiment of the present invention further provides a driving method of a display panel, where the display panel includes a pixel circuit and a driving signal line connected to the pixel circuit;
the driving method of the display panel includes:
in a first refreshing frequency stage, when a target display gray scale is displayed, transmitting a first driving signal to the pixel circuit through the driving signal line;
in a second refreshing frequency stage, when the target display gray scale is displayed, a second driving signal is transmitted to the pixel circuit through the driving signal line, so that the brightness of the display panel is consistent when the same display gray scale is displayed in different refreshing frequency stages;
wherein the first drive signal is different from the second drive signal, and the first refresh frequency is less than the second refresh frequency.
According to the technical scheme provided by the embodiment of the invention, in a first refreshing frequency stage, a driving signal line is configured to transmit a first driving signal to a pixel circuit when a target display gray scale is displayed; in the second refresh frequency stage, the driving signal line is configured to transmit a second driving signal to the pixel circuit when the target display gray scale is displayed, so that the brightness of the display panel is consistent when the same display gray scale is displayed in different refresh frequency stages. When the display panel displays at different refreshing frequencies, different signals are applied to the pixel circuit to change the luminance of the pixel when the target display gray scale is displayed due to different driving signals transmitted to the pixel circuit, so that the luminance of the display panel is consistent when the same display gray scale is displayed at different refreshing frequency stages, and the display effect of the display panel sharing the same set of gamma debugging data at different refreshing frequencies is improved.
Drawings
Fig. 1 is a schematic structural diagram of a display panel according to an embodiment of the present invention;
FIG. 2 is a waveform diagram of a driving signal according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of a pixel circuit according to an embodiment of the present invention;
FIG. 4 is a timing control waveform diagram of a pixel circuit according to an embodiment of the present invention;
fig. 5 is a waveform diagram of an initialization voltage corresponding to a reset signal line according to an embodiment of the present invention;
fig. 6 is a schematic structural diagram of another pixel circuit according to an embodiment of the present invention;
FIG. 7 is a timing control waveform diagram of another pixel circuit according to an embodiment of the present invention;
FIG. 8 is a timing control waveform diagram of another pixel circuit according to an embodiment of the present invention;
fig. 9 is a driving method of a display panel according to an embodiment of the invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.
As described in the background art, the display panel in the prior art has brightness difference at different refresh frequencies, which affects the display effect of the display panel. The inventor finds that the above problem occurs because when the display panel performs display at different refresh rates, the leakage time between two adjacent frames during the display at a lower refresh rate is longer than the leakage time between two adjacent frames during the display at a higher refresh rate, thereby causing brightness difference of the display panel. In the prior art, different gamma debugging is usually adopted for different refresh frequencies, so as to reduce the brightness difference of the display panel under different refresh frequencies. That is, the display brightness of the display panel is adjusted by setting different gamma voltages according to the refresh frequency. But adopt different gamma debugging schemes that the different refresh frequency corresponds to for the gamma debugging time that corresponds increases, is unfavorable for improving and produces line efficiency.
The different refresh frequencies share the same set of gamma debug data, which can save the debug time, but the display effect of the display panel at the corresponding refresh frequency meets the requirement due to the different corresponding leakage or charging durations of the display panel at the different refresh frequencies, and when the display panel is switched to other frequencies, the display brightness difference occurs. In view of the foregoing problems, embodiments of the present invention provide a display panel to improve the brightness difference of the display panel at different refresh frequencies, and improve the display effect. In this embodiment, the display panel shares the same set of gamma debug data at different refresh frequencies. Fig. 1 is a schematic structural diagram of a display panel according to an embodiment of the present invention, fig. 2 is a waveform diagram of a driving signal according to an embodiment of the present invention, and referring to fig. 1 and fig. 2, the display panel according to an embodiment of the present invention includes a pixel circuit PX and a driving signal line connected to the pixel circuit PX.
In the first refresh frequency phase P1, the driving signal line is configured to transmit the first driving signal DR1 to the pixel circuit PX at the time of displaying the target display gray scale.
At the second refresh frequency stage P2, the driving signal line is configured to transmit the second driving signal DR2 to the pixel circuit PX when the target display gray scale is displayed, so that the display panel has the same brightness when the same display gray scale is displayed at different refresh frequency stages; the first driving signal DR1 is different from the second driving signal DR2, and the first refresh frequency is less than the second refresh frequency.
Specifically, the driving signal line may include a scanning signal line (GL1 … … GLk) connected to the gate driver 110 for supplying the gate driving signal to the pixel circuit PX; a reset signal line (RE1 … … REj) connected to the driving chip 120 may be further included to supply an initialization voltage to the pixel circuit PX. The target display gray scale comprises high gray scale display and low gray scale display, and under the normal condition, the high gray scale display has higher brightness and larger corresponding drive current; the brightness of low gray scale display is lower, and the corresponding driving current is smaller. The driving current is a current output to the light emitting diode. The target display gray scale can be any gray scale that can be displayed by the display panel, for example, the range of the gray scale that can be displayed by the display panel is 0-255, the target display gray scale can be any gray scale of 0-255, the low display gray scale can be 0-32 gray scale, and the high display gray scale can be 33-255 gray scale. In this embodiment, the first refresh frequency and the second refresh frequency may be any refresh frequency that the display panel can support, and the first refresh frequency and the second refresh frequency are two different frequencies, for example, the first refresh frequency is 60Hz, and the second refresh frequency may be 90 Hz.
The driving signals are signals output by corresponding driving signal lines, and different driving signals are configured according to the refreshing frequency of the display panel, so that the driving currents output by the pixel circuits under the same display gray scale are the same, and the brightness of the display panel is consistent when the same display gray scale is displayed at different refreshing frequency stages. Since the first refresh frequency is less than the second refresh frequency, the leakage time of the pixel circuit PX in the first refresh frequency phase P1 is longer than that in the first refresh frequency phase P2, and therefore, for different leakage time (i.e. corresponding refresh frequency), the driving signal lines are configured to transmit different driving signals to the pixel circuit PX when displaying the same display gray scale, so that when the pixel circuit PX displays the target display gray scale, the driving currents (voltages) output by the pixel circuit PX after the leakage are the same, and thus the display luminance of the display panel is uniform. For example, in the first refresh frequency phase P1, the driving signal line is configured to transmit the first driving signal DR1 to the pixel circuit PX; in the second refresh frequency phase P2, the driving signal line is configured to transmit the second driving signal DR2 to the pixel circuit PX. The first driving signal DR1 and the second driving signal DR2 are different, and specifically, the driving voltages of the first driving signal DR1 and the second driving signal DR2 may be different, or the on-time periods of the first driving signal DR1 and the second driving signal DR2 may be different.
The display panel provided by the embodiment of the invention comprises a pixel circuit and a driving signal line connected with the pixel circuit, wherein in a first refreshing frequency stage, the driving signal line is configured to transmit a first driving signal to the pixel circuit when a target display gray scale is displayed; in the second refresh frequency stage, the driving signal line is configured to transmit a second driving signal to the pixel circuit when the target display gray scale is displayed, so that the brightness of the display panel is consistent when the same display gray scale is displayed in different refresh frequency stages. When the display panel displays at different refreshing frequencies, different signals are applied to the pixel circuit to change the luminance of the pixel when the target display gray scale is displayed due to different driving signals transmitted to the pixel circuit, so that the luminance of the display panel is consistent when the same display gray scale is displayed at different refreshing frequency stages, and the display effect of the display panel sharing the same set of gamma debugging data at different refreshing frequencies is improved.
Fig. 3 is a schematic structural diagram of a pixel circuit according to an embodiment of the present invention, referring to fig. 3, the pixel circuit includes a driving transistor Tdrv, a storage capacitor Cst, a first switching transistor T1, and a second switching transistor T2, and a driving signal line includes a first scanning signal line and a second scanning signal line.
A gate of the first switching transistor T1 is connected to the first scan signal line, a first pole of the first switching transistor T1 is connected to the gate of the driving transistor Tdrv, and a second pole of the first switching transistor T1 is connected to the second pole of the driving transistor Tdrv; a gate of the second switching transistor T2 is connected to the second scan signal line, a first pole of the second switching transistor T2 is connected to the gate of the driving transistor Tdrv, and a second pole of the second switching transistor T2 is connected to the initialization voltage Vref; the storage capacitor Cst is connected between the gate electrode of the driving transistor Tdrv and the first power line ELVDD, and the driving transistor Tdrv is connected between the first power line ELVDD and the second power line ELVSS.
The first and second driving signals DR1 and DR2 each include and turn-off voltages for turning off the first and second switching transistors T1 and T2; the turn-off voltage corresponding to the first driving signal DR1 is greater than the turn-off voltage corresponding to the second driving signal DR 2.
Specifically, in the present embodiment, the driving signal line corresponds to the scanning signal line, and thus the driving signal corresponds to the first scanning signal Scan1 output from the first scanning signal line and the second scanning signal Scan2 output from the second scanning signal line. The pixel circuit further includes a data writing module 101 for writing a data voltage to the driving transistor Tdrv, a second initialization module 104 for initializing an anode of the light emitting diode D (where the second switching transistor T2 is used as a first initialization module for initializing a gate of the driving transistor Tdrv), and a first light emission control module 102 and a second light emission control module 103 for controlling the light emitting diode D to emit light, and the first switching transistor T1 is used for implementing a threshold compensation function of the driving transistor Tdrv. The first switch transistor T1 and the second switch transistor T2 are both P-type double gate transistors.
Fig. 4 is a timing control waveform diagram of a pixel circuit according to an embodiment of the present invention, and with reference to fig. 3 and 4, the pixel circuit PX at least includes an initialization stage, a data writing stage, and a light emitting stage.
In the initialization stage, the second Scan signal line is configured to output the second Scan signal Scan2 of a low level to the second switching transistor T2, the second switching transistor T2 is turned on, and the potential of the gate of the second switching transistor T2 is initialized by writing the initialization voltage Vref to the gate of the first switching transistor T1. Of course, in other embodiments, the anode of the light emitting diode D is also initialized by the second initialization module 104 in the initialization stage.
In the data writing phase, the first switching transistor T1 and the data writing module 101 are turned on by the first Scan signal Scan1, the data voltage Vdata is written into the gate of the driving transistor Tdrv through the data writing module 101 and the first switching transistor T1 and the end of the storage capacitor Cst connected to the gate of the driving transistor Tdrv, and the storage capacitor Cst maintains the potential of the gate of the driving transistor Tdrv at Vdata + Vth, where Vth is the threshold voltage of the driving transistor Tdrv.
In the light emitting phase, the light emission control signal EM controls the first and second light emission control modules 102 and 103 to be turned on, the voltage on the first power line ELVDD is transmitted to the anode of the light emitting diode D, the voltage on the second power line ELVSS is input to the cathode of the light emitting diode D, and the driving transistor Tdrv generates the driving current to drive the light emitting diode D to emit light because the storage capacitor Cst maintains the potential of the gate of the driving transistor Tdrv at Vdata + Vth.
When the first refresh frequency phase P1 and the second refresh frequency phase P2 share one set of gamma debug, the adopted gamma debug data are the same, and therefore, the data voltage Vdata written into the gate of the driving transistor Tdrv is the same when displaying the same gray scale. During the light emitting process, the first switching transistor T1 and the second switching transistor T2 are in an off state, and the storage capacitor Cst generates leakage current through the first switching transistor T1 and the second switching transistor T2, so that the gate potential of the driving transistor Tdrv changes. Since the leakage time lengths of the first refresh frequency phase P1 and the second refresh frequency phase P2 are different, the potentials of the gates of the driving transistors Tdrv are also different under the condition that the leakage currents are the same, so that the driving currents generated by the driving transistors Tdrv are different, and the light emitting brightness is different.
It is easily understood that the leakage time period between two adjacent frames when the display is performed at the lower refresh frequency is higher than that when the display is performed at the higher refresh frequency, and therefore, the leakage time period of the first refresh frequency phase P1 is greater than that of the second refresh frequency phase P2.
With continued reference to fig. 4, the first driving signal includes a first Scan signal Scan1 and a second Scan signal Scan2, and the second driving signal also includes a first Scan signal Scan1 and a second Scan signal Scan 2. The first Scan driving signal Scan1 includes on voltages (V5 and V7) for turning on the first switching transistor T1, and off voltages (V6 and V8) for turning off the first switching transistor T1; the second Scan driving signal Scan2 includes turn-on voltages (V1 and V3) for turning on the second switching transistor T2, and turn-off voltages (V2 and V4) for turning off the second switching transistor T2. According to the current-voltage characteristic curve of the switching transistor, when the voltages at the two ends of the drain and the source of the switching transistor are constant, different gate voltages correspond to different currents, so that different turn-off voltages correspond to different leakage currents. Because the leakage time corresponding to the first refresh frequency phase P1 is long, the leakage current generated in the first refresh frequency phase P1 can be smaller than the leakage current generated in the second refresh frequency phase P2 by optimizing the turn-off voltages of the first switch transistor T1 and the second switch transistor T2, so that the leakage charges of the pixel circuit in one frame time in the first refresh frequency phase P1 and the second refresh frequency phase P2 are the same, and the brightness of the display panel in the first refresh frequency and the second refresh frequency is the same when the same target display gray scale is displayed.
When the switching transistor is turned off, the larger the turn-off voltage is, the smaller the corresponding leakage current is. Therefore, by setting the off-voltage corresponding to the first driving signal to be greater than the off-voltage corresponding to the second driving signal, the leakage current generated by the display panel in the first refresh frequency phase P1 can be made smaller than the leakage current generated in the second refresh frequency phase P2. Based on the longer leakage time of the first refresh frequency phase P1, according to the charge formula Id1*Tf1＝Id2*Tf2The leakage charge of the first refresh frequency phase P1 and the second refresh frequency phase P2 can be guaranteed to be the same. Wherein, Id1And Id2Leakage current, T, of the first refresh frequency phase P1 and the second refresh frequency phase P2, respectivelyf1And Tf2The leakage time lengths corresponding to the first refresh frequency stage P1 and the second refresh frequency stage P2, respectively, and the current formula of the switch transistor is Id＝W/L*Cox(VG-Vth)*VDW/L is the width-to-length ratio of the channel of the switching transistor, Cox is the capacitance of the gate dielectric layer, and VGIs the off voltage.
In this embodiment, the off-voltage corresponding to the first driving signal and the off-voltage corresponding to the second driving signal satisfy:
VGf1＝(A*VGf2+BVth)*VD，
wherein, VGf1Is the turn-off voltage, V, corresponding to the first drive signalGf2Vth is the threshold voltage of the first switching transistor T1 or the second switching transistor T2 corresponding to the turn-off voltage of the second driving signal, VDA and B are constants for the voltage corresponding to the first pole at which the first switching transistor T1 or the second switching transistor T2 is connected to the gate of the driving transistor Tdrv. Taking the first refresh frequency as 60Hz and the second refresh frequency as 90Hz as an example, the relation between the turn-off voltages corresponding to the first refresh frequency and the second refresh frequency can be obtained based on the charge formula and satisfies VG60＝(2/3*VG90+1/3Vth)*VD. The turn-off voltages of the first switch transistor T1 and the second switch transistor T2 at the corresponding refresh frequency are set according to the formula, so that the electric charges of the first refresh frequency phase P1 and the second refresh frequency phase P2 can be ensured to be the same, and the brightness difference between the first refresh frequency phase P1 and the second refresh frequency phase P2 is reduced.
According to the technical scheme provided by the embodiment, according to the leakage time length of the first refresh frequency stage P1 and the second refresh frequency stage P2, the leakage current generated in the first refresh frequency stage P1 is smaller than the leakage current generated in the second refresh frequency stage P2 by optimizing the turn-off voltage of the first switch transistor T1 and the second switch transistor T2, so that the leakage charges of the pixel circuit in one frame time in the first refresh frequency stage P1 and the second refresh frequency stage P2 are the same, the brightness of the display panel in the first refresh frequency and the second refresh frequency in the one frame time is ensured to be the same, and the display effect that different refresh frequencies share the same gamma debugging data is improved.
Continuing with the pixel circuit shown in fig. 3 as an example, when the driving signal line includes a reset signal line, the reset signal line is configured such that the initialization voltage Vref transmitted to the second switching transistor T2 in the non-active area between the adjacent two display frames jumps from the low level to the high level in the first refresh frequency phase P1 and the second refresh frequency phase P2, and the initialization voltage Vref jumps from the high level to the low level in the active area. Fig. 5 is a waveform diagram of an initialization voltage corresponding to a reset signal line according to an embodiment of the present invention, and referring to fig. 5, a TE signal is a non-display trigger signal, and a signal transmitted on the reset signal line changes along with a change of the TE signal. Where VFP is the ending phase of the previous frame, VBP is the starting phase of the next frame, the high level of the TE signal may correspond to the non-display phase (e.g., the display panel is in the dark state), and the low level corresponds to the display phase. Illustratively, when the display panel is in a dark state, the data voltage Vdata stored on the storage capacitor Cst is high, and at this time, the reset signal line transmits a high-level initialization voltage to the second switching transistor T2 to reduce a voltage difference between the storage capacitor Cst and the reset signal line, so that leakage of the storage capacitor Cst to the reset signal line can be reduced. Since the leakage of the storage capacitor Cst is reduced, when the first refresh frequency phase P1 and the second refresh frequency phase P2 share the same set of gamma debug data, the brightness difference caused by the leakage of the storage capacitor Cst can be reduced. Alternatively, in the non-display period, the initialization voltage Vref is set to a positive voltage, which is beneficial to reduce the voltage difference between the storage capacitor Cst and the initialization voltage Vref, so as to further reduce the leakage of the storage capacitor Cst to the reset signal line.
Fig. 6 is a schematic structural diagram of another pixel circuit according to an embodiment of the present invention, fig. 7 is a timing control waveform diagram of another pixel circuit according to an embodiment of the present invention, referring to fig. 6 and 7, the pixel circuit includes a driving transistor Tdrv, a storage capacitor Cst, and a third switching transistor T3, and the driving signal line includes a third scanning signal line; the display panel further includes a data line.
A gate of the third switching transistor T3 is connected to the third scan signal line, a first pole of the third switching transistor T3 is connected to the data line, and a second pole of the third switching transistor T3 is connected to the first pole of the driving transistor Tdrv; the storage capacitor Cst is connected between the gate electrode of the driving transistor Tdrv and the first power line ELVDD, a first pole of the driving transistor Tdrv is connected to the first power line ELVDD, and a second pole of the driving transistor Tdrv is connected to the second power line ELVSS.
The first driving signal and the second driving signal transmitted on the third scan signal line each include a turn-on voltage for turning on the third switching transistor T3.
When the target display gray scale is a high gray scale, the duration of the starting voltage corresponding to the first driving signal is longer than the duration of the starting voltage corresponding to the second driving signal in a display frame.
Specifically, the detailed description of the first and second switching transistors T1 and T2 may refer to the related description of the above embodiments. The third switching transistor T3 is used to write the data voltage transmitted on the data line to the gate of the driving transistor Tdrv, and the third Scan signal Scan3 transmitted on the third Scan signal line is used to control the on-time of the third switching transistor T3.
For the case that different refresh frequencies share the same set of gamma debug data, the data lines are configured to have the same data voltage Vdata written to the gates of the driving transistors Tdrv when displaying the same target display gray scale in the first refresh frequency stage P1 and the second refresh frequency stage P2.
When displaying high gray scale, the voltage value of the data voltage Vdata corresponding to the display panel is lower, and the lower the data voltage Vdata, the brighter the corresponding display brightness. After the data writing phase is finished, the first Scan signal Scan1 has a low level to jump to a high level, so that the first switch transistor T1 is turned off, and due to the dual-gate function of the first switch transistor T1, the potential of the middle node (N point) of the first switch transistor T1 is increased, so that the first switch transistor T1 leaks electricity to the storage capacitor Cst (certainly, the electricity leaks to the reset signal line, but since the voltage difference between the first switch transistor T1 and the storage capacitor Cst is greater than the voltage difference between the first switch transistor T1 and the reset signal line, the first switch transistor T1 mainly leaks electricity to the storage capacitor Cst), and the storage capacitor Cst is charged. Due to the long drain time of the first refresh frequency phase P1, the average data voltage in the first refresh frequency phase P1 is larger than the average data voltage in the second refresh frequency phase P2 within one display frame, so that the display brightness of the first refresh frequency phase P1 is lower than the display brightness of the second refresh frequency phase P2.
Therefore, in the high gray scale display, the duration ta of the turn-on voltage VK1 corresponding to the first driving signal is shorter than the duration tb of the turn-on voltage VK2 corresponding to the second driving signal. That is to say, under the condition that the data voltages Vdata transmitted by the data lines are the same, the writing duration of the data voltage in the first refresh frequency phase P1 is reduced, so that the data voltage is insufficiently written, and further, the voltage value written by the data voltage Vdata is reduced, after the electric leakage occurs, it is beneficial to make the average data voltage in the first refresh frequency phase P1 equal to the average data voltage in the second refresh frequency phase P2, so as to ensure that the display brightness of the first refresh frequency phase P1 is the same as the display brightness of the second refresh frequency phase P2.
Similarly, in the low gray scale display, the voltage value of the data voltage Vdata corresponding to the display panel is higher, and the higher the data voltage Vdata is, the darker the corresponding display brightness is. At this time, a voltage difference between the storage capacitor Cst and the reset signal line is large, so that the storage capacitor Cst is leaked to the reset signal line through the second switching transistor T2, and the storage capacitor Cst is discharged. Due to the fact that the leakage time length of the first refresh frequency phase P1 is long, the average data voltage of the first refresh frequency phase P1 is smaller than the average data voltage of the second refresh frequency phase P2 in one display frame, and therefore the display brightness of the first refresh frequency phase P1 is higher than the display brightness of the second refresh frequency phase P2.
Fig. 8 is a timing control waveform diagram of another pixel circuit according to an embodiment of the invention, which combines fig. 6 and fig. 8, so that the duration ta of the turn-on voltage VK1 corresponding to the first driving signal is longer than the duration tb of the turn-on voltage VK2 corresponding to the second driving signal during the low gray scale display. That is, under the condition that the data voltages Vdata transmitted by the data lines are the same, the writing duration of the data voltage in the first refresh frequency phase P1 is increased, so that the data voltage is written more fully, and further, the voltage value written by the data voltage Vdata is increased, after the electric leakage occurs, the average data voltage in the first refresh frequency phase P1 is favorably equal to the average data voltage in the second refresh frequency phase P2, so as to improve the difference of the display brightness between the first refresh frequency phase P1 and the second refresh frequency phase P2.
Of course, in other embodiments, in order to ensure that the brightness difference between different refresh frequencies is smaller in the low gray scale display, the writing duration of the data voltage in the second refresh frequency phase P2 may be reduced while the writing duration of the data voltage in the first refresh frequency phase P1 is increased, so as to ensure that the average data voltage in the first refresh frequency phase P1 can be equal to the average data voltage in the second refresh frequency phase P2.
According to the technical scheme provided by the embodiment of the invention, when the display is carried out at different refreshing frequencies, the data voltage is compensated in a mode of changing the writing duration of the data voltage according to the target display gray scale, so that the initial brightness of the display panel is brighter when the display panel is displayed at a lower refreshing frequency, and is darker when the display panel is displayed at a lower refreshing frequency, and the display brightness of the first refreshing frequency stage P1 is ensured to be the same as the display brightness of the second refreshing frequency stage P2.
With continued reference to fig. 6, when the driving signal line includes a reset signal line, the reset signal line is configured to transmit an initialization voltage to the second switching transistor T2 when a target display gray scale is displayed. When the target display gray scale is a high gray scale, the voltage corresponding to the first driving signal is less than the voltage corresponding to the second driving signal. That is, when the display is performed at the first refresh frequency, the initialization voltage is reduced to lower the initial voltage of the gate of the driving transistor Tdrv, and further, when the data voltage Vdata is written, the voltage stored on the storage capacitor Cst can be made lower, after the leakage occurs, it is beneficial to make the average data voltage in the first refresh frequency phase P1 equal to the average data voltage in the second refresh frequency phase P2, so as to ensure that the display brightness in the first refresh frequency phase P1 is the same as the display brightness in the second refresh frequency phase P2.
Similarly, when the target display gray scale is a low gray scale, the voltage corresponding to the first driving signal is greater than the voltage corresponding to the second driving signal. That is, when the display is performed at the first refresh frequency, the initialization voltage is increased to make the initial voltage of the gate of the driving transistor Tdrv higher, and further, when the data voltage Vdata is written, the gate voltage of the driving transistor Tdrv can more easily reach the target data voltage, which is beneficial to reducing the probability of the leakage of the storage capacitor Cst to the reset signal line. After the leakage, it is advantageous to make the average data voltage of the first refresh frequency phase P1 equal to the average data voltage in the second refresh frequency phase P2, so as to improve the difference of the display brightness between the first refresh frequency phase P1 and the second refresh frequency phase P2.
It should be noted that the technical solutions provided by any embodiments of the present invention can be combined with each other to further improve the display effect. For example, on the basis of optimizing the turn-off voltages of the first and second switching transistors T1 and T2, the writing of the data voltage Vdata may be further optimized to ensure that the brightness of the display panel is the same when the same target gray scale is displayed at the first and second refresh frequencies.
Fig. 9 is a driving method of a display panel according to an embodiment of the present invention, where the display panel includes a pixel circuit and a driving signal line connected to the pixel circuit. Referring to fig. 9, a method for driving a display panel according to an embodiment of the present invention includes:
s110, in the first refresh frequency stage, when the target display gray scale is displayed, a first driving signal is transmitted to the pixel circuit through the driving signal line.
And S120, in the second refreshing frequency stage, when the target display gray scale is displayed, transmitting a second driving signal to the pixel circuit through the driving signal line so as to enable the brightness of the display panel to be consistent when the same display gray scale is displayed in different refreshing frequency stages.
In this embodiment, the first driving signal is different from the second driving signal, and the first refresh frequency is less than the second refresh frequency. The driving signals are signals output by corresponding driving signal lines, and different driving signals are configured according to the refreshing frequency of the display panel, so that the driving currents output by the pixel circuits under the same display gray scale are the same, and the brightness of the display panel is consistent when the same display gray scale is displayed at different refreshing frequency stages. Because the first refresh frequency is less than the second refresh frequency, compared with the first refresh frequency stage, the pixel circuit has a longer leakage time length in the first refresh frequency stage, and therefore, for different leakage time lengths (i.e., corresponding refresh frequencies), the driving signals transmitted to the pixel circuit through the driving signal lines when displaying the same display gray scale are different, so that when the pixel circuit displays the target display gray scale, the driving currents output by the pixel circuit after the leakage are the same, and the display brightness of the display panel is consistent. Since the driving method of the display panel provided by this embodiment is used for driving the display panel provided by any embodiment of the present invention, the driving method of the display panel provided by this embodiment also has the beneficial effects described in any embodiment of the present invention.
It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.
Claims (10)
1. A display panel includes a pixel circuit and a driving signal line connected to the pixel circuit;
in a first refresh frequency phase, the driving signal line is configured to transmit a first driving signal to the pixel circuit when a target display gray scale is displayed;
in a second refresh frequency stage, the driving signal line is configured to transmit a second driving signal to the pixel circuit when the target display gray scale is displayed, so that the brightness of the display panel is consistent when the same display gray scale is displayed in different refresh frequency stages; wherein the first drive signal is different from the second drive signal, and the first refresh frequency is less than the second refresh frequency.
2. The display panel according to claim 1, wherein the pixel circuit includes a driving transistor, a storage capacitor, a first switching transistor, and a second switching transistor, and wherein the driving signal line includes a first scanning signal line and a second scanning signal line;
a gate of the first switching transistor is connected to the first scan signal line, a first pole of the first switching transistor is connected to the gate of the driving transistor, and a second pole of the first switching transistor is connected to the second pole of the driving transistor; the grid electrode of the second switching transistor is connected with the second scanning signal line, the first pole of the second switching transistor is connected with the grid electrode of the driving transistor, and the second pole of the second switching transistor is connected with an initialization voltage; the storage capacitor is connected between the grid electrode of the driving transistor and a first power line, and the driving transistor is connected between the first power line and a second power line;
the first drive signal and the second drive signal each comprise an off voltage for turning off the first switching transistor and the second switching transistor; the turn-off voltage corresponding to the first driving signal is greater than the turn-off voltage corresponding to the second driving signal.
3. The display panel according to claim 2, wherein the off voltage corresponding to the first driving signal and the off voltage corresponding to the second driving signal satisfy:
VGf1＝(A*VGf2+BVth)*VD，
wherein, VGf1For the turn-off voltage, V, corresponding to the first drive signalGf2The second driving signal is the corresponding turn-off voltage, Vth is the threshold voltage of the first switch transistor or the second switch transistor, VDA and B are constants for the voltage corresponding to the first pole of the first switch transistor or the second switch transistor connected to the gate of the drive transistor.
4. The display panel according to claim 1, wherein the pixel circuit comprises a driving transistor, a storage capacitor, a first switching transistor, and a second switching transistor, wherein the driving signal line comprises a reset signal line, and wherein the display panel further comprises a first scanning signal line and a second scanning signal line;
a gate of the first switching transistor is connected to the first scan signal line, a first pole of the first switching transistor is connected to the gate of the driving transistor, and a second pole of the first switching transistor is connected to the second pole of the driving transistor; a gate of the second switching transistor is connected to the second scanning signal line, a first pole of the second switching transistor is connected to the gate of the driving transistor, and a second pole of the second switching transistor is connected to the reset signal line; the storage capacitor is connected between the grid electrode of the driving transistor and a first power line, and the driving transistor is connected between the first power line and a second power line;
in the first refresh frequency phase and the second refresh frequency phase, the reset signal line is configured to jump an initialization voltage transmitted to the second switching transistor from a low level to a high level in a non-active area between two adjacent display frames, and jump the initialization voltage from a high level to a low level in an active area.
5. The display panel according to claim 4, wherein an initialization voltage transmitted to the reset signal line in a non-active area between two adjacent display frames is a positive voltage.
6. The display panel according to claim 1, wherein the pixel circuit includes a driving transistor, a storage capacitor, and a third switching transistor, and wherein the driving signal line includes a third scanning signal line; the display panel further comprises a data line;
a gate of the third switching transistor is connected to the third scanning signal line, a first electrode of the third switching transistor is connected to the data line, and a second electrode of the third switching transistor is connected to the first electrode of the driving transistor; the storage capacitor is connected between the grid electrode of the driving transistor and a first power line, the first pole of the driving transistor is connected with the first power line, and the second pole of the driving transistor is connected with a second power line;
the first driving signal and the second driving signal transmitted on the third scanning signal line each include a turn-on voltage for turning on the third switching transistor;
when the target display gray scale is a high gray scale, in a display frame, the duration of the starting voltage corresponding to the first driving signal is less than the duration of the starting voltage corresponding to the second driving signal.
7. The display panel according to claim 6, wherein the duration of the turn-on voltage corresponding to the first driving signal is longer than the duration of the turn-on voltage corresponding to the second driving signal in a display frame when the target display gray scale is a low gray scale.
8. The display panel according to claim 1, wherein the pixel circuit comprises a driving transistor, a storage capacitor, a first switching transistor, and a second switching transistor, wherein the driving signal line comprises a reset signal line, and wherein the display panel further comprises a first scanning signal line and a second scanning signal line;
a gate of the first switching transistor is connected to the first scan signal line, a first pole of the first switching transistor is connected to the gate of the driving transistor, and a second pole of the first switching transistor is connected to the second pole of the driving transistor; a gate of the second switching transistor is connected to the second scanning signal line, a first pole of the second switching transistor is connected to the gate of the driving transistor, and a second pole of the second switching transistor is connected to the reset signal line; the storage capacitor is connected between the grid electrode of the driving transistor and a first power line, the first pole of the driving transistor is connected with the first power line, and the second pole of the driving transistor is connected with a second power line;
when the target display gray scale is a high gray scale, the initialization voltage corresponding to the first driving signal is smaller than the initialization voltage corresponding to the second driving signal.
9. The display panel according to claim 8, wherein the initialization voltage corresponding to the first driving signal is greater than the initialization voltage corresponding to the second driving signal when the target display gray scale is a low gray scale.
10. A driving method of a display panel, the display panel including a pixel circuit and a driving signal line connected to the pixel circuit;
the driving method of the display panel includes:
in a first refreshing frequency stage, when a target display gray scale is displayed, transmitting a first driving signal to the pixel circuit through the driving signal line;
in a second refreshing frequency stage, when the target display gray scale is displayed, a second driving signal is transmitted to the pixel circuit through the driving signal line, so that the brightness of the display panel is consistent when the same display gray scale is displayed in different refreshing frequency stages;
wherein the first drive signal is different from the second drive signal, and the first refresh frequency is less than the second refresh frequency.
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