JP2012108192A - Display device and driving method of display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a display device which has high definition and improves a display quality by reducing a threshold reliability shift of a drive transistor, and a driving method of the display device.SOLUTION: A display device includes a display element 16 and a pixel circuit 18 and comprises a plurality of pixel portions PX which are disposed in a matrix shape on a substrate. The pixel circuit includes a first output switch PCT connected to reset power supply wiring and a high-potential voltage power source, a drive transistor DRT connected to an anode of a light-emitting element and the reset power supply wiring, a second output switch BCT which is connected between the light-emitting element and the drive transistor DRT and of which the control terminal is connected to a second scan line, a hold capacitor connected between a first terminal of the drive transistor and a first terminal of the second output switch, and a pixel switch SST which is connected between video signal wiring and a control terminal of the drive transistor and of which the control terminal is connected to a third scan line. A scan line drive circuit has a plurality of reset switches RST which are connected between a reset power source and the reset power supply wiring and of each of which the control terminal is connected to a fourth scan line.

Description

  Embodiments described herein relate generally to a display device and a driving method of the display device, for example, an active matrix display device and a driving method thereof.

  In recent years, the demand for flat display devices typified by liquid crystal display devices has been rapidly increased by taking advantage of the features of thinness, light weight, and low power consumption. Among them, an active matrix display device in which each pixel is provided with a pixel switch having a function of electrically separating an on-pixel and an off-pixel and holding a video signal to the on-pixel includes various types of information including portable information devices. It is used for the display.

  As such a flat-type active matrix display device, an organic EL display device using a self-luminous element has attracted attention, and research and development have been actively conducted. The organic EL display device has characteristics that it does not require a backlight, is suitable for moving image reproduction because of high-speed responsiveness, and is suitable for use in a cold region because the luminance does not decrease at low temperatures.

  In general, an organic EL display device includes a plurality of display pixels that are arranged in a plurality of rows and a plurality of columns to form a display screen. Each display pixel includes an organic EL element that is a self-light emitting element and a pixel circuit that supplies a drive current to the organic EL element, and performs a display operation by controlling the light emission luminance of the organic EL element.

  As a pixel circuit driving method, a method using a voltage signal is known. In addition, the voltage power supply is switched to switch between low and high, and both the video signal and the initialization signal are output from the video signal wiring, thereby reducing the number of constituent elements and wiring of the display pixel. There has been proposed a display device that achieves higher definition by reducing the layout area.

US Pat. No. 6,229,506 JP 2005-031630 A JP 2007-310311 A

  In recent years, thin film transistors (TFTs) that have little local variation in characteristics such as amorphous silicon (a-Si) and In-Ga-ZnO4 (IGZO) and do not require characteristic compensation in pixel circuits / MDL circuits to ensure display uniformity. A display device using an array substrate has attracted attention. However, in the TFT, there is a threshold (Vth) shift that reduces the reliability. Therefore, it is necessary to compensate the pixel circuit / MDL circuit.

  As a pixel circuit for compensating Vth, for example, there is the above-described pixel circuit of the voltage signal driving system. However, in these pixel configurations, in reality, it is necessary to have about five transistors and about one capacitor or more. Therefore, the number of elements is large and the layout area of the display pixel is large, which is not suitable for small and high definition.

  A display device that achieves high definition by reducing the layout area of the display pixel is configured to compensate for both TFT mobility / Vth, and in TFT processes with low mobility such as a-Si and IGZO, the mobility is low. A huge TFT (switch TFT) is required for compensation. Therefore, this display device also has a large display pixel layout area and is not suitable for small size and high definition.

  The present invention has been made in view of the above circumstances, and even when a TFT process with low mobility such as a-Si or IGZO is used, an active matrix type that corrects the Vth shift and realizes small size and high definition. It is an object of the present invention to provide a display device and a driving method thereof.

A display device according to an embodiment includes a light emitting element and a pixel circuit that supplies a driving current to the light emitting element, and includes a plurality of pixel portions arranged in a matrix on a substrate, and the pixel portions are arranged. A plurality of scanning lines arranged along a row, a plurality of video signal wirings arranged along a column where the pixel portions are arranged, and a plurality of lines arranged along a row or a column where the pixel portions are arranged A reset power supply wiring; a high-potential voltage power supply line; a low-potential voltage power supply line; a scanning line drive circuit that sequentially supplies a control signal to the plurality of scanning lines to scan the pixel portion line by line; and the video signal A signal line driving circuit for supplying a video voltage signal to the wiring in accordance with the line sequential scanning,
The pixel circuit includes a first output switch having a first terminal connected before the reset power supply wiring, a second terminal connected to the high-potential voltage power supply, and a control terminal connected to the first scanning line; A drive transistor having a terminal indirectly connected to the anode of the light emitting element, a second terminal connected to the reset power supply line, a first terminal connected to the anode of the light emitting element, and a second terminal being the drive transistor And a storage capacitor connected between the control terminal of the drive transistor and the first terminal of the second output switch, the second output switch having a control terminal connected to the second scanning line, and a control terminal connected to the second scanning line. The first terminal is connected to the video signal wiring, the second terminal is connected to the control terminal of the driving transistor, the control terminal is connected to the third scanning line, and the video voltage signal is taken in from the video signal wiring. in front A pixel switch that holds the storage capacitor,
The scanning line driving circuit is provided for each reset power supply wiring, a plurality of first terminals connected to the reset power supply, a second terminal connected to the reset power supply wiring, and a control terminal connected to the fourth scanning line. Has a reset switch.

  According to an embodiment of the present invention, there is provided a display device driving method in which an initialization potential is applied from a video signal line to a control terminal of a drive transistor, and a reset potential is applied from a reset power supply line to the first terminal of the drive transistor. In a state where the initialization potential is applied from the video signal wiring to the control terminal of the drive transistor, a current is passed from the high potential voltage power supply line to the drive transistor, the threshold offset of the drive transistor is canceled, and the video The video voltage signal is written from the signal wiring to the control terminal of the driving transistor, and a driving current corresponding to the video voltage signal is supplied to the display element from the high potential voltage power line through the driving transistor.

FIG. 1 is a plan view schematically showing the organic EL display device according to the first embodiment. FIG. 2 is a plan view showing an equivalent circuit of display pixels in the organic EL display device. FIG. 3 is a timing chart showing a potential change of a control signal in the organic EL display device. FIG. 4 is a plan view showing an equivalent circuit of a display pixel in the organic EL display device according to the second embodiment. FIG. 5 is a timing chart showing potential changes of control signals in the organic EL display devices according to the second and third embodiments. FIG. 6 is a plan view showing an equivalent circuit of a display pixel in the organic EL display device according to the third embodiment. FIG. 7 is a plan view showing an equivalent circuit of a display pixel in the organic EL display device according to the fourth embodiment. FIG. 8 is a timing chart showing a potential change of a control signal in the organic EL display device according to the fourth embodiment. FIG. 9 is a plan view showing an equivalent circuit of a display pixel in the organic EL display device according to the fifth embodiment. FIG. 10 is a timing chart showing potential changes of control signals in the organic EL display device according to the fifth embodiment. FIG. 11 is a plan view showing an equivalent circuit of a display pixel in an organic EL display device according to a sixth embodiment. FIG. 12 is a timing chart showing potential changes of control signals in the organic EL display device according to the sixth embodiment.

Hereinafter, organic EL display devices according to various embodiments will be described in detail with reference to the drawings.
(First embodiment)
FIG. 1 is a plan view schematically showing the organic EL display device according to the first embodiment. As shown in FIG. 1, the organic EL display device is configured as, for example, an active matrix type display device of two or more types, and includes an organic EL panel 10 and a controller 12 that controls the operation of the organic EL panel 10. .

  The organic EL panel 10 includes a light-transmitting insulating substrate 8 such as a glass plate, m × n display pixels PX that are arranged in a matrix on the insulating substrate and constitute a display region 11, and each display pixel row. The first scanning line Sga (1 to m), the second scanning line Sgb (1 to m), the third scanning line Sgc (1 to m), and the fourth scanning line Sga (1 to m), which are connected and provided independently by m. The scanning line Sgd (1 to m) and n video signal lines X (1 to n) connected to each column of the display pixels PX are provided. The organic EL panel 10 is connected to each row of the display pixels PX and includes m reset power supply lines Vrst (described later), a high potential voltage power supply line PVDD, and a low potential. And a reference voltage power supply line PVSS.

  The organic EL panel 10 includes scanning line driving circuits 14a and 14b that sequentially drive the first scanning line Sga (1 to m) to the fourth scanning line Sgd (1 to m) for each row of the display pixels PX, and a plurality of video signals. A signal line driving circuit 15 for driving the wiring X (1 to n) is provided. The scanning line driving circuits 14 a and 14 b and the signal line driving circuit 15 are integrally formed on the insulating substrate 8 outside the display area 11 and constitute a control unit together with the controller 12.

  Each display pixel PX that functions as a pixel portion includes a display element having a photoactive layer (not shown) between counter electrodes (not shown), and a pixel circuit 18 that supplies a drive current to the display element. Contains. The display element is, for example, a self-luminous element, and in this embodiment, an organic EL element including at least an organic light-emitting layer as a photoactive layer is used.

  FIG. 2 shows an equivalent circuit of the display pixel PX. In each row, three display pixels PX for R (red) display, G (green) display, and B (blue) display are alternately arranged. The pixel circuit 18 of each display pixel PX is a voltage signal type pixel circuit that controls light emission of the organic EL element 16 in accordance with a video signal composed of a voltage signal, and includes a pixel switch SST, a drive transistor DRT, an output switch BCT, and It has a storage capacitor Cs as a capacitor. At least one of the display pixels PX in each row has an output switch PCT. In the present embodiment, an output switch PCT is provided in one display pixel PX among RGB, three display pixels PX. Further, the scanning line driving circuit 14a is provided with a plurality of reset switches RST, each connected to the reset power supply wiring Vrst of each row.

  In the display device according to the present embodiment, each drive transistor DRT, pixel switch SST, output switch BCT, output switch PCT, and reset switch RST are formed of the same conductivity type, for example, N-channel type thin film transistors. The driving transistor DRT and the thin film transistors constituting each switch are all formed in the same process and the same layer structure, and are, for example, a top gate thin film transistor using IGZO, a-Si, or polysilicon for the semiconductor layer. . Each switch is not limited to the N-channel type, but may be a P-channel type as long as it functions as a switch.

  Each of the pixel switch SST, the drive transistor DRT, the output switch PCT, the output switch BCT, and the reset switch RST has a first terminal, a second terminal, and a control terminal. In the present embodiment, these first terminal, second switch The terminal and the control terminal are a source, a drain, and a gate, respectively.

  In the pixel circuit 18 of the display pixel PX, for example, in the display pixel PX for green (G) display, the drive transistor DRT, the output switch PCT, and the output switch BCT are the high potential voltage power supply line PVDD and the low potential reference voltage power supply. The organic EL element 16 is connected in series with the line PVSS. The voltage power supply line PVDD is set to a potential of 10V, for example, and the reference voltage power supply line PVSS is set to a potential of 1.5V, for example. The voltage power supply line PVDD and the reference voltage power supply line PVSS are connected to the signal line drive circuit XDR and supplied with the power supply voltage from the signal line drive circuit XDR.

  The output switch PCT functioning as the first output switch has its second terminal, here the drain, connected to the voltage power supply line PVDD, and the first terminal, here the source, is the second terminal of the drive transistor DRT, here the drain. It is connected to the. The gate of the output switch PCT is connected to the first scanning line Sga (1 to m). Accordingly, the output switch PCT is turned on (conductive state) and off (non-conductive state) by the control signal PG (1 to m) from the first scanning line Sga (1 to m), and the organic EL element 16 emits light. Control the time.

  The drain of the drive transistor DRT is connected to the source of the output switch PCT and the reset power supply wiring Vrst, and the source is connected to one electrode, here the anode, of the organic EL element 16 via the output switch BCT. The cathode of the organic EL element 16 is connected to the reference voltage power line PVSS. The drive transistor DRT outputs a drive current having a current amount corresponding to the video signal to the organic EL element 16. In FIG. 2, the symbol Cel indicates the parasitic capacitance of the organic EL element 16.

  Since the output switch PCT is shared by a plurality of pixel circuits, for example, in the display pixel PX of red (R) and blue (B), the output switch PCT is not provided, and the drive transistor DRT is It is connected between the organic EL element 16 and the reset power supply wiring Vrst wiring.

  The output switch BCT functioning as the second output switch has its first terminal, here the source connected to one electrode of the organic EL element 16, here the anode, and its second terminal, here the drain, the drive transistor DRT. Connected to the source. The gate of the output switch BCT is connected to the second scanning line Sgb (1 to m) functioning as a light emission period control gate line, and the control signal BG (1 to 1) supplied from the second scanning line Sgb (1 to m). On / off control is performed by m).

  The pixel switch SST has a source connected to the video signal wiring X (1 to n) and a drain connected to the gate of the drive transistor DRT. The gate of the pixel switch SST is connected to the third scanning line Sgc (1 to m) functioning as a signal writing control gate wiring, and the control signal SG (1 to 1) supplied from the third scanning line Sgc (1 to m). On / off control is performed by m). The pixel switch SST controls connection / disconnection between the pixel circuit 18 and the video signal wiring X (1-n) in response to the control signal SG (1-m), and the corresponding video signal wiring X ( 1 to n), the gradation video voltage signal is taken into the pixel circuit 18.

  The holding capacitor Cs has two electrodes facing each other, is connected between the gate of the driving transistor DRT and the source of the output switch BCT, and holds the gate control potential of the driving transistor DRT determined by the video signal.

  For each row, the reset switch RST provided in the scanning line driving circuit 14b is connected between the drain of the driving transistor DRT and the reset power supply Vrst. The gate of the reset switch RST is connected to a fourth scanning line Sge (1 to m) that functions as a reset control gate wiring. The reset switch RST is on (conducting state) and off (non-conducting state) controlled according to the control signal RG (1 to m) from the fourth scanning line Sge (1 to m), and the source potential of the driving transistor DRT is set. initialize.

  On the other hand, the controller 12 shown in FIG. 1 is formed on a printed circuit board (not shown) arranged outside the organic EL panel 10 and controls the scanning line driving circuits 14 a and 14 b and the signal line driving circuit 15. The controller 12 receives a digital video signal and a synchronization signal supplied from the outside, and generates a vertical scanning control signal for controlling the vertical scanning timing and a horizontal scanning control signal for controlling the horizontal scanning timing based on the synchronizing signal.

  The controller 12 supplies the vertical scanning control signal and the horizontal scanning control signal to the scanning line driving circuits 14a and 14b and the signal line driving circuit 15, respectively, and at the same time, the digital video signal and the initial stage are synchronized with the horizontal and vertical scanning timings. The signal is supplied to the signal line drive circuit 15.

  The signal line driving circuit 15 converts the video signals sequentially obtained in each horizontal scanning period into an analog format under the control of the horizontal scanning control signal, and the red video voltage signal, the green video voltage signal, and the blue video corresponding to the video signal. A plurality of gradation voltage signals Vsig including a voltage signal are supplied in parallel to the plurality of video signal lines X (1 to n). Further, the signal line driving circuit 15 supplies the initialization voltage signal in parallel to the plurality of video signal lines X (1 to n) every horizontal period.

  The scanning line driving circuits 14a and 14b include a shift register (not shown), an output buffer (not shown), and the like, and sequentially transfer a horizontal scanning start pulse supplied from the outside to the next stage. 4, four types of control signals, that is, control signals PG (1 to m), BG (1 to m), SG (1 to m), and RG (1) are applied to the display pixels PX in each row via the output buffer. ~ M). As a result, the first scanning line Sga (1 to m) to the fourth scanning line Sgd (1 to m) are respectively supplied to the control signals PG (1 to m), BG (1 to m), SG (1 to m), and RG. Driven by (1-m).

  Next, the operation of the organic EL display device configured as described above will be described. FIG. 3 shows a timing chart of the control signals of the scanning line drive circuits 14a and 14b during operation display. For example, the scanning line driving times 14a and 14b generate a pulse having a width of one horizontal scanning period corresponding to each horizontal scanning period H from a start signal and a clock, and the pulses are generated as control signals PG (1 to m), BG. (1 to m), SG (1 to m), and RG (1 to m) are output.

  The operation of the pixel circuit 18 is divided into a reset operation, a threshold offset cancel (OC) operation, a writing operation, and a light emitting operation. FIG. 3 is a timing chart for explaining an example of a method for driving the display device according to the present embodiment.

  First, a reset operation is performed. In the reset operation, from the scanning line drive circuits 14a and 14b, the level at which the output switch PCT is turned off (off potential), here, the low level control signal PG, the level at which the output switch BCT is turned on (on potential), Here, a high level control signal BG, a level at which the pixel switch SST is turned on (on potential), a high level control signal SG, a level at which the reset switch RST is turned on, a high level control here. A signal RG is output. As a result, the output switch PCT is turned off (non-conducting state), the output switch BCT, the pixel switch SST, and the reset switch RST are turned on (conducting state), and the reset operation is started.

  In the reset period, the initialization voltage signal VINI output from the video signal wiring X (1 to n) is applied to the gate of the driving transistor DRT through the pixel switch SST. As a result, the gate potential of the drive transistor DRT is reset to a potential corresponding to the initialization voltage signal VINI, and information of the previous frame is initialized. The initialization voltage signal VINI is set to 2V, for example.

  Further, the reset voltage signal VRST output from the reset power supply wiring Vrst is applied to the source and drain of the drive transistor DRT through the reset switch RST. As a result, the source and drain potentials of the drive transistor DRT are reset to a potential corresponding to the reset voltage signal VRST, for example, −2 V, and the information of the previous frame is initialized.

  Subsequently, an offset cancel (OC) operation is performed. The control signal PG is turned on (high level), and the control signal RG is turned off (low level). As a result, the reset switch RST is turned off (non-conducting state), the output switch PCT, the output switch BCT, and the pixel switch SST are turned on (conducting state), and the threshold value offset cancel operation is started.

  In the offset cancel period, the gate voltage of the drive transistor DRT is applied to the initialization voltage signal VINI output from the video signal wiring X (1 to n) through the pixel switch SST and is fixed to VINI.

  Further, since the output switch PCT is in the ON state, a current flows from the voltage power supply line PVDD to the drive transistor DRT. The source potential of the drive transistor DRT absorbs variation in TFT characteristics of the drive transistor while gradually reducing the current flowing through the drain-source of the drive transistor DRT, with the potential VRST written during the reset period as an initial value. Shifting to the high potential side while compensating. In the present embodiment, the offset cancellation period is set to about 5 μsec, for example. At the end of the cancel period, the source potential of the drive transistor DRT becomes VINI-Vth. Vth is a threshold voltage of the drive transistor DRT. As a result, the gate-source voltage of the drive transistor DRT reaches the cancel point, and a potential difference corresponding to the cancel point is stored in the storage capacitor Cs.

  Subsequently, a write operation is performed. In the writing operation, a low level control signal BG for turning off the output switch BCT and a high level control signal SG for turning on the pixel switch SST are output. As a result, the output switch BCT and the reset switch RST are turned off, the output switch PCT and the pixel switch SST are turned on (conductive state), and the writing operation is started.

  In the writing period, the gradation video voltage signal Vsig is written from the video signal wiring X (1 to n) through the pixel switch SST to the gate of the driving transistor DRT. The gate potential of the drive transistor DRT is Vsig (R, G, B), and the source potential of the output switch BCT is VINI−Vth + Cs (Vsig−VINI) / (Cs + Cel).

  At the same time or subsequently, the control signal SG becomes low level and the control signal BG becomes high level, and the light emission period is started. In the light emission period, a drive current flows from the voltage power supply line PVDD to the drive transistor DRT of each of the R, G, and B display pixels PX through the output switch PCT and the reset power supply wiring Vrst.

  The drive transistor DRT outputs a drive current Ie having a current amount corresponding to the gate control voltage written in the storage capacitor Cs. This drive current Ie is supplied to the organic EL element 16 via the output switch BCT. Thereby, the organic EL element 16 emits light with a luminance corresponding to the drive current Ie, and performs a light emission operation. The organic EL element 16 maintains the light emitting state until the control signal BG becomes the off potential again after one frame period.

  The above-described reset operation, offset cancel operation, write operation, and light emission operation are sequentially performed on each display pixel to display a desired image.

According to the organic EL display device configured as described above, during the light emission period, the current Ie flowing through the organic EL element 16 is expressed as a current value in the saturation region of the drive transistor DRT.
Ie = β × {(Vsig−VINI) × Cel / (Cs + Cel)} ²
β = μ · CelxW / 2L, (W: channel width of TFT channel layer, L: channel length)
Thus, the value does not depend on the threshold value (Vth) of the drive transistor DRT. Therefore, it is possible to eliminate the influence due to the variation in the threshold value of the driving transistor. Even when TFTs with low mobility such as a-Si and IGZO are used, the threshold shift of the drive transistor can be corrected, and a small and high-definition active matrix display device and a driving method thereof can be provided. .

(Second Embodiment)
Next, an organic EL display device according to the second embodiment will be described. Note that in the second embodiment, the same components as those in the first embodiment described above are denoted by the same reference numerals, description thereof is omitted, and different components are described in detail.
FIG. 4 shows an equivalent circuit of the display pixel PX in the organic EL display device according to the second embodiment. In the first embodiment described above, the initialization signal is supplied to each pixel circuit through the video signal line. In the second embodiment, the initialization power supply line Vini is provided for each row of display pixels of the display panel. Each pixel circuit 18 includes an initialization switch IST that takes in an initialization signal from an initialization power supply line. In addition, the display panel includes fifth scan lines Sge (1 to m) provided for each row of display pixels, and the initialization switch IST is controlled to be turned on / off by the fifth scan lines.

  As shown in FIG. 4, in each row where a plurality of display pixels PX are arranged, three display pixels PX for red (R) display, green (G) display, and blue (B) display are periodically arranged. Is provided. The pixel circuit 18 of each display pixel PX is a voltage signal type pixel circuit that controls light emission of the organic EL element 16 in accordance with a video signal composed of a voltage signal, and includes a pixel switch SST, a drive transistor DRT, an output switch PCT, and an output. A switch BCT, an initialization switch IST, and a holding capacitor Cs as a capacitor are included. The output switch PCT is shared by a plurality of pixel circuits. One of the scanning line drive circuits 14a and 14b is provided with a plurality of reset switches RST, each connected to the reset power supply wiring Vrst of each row.

  In the display device according to the present embodiment, each drive transistor DRT, pixel switch SST, output switch BCT, output switch PCT, reset switch RST, and initialization switch IST are composed of thin film transistors of the same conductivity type, for example, N-channel type. Has been. The driving transistor DRT and the thin film transistors constituting each switch are all formed in the same process and the same layer structure, and are, for example, a top gate thin film transistor using IGZO, a-Si, or polysilicon for the semiconductor layer. . Each switch is not limited to the N-channel type, but may be a P-channel type as long as it functions as a switch.

  In the pixel circuit 18 of the display pixel PX, the drive transistor DRT, the output switch PCT, and the output switch BCT are connected in series with the organic EL element 16 between the high potential voltage power supply line PVDD and the low potential reference voltage power supply line PVSS. It is connected. The voltage power supply line PVDD is set to a potential of 10V, for example, and the reference voltage power supply line PVSS is set to a potential of 1.5V, for example. The voltage power supply line PVDD and the reference voltage power supply line PVSS are connected to the signal line drive circuit and supplied with the power supply voltage from the signal line drive circuit.

  The output switch PCT has a drain connected to the voltage power supply line PVDD and a source connected to the drain of the drive transistor DRT. The gate of the output switch PCT is connected to the first scanning line Sga (1 to m). As a result, the output switch PCT is turned on and off by the control signal PG (1 to m) from the first scanning line Sga (1 to m), and controls the light emission time of the organic EL element 16.

  The drain of the drive transistor DRT is connected to the source of the output switch PCT and the reset power supply wiring Vrst, and the source is connected to one electrode, here the anode, of the organic EL element 16 via the output switch BCT. The cathode of the organic EL element 16 is connected to the reference voltage power line PVSS. The drive transistor DRT outputs a drive current having a current amount corresponding to the video signal to the organic EL element 16. In FIG. 4, the symbol Cel indicates the parasitic capacitance of the organic EL element 16.

  The output switch BCT has a source connected to one electrode of the organic EL element 16, here an anode, and a drain connected to the source of the drive transistor DRT. The gate of the output switch BCT is connected to the second scanning line Sgb (1 to m) functioning as a light emission period control gate line, and the control signal BG (1 to 1) supplied from the second scanning line Sgb (1 to m). On / off control is performed by m).

  The pixel switch SST has a source connected to the video signal wiring X (1 to n) and a drain connected to the gate of the drive transistor DRT. The gate of the pixel switch SST is connected to the third scanning line Sgc (1 to m) functioning as a signal writing control gate wiring, and the control signal SG (1 to 1) supplied from the third scanning line Sgc (1 to m). On / off control is performed by m). The pixel switch SST controls connection / disconnection between the pixel circuit 18 and the video signal wiring X (1-n) in response to the control signal SG (1-m), and the corresponding video signal wiring X ( 1 to n), the gradation video voltage signal is taken into the pixel circuit 18.

  The holding capacitor Cs has two electrodes facing each other, is connected between the gate of the driving transistor DRT and the source of the output switch BCT, and holds the gate control potential of the driving transistor DRT determined by the video signal.

  For each row, the reset switch RST provided in the scanning line driving circuit 14b is connected between the drain of the driving transistor DRT and the reset power supply Vrst. The gate of the reset switch RST is connected to a fourth scanning line Sge (1 to m) that functions as a reset control gate wiring. The reset switch RST is turned on / off in response to a control signal RG (1-m) from the fourth scanning line Sge (1-m), and initializes the source potential of the driving transistor DRT.

  The initialization switch IST has a source connected to the initialization power supply line Vini and a drain connected to the gate of the drive transistor DRT. The gate of the initialization switch IST is connected to the fifth scanning line Sge (1 to m) functioning as a signal writing control gate wiring, and is supplied from the scanning line driving circuit through the fifth scanning line Sge (1 to m). On / off control is performed by a control signal IG (1 to m).

The scanning line drive circuits 14a and 14b of the organic EL display device apply five types of control signals to the display pixels PX in each row, that is, control signals PG (1 to m), BG (1 to m), and SG (1 to m). , RG (1 to m) and IG (1 to m) are supplied. As a result, the first scanning line Sga (1 to m) to the fifth scanning line Sge (1 to m) are controlled by the control signals PG (1 to m), BG (1 to m), SG (1 to m), and RG, respectively. (1 to m) and IG (1 to m).
Other configurations of the organic EL display device according to the second embodiment are the same as those of the first embodiment described above.

  Next, the operation of the organic EL display device according to the second embodiment will be described. FIG. 5 shows a timing chart of control signals of the scanning line drive circuits 14a and 14b during the display operation. For example, the scanning line driving times 14a and 14b generate a pulse having a width of one horizontal scanning period corresponding to each horizontal scanning period H from a start signal and a clock, and the pulses are generated as control signals PG (1 to m), BG. (1 to m), SG (1 to m), RG (1 to m), and IG (1 to m) are output.

  The operation of the pixel circuit 18 is divided into a reset operation, a threshold offset cancel (OC) operation, a writing operation, and a light emitting operation. First, a reset operation is performed. In the reset operation, from the scanning line drive circuits 14a and 14b, the level at which the output switch PCT is turned off (off potential), here, the low level control signal PG, the level at which the output switch BCT is turned on (on potential), Here, a high-level control signal BG, a low-level control signal SG that turns off the pixel switch SST, a high-level control signal RG that turns on the reset switch RST, and a high level that turns on the initialization switch IST The control signal IG is output.

  As a result, the output switch PCT and the pixel switch SST are turned off (non-conducting state), the output switch BCT, the reset switch RST, and the initialization switch IST are turned on (conducting state), and the reset operation is started.

  In the reset period, the initialization voltage signal VINI output from the initialization power supply wiring Vini is applied to the gate of the drive transistor DRT through the initialization switch IST. As a result, the gate potential of the drive transistor DRT is reset to a potential corresponding to the initialization voltage signal VINI, and information of the previous frame is initialized. The initialization voltage signal VINI is set to 2V, for example.

  The reset voltage signal VRST output from the reset power supply wiring Vrst is applied to the source and drain of the drive transistor DRT through the reset switch RST. As a result, the source and drain potentials of the drive transistor DRT are reset to a potential corresponding to the reset voltage signal VRST, for example, −2 V, and the information of the previous frame is initialized.

  Subsequently, an offset cancel (OC) operation is performed. The control signal PG is set to an on potential (high level), and the control signal RG is set to an off potential (low level). Accordingly, the reset switch RST and the pixel switch SST are turned off (non-conducting state), the output switch PCT, the output switch BCT, and the initialization switch IST are turned on (conducting state), and the threshold value offset cancel operation is started.

  In the offset cancel period, the gate potential of the drive transistor DRT is output from the initialization power supply wiring, and the initialization voltage signal VINI is applied through the initialization switch IST, and is fixed to the initialization potential.

  Since the output switch PCT is in the on state, a current flows from the voltage power supply line PVDD to the drive transistor DRT. The source potential of the drive transistor DRT absorbs variations in TFT characteristics of the drive transistor while gradually reducing the current flowing through the drain-source of the drive transistor DRT, with the potential Vrst written during the reset period as an initial value. Shifting to the high potential side while compensating. In the present embodiment, the offset cancellation period is set to about 10 μsec, for example. At the end of the cancel period, the source potential of the drive transistor DRT becomes VINI-Vth. Vth is a threshold voltage of the drive transistor DRT. As a result, the gate-source voltage of the drive transistor DRT reaches the cancel point, and a potential difference corresponding to the cancel point is stored in the storage capacitor Cs.

  Subsequently, a write operation is performed. The control signal BG sets the output switch BCT to the off potential (low level), the control signal IG sets the initialization switch IST to the off potential (low level), and the control signal SG sets the pixel switch to the on potential (high level). As a result, the reset switch RST, the output switch BCT, and the initialization switch IST are turned off (non-conducting state), the output switch PCT and the pixel switch SST are turned on (conducting state), and the writing operation is started.

  In the writing period, the video voltage signal Vsig is written from the video signal wiring X (1 to n) through the pixel switch SST to the gate of the drive transistor DRT. The gate potential of the drive transistor DRT is Vsig (R, G, B), and the source potential of the output switch BCT is VINI−Vth + Cs (Vsig−VINI) / (Cs + Cel).

  At the same time or subsequently, the control signal SG is set to the low level and the control signal BG is set to the high level, and the light emission operation is started. In the light emission period, a drive current flows from the voltage power supply line PVDD to the drive transistor DRT of each of the R, G, and B display pixels PX through the output switch BCT and the reset power supply wiring Vrst.

  The drive transistor DRT outputs a drive current Ie having a current amount corresponding to the gate control voltage written in the storage capacitor Cs. This drive current Ie is supplied to the organic EL element 16. Thereby, the organic EL element 16 emits light with a luminance corresponding to the drive current Ie, and performs a light emission operation. The organic EL element 16 maintains the light emitting state until the control signal BG becomes the off potential again after one frame period. The above-described reset operation, offset cancel operation, write operation, and light emission operation are sequentially performed on each display pixel to display a desired image.

According to the organic EL display device configured as described above, during the light emission period, the current Ie flowing through the organic EL element 16 is expressed as a current value in the saturation region of the drive transistor DRT.
Ie = β × {(Vsig−VINI) × Cel / (Cs + Cel)} ²
β = μ · CelxW / 2L (W: channel width, L: channel length)
Thus, the value does not depend on the threshold value Vth of the drive transistor DRT. Therefore, it is possible to eliminate the influence due to the variation in the threshold value of the driving transistor. Even when TFTs with low mobility such as a-Si and IGZO are used, the threshold shift of the drive transistor can be corrected, and a small and high-definition active matrix display device and a driving method thereof can be provided. .

(Third embodiment)
Next, an organic EL display device according to a third embodiment will be described. Note that, in the third embodiment, the same parts as those in the second embodiment described above are denoted by the same reference numerals, description thereof is omitted, and different components will be described in detail.
FIG. 6 shows an equivalent circuit of the display pixel PX in the organic EL display device according to the third embodiment. In the third embodiment, each pixel circuit 18 further includes a storage capacitor Ck as a capacitor. The storage capacitor CK has two electrodes and is connected between the source of the output switch BCT and the voltage power supply line PVDD. The power supply wiring to which the storage capacitor CK is connected is not limited to the voltage power supply line PVDD but may be other power supply wiring such as the reset power supply wiring Vrst and the initialization power supply wiring Vini.
In the third embodiment, other configurations of the pixel circuit 18 and other configurations of the organic EL display device are the same as those of the second embodiment described above.

  The operation of the organic EL display device according to the third embodiment configured as described above is the same as that of the organic EL display device according to the second embodiment described above, and the control signal shown in FIG. The operation is the same as the timing chart. That is, the operation of each pixel circuit 18 is divided into a reset operation, a threshold offset cancel (OC) operation, a writing operation, and a light emitting operation.

  In the third embodiment, in the write operation, the control signal BG turns off the output switch BCT (low level), the control signal IG turns off the initialization switch IST (low level), and the control signal SG turns on the pixel switch. Set to potential (high level). As a result, the reset switch RST, the output switch BCT, and the initialization switch IST are turned off (non-conductive state), the output switch PCT and the pixel switch SST are turned on (conductive state), and the writing operation is started.

  In the writing period, the video voltage signal Vsig is written from the video signal wiring X (1 to n) through the pixel switch SST to the gate of the drive transistor DRT. The gate potential of the drive transistor DRT is Vsig (R, G, B), and the source potential of the output switch BCT is VINI−Vth + Cs (Vsig−VINI) / (Cs + Cel + Ck).

  At the same time or subsequently, the control signal SG becomes low level and the control signal BG becomes high level, and the light emission operation is started. In the light emission period, a drive current flows from the voltage power supply line PVDD to the drive transistor DRT of each of the R, G, and B display pixels PX through the output switch BCT and the reset power supply wiring Vrst.

  The drive transistor DRT outputs a drive current Ie having a current amount corresponding to the gate control voltage written in the storage capacitor Cs. This drive current Ie is supplied to the organic EL element 16. Thereby, the organic EL element 16 emits light with a luminance corresponding to the drive current Ie, and performs a light emission operation. The organic EL element 16 maintains the light emitting state until the control signal BG becomes the off potential again after one frame period.

According to the organic EL display device configured as described above, during the light emission period, the current Ie flowing through the organic EL element 16 is expressed as a current value in the saturation region of the drive transistor DRT.
Ie = β × {(Vsig−VINI) × (Cel + Ck) / (Cs + Cel + Ck)} ²
β = μ · CoxW / 2L, (W: channel width, L: channel length)
Thus, the value does not depend on the threshold value Vth of the drive transistor DRT. Therefore, it is possible to eliminate the influence due to the variation in the threshold value of the driving transistor. Even when TFTs with low mobility such as a-Si and IGZO are used, the threshold shift of the drive transistor can be corrected, and a small and high-definition active matrix display device and a driving method thereof can be provided. . Further, the current Ie has a value corresponding to the voltage division ratio between the holding capacitor Cs and the parasitic capacitance Cel of the organic EL element 16, and at this time, by setting the holding capacitor CK to a constant value, the variation of the parasitic capacitance Cel is reduced. It can be adjusted by Ck. Thereby, the drive current of the drive transistor DRT can be set to a stable value.

(Fourth embodiment)
Next, an organic EL display device according to a fourth embodiment will be described. Note that in the third embodiment, the same components as those in the third embodiment described above are denoted by the same reference numerals, description thereof is omitted, and different components are described in detail.
FIG. 7 shows an equivalent circuit of the display pixel PX in the organic EL display device according to the fourth embodiment. According to the fourth embodiment, the holding capacitors Cs and Ck are connected to the source of the driving transistor, and are not directly connected to the parasitic capacitor Cel of the organic EL element 16. In the fourth embodiment, other configurations of the pixel circuit 18 and other configurations of the organic EL display device are the same as those of the third embodiment described above.

  The operation of the organic EL display device configured as described above will be described. FIG. 8 shows a timing chart of control signals of the scanning line driving circuit during the display operation. The operation of the pixel circuit 18 is divided into a reset operation, a threshold offset cancel (OC) operation, a writing operation, and a light emitting operation.

  First, the pixel circuit 18 performs a reset operation. In the reset operation, the scanning line driving circuit causes the control signal PG to be at a low level that turns off the output switch PCT, the control signal BG to be at a low level that turns off the output switch BCT, and the control signal SG to turn off the pixel switch SST. The control signal RG is set to a high level that turns on the reset switch RST, and the control signal IG is set to a high level that turns on the initialization switch IST. As a result, the output switch PCT, the pixel switch SST, and the output switch BCT are turned off (non-conductive state), the reset switch RST and the initialization switch IST are turned on (conductive state), and the reset operation is started.

  In the reset period, the initialization voltage signal VINI output from the initialization power supply wiring Vini is applied to the gate of the drive transistor DRT through the initialization switch IST. As a result, the gate potential of the drive transistor DRT is reset to a potential corresponding to the initialization voltage signal VINI, and information of the previous frame is initialized. The initialization voltage signal VINI is set to 2V, for example.

  Further, the reset voltage signal VRST output from the reset power supply wiring Vrst is applied to the source and drain of the drive transistor DRT through the reset switch RST. As a result, the source and drain potentials of the drive transistor DRT are reset to a potential corresponding to the reset voltage signal VRST, for example, −2 V, and the information of the previous frame is initialized.

  Subsequently, an offset cancel operation is performed. The control signal PG is turned on (high level), and the control signal RG is turned off (low level). Accordingly, the reset switch RST, the pixel switch SST, and the output switch BCT are turned off (non-conducting state), the output switch PCT and the initialization switch IST are turned on (conducting state), and the threshold value offset cancel operation is started.

  In the offset cancel period, the gate potential of the drive transistor DRT is output from the initialization power supply wiring Vini, and the initialization voltage signal VINI is applied through the initialization switch IST, and is fixed to VINI.

  Further, since the output switch PCT is in the ON state, a current flows from the voltage power supply line PVDD to the drive transistor DRT. The source potential of the drive transistor DRT absorbs variation in TFT characteristics of the drive transistor while gradually reducing the current flowing through the drain-source of the drive transistor DRT, with the potential VRST written during the reset period as an initial value. Shifting to the high potential side while compensating. In the present embodiment, the offset cancellation period is set to about 10 μsec, for example. At the end of the cancel period, the source potential of the drive transistor DRT becomes VINI-Vth. Vth is a threshold voltage of the drive transistor DRT. As a result, the gate-source voltage of the drive transistor DRT reaches the cancel point, and a potential difference corresponding to the cancel point is stored in the storage capacitor Cs.

  Subsequently, in the writing period, the control signal IG sets the initialization switch IST to the off potential (low level), and the control signal SG sets the pixel switch to the on potential (high level). As a result, the reset switch RST, the output switch BCT, and the initialization switch IST are turned off (non-conductive state), the output switch PCT and the pixel switch SST are turned on (conductive state), and the writing operation is started.

  In the writing period, the video voltage signal Vsig is written from the video signal wiring X (1 to n) through the pixel switch SST to the gate of the drive transistor DRT. The gate potential of the drive transistor DRT is Vsig (R, G, B), and the source potential of the drive transistor DRT is VINI−Vth + Cs (Vsig−VINI) / (Cs + Ck).

  At the same time or subsequently, the control signal SG becomes low level and the control signal BG becomes high level, and the light emission period is started. In the light emission period, a drive current flows from the voltage power supply line PVDD to the drive transistor DRT of each of the R, G, and B display pixels PX through the output switch BCT and the reset power supply wiring Vrst.

  The drive transistor DRT outputs a drive current Ie having a current amount corresponding to the gate control voltage written in the storage capacitor Cs. This drive current Ie is supplied to the organic EL element 16. Thereby, the organic EL element 16 emits light with a luminance corresponding to the drive current Ie, and performs a light emission operation. The organic EL element 16 maintains the light emitting state until the control signal BG becomes the off potential again after one frame period.

  The above-described reset operation, offset cancel operation, write operation, and light emission operation are sequentially performed on each display pixel to display a desired image.

According to the organic EL display device configured as described above, during the light emission period, the current Ie flowing through the organic EL element 16 is expressed as a current value in the saturation region of the drive transistor DRT.
Ie = β × {(Vsig−VINI) × Ck) / (Cs + Ck)} ²
β = μ · CelxW / 2L (W: channel width, L: channel length)
Thus, the value does not depend on the threshold value Vth of the drive transistor DRT. Therefore, it is possible to eliminate the influence due to the variation in the threshold value of the driving transistor. Even when TFTs with low mobility such as a-Si and IGZO are used, the threshold shift of the drive transistor can be corrected, and a small and high-definition active matrix display device and a driving method thereof can be provided. . Further, since the holding capacitors Cs and Ck are not directly connected to the parasitic capacitance Cel of the organic EL element 16, the current value Ie output from the drive transistor DRT is not affected by the parasitic capacitance Cel, and the holding capacitance Cs, Depends on the Ck partial pressure ratio. Therefore, it is possible to suppress fluctuations in the drive current due to variations in the parasitic capacitance Cel.

(Fifth embodiment)
Next, an organic EL display device according to a fifth embodiment will be described. Note that in the fifth embodiment, parts that are the same as those in the third embodiment described above are given the same reference numerals, and descriptions thereof are omitted, and different components will be described in detail.
FIG. 9 shows an equivalent circuit of the display pixel PX in the organic EL display device according to the fifth embodiment. The organic EL panel of the organic EL display device is connected to each row of the display pixels PX, and is independently provided with m second scanning lines Sgb (1 to m) and third scanning lines Sgc (1). M), the fourth scanning line Sgd (1 to m), the fifth scanning line Sge (1 to m), the sixth scanning line Sgf (1 to m), and n lines connected to each column of the display pixels PX. Video signal wiring X (1 to n) is provided.

  Further, the organic EL panel has a reset power supply wiring Vrst, an initialization power supply wiring Vini, a high potential voltage power supply line PVDD, and a low potential reference voltage power supply line PVSS which are connected to each row of the display pixels PX. And have.

  The organic EL panel includes scanning line driving circuits 14a and 14b that sequentially drive the second scanning line Sgb (1 to m) to the sixth scanning line Sgf (1 to m) for each row of the display pixels PX, and a plurality of video signal wirings. A signal line driving circuit for driving X (1 to n) is provided. The scanning line driving circuits 14a and 14b and the signal line driving circuit are integrally formed on the insulating substrate outside the display area, and constitute a controller together with the controller.

  As shown in FIG. 9, each display pixel PX includes an organic EL element 16 having at least an organic light emitting layer as a photoactive layer, and a pixel circuit 18 that supplies a driving current to the display element. In each row in which a plurality of display pixels PX are arranged, three display pixels PX for red (R) display, green (G) display, and blue (B) display are periodically arranged.

  The voltage signal type pixel circuit 18 includes a pixel switch SST, a drive transistor DRT, an output switch BCT, an initialization switch IST, and holding capacitors Cs and Ck as capacitors. The scanning line driving circuit 14a (or the scanning line driving circuit 14b) is provided with a plurality of reset switches RST, each connected to the reset power supply wiring Vrst in each row. The scanning line driving circuit 14a (or scanning line driving circuit 14b) is provided with a plurality of initialization switches IST2, and each is connected to the initialization power supply wiring Vini.

  Here, the driving transistor DRT, the pixel switch SST, the output switch BCT, the reset switch RST, the initialization switch IST, and IST2 are formed of the same conductivity type, for example, N-channel type thin film transistors. The driving transistor DRT and the thin film transistors constituting each switch are all formed in the same process and the same layer structure, and are, for example, a top gate thin film transistor using IGZO, a-Si, or polysilicon for the semiconductor layer. . Each switch is not limited to the N-channel type, but may be a P-channel type as long as it functions as a switch.

  In the pixel circuit 18 of the display pixel PX, the drive transistor DRT and the output switch BCT are connected in series with the organic EL element 16 between the high potential voltage power supply line PVDD and the low potential reference voltage power supply line PVSS. The voltage power supply line PVDD is set to a potential of 10V, for example, and the reference voltage power supply line PVSS is set to a potential of 1.5V, for example. The voltage power supply line PVDD and the reference voltage power supply line PVSS are connected to the signal line drive circuit XDR and supplied with the power supply voltage from the signal line drive circuit XDR.

  The drive transistor DRT has its drain connected to the voltage power supply line PVDD and its source indirectly connected to one electrode (here, the anode) of the organic EL element 16 via an output switch BCT described later. The cathode of the organic EL element 16 is connected to the reference voltage power line PVSS. The drive transistor DRT outputs a drive current having a current amount corresponding to the video signal to the organic EL element 16. The symbol Cel indicates the parasitic capacitance of the organic EL element 16.

  The output switch BCT has its first terminal, here the source, connected to one electrode of the organic EL element 16, here the anode, and its second terminal, here the drain, connected to the source of the drive transistor DRT. ing. The gate of the output switch BCT is connected to the second scanning line Sgb (1 to m) functioning as a light emission period control gate line, and the control signal BG (1 to 1) supplied from the second scanning line Sgb (1 to m). On / off control is performed by m).

  The pixel switch SST has a source connected to the video signal wiring X (1 to n) and a drain connected to the gate of the drive transistor DRT. The gate of the pixel switch SST is connected to the third scanning line Sgc (1 to m) functioning as a signal writing control gate wiring, and the control signal SG (1 to 1) supplied from the third scanning line Sgc (1 to m). On / off control is performed by m). The pixel switch SST controls connection / disconnection between the pixel circuit and the video signal wiring X (1-n) in response to the control signal SG (1-m), and the corresponding video signal wiring X (1 ~ N), the gradation video voltage signal is taken into the pixel circuit.

  The holding capacitor Cs is connected between the gate of the driving transistor DRT and the source of the output switch BCT, and holds the gate control potential of the driving transistor DRT determined by the video signal.

  For each row, the reset switch RST provided in the scanning line driving circuit 14b is connected between the drain of the initialization switch IST and the reset power supply Vrst. The gate of the reset switch RST is connected to a fourth scanning line Sge (1 to m) that functions as a reset control gate wiring. The reset switch RST is on (conducting state) and off (non-conducting state) controlled according to the control signal RG (1 to m) from the fourth scanning line Sge (1 to m), and the source potential of the driving transistor DRT is set. initialize.

The initialization switch IST has its drain connected to the source of the reset switch RST and its source connected to the gate of the drive transistor DRT. The gate of the initialization switch IST is connected to the fifth scanning line Sge (1 to m) functioning as a signal writing control gate wiring, and the control signal IG (1) supplied from the fifth scanning line Sge (1 to m). ~ M), the on / off control.
The holding capacitor Ck has two electrodes and is connected between the source of the output switch BCT and the gate of the reset switch RST.

  For each row, the initialization switch IST2 provided in the scanning line driving circuit is connected between the drain of the initialization switch IST and the initialization power supply line Vini. The gate of the initialization switch IST2 is connected to the sixth scanning line Sgf (1 to m) that functions as an initialization control gate wiring. The initialization switch IST2 is ON (conductive state) and OFF (non-conductive state) controlled according to the control signal IG2 (1 to m) from the sixth scanning line Sgf (1 to m), and the source potential of the drive transistor DRT. Is initialized.

  In addition, the organic EL display device has the same configuration as that of the above-described third embodiment, and includes a controller that controls the scanning line driving circuits 14a and 14b and the signal line driving circuit. The controller receives a digital video signal and a synchronizing signal supplied from the outside, and generates a vertical scanning control signal for controlling the vertical scanning timing and a horizontal scanning control signal for controlling the horizontal scanning timing based on the synchronizing signal.

  Next, the operation of the organic EL display device configured as described above will be described. FIG. 10 shows a timing chart of the control signal of the scanning line driving circuit during the display operation. The operation of the pixel circuit 18 is divided into a reset operation, a threshold offset cancel (OC) operation, a writing operation, and a light emitting operation. First, the pixel circuit 18 performs a reset operation.

  As shown in FIG. 9 and FIG. 10, in the reset operation, the scanning line drive circuits 14a and 14b cause the control signal BG to turn on the output switch BCT (on potential), where the high level and the control signal SG are The level at which the pixel switch SST is turned off (off potential), here, the low level, and the control signal RG is at the level (on potential) that turns on the reset switch RST, here the high level, and the control signal IG is the initialization switch The level at which the IST is turned on (on potential), here is set to the high level, and the control signal IG2 is set to the level at which the initialization switch IST2 is turned off (off potential), here, the low level.

  Accordingly, the pixel switch SST and the initialization switch IST2 are turned off (non-conducting state), the output switch BCT, the reset switch RST, and the initialization switch IST are turned on (conducting state), and the reset operation is started.

  In the reset period, the reset voltage signal VRST output from the reset power supply wiring Vrst is applied to the gate of the drive transistor DRT through the reset switch RST and the initialization switch IST. Thereby, the source potential of the drive transistor DRT is set to a potential Vx at which the current flowing through the drive transistor DRT and the current flowing through the light emitting element 16 are equal. The potential corresponding to the reset voltage signal VRST, for example, 7V is reset, and information of the previous frame is initialized.

  Subsequently, a pre-offset cancel (OC) operation is performed. The control signal SG is set to an on potential (high level), and the control signal RG is set to an off potential (low level). As a result, the reset switch RST and the initialization switch IST2 are turned off (non-conducting state), the output switch BCT, the pixel switch SST, and the initialization switch IST are turned on (conducting state), and the threshold pre-offset canceling operation is started.

  In the pre-offset cancel period, the gate voltage of the driving transistor DRT is fixed to VINI by applying the initialization voltage signal VINI (Vip) output from the video signal wiring X (1 to n) through the pixel switch SST. At this time, the source potential of the drive transistor DRT is Vx ′ = Vx + (VINI−Vrst) * Cs / (Cs + Cel + Ck).

  In addition, a current flows from the voltage power supply line PVDD to the drive transistor DRT. The source potential of the drive transistor DRT absorbs variation in TFT characteristics of the drive transistor while gradually reducing the current flowing through the drain-source of the drive transistor DRT with the potential Vx ′ set in the reset period as an initial value.・ Shift to higher potential while compensating. In this embodiment, the pre-offset cancellation period is set to about 5 μsec, for example.

  Subsequently, an offset cancel (OC) operation is performed. The control signal SG is set to an off potential (low level), and the control signal IG2 is set to an on potential (high level). Accordingly, the reset switch RST and the pixel switch SST are turned off (non-conducting state), the output switch BCT, the initialization switch IST2, and the initialization switch IST are turned on (conducting state), and the threshold value offset cancel operation is started.

  In the offset cancel period, the gate voltage of the drive transistor DRT is fixed to VINI by applying the initialization voltage signal VINI output from the initialization power supply wiring through the initialization switch IST and the initialization 2 switch IST2.

  In addition, a current flows from the voltage power supply line PVDD to the drive transistor DRT. The source potential of the drive transistor DRT shifts to the high potential side while absorbing and compensating for TFT characteristic variations of the drive transistor while gradually reducing the amount of current flowing through the drain-source of the drive transistor DRT. In the present embodiment, the offset cancellation period is set to about 10 μsec, for example. At the end of the cancel period, the source potential of the drive transistor DRT becomes VINI-Vth. Vth is a threshold voltage of the drive transistor DRT. As a result, the gate-source voltage of the drive transistor DRT reaches the cancel point, and a potential difference corresponding to the cancel point is stored in the storage capacitor Cs.

  Subsequently, in the writing period, the control signal BG turns off the output switch BCT (low level), the control signal IG turns off the initialization switch IST (low level), and the control signal IG2 turns off the initialization switch IST2. Low level), the control signal SG sets the pixel switch to the ON potential (high level). As a result, the reset switch RST, the output switch BCT, the initialization switch IST, and the initialization switch IST2 are turned off (non-conducting state), the pixel switch SST is turned on (conducting state), and the writing operation is started.

  In the writing period, the gradation video voltage signal Vsig is written from the video signal wiring X (1 to n) through the pixel switch SST to the gate of the driving transistor DRT. The gate potential of the drive transistor DRT is Vsig (R, G, B), and the source potential of the output switch BCT is VINI−Vth + Cs (Vsig−VINI) / (Cs + Cel + Ck).

  At the same time or subsequently, the control signal SG becomes low level and the control signal BG becomes high level, and the light emission period is started. In the light emission period, a drive current flows from the voltage power supply line PVDD to the drive transistor DRT of each of the R, G, and B display pixels PX through the output switch BCT and the reset power supply wiring Vrst.

  The drive transistor DRT outputs a drive current Ie having a current amount corresponding to the gate control voltage written in the storage capacitor Cs. This drive current Ie is supplied to the organic EL element 16. Thereby, the organic EL element 16 emits light with a luminance corresponding to the drive current Ie, and performs a light emission operation. The organic EL element 16 maintains the light emitting state until the control signal BG becomes the off potential again after one frame period. The above-described reset operation, offset cancel operation, write operation, and light emission operation are sequentially performed on each display pixel to display a desired image.

According to the organic EL display device configured as described above, during the light emission period, the current Ie flowing through the organic EL element 16 is expressed as a current value in the saturation region of the drive transistor DRT.
Ie = β × {(Vsig−VINI) × (Cel + Ck) / (Cs + Cel + Ck)} ²
β = μ · CelxW / 2L (W: channel width, L: channel length)
Thus, the value does not depend on the threshold value Vth of the drive transistor DRT. Therefore, it is possible to eliminate the influence due to the variation in the threshold value of the driving transistor. In addition, the number of elements in each pixel circuit can be reduced. Thus, even when TFTs with low mobility such as a-Si and IGZO are used, the threshold shift of the drive transistor can be corrected, and a small and high-definition active matrix display device and a driving method thereof are provided. be able to.

(Sixth embodiment)
Next, an organic EL display device according to a sixth embodiment will be described. Note that in the sixth embodiment, identical parts to those in the fifth embodiment described above are denoted by the same reference numerals, description thereof is omitted, and different components are described in detail.
FIG. 11 shows an equivalent circuit of the display pixel PX in the organic EL display device according to the sixth embodiment. According to the sixth embodiment, the holding capacitors Cs and Ck are connected to the source of the driving transistor, and are not directly connected to the parasitic capacitor Cel of the organic EL element 16. In the sixth embodiment, other configurations of the pixel circuit 18 and other configurations of the organic EL display device are the same as those of the fifth embodiment described above.

  The operation of the organic EL display device configured as described above will be described. FIG. 12 shows a timing chart of the control signal of the scanning line driving circuit during the display operation. The operation of the pixel circuit 18 is divided into a reset operation, a pre-offset cancel (OC) operation, a threshold offset cancel (OC) operation, a write operation, and a light emission operation.

  First, the pixel circuit 18 performs a reset operation. In the reset operation, the scanning line driving circuit causes the control signal BG to be at a high level for turning on the output switch BCT, the control signal SG to be at a low level for turning off the pixel switch SST, and the control signal RG to turn on the reset switch RST. The control signal IG is set to a high level for turning on the initialization switch IST, and the control signal IG2 is set to a low level for turning off the initialization switch IST2. Accordingly, the pixel switch SST and the initialization switch IST2 are turned off (non-conducting state), the output switch BCT, the reset switch RST, and the initialization switch IST are turned on (conducting state), and the reset operation is started.

  In the reset period, the reset voltage signal VRST output from the reset power supply wiring Vrst is applied to the gate of the drive transistor DRT through the reset switch RST and the initialization switch IST. Thereby, the source potential of the drive transistor DRT is set to a potential Vx at which the current flowing through the drive transistor DRT is equal to the current flowing through the light emitting element. The potential corresponding to the reset voltage signal VRST, for example, 7V is reset, and information of the previous frame is initialized.

  Subsequently, a pre-offset cancel operation is performed. The control signal SG is turned on (high level), the control signal BG is turned off (low level), and the control signal RG is turned off (low level). Thereby, the reset switch RST, the output switch BCT, and the initialization switch IST2 are turned off (non-conducting state), the pixel switch SST and the initialization switch IST are turned on (conducting state), and the threshold pre-offset canceling operation is started.

  In the pre-offset cancel period, the gate voltage of the drive transistor DRT is fixed to VINI by applying the initialization voltage signal VINI (Vip) output from the video signal wiring through the pixel switch SST. At this time, the source potential of the drive transistor DRT is Vx ′ = Vx + (VINI−Vrst) * Cs / (Cs + Ck).

  In addition, a current flows from the voltage power supply line PVDD to the drive transistor DRT. The source potential of the drive transistor DRT absorbs variation in TFT characteristics of the drive transistor while gradually reducing the current flowing through the drain-source of the drive transistor DRT with the potential Vx ′ set in the reset period as an initial value.・ Shift to higher potential while compensating. In this embodiment, the pre-offset cancellation period is set to about 5 μsec, for example.

  Subsequently, an offset cancel operation is performed. The control signal SG is turned off (low level), and the control signal IG2 is turned on (high level). Accordingly, the reset switch RST, the pixel switch SST, and the output switch BCT are turned off (non-conducting state), the initialization switch IST2 and the initialization switch IST are turned on (conducting state), and the threshold value offset cancel operation is started.

  In the offset cancel period, the gate voltage of the drive transistor DRT is fixed to VINI by applying the initialization voltage signal VINI output from the initialization power supply wiring through the initialization switch IST and the initialization switch IST2.

  In addition, a current flows from the voltage power supply line PVDD to the drive transistor DRT. The source potential of the drive transistor DRT shifts to the high potential side while absorbing and compensating for TFT characteristic variations of the drive transistor while gradually reducing the amount of current flowing through the drain-source of the drive transistor DRT. In the present embodiment, the offset cancellation period is set to about 10 μsec, for example. At the end of the cancel period, the source potential of the drive transistor DRT becomes VINI-Vth. Vth is a threshold voltage of the drive transistor DRT. As a result, the gate-source voltage of the drive transistor DRT reaches the cancel point, and a potential difference corresponding to the cancel point is stored in the storage capacitor Cs.

  Subsequently, in the writing period, the control signal IG turns off the initialization switch IST (low level), the control signal IG2 turns off the initialization switch IST2, and the control signal SG turns on the pixel switch (high level). Level). As a result, the reset switch RST, the output switch BCT, the initialization switch IST, and the initialization switch IST2 are turned off (non-conducting state), the pixel switch SST is turned on (conducting state), and the writing operation is started.

  In the writing period, the gradation video voltage signal Vsig is written from the video signal wiring X (1 to n) through the pixel switch SST to the gate of the driving transistor DRT. The gate potential of the drive transistor DRT is Vsig (R, G, B), and the source potential of the drive transistor DRT is VINI−Vth + Cs (Vsig−VINI) / (Cs + Ck).

  At the same time or subsequently, the control signal SG becomes low level and the control signal BG becomes high level, and the light emission operation is started. In the light emission period, a drive current flows from the voltage power supply line PVDD to the drive transistor DRT of each of the R, G, and B display pixels PX through the output switch BCT and the reset power supply wiring Vrst.

  The drive transistor DRT outputs a drive current Ie having a current amount corresponding to the gate control voltage written in the storage capacitor Cs. This drive current Ie is supplied to the organic EL element 16. Thereby, the organic EL element 16 emits light with a luminance corresponding to the drive current Ie, and performs a light emission operation. The organic EL element 16 maintains the light emitting state until the control signal BG becomes the off potential again after one frame period. The above-described reset operation, offset cancel operation, write operation, and light emission operation are sequentially performed on each display pixel to display a desired image.

According to the organic EL display device configured as described above, during the light emission period, the current Ie flowing through the organic EL element 16 is expressed as a current value in the saturation region of the drive transistor DRT.
Ie = β × {(Vsig−VINI) × (Ck) / (Cs + Ck)} ²
β = μ · CelxW / 2L (W: channel width, L: channel length)
Thus, the value does not depend on the threshold value Vth of the drive transistor DRT. Therefore, it is possible to eliminate the influence due to the variation in the threshold value of the driving transistor. Even when TFTs with low mobility such as a-Si and IGZO are used, the threshold shift of the drive transistor can be corrected, and a small and high-definition active matrix display device and a driving method thereof can be provided. . In addition, since the holding capacitors Cs and Ck are not directly connected to the parasitic capacitance Cel of the organic EL element 16, the current value Ie output from the driving transistor DRT is not received by the parasitic capacitance Cel, and the holding capacitance It depends on the partial pressure ratio of Cs and Ck. Therefore, it is possible to suppress fluctuations in the drive current due to variations in the parasitic capacitance Cel.

  As described above, according to the various embodiments described above, it is possible to obtain an active matrix display device and a driving method thereof that suppress a reliability shift of the TFT, and have high definition and display quality.

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

  For example, in the fifth and sixth embodiments described above, the pre-offset cancel operation in the operation of the pixel circuit may be omitted. In the above-described embodiment, the plurality of reset power supply lines and the plurality of initialization power supply lines are not limited to each row of the pixel portion, and may be provided for each column. The shapes and dimensions of the transistors and switches are not limited to the above-described embodiments, and can be changed as necessary. Although one output switch is provided for each dot, the present invention is not limited thereto, and one output switch may be provided for a plurality of dots as necessary. The self-luminous elements constituting the display pixels are not limited to organic EL elements, and various display elements capable of self-luminance are applicable.

PX ... display pixel, Sga ... first scanning line, Sgb ... second scanning line, Sgc ... third scanning line,
Sgd: fourth scanning line, Sge: fifth scanning line, Sgf: sixth scanning line,
Vini: initialization power supply wiring, Vrst: reset power supply wiring, PVDD: voltage power supply line,
PVSS ... reference voltage power supply line, 15 ... signal line drive circuit, DRT ... drive transistor,
Cs: holding capacity, BCT: output switch, PCT: output switch,
RST ... Reset switch, IST ... Initialization switch, SST ... Pixel switch,
VRST: reset potential, Cel: parasitic capacitance, 14a, 14b: scanning line driving circuit,
12 ... Controller, 16 ... Organic EL element (light emitting element)

Claims (20)

A plurality of pixel portions including a light emitting element and a pixel circuit for supplying a driving current to the light emitting element, the pixel parts being arranged in a matrix on the substrate;
A plurality of scanning lines arranged along rows of the pixel portions;
A plurality of video signal wirings arranged along a row in which the pixel portions are arranged;
A plurality of reset power supply wirings arranged along rows or columns of the pixel portions;
A high potential voltage power line and a low potential voltage power line;
A scanning line driving circuit that sequentially supplies a control signal to the plurality of scanning lines to scan the pixel portion line by line in a row unit;
A signal line driving circuit for supplying a video voltage signal to the video signal wiring in accordance with the line sequential scanning;
The pixel circuit includes:
A first output switch having a first terminal connected before the reset power supply wiring, a second terminal connected to the high potential voltage power supply, and a control terminal connected to the first scan line;
A drive transistor having a first terminal indirectly connected to the anode of the light emitting element and a second terminal connected to the reset power supply wiring;
A second output switch having a first terminal connected to the anode of the light emitting element, a second terminal connected to the first terminal of the driving transistor, and a control terminal connected to a second scanning line;
A storage capacitor connected between a control terminal of the drive transistor and a first terminal of the second output switch;
The first terminal is connected to the video signal wiring, the second terminal is connected to the control terminal of the driving transistor, the control terminal is connected to the third scanning line, and the video voltage signal is captured from the video signal wiring and held. A pixel switch that holds the capacitor,
The scanning line driving circuit is provided for each reset power supply wiring, a plurality of first terminals connected to the reset power supply, a second terminal connected to the reset power supply wiring, and a control terminal connected to the fourth scanning line. Display device having a reset switch. A plurality of pixel portions including a light emitting element and a pixel circuit for supplying a driving current to the light emitting element, the pixel parts being arranged in a matrix on the substrate;
A plurality of scanning lines arranged along rows of the pixel portions;
A plurality of video signal wirings arranged along a row in which the pixel portions are arranged;
A plurality of reset power supply wirings arranged along rows or columns of the pixel portions;
A high potential voltage power line and a low potential voltage power line;
A scanning line driving circuit that sequentially supplies a control signal to the plurality of scanning lines to scan the pixel portion line by line in a row unit;
A signal line driving circuit for supplying a video voltage signal to the video signal wiring in accordance with the line sequential scanning;
The pixel circuit includes:
A first output switch having a first terminal connected before the reset power supply wiring, a second terminal connected to the high potential voltage power supply, and a control terminal connected to the first scan line;
A drive transistor having a first terminal indirectly connected to the anode of the light emitting element and a second terminal connected to the reset power supply wiring;
A second output switch having a first terminal connected to the anode of the light emitting element, a second terminal connected to the first terminal of the driving transistor, and a control terminal connected to a second scanning line;
A storage capacitor connected between a control terminal and a first terminal of the drive transistor;
The first terminal is connected to the video signal wiring, the second terminal is connected to the control terminal of the driving transistor, the control terminal is connected to the third scanning line, and the video voltage signal is captured from the video signal wiring and held. A pixel switch that holds the capacitor,
The scanning line driving circuit is provided for each reset power supply wiring, a plurality of first terminals connected to the reset power supply, a second terminal connected to the reset power supply wiring, and a control terminal connected to the fourth scanning line. Display device having a reset switch. A plurality of initialization power supply wirings arranged along the rows or columns of the pixel unit;
The pixel circuit includes an initialization switch having a first terminal connected to the initialization power supply wiring, a second terminal connected to a control terminal of the drive transistor, and a control terminal connected to a fifth scanning line. The display device according to claim 1.   The display device according to claim 1, wherein the pixel circuit includes a capacitor formed between a first terminal of the second output switch and the high potential voltage power supply wiring.   The display device according to claim 1, wherein the pixel circuit includes a capacitor formed between a first terminal of the second output switch and the reset power supply wiring.   The display device according to claim 1, wherein the pixel circuit includes a capacitor formed between a first terminal of the second output switch and the fourth scanning line.   4. The display device according to claim 1, wherein the pixel circuit includes a capacitor formed between a first terminal of the second output switch and one of fixed power wirings in the pixel.   The display device according to claim 2, wherein the pixel circuit includes a capacitor formed between a first terminal of the driving transistor and the high-potential voltage power supply wiring.   The display device according to claim 2, wherein the pixel circuit includes a capacitor formed between a first terminal of the driving transistor and the reset power supply wiring.   The display device according to claim 2, wherein the pixel circuit includes a capacitor formed between a first terminal of the driving transistor and the fourth scanning line.   4. The display device according to claim 2, wherein the pixel circuit includes a capacitor formed between a first terminal of the driving transistor and one of fixed power supply wirings in the pixel.   The display device according to claim 1, wherein the first output switch is shared by a plurality of the pixel units. The plurality of pixel portions include a pixel portion for red display, a pixel portion for green display, and a pixel portion for blue display provided alternately arranged along each row,
13. The display device according to claim 12, wherein the first output switch is shared by three pixel portions, ie, a pixel portion for red display, a pixel portion for green display, and a pixel portion for blue display.   14. The display device according to claim 1, wherein the first output switch, the second output switch, the pixel switch, and the reset switch are formed of N-channel or P-channel thin film transistors. A plurality of pixel portions including a light emitting element and a pixel circuit for supplying a driving current to the light emitting element, the pixel parts being arranged in a matrix on the substrate;
A plurality of scanning lines arranged along rows of the pixel portions;
A plurality of video signal wirings arranged along a row in which the pixel portions are arranged;
A plurality of reset power supply wirings arranged along rows or columns of the pixel portions;
A plurality of initialization power supply wirings arranged along rows or columns in which the pixel portions are arranged;
A high potential voltage power line and a low potential voltage power line;
A scanning line driving circuit that sequentially supplies a control signal to the plurality of scanning lines to scan the pixel portion line by line in a row unit;
A signal line driving circuit for supplying a video voltage signal to the video signal wiring in accordance with the line sequential scanning;
The pixel circuit includes:
A drive transistor having a first terminal indirectly connected to the anode of the light emitting element and a second terminal connected to the high potential voltage power source;
An output switch having a first terminal connected to the anode of the light emitting element, a second terminal connected to the first terminal of the driving transistor, and a control terminal connected to the first scanning line;
A storage capacitor connected between a first terminal and a control terminal of the drive transistor;
The first terminal is connected to the video signal wiring, the second terminal is connected to the control terminal of the driving transistor, the control terminal is connected to the second scanning line, and the video voltage signal is captured from the video signal wiring and held. A pixel switch held in the capacitor;
An initialization switch having a first terminal connected to the initialization power supply wiring, a second terminal connected to a control terminal of the driving transistor, and a control terminal connected to a third scanning line;
The scanning line driving circuit is provided for each reset power supply wiring, a plurality of first terminals connected to the reset power supply, a second terminal connected to the reset power supply wiring, and a control terminal connected to the fourth scanning line. The reset switch
Provided for each of the initialization power supply wirings, a plurality of second initial connections in which a first terminal is connected to the initialization power supply, a second terminal is connected to the initialization power supply wiring, and a control terminal is connected to the fifth scan line. Switch
A capacitor connected between the first terminal of the driving transistor and the fourth scanning line;
A display device comprising: A plurality of pixel portions including a light emitting element and a pixel circuit for supplying a driving current to the light emitting element, the pixel parts being arranged in a matrix on the substrate;
A plurality of scanning lines arranged along rows of the pixel portions;
A plurality of video signal wirings arranged along a row in which the pixel portions are arranged;
A plurality of reset power supply wirings arranged along rows or columns of the pixel portions;
A plurality of initialization power supply wirings arranged along rows or columns in which the pixel portions are arranged;
A high potential voltage power line and a low potential voltage power line;
A scanning line driving circuit that sequentially supplies a control signal to the plurality of scanning lines to scan the pixel portion line by line in a row unit;
A signal line driving circuit for supplying a video voltage signal to the video signal wiring in accordance with the line sequential scanning;
The pixel circuit includes:
A drive transistor having a first terminal indirectly connected to the anode of the light emitting element and a second terminal connected to the high potential voltage power source;
An output switch having a first terminal connected to the anode of the light emitting element, a second terminal connected to the first terminal of the driving transistor, and a control terminal connected to the first scanning line;
A storage capacitor connected between a control terminal of the drive transistor and a first terminal of the output switch;
The first terminal is connected to the video signal wiring, the second terminal is connected to the control terminal of the driving transistor, the control terminal is connected to the second scanning line, and the video voltage signal is captured from the video signal wiring and held. A pixel switch that holds the capacitance,
An initialization switch having a first terminal connected to the initialization power supply wiring, a second terminal connected to a control terminal of the driving transistor, and a control terminal connected to a third scanning line;
The scanning line driving circuit is provided for each reset power supply wiring, a plurality of first terminals connected to the reset power supply, a second terminal connected to the reset power supply wiring, and a control terminal connected to the fourth scanning line. The reset switch
Provided for each of the initialization power supply wirings, a plurality of second initial connections in which a first terminal is connected to the initialization power supply, a second terminal is connected to the initialization power supply wiring, and a control terminal is connected to the fifth scan line. Switch
A capacitor connected between the first terminal of the output switch and the fourth scanning line;
A display device comprising: A driving method of a display device according to claim 1 or 2,
An initialization potential is applied from the video signal wiring to the control terminal of the driving transistor, a reset potential is applied from the reset power supply wiring to the first terminal of the driving transistor, and the driving transistor is initialized.
In a state where the initialization potential is applied from the video signal wiring to the control terminal of the drive transistor, a current is passed from the high potential voltage power supply line to the drive transistor, and the threshold offset of the drive transistor is canceled.
Write the video voltage signal from the video signal wiring to the control terminal of the drive transistor,
A driving method of a display device, wherein a driving current corresponding to the video voltage signal is supplied from the high potential voltage power supply line to the display element through the driving transistor. A driving method of a display device according to claim 3,
An initialization potential is applied from the initialization power supply wiring to the control terminal of the drive transistor, a reset potential is applied from the reset power supply wiring to the first terminal of the drive transistor, and the drive transistor is initialized.
In a state where an initialization potential is applied from the initialization power supply wiring to the control terminal of the drive transistor, a current is passed from the high potential voltage power supply line to the drive transistor, and a threshold offset of the drive transistor is canceled.
Write the video voltage signal from the video signal wiring to the control terminal of the drive transistor,
A driving method of a display device, wherein a driving current corresponding to the video voltage signal is supplied from the high potential voltage power supply line to the display element through the driving transistor. A driving method of a display device according to claim 15 or 16,
Initialize the drive transistor by applying a reset potential from the reset power supply wiring to the control terminal of the drive transistor,
In a state where the initialization potential is applied from the video signal wiring to the control terminal of the drive transistor, a current is passed from the high potential voltage power supply line to the drive transistor, and the threshold offset of the drive transistor is canceled.
In a state where the initialization potential is applied from the initialization power supply wiring to the control terminal of the drive transistor, a current is passed from the high potential voltage power supply line to the drive transistor, and the threshold offset of the drive transistor is canceled.
Write the video voltage signal from the video signal wiring to the control terminal of the drive transistor,
A driving method of a display device, wherein a driving current corresponding to the video voltage signal is supplied from the high potential voltage power supply line to the display element through the driving transistor.   20. The display device according to claim 17, wherein an initialization voltage signal, a red video voltage signal, a green video voltage signal, and a blue video voltage signal are sequentially output from the signal line driving circuit within one horizontal period. Driving method.

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