JP2010122320A - Active matrix display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an active matrix display device displaying an excellent image. <P>SOLUTION: The display device includes display elements 16, pixel circuits 18, a plurality of image signal lines, and a signal line driving circuit 15. Each of the pixel circuits includes a drive transistor DRT; an output switch BCT; a first switch TCT; a first retention volume C1 connected between a first terminal of the drive transistor and a first terminal of the first switch; a second retention volume C2 connected between a control terminal of the drive transistor and the first terminal of the first switch; an initialization switch IST wherein a first terminal is connected to an initialization power source 22, a second terminal is connected to the control terminal of the drive transistor, and a control terminal is connected to a cancel time control scanning line; a reset switch RST wherein a first terminal is connected to a reset power source 23, a second terminal is connected to the first terminal of the first switch, and a control terminal is connected to a reset time control scanning line; and a pixel switch SST retrieving an image voltage signal from the image signal lines. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to an active matrix display device, and more particularly to an active matrix display device that performs signal writing using a voltage signal.

  In recent years, the demand for flat display devices typified by liquid crystal display devices has been rapidly increased by taking advantage of the features of thinness, light weight, and low power consumption. In particular, an active matrix display device in which a pixel switch having a function of electrically separating an on pixel and an off pixel and holding a video signal to the on pixel is provided in each pixel has crosstalk between adjacent pixels. Therefore, it is used for various displays including portable information devices.

  As such a flat-type active matrix display device, an organic EL display device using a self-luminous element has attracted attention, and research and development have been actively conducted. The organic EL display device does not require a backlight that obstructs the reduction in thickness and weight, is suitable for moving image reproduction because of high-speed response, and further has a feature that it can be used even in a cold region because the luminance does not decrease at low temperatures.

  In general, an organic EL display device includes a plurality of display pixels arranged in a plurality of rows and a plurality of columns and constituting a display screen, a plurality of scanning lines extending along each row of display pixels, and a column of display pixels. A plurality of extended video signal lines, a scanning line driving circuit for driving each scanning line, a signal line driving circuit for driving each video signal line, and the like are provided. Each display pixel includes an organic EL element that is a self-light emitting element and a pixel circuit that supplies a drive current to the organic EL element, and performs a display operation by controlling the light emission luminance of the organic EL element. Each pixel circuit is connected in series between the organic EL element and the power supply line, and is provided between an output switch for controlling on / off of a current flowing through the organic EL element, and between the output switch and the power supply line, and flows through the organic EL element. A driving transistor that controls the amount of current based on the video signal, a first holding capacitor that holds the gate control potential of the driving transistor, a second holding capacitor that changes the gate potential of the driving transistor according to the video signal, and the like are provided. .

As a driving method of the pixel circuit, a method using a voltage signal (for example, Patent Documents 1 and 2) is known.
US Pat. No. 6,229,506 B1 JP 2005-31630 A

  In the display device disclosed in Patent Document 1, there is a problem in that local display unevenness occurs due to variation in the two capacitance ratios in the pixel circuit. There is also a problem that the required signal amplitude of the voltage driver IC increases and the manufacturing cost increases.

  Since the display device disclosed in Patent Document 2 is a driving method in which the cancel period is set to one horizontal period or less, there is a problem in that variations in transistor characteristics cannot be compensated for and display unevenness occurs.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide an active matrix display device capable of suppressing display unevenness due to capacitance variation and transistor characteristic variation and performing good image display. There is to do.

To achieve the above object, an active matrix display device according to an aspect of the present invention includes a display element and a plurality of pixel circuits arranged in a matrix on a substrate, the pixel circuit supplying a driving current to the display element. A pixel unit, a plurality of video signal lines connected to each column of the pixel unit, a first voltage supply unit that outputs a video voltage signal of a plurality of gradations to the video signal line, and a reset that outputs a reset voltage signal And a signal line driver circuit having an initialization power source for outputting an initialization reset voltage signal,
Each of the pixel circuits is formed by a transistor having a first terminal connected to a high potential voltage power source and a second terminal connected to the display element, and the first terminal connected to a second terminal of the drive transistor. An output switch having a second terminal connected to the display element; a first switch that is formed by a transistor and controls connection and disconnection between a control terminal and a second terminal of the drive transistor; and the drive A first storage capacitor connected between the first terminal of the transistor and the first terminal of the first switch; and a first storage capacitor connected between the control terminal of the driving transistor and the first terminal of the first switch. 2 formed of a storage capacitor and a transistor, the first terminal is connected to the initialization power source, the second terminal is connected to the control terminal of the drive transistor, and the control terminal is An initialization switch that is connected to the scanning line for controlling Le time,
A reset switch formed by a transistor, having a first terminal connected to the reset power supply, a second terminal connected to a first terminal of the first switch, and a control terminal connected to a scan line for reset time control; A pixel switch formed by a transistor, connected between the video signal line and the second terminal of the reset switch, and taking in a video voltage signal from the video signal line.

  According to the above configuration, it is possible to provide an active matrix display device capable of suppressing display unevenness due to variations in capacitance and transistor characteristics and performing high-quality image display.

Hereinafter, an organic EL display device according to a first embodiment of the present invention will be described in detail with reference to the drawings.
FIG. 1 is a plan view schematically showing an organic EL display device. As shown in FIG. 1, the organic EL display device is configured as, for example, an active matrix display device of two or more types, and includes an organic EL panel 10 and a controller 12 that controls the operation of the organic EL panel 10.

  The organic EL panel 10 includes a light-transmitting insulating substrate 8 such as a glass plate, m × n display pixels PX arranged in a matrix on the insulating substrate and constituting a display region 11, and each display pixel row. The first scanning lines (reset time control gate wirings) Sga (1 to m), the second scanning lines (cancellation time control gate wirings) Sgb (1 to 1), which are connected and provided independently by m, respectively. m), the third scanning line (signal writing control gate wiring) Sgc (1 to m), the fourth scanning line (EL light emission controlling gate wiring) Sgd (1 to m), and connected to each column of the display pixels PX. N video signal lines X (1 to n), n first signal lines Y (1 to n) and n second signal lines Z (1 to n) connected to each column of the display pixels PX. ).

  The organic EL panel 10 displays the first, second, third, and fourth scanning lines Sga (1 to m), Sgb (1 to m) Sgc (1 to m), and Sgd (1 to m) as display pixels. Signals for driving the scanning line driving circuits 14a and 14b, the plurality of video signal lines X, the plurality of first signal lines Y (1 to n), and the second signal lines Z (1 to n) that are sequentially driven for each row of PX. A line drive circuit 15 is provided. The scanning line driving circuits 14 a and 14 b and the signal line driving circuit 15 are integrally formed on the insulating substrate 8 outside the display area 11 and constitute a control unit together with the controller 12.

  Each display pixel PX that functions as a pixel portion includes a display element having a photoactive layer between opposing electrodes, and a pixel circuit 18 that supplies a drive current to the display element. The display element is, for example, a self-luminous element. In this embodiment, the organic EL element 16 including at least an organic light-emitting layer is used as a photoactive layer.

  FIG. 2 shows an equivalent circuit of the display pixel PX. The pixel circuit 18 is a voltage signal type pixel circuit that controls light emission of the organic EL element 16 in accordance with a video signal composed of a voltage signal. The pixel circuit 18 includes a pixel switch SST, a drive transistor DRT, a first switch TCT, and a first capacitor. A holding capacitor C1 and a second holding capacitor C2, an output switch BCT, an initialization switch IST, and a reference reset switch RST are provided.

  Here, the pixel switch SST, the drive transistor DRT, the first switch TCT, the output switch BCT, the initialization switch IST, and the reference reset switch RST are composed of thin film transistors of the same conductivity type, for example, a P-channel type. In the present embodiment, the thin film transistors each constituting each drive transistor and each switch are formed in the same process and the same layer structure, and are top gate thin film transistors using polysilicon as the semiconductor layer.

  Each of the pixel switch SST, the drive transistor DRT, the first switch TCT, the output switch BCT, the initialization switch IST, and the reference reset switch RST has a first terminal, a second terminal, and a control terminal. The first terminal, the second terminal, and the control terminal are a source, a drain, and a gate, respectively.

  In the pixel circuit 18, the driving transistor DRT and the output switch BCT are connected in series with the organic EL element 16 between the high potential voltage power supply line Vdd and the low potential reference voltage power supply line Vss, and a current corresponding to the video signal. An amount of driving current is output to the organic EL element. Here, the source of the drive transistor DRT is connected to the voltage power supply line Vdd, and the drain is connected to the anode of the organic EL element 16. The voltage power supply line Vdd and the reference voltage power supply line Vss are set to, for example, potentials of + 5V and −3V, respectively. The voltage power supply line Vdd and the reference voltage power supply line Vss are connected to the signal line drive circuit 15 and supplied with the power supply voltage from the signal line drive circuit.

  The output switch BCT has a source connected to the drain of the drive transistor DRT, a drain connected to one electrode of the organic EL element 16, here an anode, and a gate connected to the fourth scanning line Sgd (1 to m). It is connected. The output switch BCT is ON (conductive state) and OFF (non-conductive state) controlled by the control signal BG (1 to m) from the fourth scanning line Sgd (1 to m), and the drive transistor DRT and the organic EL element 16 are controlled. Controls connection / disconnection.

  The source of the pixel switch SST is connected to the video signal line X (1 to n), and the drain is connected to the gate of the drive transistor DRT via the second storage capacitor C2. The gate of the pixel switch SST is connected to the third scanning line SGc (1 to m) and is on / off controlled by a control signal SG (1 to m) supplied from the third scanning line Sgc (1 to m). . The pixel switch SST controls connection / disconnection between the pixel circuit 18 and the video signal lines X (1-n) in response to the control signal SG (1-m), and the corresponding video signal line X ( 1 to n), the gradation video voltage signal is taken into the pixel circuit 18.

  The first switch TCT is connected between the drain of the driving transistor DRT and the drain of the pixel switch SST, and the gate thereof is connected to the second scanning line Sgb (1 to m). The first switch TCT is turned on (conductive state) and turned off (non-conductive state) in response to the control signal TG (1 to m) from the second scanning line Sgb (1 to m), and the drain and pixel of the drive transistor DRT. Controls connection / disconnection between the drains of the switch SST. Further, the first switch TCT regulates current leakage from the first holding capacitor C1 and the second holding capacitor C2.

  The first holding capacitor C1 has two electrodes, is connected between the voltage power supply line Vdd and the source of the first switch TCT, and holds the gate control potential of the driving transistor determined by the video signal.

  The second storage capacitor C2 has two electrodes, is connected between the gate of the drive transistor DRT and the source of the first switch TCT, and changes the gate potential of the drive transistor DRT according to the video signal. That is, the video signal is transmitted to the gate potential of the drive transistor DRT via the second storage capacitor C2 according to the law of charge conservation. The second holding capacitor C2 holds the gate control potential of the driving transistor DRT determined by the video signal together with the first holding capacitor C1.

  The initialization switch IST functioning as a first reset switch has its source connected to the first signal line Y (1-n) and its drain connected between the gate of the drive transistor DRT and the second storage capacitor C2. Yes. The gate of the initialization switch IST is connected to a second scanning line Sgb (1 to m) that functions as a scanning line for cancel time control. The initialization switch IST is turned on (conductive state) and turned off (non-conductive state) in response to the control signal TG (1-m) from the second scanning line Sgb (1-m), and the corresponding first signal line Y The initialization reset voltage signal VINI supplied from (1 to n) is supplied to the pixel circuit 18, and the gate potential of the drive transistor DRT is set to the VINI potential every vertical period. In other words, the initialization switch IST is turned on and off in response to the control signal control signal TG (1 to m) from the second scanning line Sgb (1 to m), and the information of the previous frame of the gate potential of the driving transistor DRT is displayed. initialize.

  The reference reset switch RST functioning as the second reset switch has its source connected to the second signal line Z (1-n) and its drain connected between the drain of the pixel switch SST and the source of the first switch TCT. Further, the gate is connected to a first scanning line Sga (1 to m) that functions as a scanning line for reset time control. The reference reset switch RST is turned on (conductive state) and turned off (non-conductive state) in response to the control signal RG (1 to m) from the first inspection line Sga (1 to m), and the corresponding second signal line Z The reset voltage signal VRESET supplied from (1 to n) is supplied to the pixel circuit 18, and the potential of one electrode of the second storage capacitor C2, here the electrode opposite to the driving transistor DRT, is set to a constant value (VRET). ). That is, the reference reset switch RST is turned on / off according to the control signal RG from the first scanning line Sga1, and initializes the previous frame information of the drain potential of the pixel switch SST.

  On the other hand, the controller 12 shown in FIG. 1 is formed on a printed circuit board disposed outside the organic EL panel 10 and controls the scanning line driving circuits 14 a and 14 b and the signal line driving circuit 15. The controller 12 receives a digital video signal and a synchronization signal supplied from the outside, and generates a vertical scanning control signal for controlling the vertical scanning timing and a horizontal scanning control signal for controlling the horizontal scanning timing based on the synchronizing signal. The controller 12 supplies the vertical scanning control signal and the horizontal scanning control signal to the scanning line driving circuits 14a and 14b and the signal line driving circuit 15, respectively, and outputs a digital video signal in synchronization with the horizontal and vertical scanning timings. This is supplied to the line drive circuit 15.

  The scanning line driving circuits 14a and 14b include a shift register, an output buffer, and the like, and sequentially transfer a horizontal scanning start pulse supplied from the outside to the next stage, as shown in FIGS. 1 and 2, via the output buffer. Four types of control signals, that is, control signals RG (1 to m), TG (1 to m), SG (1 to m), and BG (1 to m) are supplied to the display pixels PX in each row. Thereby, each 1st, 2nd, 3rd, 4th scanning line Sga (1-m), Sgb (1-m), Sgc (1-m), and Sgd (1-m) are mutually different 1 horizontal. In the scanning period, they are driven by control signals RG (1 to m), TG (1 to m), SG (1 to m), and BG (1 to m), respectively.

  The signal line driving circuit 15 converts the video signals sequentially obtained in each horizontal scanning period into the analog format under the control of the horizontal scanning control signal into a voltage signal and supplies it in parallel to the plurality of video signal lines X (1 to n). To do. The signal line drive circuit 15 includes a first voltage supply unit 20 connected to each video signal line X (1 to n). The first voltage supply unit 20 functioning as a voltage source outputs a plurality of gradation voltage signals Vsig corresponding to the image signal to the image signal lines X (1 to n).

  As shown in FIGS. 1 and 2, the signal line drive circuit 15 includes a second voltage supply unit (initialization power supply) 22 that supplies an initialization reset voltage signal VINI, a reset voltage signal for each column of the display pixels PX. A third voltage supply unit (reset power supply) 23 for supplying VRET is provided. The second voltage supply unit 22 is connected to the first signal line Y (1 to n) and supplies the initialization reset voltage signal VINI to the pixel circuit 18 via the initialization reset switch IST. The third voltage supply unit 23 is connected to the second signal line Z (1 to n) and supplies the reset voltage signal VRET to the pixel circuit 18 through the reference reset switch RST.

Next, the operation of the organic EL display device configured as described above will be described. FIG. 4 shows a timing chart of the control signals of the scanning line drive circuits 14a and 14b during the operation display during the display operation.
For example, the scanning line driving circuits 14a and 14b generate a pulse having a width of one horizontal scanning period (Tw-Starta) corresponding to each horizontal scanning period H from the start signals (STV1 to 5) and the clocks (CKV1 to 5). The pulses are output as control signals Sa, Sb, Sc, Sd, and BG.

The operation of the pixel circuit 18 is divided into 1) a reset operation, 2) a cancel operation, 3) a write operation, and 4) a light emission operation.
As shown in FIGS. 3 and 4, first, a reset operation is performed. In the reset operation, the scanning line drive circuits 14a and 14b output to the display pixel PX a level (off potential) for turning off the output switch BCT and the pixel switch SST, in this case, high level control signals BG and SG. The At the same time or subsequently, the scanning line driving circuits 14a and 14b are at a level (on potential) for turning on the initialization switch IST, the first switch TCT, and the reference reset switch RST, respectively, in this case, the low level control signal RG, TG is output. As a result, the output switch BCT and the pixel switch SST are turned off (non-conductive state), the initialization switch IST, the first switch TCT, and the reference reset switch RST are turned on (conductive state), and the reset operation is started.

  In the reset period, the initialization reset voltage signal VINI output from the second voltage supply unit 22 is applied to the gate of the driving transistor DRT through the first signal line Y and the initialization switch IST. As a result, the gate potential of the drive transistor DRT is reset to a potential corresponding to the initialization reset voltage signal VINI, and the information of the previous frame is initialized. In addition, the reference reset voltage signal VRST output from the third voltage supply unit 23 is applied to the input-side electrode (electrode opposite to the driving transistor) of the second holding capacitor C2 through the second signal line Z and the reference reset switch RST. Applied. As a result, the electrode potential on the input side of the second holding capacitor C2 is reset to a potential corresponding to the reference reset voltage signal VRST, and the information of the previous frame is initialized.

  Subsequently, as shown in FIGS. 3 and 5, the control signal RG is turned off (high level), and the reference reset switch RST is turned off. The control signal TG is maintained at an on potential, and the control signals SG and BG are each maintained at an off potential. As a result, the pixel switch SST, the output switch BCT, and the reference reset switch RST are turned off, the first switch TCT and the initialization switch IST are turned on, and the threshold value offset cancel operation is started.

In the cancel period, the gate potential of the drive transistor DRT is fixed to VINI. The first switch TCT is in an on state, and the gate and drain of the drive transistor DRT are short-circuited. By maintaining this state, the drain potential of the pixel switch SST and the electrode potential on the opposite side of the driving transistor DRT of the second storage capacitor C2 have the initial values corresponding to the reference reset voltage signal VRST written during the reset period. Then, the current flowing into the voltage power supply line Vdd through the source-drain of the driving transistor DRT is gradually decreased, and the TFT characteristic variation of the driving transistor is absorbed and compensated, and shifted to the high potential side. The drain potential of the pixel switch SST at the end of the cancellation is VINI−Vth (the threshold voltage of the driving transistor). As a result, the gate-source voltage of the drive transistor DRT reaches the cancel point. In addition, a potential difference corresponding to a cancellation point is stored in the first and second holding capacitors C1 and C2.
Note that VINI is set so as to satisfy the relationship of VINI−Vth> Vdd.

  Thereafter, as shown in FIGS. 3 and 6, in the signal writing operation, the control signal SG of the display pixel PX is an on-potential that turns on the pixel switch SST, and the control signal TG is the first switch TCT and the initialization reset switch. The IST is turned off, the control signal RG is turned off, the reference reset switch RST is turned off, and the control signal BG is turned off, the output switch BCT being turned off. Accordingly, the initialization reset switch IST, the reference reset switch RST, the output switch BCT, and the first switch TCT are turned off (non-conducting state), the pixel switch SST is turned on (conducting state), and the signal writing operation is started.

  In the video voltage signal writing period, the gradation video voltage signal Vsig is output from the first voltage supply unit 20 of the signal line driving circuit 15 to the video signal line X, and the signal potential Vsig is supplied to the pixel circuit 18 via the pixel switch SST. Written. That is, the drain of the pixel switch SST becomes the Vsig potential.

   By writing the video voltage signal Vsig, the electrode potential on the pixel switch SST side of the second storage capacitor C2 is shifted from the potential (VINI−Vth) after the cancel operation to the video voltage signal Vsig. Along with this potential change, the gate potential of the drive transistor DRT becomes Vsig + Vth according to the law of charge conservation. At this time, if Vgs of the driving transistor DRT necessary for achieving the white-black gradation is Vgs0, the Vsig amplitude necessary for achieving the white-black gradation is equal to Vgs0. As a result, the Vsig amplitude of the driver IC in the signal line drive circuit can be made smaller than before, leading to cost reduction.

  Next, as shown in FIGS. 3 and 7, the control signal SG is turned off (high level), and the pixel switch SST is turned off. Thereby, the gradation video voltage signal writing operation is completed. At the same time or subsequently, the control signal BG becomes a level (on potential) that turns on the output switch BCT. Thereby, the switches IST, RST, SST, and TCT are turned off (non-conducting state), only the output switch BCT is turned on (conducting state), and the light emission operation is started.

In the light emission period, the drive transistor DRT outputs a drive current Ie having a corresponding amount of current by the gate control voltage written in the second storage capacitor C2. This drive current Ie is supplied to the organic EL element 16 through the output switch BCT. Thereby, the organic EL element 16 emits light with a luminance corresponding to the drive current Ie, and performs a light emission operation. The organic EL element 16 maintains the light emitting state until the control signal BG becomes the off potential again after one frame period.
The above-described reset operation, cancel operation, video voltage signal writing operation, and light emission operation are sequentially performed on each display pixel to display a desired image.

According to the organic EL display device configured as described above, during the light emission period, the current Ie flowing through the organic EL element 16 is the current value in the saturation region of the drive transistor DRT.
Ie = βx (Vsig−Vdd) ² (β = μCoxW / 2L),
The value does not depend on the threshold value Vth of the transistor or the capacitance ratio of the storage capacitors C1 and C2. Therefore, it is not affected by variations in the threshold ratio and the capacity ratio of the storage capacitors, and it is possible to suppress the occurrence of display defects, unevenness, and rough feeling due to these variations, and to perform high-quality image display.

  Further, the change in the voltage video signal Vsig can be made equal to the change in the gate potential of the drive transistor, and the Vsig amplitude of the driver IC in the signal line drive circuit can be reduced. As a result, the cost of the driver IC can be reduced and the manufacturing cost can be reduced.

Next, an organic EL display device according to the second embodiment will be described. Note that in the second embodiment, the same components as those in the first embodiment described above are denoted by the same reference numerals, description thereof is omitted, and different components are described in detail.
FIG. 8 shows a part of an equivalent circuit of a display pixel and a signal line driving circuit in the organic EL display device according to the second embodiment.

  As shown in FIG. 8, according to the second embodiment, the second voltage supply unit in the signal line drive circuit 15 is omitted, and the voltage power supply line Vdd is used as a power supply for supplying the initialization reset voltage signal VINI. . The source of the initialization switch IST that functions as the first reset switch is connected to the voltage power supply line Vdd between the source of the drive transistor DRT and the first storage capacitor C1. Other configurations of the pixel circuit 18 are the same as those of the first embodiment described above.

An operation during normal display of the organic EL display device will be described. FIG. 9 shows a timing chart of the control signal of the scanning line driving circuit at the time of operation display during display operation. The operation of the pixel circuit 18 is divided into 1) a reset operation, 2) a cancel operation, 3) a write operation, and 4) a light emission operation.
As shown in FIGS. 9 and 10, first, a reset operation is performed. In the reset operation, a level (off potential) for turning off the output switch BCT and the pixel switch SST, that is, high-level control signals BG and SG are output from the scanning line driving circuit to the display pixel PX. At the same time or subsequently, the scanning line drive circuit outputs a level (on potential) for turning on the initialization switch IST, the first switch TCT, and the reference reset switch RST, in this case, low level control signals RG and TG. Is done. As a result, the output switch BCT and the pixel switch SST are turned off (non-conductive state), the initialization switch IST, the first switch TCT, and the reference reset switch RST are turned on (conductive state), and the reset operation is started.

  In the reset period, the power supply voltage Vdd is applied from the voltage power supply line Vdd as an initialization reset voltage signal to the gate of the drive transistor DRT through the initialization switch IST. As a result, the gate potential of the drive transistor DRT is reset to a potential corresponding to the initialization reset voltage signal Vdd, and information of the previous frame is initialized. In addition, the reference reset voltage signal VRST output from the third voltage supply unit 23 is applied to the input-side electrode (electrode opposite to the driving transistor) of the second holding capacitor C2 through the second signal line Z and the reference reset switch RST. Applied. As a result, the electrode potential on the input side of the second holding capacitor C2 is reset to a potential corresponding to the reference reset voltage signal VRST, and the information of the previous frame is initialized.

  Subsequently, as shown in FIGS. 9 and 11, the control signal RG is turned off (high level), and the reference reset switch RST is turned off. The control signal TG is maintained at an on potential, and the control signals SG and BG are each maintained at an off potential. As a result, the pixel switch SST, the output switch BCT, and the reference reset switch RST are turned off, the first switch TCT and the initialization switch IST are turned on, and the threshold value offset cancel operation is started.

In the cancel period, the gate potential of the drive transistor DRT is fixed at Vdd. The first switch TCT is in an on state, and the gate and drain of the drive transistor DRT are short-circuited. By maintaining this state, the drain potential of the pixel switch SST and the electrode potential on the opposite side of the driving transistor DRT of the second storage capacitor C2 have the initial values corresponding to the reference reset voltage signal VRST written during the reset period. Then, the current flowing into the voltage power supply line Vdd through the source-drain of the driving transistor DRT is gradually decreased, and the TFT characteristic variation of the driving transistor is absorbed and compensated, and shifted to the high potential side. The drain potential of the pixel switch SST at the end of the cancellation is Vdd−Vth (threshold voltage of the driving transistor). As a result, the gate-source voltage of the drive transistor DRT reaches the cancel point. In addition, a potential difference corresponding to a cancellation point is stored in the first and second holding capacitors C1 and C2.
Thereafter, as shown in FIG. 9 and FIG. 12, in the signal writing operation, the control signal SG of the display pixel PX is an on potential for turning on the pixel switch SST, and the control signal TG is the first switch TCT and the initialization reset switch. The IST is turned off, the control signal RG is turned off, the reference reset switch RST is turned off, and the control signal BG is turned off, the output switch BCT being turned off. Accordingly, the initialization reset switch IST, the reference reset switch RST, the output switch BCT, and the first switch TCT are turned off (non-conducting state), the pixel switch SST is turned on (conducting state), and the signal writing operation is started.

  In the video voltage signal writing period, the grayscale video voltage signal Vsig is output from the first voltage supply unit 20 of the signal line driver circuit to the video signal line X, and the signal potential Vsig is written to the pixel circuit 18 via the pixel switch SST. It is. That is, the drain of the pixel switch SST becomes the Vsig potential.

  By writing the video voltage signal Vsig, the electrode potential on the pixel switch SST side of the second storage capacitor C2 is shifted from the potential (Vdd−Vth) after the cancel operation to the video voltage signal Vsig. Along with this potential change, the gate potential of the drive transistor DRT becomes Vsig + Vth according to the law of charge conservation. At this time, if Vgs of the driving transistor DRT necessary for achieving the white-black gradation is Vgs0, the Vsig amplitude necessary for achieving the white-black gradation is equal to Vgs0. As a result, the Vsig amplitude of the driver IC in the signal line drive circuit can be made smaller than before, leading to cost reduction.

  Next, as shown in FIGS. 9 and 13, the control signal SG is turned off (high level), and the pixel switch SST is turned off. Thereby, the gradation video voltage signal writing operation is completed. At the same time or subsequently, the control signal BG becomes a level (on potential) that turns on the output switch BCT. Thereby, the switches IST, RST, SST, and TCT are turned off (non-conducting state), only the output switch BCT is turned on (conducting state), and the light emission operation is started.

In the light emission period, the drive transistor DRT outputs a drive current Ie having a corresponding amount of current by the gate control voltage written in the second storage capacitor C2. This drive current Ie is supplied to the organic EL element 16 through the output switch BCT. Thereby, the organic EL element 16 emits light with a luminance corresponding to the drive current Ie, and performs a light emission operation. The organic EL element 16 maintains the light emitting state until the control signal BG becomes the off potential again after one frame period.
The above-described reset operation, cancel operation, video voltage signal writing operation, and light emission operation are sequentially performed on each display pixel to display a desired image.

Also in the organic EL display device configured as described above, the current Ie flowing through the organic EL element 16 during the light emission period is the current value in the saturation region of the drive transistor DRT.
Ie = βx (Vsig−Vdd) ² (β = μCoxW / 2L),
The value does not depend on the threshold value Vth of the transistor or the capacitance ratio of the storage capacitors C1 and C2. Therefore, it is not affected by variations in the threshold ratio and the capacity ratio of the storage capacitors, and it is possible to suppress the occurrence of display defects, unevenness, and rough feeling due to these variations, and to perform high-quality image display.

  Further, the change in the voltage video signal Vsig can be made equal to the change in the gate potential of the drive transistor, and the Vsig amplitude of the driver IC in the signal line drive circuit can be reduced. As a result, the cost of the driver IC can be reduced and the manufacturing cost can be reduced. Furthermore, according to the second embodiment, an independent power source for initialization reset can be omitted, and the manufacturing cost can be reduced.

Next, an organic EL display device according to a third embodiment will be described. Note that in the third embodiment, the same components as those in the first and second embodiments described above are denoted by the same reference numerals, description thereof is omitted, and different components will be described in detail.
FIG. 14 shows an equivalent circuit of a display pixel and a part of a signal line driving circuit in the organic EL display device according to the third embodiment.

  As shown in FIG. 14, according to the third embodiment, the second voltage supply unit in the signal line drive circuit 15 is omitted, and the voltage power supply line Vdd is used as a power supply for supplying the initialization reset voltage signal VINI. . The source of the initialization switch IST that functions as the first reset switch is connected to the voltage power supply line Vdd between the source of the drive transistor DRT and the first storage capacitor C1.

Further, the pixel circuit 18 includes a third storage capacitor C3. The third storage capacitor C3 has two electrodes and is connected between the first scanning line Sga1 and the drain of the pixel switch SST. The third storage capacitor C3 uses the reset signal potential VRST at the end of the reset period as the drain potential of the pixel switch SST in the early cancellation period,
(VGH−VGL) Plays a role of changing only XC3 / (C1 + C2 + C3). Here, VGH indicates the high level potential of the control signal RG, and VGL indicates the low level potential of the control signal RG.
Other configurations of the pixel circuit 18 are the same as those of the first embodiment described above.

An operation during normal display of the organic EL display device will be described. FIG. 15 shows a timing chart of the control signal of the scanning line driving circuit at the time of operation display during display operation. The operation of the pixel circuit 18 is divided into 1) a reset operation, 2) a cancel operation, 3) a write operation, and 4) a light emission operation.
As shown in FIGS. 15 and 16, first, a reset operation is performed. In the reset operation, a level (off potential) for turning off the output switch BCT and the pixel switch SST, that is, high-level control signals BG and SG are output from the scanning line driving circuit to the display pixel PX. At the same time or subsequently, the scanning line drive circuit outputs a level (on potential) for turning on the initialization switch IST, the first switch TCT, and the reference reset switch RST, in this case, low level control signals RG and TG. Is done. As a result, the output switch BCT and the pixel switch SST are turned off (non-conductive state), the initialization switch IST, the first switch TCT, and the reference reset switch RST are turned on (conductive state), and the reset operation is started.

  In the reset period, the power supply voltage Vdd is applied from the voltage power supply line Vdd as an initialization reset voltage signal to the gate of the drive transistor DRT through the initialization switch IST. As a result, the gate potential of the drive transistor DRT is reset to a potential corresponding to the initialization reset voltage signal Vdd, and information of the previous frame is initialized. In addition, the reference reset voltage signal VRST output from the third voltage supply unit 23 is applied to the input-side electrode (electrode opposite to the driving transistor) of the second holding capacitor C2 through the second signal line Z and the reference reset switch RST. Applied. As a result, the electrode potential on the input side of the second holding capacitor C2 is reset to a potential corresponding to the reference reset voltage signal VRST, and the information of the previous frame is initialized.

At this time, since the third holding capacitor C3 is provided, the potential on the input side of the second holding capacitor C2 at the end of the reset period is from the reset signal potential VRST.
It goes up by (VGH-VGL) XC3 / (C1 + C2 + C3).

  Subsequently, as shown in FIGS. 15 and 17, the control signal RG is turned off (high level), and the reference reset switch RST is turned off. The control signal TG is maintained at an on potential, and the control signals SG and BG are each maintained at an off potential. As a result, the pixel switch SST, the output switch BCT, and the reference reset switch RST are turned off, the first switch TCT and the initialization switch IST are turned on, and the threshold value offset cancel operation is started.

In the cancel period, the gate potential of the drive transistor DRT is fixed at Vdd. The first switch TCT is in an on state, and the gate and drain of the drive transistor DRT are short-circuited. By maintaining this state, the drain potential of the pixel switch SST and the electrode potential on the opposite side of the driving transistor DRT of the second storage capacitor C2 are set to the potential corresponding to the reference reset voltage signal VRST written in the reset period. The driving transistor gradually decreases the amount of current flowing from the initial potential obtained by adding the push-up potential (VGH−VGL) XC3 / (C1 + C2 + C3) of the storage capacitor C3 to the voltage power supply line Vdd through the source-drain of the driving transistor DRT. The TFT characteristics are shifted to the high potential side while absorbing and compensating for the TFT characteristic variation. The drain potential of the pixel switch SST at the end of the cancellation is Vdd−Vth (threshold voltage of the driving transistor). As a result, the gate-source voltage of the drive transistor DRT reaches the cancel point. In addition, a potential difference corresponding to a cancellation point is stored in the first and second holding capacitors C1 and C2.
Thereafter, as shown in FIG. 15 and FIG. 18, in the signal writing operation, the control signal SG of the display pixel PX is an ON potential for turning on the pixel switch SST, and the control signal TG is the first switch TCT and the initialization reset switch. The IST is turned off, the control signal RG is turned off, the reference reset switch RST is turned off, and the control signal BG is turned off, the output switch BCT being turned off. Accordingly, the initialization reset switch IST, the reference reset switch RST, the output switch BCT, and the first switch TCT are turned off (non-conducting state), the pixel switch SST is turned on (conducting state), and the signal writing operation is started.

  In the video voltage signal writing period, the grayscale video voltage signal Vsig is output from the first voltage supply unit 20 of the signal line driver circuit to the video signal line X, and the signal potential Vsig is written to the pixel circuit 18 via the pixel switch SST. It is. That is, the drain of the pixel switch SST becomes the Vsig potential.

  By writing the video voltage signal Vsig, the electrode potential on the pixel switch SST side of the second storage capacitor C2 is shifted from the potential (Vdd−Vth) after the cancel operation to the video voltage signal Vsig. Along with this potential change, the gate potential of the drive transistor DRT becomes Vsig + Vth according to the law of charge conservation. At this time, if Vgs of the driving transistor DRT necessary for achieving the white-black gradation is Vgs0, the Vsig amplitude necessary for achieving the white-black gradation is equal to Vgs0. As a result, the Vsig amplitude of the driver IC in the signal line drive circuit can be made smaller than before, leading to cost reduction.

  Next, as shown in FIGS. 15 and 19, the control signal SG is turned off (high level), and the pixel switch SST is turned off. Thereby, the gradation video voltage signal writing operation is completed. At the same time or subsequently, the control signal BG becomes a level (on potential) that turns on the output switch BCT. Thereby, the switches IST, RST, SST, and TCT are turned off (non-conducting state), only the output switch BCT is turned on (conducting state), and the light emission operation is started.

In the light emission period, the drive transistor DRT outputs a drive current Ie having a corresponding amount of current by the gate control voltage written in the second storage capacitor C2. This drive current Ie is supplied to the organic EL element 16 through the output switch BCT. Thereby, the organic EL element 16 emits light with a luminance corresponding to the drive current Ie, and performs a light emission operation. The organic EL element 16 maintains the light emitting state until the control signal BG becomes the off potential again after one frame period.
The above-described reset operation, cancel operation, video voltage signal writing operation, and light emission operation are sequentially performed on each display pixel to display a desired image.

Also in the organic EL display device configured as described above, the current Ie flowing through the organic EL element 16 during the light emission period is the current value in the saturation region of the drive transistor DRT.
Ie = βx (Vsig−Vdd) ² (β = μCoxW / 2L),
The value does not depend on the threshold value Vth of the transistor or the capacitance ratio of the storage capacitors C1 and C2. Therefore, it is not affected by variations in the threshold ratio and the capacity ratio of the storage capacitors, and it is possible to suppress the occurrence of display defects, unevenness, and rough feeling due to these variations, and to perform high-quality image display.

  Further, the change in the voltage video signal Vsig can be made equal to the change in the gate potential of the drive transistor, and the Vsig amplitude of the driver IC in the signal line drive circuit can be reduced. As a result, the cost of the driver IC can be reduced and the manufacturing cost can be reduced. Furthermore, according to the third embodiment, by providing the third holding capacitor, the reset potential at the start of the cancel operation can be increased by the pushing potential of the holding capacitor, and the reset voltage power supply can be reduced in size. it can.

  In the first to third embodiments described above, the pixel switch SST, the first switch TCT, the output switch BCT, the initialization switch IST, and the reference reset switch RST that constitute the pixel circuit are only required to be able to be turned on and off. Not only the channel type but also an N channel type transistor may be used. Similarly, the drive transistor DRT is not limited to the P-channel type, and an N-channel type transistor can also be used.

  FIG. 20 shows a part of an equivalent circuit of a display pixel and a signal line driving circuit in the organic EL display device according to the fourth embodiment, and FIG. 21 is a timing chart showing a potential change of a control signal in the organic EL display device. It is.

  As shown in FIG. 20, according to the fourth embodiment, the pixel circuit 18 has the same circuit configuration as the pixel circuit of the organic EL display device according to the first embodiment described above, and includes a pixel switch SST, The one switch TCT, the initialization switch IST, and the reference reset switch RST are formed by N-channel transistors. As shown in FIG. 21, the potential change of the control signal for controlling on / off of the pixel switch SST, the first switch TCT, the initialization switch IST, and the reference reset switch RST is the same as in the first embodiment. Low is set in reverse.

  FIG. 20 shows a part of an equivalent circuit of a display pixel and a signal line driving circuit in the organic EL display device according to the fourth embodiment, and FIG. 21 is a timing chart showing a potential change of a control signal in the organic EL display device. It is.

FIG. 22 shows an equivalent circuit of a display pixel and a part of a signal line driving circuit in the organic EL display device according to the fifth embodiment.
As shown in FIG. 22, according to the fifth embodiment, the pixel circuit 18 has the same circuit configuration as the pixel circuit of the organic EL display device in the second embodiment described above, and includes the pixel switch SST, The one switch TCT, the initialization switch IST, and the reference reset switch RST are formed by N-channel transistors. The potential change of the control signal for controlling on / off of the pixel switch SST, the first switch TCT, the initialization switch IST, and the reference reset switch RST is the same as that in the fourth embodiment shown in FIG.

FIG. 23 shows a part of an equivalent circuit of a display pixel and a signal line driving circuit in the organic EL display device according to the sixth embodiment.
As shown in FIG. 23, according to the sixth embodiment, the pixel circuit 18 has the same circuit configuration as the pixel circuit of the organic EL display device in the third embodiment described above, and includes the pixel switch SST, The one switch TCT, the initialization switch IST, and the reference reset switch RST are formed by N-channel transistors. The potential change of the control signal for controlling on / off of the pixel switch SST, the first switch TCT, the initialization switch IST, and the reference reset switch RST is the same as that in the fourth embodiment shown in FIG.
In the fourth, fifth, and sixth embodiments, the other configurations of the organic EL display device are the same as those of the first, second, and third embodiments described above, and a detailed description thereof is omitted. In the fourth, fifth, and sixth embodiments, the same operational effects as those of the first, second, and third embodiments described above can be obtained.

  Note that the present invention is not limited to the above-described embodiment as it is, and can be embodied by modifying the constituent elements without departing from the scope of the invention in the implementation stage. In addition, various inventions can be formed by appropriately combining a plurality of components disclosed in the embodiment. For example, some components may be deleted from all the components shown in the embodiment. Furthermore, constituent elements over different embodiments may be appropriately combined.

  The semiconductor layer of the thin film transistor is not limited to polysilicon but can be composed of amorphous silicon. The shapes and dimensions of the transistors and switches are not limited to the above-described embodiments, and can be changed as necessary. The self-luminous elements constituting the display pixels are not limited to organic EL elements, and various display elements capable of self-luminance are applicable.

FIG. 1 is a plan view schematically showing an organic EL display device according to an embodiment of the present invention. FIG. 2 is a plan view showing an equivalent circuit of display pixels in the organic EL display device. FIG. 3 is a timing chart showing the potential change of the control signal in the organic EL display device. FIG. 4 is a plan view showing an equivalent circuit of the display pixel during the reset operation of the organic EL display device. FIG. 5 is a plan view showing an equivalent circuit of the display pixel during the cancel operation of the organic EL display device. FIG. 6 is a plan view showing an equivalent circuit of a display pixel at the time of writing a signal current in the organic EL display device. FIG. 7 is a plan view showing an equivalent circuit of the display pixel during the light emitting operation in the normal driving operation of the organic EL display device. FIG. 8 is a plan view showing an equivalent circuit of a display pixel in the organic EL display device according to the second embodiment. FIG. 9 is a timing chart showing changes in the potential of the control signal in the organic EL display device. FIG. 10 is a plan view showing an equivalent circuit of the display pixel during the reset operation of the organic EL display device. FIG. 11 is a plan view showing an equivalent circuit of a display pixel during a cancel operation of the organic EL display device. FIG. 12 is a plan view showing an equivalent circuit of a display pixel at the time of writing a signal current in the organic EL display device. FIG. 13 is a plan view showing an equivalent circuit of the display pixel during the light emission operation in the normal driving operation of the organic EL display device. FIG. 14 is a plan view showing an equivalent circuit of a display pixel in the organic EL display device according to the third embodiment. FIG. 15 is a timing chart showing changes in the potential of the control signal in the organic EL display device. FIG. 16 is a plan view showing an equivalent circuit of a display pixel during a reset operation of the organic EL display device. FIG. 17 is a plan view showing an equivalent circuit of the display pixel during the cancel operation of the organic EL display device. FIG. 18 is a plan view showing an equivalent circuit of a display pixel at the time of writing a signal current in the organic EL display device. FIG. 19 is a plan view showing an equivalent circuit of the display pixel during the light emission operation in the normal driving operation of the organic EL display device. FIG. 20 is a plan view showing an equivalent circuit of a display pixel in the organic EL display device according to the fourth embodiment. FIG. 21 is a timing chart showing potential changes of the control signal in the organic EL display device according to the fourth embodiment. FIG. 22 is a plan view showing an equivalent circuit of a display pixel in the organic EL display device according to the fifth embodiment. FIG. 23 is a plan view showing an equivalent circuit of a display pixel in the organic EL display device according to the sixth embodiment.

Explanation of symbols

8 ... Insulating substrate, 10 ... Organic EL panel, 11 ... Display area, 12 ... Controller,
14a, 14b ... scanning line drive circuit, 15 ... signal line drive circuit, 16 ... organic EL element,
18 ... pixel circuit, 20 ... first voltage supply unit, 22 ... second voltage supply unit,
23 ... Third voltage supply unit, SST ... Pixel switch, DRT ... Drive transistor,
TCT ... first switch, IST ... initialization reset switch,
RST ... reference reset switch, BCT ... output switch, X ... video signal line,
Y ... first signal line, Z ... second signal line

Claims (5)

A plurality of pixel portions including a display element and a pixel circuit for supplying a driving current to the display element, the pixel parts being arranged in a matrix on the substrate;
A plurality of video signal lines connected to each column of the pixel portion;
A first voltage supply unit that outputs a video voltage signal of a plurality of gradations to the video signal line, a reset power source that outputs a reset voltage signal, and a signal line drive circuit that has an initialization power source that outputs an initialization reset voltage signal; Comprising
Each of the pixel circuits is
A drive transistor having a first terminal connected to a high potential voltage power supply and a second terminal connected to the display element;
An output switch formed by a transistor, having a first terminal connected to a second terminal of the driving transistor and a second terminal connected to the display element;
A first switch formed by a transistor and controlling connection and disconnection between a control terminal and a second terminal of the drive transistor;
A first storage capacitor connected between a first terminal of the driving transistor and a first terminal of the first switch;
A second storage capacitor connected between a control terminal of the driving transistor and a first terminal of the first switch;
An initialization switch formed by a transistor, having a first terminal connected to the initialization power source, a second terminal connected to a control terminal of the driving transistor, and a control terminal connected to a scan line for cancel time control;
A reset switch formed by a transistor, having a first terminal connected to the reset power supply, a second terminal connected to a first terminal of the first switch, and a control terminal connected to a scan line for reset time control;
An active matrix display device comprising: a pixel switch formed by a transistor, connected between the video signal line and a second terminal of the reset switch, and for taking a video voltage signal from the video signal line.   A reset period in which the pixel circuit applies an initialization reset voltage to a control terminal of the drive transistor through the initialization switch, and applies a reset voltage to the first terminal of the first switch through the reset switch; A cancel period in which current flows from the second storage capacitor through the first switch and the drive transistor, a write period in which a video voltage signal captured through the pixel switch is written to a control terminal of the drive transistor, and the drive 4. The active matrix display device according to claim 2, further comprising: a light emission period in which a driving current is supplied from the transistor to the display element through the output switch. A plurality of pixel portions including a display element and a pixel circuit for supplying a driving current to the display element, the pixel parts being arranged in a matrix on the substrate;
A plurality of video signal lines connected to each column of the pixel portion;
A first voltage supply unit that outputs a video voltage signal of a plurality of gradations to the video signal line, and a signal line driving circuit having a reset power source that outputs a reset voltage signal,
Each of the pixel circuits is
A drive transistor having a first terminal connected to the high potential voltage power line and a second terminal connected to the display element;
An output switch formed by a transistor, having a first terminal connected to a second terminal of the driving transistor and a second terminal connected to the display element;
A first switch formed by a transistor and controlling connection and disconnection between a control terminal and a second terminal of the drive transistor;
A first storage capacitor connected between a first terminal of the driving transistor and a first terminal of the first switch;
A second storage capacitor connected between a control terminal of the driving transistor and a first terminal of the first switch;
Formed by a transistor, a first terminal is connected to the high-potential voltage power line, a second terminal is connected between the control terminal of the drive transistor and the second storage capacitor, and the control terminal is for cancel time control An initialization switch connected to the scan line;
A reset switch formed by a transistor, having a first terminal connected to the reset power supply, a second terminal connected to a first terminal of the first switch, and a control terminal connected to a scan line for reset time control;
An active matrix display device comprising: a pixel switch formed by a transistor, connected between the video signal line and a second terminal of the reset switch, and for taking a video voltage signal from the video signal line.   The pixel circuit includes a third storage capacitor having two electrodes, one electrode connected to the reset time control scanning line and the other electrode connected to a second terminal of the pixel switch. The active matrix display device according to claim 2.   A reset period in which the pixel circuit applies an initialization reset voltage to a control terminal of the drive transistor through the initialization switch, and applies a reset voltage to the first terminal of the first switch through the reset switch; A cancel period in which current flows from the second storage capacitor through the first switch and the drive transistor, a write period in which a video voltage signal captured through the pixel switch is written to a control terminal of the drive transistor, and the drive The active matrix display device according to claim 3, further comprising: a light emission period for supplying a driving current from a transistor to the display element through the output switch.

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