JP2009193027A - Active matrix type display apparatus and driving method therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an active matrix type display apparatus that can achieve a satisfactory display by minimizing a luminance increase on a low gradation display, and to provide a driving method therefor. <P>SOLUTION: The display apparatus includes: a plurality of pixel parts PX; a plurality of video signal lines X connected to the corresponding lines of pixel parts; and a signal line driving circuit that outputs a reference current and a gradation signal current to the video signal lines. Each of the pixel circuits 18 has: a driving transistor 20; a first holding capacity C1, which holds the potential of a control terminal of the driving transistor; a first switch 21 by which a reference current and gradation signal current supplied from the video signal line are caused to flow through the driving transistor; a second switch 22; a second holding capacity C2, which holds a potential according to a difference between the reference current and gradation signal current; a third switch 23; a fourth switch 24 that controls connection and disconnection between the second terminal and control terminal of the driving transistor; and an output switch 26 that controls connection and disconnection between the second terminal and the display element of the driving transistor. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to an active matrix display device in which display pixels including display elements such as organic electroluminescence (hereinafter referred to as EL) elements are arranged in a matrix to form a display screen, and a driving method thereof.

  2. Description of the Related Art Planar active matrix display devices are widely used as display devices for personal computers, portable information terminals, and televisions. In recent years, as such a flat-type active matrix display device, an organic EL display device using a self-luminous element such as an organic EL element has attracted attention and has been actively researched and developed. This organic EL display device does not require a backlight that obstructs the reduction in thickness and weight, is suitable for video playback because of its high-speed response, and can be used even in cold regions because it does not decrease brightness at low temperatures. I have.

  In general, an organic EL display device includes a plurality of display pixels arranged in a plurality of rows and a plurality of columns and constituting a display screen, a plurality of scanning lines extending along each row of display pixels, and a column of display pixels. A plurality of extended signal lines, a scanning line driving circuit for driving each scanning line, a signal line driving circuit for driving each signal line, and the like are provided. Each display pixel includes an organic EL element that is a self-light-emitting element and a pixel circuit that supplies a drive current to the organic EL element (for example, Patent Document 1).

Each pixel circuit includes a pixel switch arranged in the vicinity of the intersection of the scanning line and the signal line, a driving transistor configured by a thin film transistor connected in series with an organic EL element between a pair of power supply lines, and a gate control voltage of the driving transistor Has a holding capacity. The pixel switch is turned on in response to the scanning signal supplied from the corresponding scanning line, and takes in the video signal supplied from the corresponding signal line. The gate-source potential of the drive transistor corresponding to this video signal is written as a gate control voltage in the storage capacitor and held for a predetermined period. Then, the driving transistor supplies a current amount corresponding to the gate control voltage written in the storage capacitor to the organic EL element to perform a light emitting operation.
As the pixel circuit, a current copy type circuit using a current as a video signal is used.
JP 2000-208252 A

  However, when a current is used as a video signal, the signal current becomes small in low gradation display, so that the signal current is insufficiently written due to the influence of the load capacity of the signal line, and the gate voltage of the driving transistor is set to a desired value. It becomes difficult to set. This causes an increase in luminance in low gradation display.

  The present invention has been made in view of the above points, and an object of the present invention is to reduce a shortage of signal current writing in low gradation display and to realize a good display by suppressing an increase in luminance in low gradation display. It is an object of the present invention to provide an active matrix display device and a driving method thereof.

In order to achieve the above object, an active matrix display device according to an aspect of the present invention includes a display element and a plurality of pixel circuits arranged in a matrix on a substrate, the pixel circuit supplying a driving current to the display element. A plurality of video signal lines connected to each column of the pixel unit, and a signal line driving circuit that outputs a reference current and a gradation signal current to the video signal line,
Each of the pixel circuits includes a driving transistor having a first terminal connected to a voltage power source and a second terminal connected to the display element, and is connected between a first terminal and a control terminal of the driving transistor. A first holding capacitor for holding a potential of a control terminal; a second terminal of the driving transistor; and the video signal line connected to the reference current and the grayscale signal current supplied from the video signal line. A first switch flowing through the drive transistor; a second switch connected between the second terminal of the drive transistor and the first storage capacitor; and a control terminal of the drive transistor and the first storage capacitor. A third storage capacitor provided between the first storage capacitor and the second storage capacitor, and a second storage capacitor that holds a potential corresponding to a difference between the reference current and the gradation signal current. , A fourth switch provided between the second terminal and the control terminal of the drive transistor, and controlling connection / disconnection between the second terminal and the control terminal, and a second terminal of the drive transistor And an output switch for controlling connection / disconnection between the display element and the display element.

  A driving method of an active matrix display device according to another aspect of the present invention is a driving method of the active matrix display device, wherein a reference current is supplied from the video signal line through a driving transistor of the pixel circuit, and the reference current is supplied. The first signal writing to write the grayscale signal current by passing the grayscale signal current from the video signal line through the driving transistor of the pixel circuit, and writing the grayscale signal current to the second storage capacitor. The second signal writing that holds the potential according to the difference between the second transistor and the fourth switch, the control terminal and the second terminal of the driving transistor are made conductive by the fourth switch, the threshold value offset of the driving transistor is canceled, and the second transistor A driving current corresponding to the potential written in the two holding capacitors and the first holding capacitor is output from the driving transistor to the display element; A driving method for emitting 示素Ko.

  According to an aspect of the present invention, an active matrix display device capable of reducing insufficient writing of a signal current in low gradation display and suppressing luminance increase in low gradation display and realizing good display and its A driving method can be provided. Further, it is possible to provide an active matrix display device with improved display quality and a driving method thereof, which can control light emission current regardless of variations in threshold voltage and mobility of transistors.

Hereinafter, an organic EL display device according to an embodiment of the present invention will be described in detail with reference to the drawings.
FIG. 1 schematically shows the entire organic EL device. As shown in FIG. 1, the organic EL display device is configured as, for example, a large active matrix display device of 10 type or more, and includes an organic EL panel 10 and a controller 12 that controls the organic EL panel 10.

  The organic EL panel 10 is arranged in the form of a matrix on an insulating substrate 8 such as a glass plate, and is connected to each row of the display pixels, each of which is connected to each row of the display pixels 11 and independently. A first scanning line Sga (1 to m), a second scanning line Sgb (1 to m), a third scanning line Sgc (1 to m), a fourth scanning line Sgd (1 to m) provided m by m, A fifth scanning line Sge (1 to m) and n video signal lines X (1 to n) connected to each column of the display pixels PX are provided. The organic EL panel 10 includes first, second, third, fourth, and fifth scanning lines Sga (1 to m), Sgb (1 to m), Sgc (1 to m), and Sgd (1 to m). , Sge (1 to m) are sequentially provided for each row of the display pixels PX, and scanning line driving circuits 14a and 14b and a signal line driving circuit 15 for driving the plurality of video signal lines X (1 to n) are provided. . The scanning line driving circuits 14 a and 14 b and the signal line driving circuit 15 are integrally formed on the insulating substrate 8 outside the display area 11.

  Each display pixel PX that functions as a pixel portion includes a display element having a photoactive layer between opposing electrodes, and a pixel circuit 18 that supplies a drive current to the display element. The display element is, for example, a self-light-emitting element, and in this embodiment, a current-driven organic EL element 16 having at least an organic light-emitting layer as a photoactive layer is used.

  FIG. 2 shows an equivalent circuit of the display pixel PX. The pixel circuit 18 is a current-driven pixel circuit that controls light emission of the organic EL element 16 in accordance with a video signal including a current signal. The pixel circuit 18 includes a first switch 21, a second switch 22, a third switch 23, A fourth switch 24, a drive transistor 20, an output switch 26, a first holding capacitor C1, and a second holding capacitor C2 are provided.

  Here, the first switch 21, the second switch 22, the third switch 23, the fourth switch 24, the driving transistor 20, and the output switch 26 are configured by thin film transistors of the same conductivity type, for example, a P-channel type. In this embodiment, all the thin film transistors constituting the pixel circuit 18 are formed in the same process and the same layer structure, and are top gate thin film transistors using polysilicon as a semiconductor layer.

  Each of the first switch 21, the second switch 22, the third switch 23, the fourth switch 24, the drive transistor 20, and the output switch 26 has a first terminal, a second terminal, and a control terminal. The first terminal, the second terminal, and the control terminal are a source, a drain, and a gate, respectively.

  The drive transistor 20, the output switch 26, and the organic EL element 16 are connected in series in this order between the low potential first voltage power supply line Vss and the high potential second voltage power supply line Vdd. The first voltage power line Vss and the second voltage power line Vdd are set to potentials of −9 V and +6 V, for example. The source of the driving transistor 20 is connected to the second voltage power supply line Vdd. The organic EL element 16 has one electrode, here the cathode, connected to the first voltage power supply line Vss. The source of the output switch 26 is connected to the second terminal of the driving transistor 20, here the drain. The output switch 26 has a drain connected to the anode of the organic EL element 16 and a gate connected to the fifth scanning line Sge.

  The drive transistor 20 outputs a light emission current having a current amount corresponding to the video signal to the organic EL element 16. The output switch 26 is controlled to be on (conductive state) and off (non-conductive state) by the fifth control signal Se (1 to m) from the fifth scanning line Sge, and the connection between the drive transistor 20 and the organic EL element 16 is controlled. Control the disconnection.

  The first switch 21 is connected between the corresponding video signal line X (1 to n) and the drain of the driving transistor 20, and the gate thereof is connected to the first scanning line Sga. The first switch 21 captures a signal current as a gradation current from the corresponding video signal line X (1 to n) in response to the first control signal Sa (1 to m) supplied from the first scanning line Sga. .

  One electrode of the first storage capacitor C1 is connected to the first voltage power supply line Vdd. One electrode of the second storage capacitor C <b> 2 is connected to the gate of the drive transistor 20. The first and second holding capacitors C1 and C2 hold the gate control potential of the driving transistor 20 determined by the video signal.

  The second switch 22 is connected between the drain of the driving transistor 20 and the first storage capacitor C1, and the gate thereof is connected to the second scanning line Sgb. The second switch 22 is controlled to be on (conductive state) and off (non-conductive state) by a second control signal Sb (1 to m) supplied from the second scanning line Sgb.

  The third switch 23 is connected between the first storage capacitor C1 and the second storage capacitor C2, and the gate thereof is connected to the third scanning line Sgc. The third switch 23 is controlled to be on (conductive state) and off (non-conductive state) by a third control signal Sc (1 to m) supplied from the third scanning line Sgc.

  The fourth switch 24 is connected between the drain and gate of the driving transistor 20, and the gate thereof is connected to the fourth scanning line Sge. The fourth switch 24 is ON / OFF controlled according to the fourth control signal Sa (1 to m) supplied from the fourth scanning line Sge, and controls connection / disconnection between the gate and drain of the drive transistor 20. At the same time, current leakage from the holding capacitor C2 is regulated.

  On the other hand, the controller 12 shown in FIG. 1 is formed on a printed circuit board disposed outside the organic EL panel 10 and controls the scanning line driving circuits 14 a and 14 b and the signal line driving circuit 15. The controller 12 receives a digital video signal and a synchronization signal supplied from the outside, and generates a vertical scanning control signal for controlling the vertical scanning timing and a horizontal scanning control signal for controlling the horizontal scanning timing based on the synchronizing signal. The scanning control signal and the horizontal scanning control signal are supplied to the scanning line driving circuits 14a and 14b and the signal line driving circuit 15, respectively, and the digital video signal is supplied to the signal line driving circuit 15 in synchronization with the horizontal and vertical scanning timings.

  The scanning line driving circuits 14a and 14b include a shift register, an output buffer, and the like, and sequentially transfer a horizontal scanning start pulse supplied from the outside to the next stage, as shown in FIGS. 1 and 2, via the output buffer. Four types of control signals, that is, control signals Sa (1 to m), Sb (1 to m), Sc (1 to m), Sd (1 to m), and Se (1 to m) are applied to the display pixels PX in each row. Supply. Thereby, each 1st, 2nd, 3rd, 4th, 5th scanning line Sga (1-m), Sgb (1-m), Sgc (1-m), Sgd (1-m), Sge ( 1 to m) are control signals Sa (1 to m), control signals Sb (1 to m), Sc (1 to m), control signals Sd (1 to m), and control in one horizontal scanning period different from each other. Driven by the signal Se (1 to m).

  The signal line driving circuit 15 converts the video signal sequentially obtained in each horizontal scanning period into the analog format under the control of the horizontal scanning control signal to be the first signal current Iref and the second signal current Isig, and the first and second signals Current is supplied in parallel to the plurality of video signal lines X (1 to n). As shown in FIG. 2, the signal line drive circuit 15 has a current supply unit I connected to each video signal line X (1 to n). The current supply unit I supplies the first signal current Iref as the reference current and the second signal current Isig as the gradation current to the pixel circuit 18 through the video signal lines X (1 to n). The first signal current Iref and the second signal current Isig are supplied to the plurality of display pixels PX using the same video signal wiring X (1 to n) by time division.

  The amount of current of the first signal current Iref and the second signal current Isig is set to an amount of current that does not cause insufficient writing of the video signal line. That is, the current amount of the first signal current Iref and the second signal current Isig is the potential from the highest gradation display to the lowest gradation display in the wiring capacity (Cp) of the video signal line X in one horizontal scanning period (t). It is set to a value larger than the amount of charge corresponding to the value multiplied by the change (maximum voltage change ΔV) [(Iref · Isig)> Cp × ΔV / t]. For example, the first signal current Iref and the second signal current Isig are set to the same magnitude as the drive current for performing the highest gradation display of the organic EL display device.

  In addition, one of the first signal current Iref and the second signal current Isig, for example, the first signal current Iref is a constant current, and the second signal current Isig is a signal current that varies according to the gradation. Note that the second signal current Isig may be a constant signal current, and the first signal current Iref may be a signal current that varies according to gradation. Alternatively, both the first signal current Iref and the second signal current Isig can be variable signal currents.

  In the organic EL display device configured as described above, the operation of the pixel circuit 18 includes a first signal current (reference signal current) write operation, a second signal current (grayscale signal current) write operation, a threshold cancel operation, and It can be divided into light emitting operations.

  FIG. 3 is a timing chart showing on / off timings of the control signals Sa, Sb, Sc, and Sd. FIG. 4 schematically illustrates the operation of the pixel circuit 18 in the display pixel PX in the first row. It shows.

  As shown in FIGS. 3 and 4, in the first signal current (reference signal current) writing operation, for example, the first switch 21 and the second switch from the first scanning line driving circuit 14a to the display pixel PX in the first row. A level (ON potential) that turns on the switch 22 and the third switch 23, that is, low-level control signals Sa, Sb, and Sc are output here. At the same time, from the second scanning line driving circuit 14b, a low level control signal Sd for turning on the fourth switch 24 and a level (off potential) for turning off the output switch 26, in this case, a high level control signal Se. Is output. As a result, the first to fourth switches 21 to 24 are turned on (conductive state) and the output switch 26 is turned off (non-conductive state), and the first signal current writing operation is started.

In the first signal current writing period, for example, the first signal current Iref set to a predetermined constant current is supplied to the video signal line X from the corresponding current supply unit I of the signal line driving circuit 15. In the display pixel PX, the first, second, third, and fourth switches 21 to 24 are in an on state, and the gate and drain of the driving transistor 20 are in a diode connection state. As a result, the reference signal current Iref flows from the first voltage power supply line Vdd to the video signal line X through the drive transistor 20. Therefore, the gate potential of the drive transistor 20 becomes the reference potential Vref corresponding to the amount of the reference signal current Iref. The gate voltage Vgs of the driving transistor 20 at this time is expressed by the following formula 1.
Vgs = Vdd−Vref (Formula 1)
Therefore, the current equation when the reference current Iref flows through the driving transistor 20 is expressed by the following equation 2 from the transistor current equation.
Iref = β × (Vgs−Vth) ²
= Β × (Vdd−Vref−Vth) ² (Expression 2)
Here, Vth is a threshold value of the drive transistor 20, and β is a constant including the mobility, channel length, channel width, gate capacitance value, and the like of the drive transistor.

Therefore, Vref is expressed by Equation 3 below.
Vref = Vdd−Vth− (Iref / β) ^1/2 (Expression 3)
The reference potential Vref is written to the first storage capacitor C1 through the second switch 22.

  Subsequently, as shown in FIGS. 3 and 5, the control signal Sb is turned off (high level), and the second switch 22 is turned off. As a result, the first signal current writing operation is completed and the second signal current (gradation signal current) writing operation is started.

  In the second signal current writing period, the second signal current Isig corresponding to the gradation signal is supplied to the video signal line X from the corresponding current supply unit I of the signal line driving circuit 15. In the display pixel PX, the first, third, and fourth switches 21, 23, and 24 are in an on state, the output switch 26 is in an off state, and the drive transistor 20 has a diode-connected state between its gate and drain. As a result, the gradation signal current Isig flows from the first voltage power supply line Vdd to the video signal line X through the drive transistor 20 and the first switch 21.

Accordingly, the gate potential of the driving transistor 20 changes from Vref to Vsig. Vsig is expressed by the following expression 4 similarly to expression 3.
Vsig = Vdd−Vth− (Isig / β) ^1/2 (Formula 4)
The potential fluctuation (Vsig−Vref) generated at the gate of the driving transistor 20 is capacitively coupled to the node n1 between the first holding capacitor C1 and the third switch 23 via the second holding capacitor C2. When the capacitance values of the first storage capacitor C1 and the second storage capacitor C2 are C1 and C2, respectively, the capacitance coupling corresponding to the change in the gate potential of the drive transistor 20 is
(Vsig−Vref) × C2 / (C1 + C2)
It is represented by

Therefore, the potential V1 of the node n1 is added to the original Vref by this coupling, and is expressed by the following Expression 5.
V1 = Vref + (Vsig−Vref) × C2 / (C1 + C2) (Formula 5)
Here, since the voltage ΔV held in the second holding capacitor C2 is V1−Vsig, the following Expression 6 is obtained by substituting Expressions 3, 4, and 5.
ΔV = V1−Vsig
= (Vsig−Vref) × C2 / (C1 + C2)
= (Isig ^1/2 -Iref ^1/2 ) × C1 / {(C1 + C2) × β ^1/2 } (Formula 6)
From this equation, a voltage corresponding to the difference between the second signal current Isig and the first signal current Iref is held in the second holding capacitor C2.
The first signal current writing and the second signal current writing are sequentially performed within one horizontal period H.

  Next, as shown in FIGS. 3 and 6, the first control signal Sa and the third control signal Sc become high level (off potential), and the first switch 21 and the third switch 23 are turned off. Thereby, the second signal current writing operation is completed, and the threshold canceling operation of the driving transistor 20 is performed.

  In the threshold cancellation period, the second switch 22 and the fourth switch 24 of the pixel circuit 18 are turned on, and the first switch 21, the third switch 23, and the output switch 26 are turned off. As a result, a current flows from the first voltage power supply line Vdd through the drive transistor 20 and the fourth switch 24 to charge the first storage capacitor C1, and the gate potential of the drive transistor 20 is raised. The current stops flowing when the gate voltage of the drive transistor 20 reaches the threshold voltage. Therefore, the threshold voltage Vth is held in the first holding capacitor C1.

  Next, a light emission operation is performed. As shown in FIGS. 3 and 7, in the light emission period, the third switch 23 and the output switch 26 are turned on, and the first switch 21, the second switch 22, and the fourth switch 24 are turned off. The drive transistor 20 is maintained in a conductive state by the gate control voltage written in the first and second holding capacitors C1 and C2, and outputs a light emission current IEL having a current amount corresponding to the gate control voltage from the second voltage power supply line Vdd. Supply to the switch 26 side. The light emission current IEL is supplied to the organic EL element 16 after passing through the output switch 26. Thereby, the organic EL element 16 emits light, and the light emission operation is started. Then, the organic EL element 16 maintains the light emitting state until the fifth control signal Se becomes the off potential again after one frame period.

The gate voltage Vgs of the driving transistor 20 during this light emission period is the sum of the voltage held in the first holding capacitor C1 and the voltage held in the second holding capacitor C2. When the third switch 23 is turned on and the first and second holding capacitors C1 and C2 are connected, the first holding capacitor C1 and the second holding capacitor C2 are larger in capacity than the gate capacitance of the driving transistor 20. The first holding capacitor C1 and the second holding capacitor C2 are connected while holding charges. Therefore, the gate voltage Vgs of the driving transistor 20 is the sum of the threshold voltage Vth of the driving transistor 20 held in the first holding capacitor C1 and the voltage ΔV held in the second holding capacitor C2. This is expressed by Equation 7.
Vgs = Vth + ΔV
= Vth + (Isig ^1/2 −Iref ^1/2 ) × C1 / {(C1 + C2) × β ^1/2 }
On the other hand, the light emission current I _EL is expressed by the following Expression 8.
I _EL = β × (Vgs−Vth) ² (Equation 8)
When Expression 7 is substituted for this, the light emission current I _EL is expressed by Expression 9 below.
I _EL = (Isig ^1/2 −Iref ^1/2 ) ² × {C1 / (C1 + C2)} ² (Equation 9)
From Equation 9, it can be seen that the light emission current IEL is determined by the difference between the second signal current Isig and the first signal current (reference current) Iref and does not depend on the threshold voltage or mobility of the drive transistor 20.

According to the organic EL display device configured as described above and the driving method thereof, a desired light emission current is determined by the difference between the first signal current and the second signal current even when low gradation display is performed. The current values of the first and second signal currents supplied to the video signal line can be set freely, and can be set to a value sufficiently larger than the wiring capacity of the video signal line. Therefore, even when displaying at low gradation, the signal current can be written in a sufficiently short time without being affected by the wiring capacity, and the display failure at low luminance, unevenness, and the feeling of roughness are eliminated. In addition, high-quality image display can be realized.
In addition, a light-emitting current can be controlled regardless of variations in the threshold voltage and mobility of the transistor, and a high-quality organic EL display device free from stripes and unevenness can be realized.

  Note that the present invention is not limited to the above-described embodiment as it is, and can be embodied by modifying the constituent elements without departing from the scope of the invention in the implementation stage. Further, various inventions can be formed by appropriately combining a plurality of constituent elements disclosed in the embodiment. For example, some components may be deleted from all the components shown in the embodiment. Furthermore, you may combine suitably the component covering different embodiment.

  For example, in the above-described embodiment, the semiconductor layer of the thin film transistor is not limited to polysilicon, but may be composed of amorphous silicon. The self-luminous elements constituting the display pixels are not limited to organic EL elements, and various display elements capable of self-luminance are applicable.

FIG. 1 is a plan view schematically showing an organic EL display device according to an embodiment of the present invention. FIG. 2 is a plan view showing an equivalent circuit of display pixels in the organic EL display device. FIG. 3 is a diagram showing ON / OFF (high, Low) timings of control signals in the organic EL display device. FIG. 4 is a plan view showing an equivalent circuit of a display pixel when writing the first signal current in the organic EL display device. FIG. 5 is a plan view showing an equivalent circuit of a display pixel when writing the second signal current in the organic EL display device. FIG. 6 is a plan view showing an equivalent circuit of the display pixel during the threshold cancel operation of the organic EL display device. It is a top view which shows the equivalent circuit of the display pixel at the time of the light emission operation | movement of the said organic electroluminescent display apparatus.

Explanation of symbols

8 ... Insulating substrate, 10 ... Organic EL panel, 11 ... Display area, 12 ... Controller,
14a, 14b ... scanning line drive circuit, 15 ... signal line drive circuit, 16 ... organic EL element,
18 ... pixel circuit, 20 ... drive transistor, 21 ... first switch,
22 ... 2nd switch, 23 ... 3rd switch, 24 ... 4th switch,
26: Output switch, C1: First holding capacitor, C2: Second holding capacitor,
Vss ... first voltage power line, Vdd ... second voltage power line,

Claims (6)

A plurality of pixel portions including a display element and a pixel circuit for supplying a driving current to the display element, the pixel parts being arranged in a matrix on the substrate;
A plurality of video signal lines connected to each column of the pixel portion;
A signal line driving circuit for outputting a reference current and a gradation signal current to the video signal line,
Each of the pixel circuits includes a driving transistor having a first terminal connected to a voltage power source and a second terminal connected to the display element, and is connected between a first terminal and a control terminal of the driving transistor. A first holding capacitor for holding a potential of a control terminal; a second terminal of the driving transistor; and the video signal line connected to the reference current and the grayscale signal current supplied from the video signal line. A first switch flowing through the drive transistor; a second switch connected between the second terminal of the drive transistor and the first storage capacitor; and a control terminal of the drive transistor and the first storage capacitor. A third storage capacitor provided between the first storage capacitor and the second storage capacitor, and a second storage capacitor that holds a potential corresponding to a difference between the reference current and the gradation signal current. , A fourth switch provided between the second terminal and the control terminal of the drive transistor, and controlling connection / disconnection between the second terminal and the control terminal, and a second terminal of the drive transistor And an output switch for controlling connection / disconnection between the display element and the display element.   2. The active matrix display device according to claim 1, wherein the first, second, third, fourth switch and output switch are formed of P-channel type thin film transistors.   The active matrix display device according to claim 1, wherein the display element is a self-luminous element including an organic light emitting layer between opposed electrodes. A display element; a pixel circuit that supplies a driving current to the display element; a plurality of pixel portions arranged in a matrix on a substrate; and a plurality of video signal lines connected to each column of the pixel portion. And a signal line driving circuit for outputting a reference current and a gradation signal current to the video signal line,
Each of the pixel circuits includes a driving transistor having a first terminal connected to a voltage power source and a second terminal connected to the display element, and is connected between a first terminal and a control terminal of the driving transistor. A first holding capacitor for holding a potential of a control terminal; a second terminal of the driving transistor; and the video signal line connected to the reference current and the grayscale signal current supplied from the video signal line. A first switch flowing through the drive transistor; a second switch connected between the second terminal of the drive transistor and the first storage capacitor; and a control terminal of the drive transistor and the first storage capacitor. And a third storage capacitor connected between the first storage capacitor and the second storage capacitor, and a second storage capacitor that holds a potential corresponding to the difference between the reference current and the grayscale signal current. , A fourth switch that is provided between the second terminal and the control terminal of the drive transistor, and controls connection / disconnection between the second terminal and the control terminal, and a second switch of the drive transistor. An active matrix display device driving method comprising an output switch for controlling connection and non-connection between a terminal and a display element,
A first signal writing in which a reference current is caused to flow from the video signal line through a driving transistor of the pixel circuit, and the reference current is written;
A gradation signal current is supplied from the video signal line through the driving transistor of the pixel circuit to write the gradation signal current, and a potential corresponding to a difference between the reference current and the gradation signal current is held in the second storage capacitor. Second signal writing to
The control terminal and the second terminal of the driving transistor are made conductive by the fourth switch to cancel the offset of the threshold value of the driving transistor,
A driving method of an active matrix display device, wherein a driving current corresponding to a potential written in the second holding capacitor and the first holding capacitor is output from the driving transistor to the display element to cause the display element to emit light.   In the first signal writing, the first, second, third, and fourth switches are turned on, the output switch is turned off, a reference current is supplied to the video signal line through the driving transistor, and in the second signal writing. 5. The active matrix display device according to claim 4, wherein the first, third, and fourth switches are turned on, the second switch and the output switch are turned off, and a reference current is supplied to the video signal line through the driving transistor. Driving method.   In the cancellation of the threshold value, the first and third switches and the output switch are turned off, the second and fourth switches are turned on, and the first, second, and fourth switches are turned off during the light emission period, 6. The driving method for an active matrix display device according to claim 5, wherein the three switches and the output switch are turned on.

Images