JP2010128183A - Active matrix type display device, and method for driving the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an active matrix type display device in which size of a picture frame can be narrowed and the number of elements is decreased, and whose definition is made high and display quality is improved, and to provide a method for driving the same. <P>SOLUTION: The active matrix type display device includes a display element 16 and a pixel circuit 18, and the device includes a plurality of pixel parts PX arranged in a matrix on a substrate, a plurality of scanning lines connected to each row, a plurality of video signal lines X connected to each column, a plurality of reset power source wiring Vrst connected to each row, a plurality of initialization power source wiring Vini connected to each row, a scanning line drive circuit, and a signal line drive circuit. The pixel circuit includes a drive transistor DRT, an output switch BCT, holding capacity Cs, an initialization switch IST, and a pixel switch SST. The scanning line driving circuit has a plurality of reset switches provided for one reset power source line. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to an active matrix display device using a light emitting element for a pixel and a driving method thereof.

  In recent years, the demand for flat display devices typified by liquid crystal display devices has been rapidly increased by taking advantage of the features of thinness, light weight, and low power consumption. In particular, an active matrix display device in which a pixel switch having a function of electrically separating an on pixel and an off pixel and holding a video signal to the on pixel is provided in each pixel has crosstalk between adjacent pixels. Therefore, it is used for various displays including portable information devices.

  As such a flat-type active matrix display device, an organic EL display device using a self-luminous element has attracted attention, and research and development have been actively conducted. The organic EL display device does not require a backlight that obstructs the reduction in thickness and weight, is suitable for moving image reproduction because of high-speed response, and further has a feature that it can be used even in a cold region because the luminance does not decrease at low temperatures.

In general, an organic EL display device includes a plurality of display pixels that are arranged in a plurality of rows and a plurality of columns to form a display screen. Each display pixel includes an organic EL element that is a self-light emitting element and a pixel circuit that supplies a drive current to the organic EL element, and performs a display operation by controlling the light emission luminance of the organic EL element.
As a driving method of the pixel circuit, a method using a voltage signal (for example, Patent Document 1) is known. In addition, the voltage power supply is switched to switch between low and high, and both the video signal and the initialization signal are output from the video signal line, thereby reducing the number of pixel components and wiring and reducing the pixel layout area. There has been proposed a display device that achieves high definition by reducing the size (for example, Patent Document 2).
US Pat. No. 6,229,506 B1 JP 2007-310311 A

  However, when the power supply voltage is switched for each row as in the display device disclosed in Patent Document 2, since the current flowing through the voltage power supply is large, the voltage drop of the switching element for switching the power supply voltage also increases. . As a result, it is necessary to enlarge the switching element, and the drive circuit becomes larger.

  Also, when outputting both the video signal potential and the reset potential from the video signal line, the signal line cannot be selectively driven, and all of the pixel initialization operation, video signal writing, and threshold cancellation operation are performed within one horizontal period. There is a need to do. For this reason, the video signal writing period or the threshold cancellation period is shortened, resulting in insufficient writing of the video signal or insufficient threshold cancellation, and display unevenness may occur. Similarly, it is difficult to sufficiently correct the mobility of the driving transistors constituting the pixel, which causes display unevenness.

  SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and its object is to reduce the number of elements by reducing the size of the drive circuit, reduce the number of elements, and improve the display quality with high definition. And a driving method thereof.

In order to achieve the above object, an active matrix display device according to an aspect of the present invention includes a display element and a pixel circuit that supplies a driving current to the display element, and is arranged in a matrix on a substrate. A plurality of pixel portions, a plurality of scanning lines connected to each row of the pixel portions, a plurality of video signal lines connected to the pixel portions, and a plurality of reset power lines connected to the pixel portions, respectively. A plurality of initialization power supply wirings connected to each row of the pixel portion, a high potential voltage power supply line and a low potential voltage power supply line, and a plurality of scanning lines to sequentially supply control signals to the pixel portion. A scanning line driving circuit that performs line sequential scanning in units, and a signal line driving circuit that supplies a video voltage signal to the video signal line in accordance with the line sequential scanning,
The pixel circuit is connected in series with the display element between the low potential voltage power supply line and the high potential voltage power supply line, a first terminal is connected to the display element, and a second terminal is connected to the reset power supply wiring. An output switch formed by the transistor, having a first terminal connected to the high potential voltage power source, a second terminal connected to the second terminal of the drive transistor, and a control terminal connected to the scanning line And a storage capacitor connected between the first terminal and the control terminal of the driving transistor, a transistor, a first terminal connected to the initialization power line, and a second terminal controlling the driving transistor An initialization switch connected to the terminal, a control terminal connected to the scanning line, and a transistor, a first terminal connected to the video signal line, and a second terminal connected to the scanning line A pixel switch connected to a control terminal of a dynamic transistor, the control terminal being connected to the scanning line, and taking in a video voltage signal from the video signal line and holding the video voltage signal in the holding capacitor; Provided for each reset power supply line, each having a plurality of reset switches in which a first terminal is connected to the reset power supply, a second terminal is connected to the reset power supply wiring, and a control terminal is connected to the scanning line. .

  In the driving method of the active matrix display device according to another aspect of the present invention, an initialization potential is applied from the initialization power supply line to the control terminal of the drive transistor, and the first of the drive transistor is supplied from the reset power supply line. A reset period in which a reset potential is applied to a terminal to initialize the drive transistor; and a current is passed from the high-potential voltage power source to the drive transistor in a state in which the initialization potential is applied to the control terminal of the drive transistor, and the drive An offset cancel period for canceling a threshold offset of the transistor; a video signal writing period for writing a video voltage signal to the video signal line; and writing the video voltage signal from the video signal line to a control terminal of the driving transistor; The potential voltage power supply line through the drive transistor It includes a mobility correction period to flow a current to the potential voltage source line, and a light emission period for supplying a drive current corresponding to the video voltage signal to the display device through the driving transistor from the high-level voltage supply line.

  According to the above configuration, an active matrix display device that can reduce the number of elements by reducing the size of the drive circuit, reduce the number of elements, improve the display quality, and provide a driving method thereof. Can do.

Hereinafter, an organic EL display device according to a first embodiment of the present invention will be described in detail with reference to the drawings.
FIG. 1 is a plan view schematically showing an organic EL display device. As shown in FIG. 1, the organic EL display device is configured as, for example, an active matrix type display device of two or more types, and includes an organic EL panel 10 and a controller 12 that controls the operation of the organic EL panel 10. .

  The organic EL panel 10 includes a light-transmitting insulating substrate 8 such as a glass plate, m × n display pixels PX arranged in a matrix on the insulating substrate and constituting a display region 11, and each display pixel row. A first scanning line (light emission time control gate wiring, reset control gate wiring) Sga (1 to m) and a second scanning line (initialization control gate) which are connected and provided independently by m. Wiring) Sgb (1 to m), third scanning line (signal writing control gate wiring) Sgc (1 to m), and n video signal lines X (1 to n) connected to each column of the display pixels PX It has. In addition, the organic EL panel 10 is connected to each row of the display pixels PX and is provided with m independent power supply lines Vini and reset power supply lines Vrst described later, and a high-potential voltage power supply line. Vdd and a low-potential reference voltage power supply line Vss.

  The organic EL panel 10 includes a scanning line driving circuit that sequentially drives the first, second, and third scanning lines Sga (1 to m) and Sgb (1 to m) Sgc (1 to m) for each row of the display pixels PX. 14a and 14b, and a signal line driving circuit 15 for driving the plurality of video signal lines X (1 to n). The scanning line driving circuits 14 a and 14 b and the signal line driving circuit 15 are integrally formed on the insulating substrate 8 outside the display area 11 and constitute a control unit together with the controller 12.

  Each display pixel PX that functions as a pixel portion includes a display element having a photoactive layer between opposing electrodes, and a pixel circuit 18 that supplies a drive current to the display element. The display element is, for example, a self-luminous element. In this embodiment, the organic EL element 16 including at least an organic light-emitting layer is used as a photoactive layer.

  FIG. 2 shows an equivalent circuit of the display pixel PX. In each row, three display pixels PX for R (red) display, G (green) display, and B (blue) display are alternately arranged. The pixel circuit 18 of each display pixel PX is a voltage signal type pixel circuit that controls light emission of the organic EL element 16 in accordance with a video signal composed of a voltage signal, and includes a pixel switch SST, a drive transistor DRT, an initialization switch IST, And a storage capacitor Cs as a capacitor. At least one of the display pixels PX in each row has an output switch BCT. In the present embodiment, the output switch BCT is provided for the G display pixel PX among the three display pixels RGB. Further, the scanning line driving circuit 14a is provided with a plurality of reset switches RST, each connected to the reset power supply wiring Vrst of each row.

  Here, the pixel switch SST, the drive transistor DRT, the initialization switch IST, and the output switch BCT are configured by the same conductivity type, for example, an N-channel type thin film transistor. The reset switch RST is composed of a thin film transistor of a reverse conductivity type to the output switch BCT, here a P-channel type. Note that the output switch BCT may be composed of a P-channel thin film transistor, and the reset switch RST may be composed of an N-channel thin film transistor. In the present embodiment, the thin film transistors each constituting each drive transistor and each switch are formed in the same process and the same layer structure, and are top gate thin film transistors using polysilicon as the semiconductor layer.

  Each of the pixel switch SST, the drive transistor DRT, the output switch BCT, the initialization switch IST, and the reset switch RST has a first terminal, a second terminal, and a control terminal. In the present embodiment, these first terminal, The two terminals and the control terminal are the source, drain and gate, respectively.

  In the pixel circuit 18 of the G display pixel PX, the drive transistor DRT and the output switch BCT are connected in series with the organic EL element 16 between the high potential voltage power supply line Vdd and the low potential reference voltage power supply line Vss. Yes. The voltage power supply line Vdd and the reference voltage power supply line Vss are set to potentials of 10 V and 1.5 V, for example. The voltage power supply line Vdd and the reference voltage power supply line Vss are connected to the signal line drive circuit 15 and supplied with the power supply voltage from the signal line drive circuit.

  The output switch BCT has its second terminal, here the drain, connected to the voltage power supply line Vdd, and the first terminal, here the source, is connected to the second terminal, here the drain, of the drive transistor DRT. The gate of the output switch BCT is connected to the first scanning line Sga. Accordingly, the output switch BCT is controlled to be on (conductive state) and off (non-conductive state) by the control signal BG (1 to m) from the first scanning line Sga (1 to m), and the organic EL element 16 emits light. Control the time.

  The drain of the driving transistor DRT is connected to the source of the output switch BCT and the reset power supply wiring Vrst, and the source is connected to one electrode of the organic EL element 16, here the anode. The cathode of the organic EL element is connected to the reference voltage power line Vss. The drive transistor DRT outputs a drive current having a current amount corresponding to the video signal to the organic EL element 16. In FIG. 2, the symbol Co indicates the parasitic capacitance of the organic EL element 16.

  In the R and B display pixels PX, the output switch BCT is not provided, and the drive transistor DRT is connected between the organic EL element 16 and the reset power supply wiring Vrst.

  In each pixel circuit 18, the initialization switch IST is connected between the gate of the drive transistor DRT and the initialization power supply wiring Vini, and the gate functions as a second scanning line Sgb (1 To m). The initialization switch IST is turned on (conductive state) and turned off (non-conductive state) in response to the control signal IG (1 to m) from the second scanning line Sgb (1 to m), and the corresponding initialization power supply wiring Vini. Is supplied to the pixel circuit 18, and the gate potential of the drive transistor DRT is set to the Vini potential every vertical period. That is, the initialization switch IST is turned on / off according to the control signal control signal IG (1-m) from the second scanning line Sgb (1-m), and the previous frame information of the gate potential of the driving transistor DRT is displayed. initialize.

  The holding capacitor CS has two electrodes, is connected between the gate and source of the driving transistor DRT, and holds the gate control potential of the driving transistor DRT determined by the video signal.

  The pixel switch SST has a source connected to the video signal line X (1 to n) and a drain connected to the gate of the drive transistor DRT. The gate of the pixel switch SST is connected to the third scanning line Sgc (1 to m) functioning as a signal writing control gate wiring, and the control signal SG (1 to 1) supplied from the third scanning line Sgc (1 to m). On / off control is performed by m). The pixel switch SST controls connection / disconnection between the pixel circuit 18 and the video signal lines X (1-n) in response to the control signal SG (1-m), and the corresponding video signal line X ( 1 to n), the gradation video voltage signal is taken into the pixel circuit 18.

  For each row, the reset switch RST provided in the scanning line driving circuit 14a is connected between the drain of the driving transistor DRT and the reset power supply wiring Vrst. The gate of the reset switch RST is connected to a first scanning line Sga (1 to m) that functions as a reset control gate wiring. The reset switch RST is on (conducting state) and off (non-conducting state) in response to the control signal BG (1 to m) from the first scanning line Sga (1 to m), and the source potential of the driving transistor DRT is set. initialize.

  As described above, the light emission time control gate wiring for controlling the output switch BCT and the reset control gate wiring for controlling the reset switch RST are formed by the common first scanning line Sga (1 to m). .

  On the other hand, the controller 12 shown in FIG. 1 is formed on a printed circuit board disposed outside the organic EL panel 10 and controls the scanning line driving circuits 14 a and 14 b and the signal line driving circuit 15. The controller 12 receives a digital video signal and a synchronization signal supplied from the outside, and generates a vertical scanning control signal for controlling the vertical scanning timing and a horizontal scanning control signal for controlling the horizontal scanning timing based on the synchronizing signal. The controller 12 supplies the vertical scanning control signal and the horizontal scanning control signal to the scanning line driving circuits 14a and 14b and the signal line driving circuit 15, respectively, and outputs a digital video signal in synchronization with the horizontal and vertical scanning timings. This is supplied to the line drive circuit 15.

  The signal line driving circuit 15 converts the video signals sequentially obtained in each horizontal scanning period into an analog format under the control of the horizontal scanning control signal, and converts the grayscale voltage signal Vsig having a plurality of gradations corresponding to the video signal to a plurality of video signal lines. X (1 to n) are supplied in parallel.

  The scanning line driving circuits 14a and 14b include a shift register, an output buffer, and the like, and sequentially transfer a horizontal scanning start pulse supplied from the outside to the next stage, as shown in FIGS. 1 and 2, via the output buffer. Three types of control signals, that is, control signals BG (1 to m), IG (1 to m), and SG (1 to m) are supplied to the display pixels PX in each row. As a result, the first, second, and third scanning lines Sga (1 to m), Sgb (1 to m), and Sgc (1 to m) are respectively supplied to the control signals BG (1 to m) and IG (1 to 1). m), driven by SG (1 to m).

Next, the operation of the organic EL display device configured as described above will be described. FIG. 3 shows a timing chart of the control signals of the scanning line drive circuits 14a and 14b at the time of display operation, and FIG. 4 shows the ON / OFF state of each switch at the time of display operation.
For example, the scanning line driving circuits 14a and 14b generate a pulse having a width of one horizontal scanning period (Tw-Starta) corresponding to each horizontal scanning period H from a start signal (STV1 to 5) and a clock (CKV1 to 5). The pulses are output as control signals BG, IG, and SG.

  The operation of the pixel circuit 18 is divided into 1) a reset operation, 2) a threshold offset cancel operation, 3) a pre-mobility correction operation, 4) a write operation, 5) a mobility correction operation, and 6) a light emission operation.

  As shown in FIGS. 3, 4, and 5, first, 1) a reset operation is performed. In the reset operation, from the scanning line driving circuits 14a and 14b, the level at which the pixel switch SST is turned off (off potential), here, the low level control signal SG, and the level at which the initialization switch IST is turned on (on potential). Here, the high level control signal IG, the level at which the output switch BCT is turned off and the reset switch RST is turned on, here, the low level control signal BG are output. As a result, the output switch BCT and the pixel switch SST are turned off (non-conducting state), the initialization switch IST and the reset switch RST are turned on (conducting state), and the reset operation is started.

  In the reset period, the initialization voltage signal VINI output from the initialization power supply line Vini is applied to the gate of the drive transistor DRT through the initialization switch IST. As a result, the gate potential of the drive transistor DRT is reset to a potential corresponding to the initialization voltage signal VINI, and the information of the previous frame is initialized. The initialization voltage signal VINI is set to 2V, for example.

  In addition, the reset voltage signal VRST output from the reset power supply wiring Vrst is applied to the source and drain of the drive transistor DRT through the reset switch RST. As a result, the source and drain potentials of the drive transistor DRT are reset to a potential corresponding to the reset voltage signal VRST, for example, −2 V, and the information of the previous frame is initialized. The reset operation is performed for one horizontal period.

  Subsequently, as shown in FIGS. 3, 4, and 6, the control signal BG is kept on (high level), the control signal IG is kept on, and the control signal SG is kept off. As a result, the pixel switch SST and the reset switch RST are turned off, the output switch BCT and the initialization switch IST are turned on, and 2) the threshold value offset cancel operation is started.

  In the offset cancel period, the gate potential of the drive transistor DRT is fixed to VINI. Further, the output switch BCT is in an ON state, and a current flows from the voltage power supply line Vdd to the drive transistor DRT. The source potential of the drive transistor DRT absorbs and compensates for variations in TFT characteristics of the drive transistor while gradually reducing the amount of current flowing through the drain-source of the drive transistor DRT, with VRST written during the reset period as an initial value. However, it shifts to the high potential side. At the end of the cancel period, the source potential of the drive transistor DRT becomes VINI−Vth (threshold voltage of the drive transistor). As a result, the gate-source voltage of the drive transistor DRT reaches the cancel point, and a potential difference corresponding to the cancel point is stored in the storage capacitor Cs. The offset cancel operation is performed for one horizontal period.

  Next, as shown in FIGS. 3, 4, and 7, 3) the pre-mobility correction operation and 4) the signal writing operation are started. In the pre-mobility correction period and the signal writing period, the control signal SG is at a low level that turns off the pixel switch SST, the control signal IG is at a low level that turns off the initialization switch IST, and the control signal BG is output from the output switch BCT. The on / reset switch RST is turned off to a high level. As a result, the initialization switch IST, the reset switch RST, and the pixel switch SST are turned off (non-conducting state), and the output switch BCT is turned on (conducting state). Further, the video voltage signal Vsig is written from the signal line driving circuit 15 to the video signal lines X (1 to n).

  In the pre-mobility correction period, a current flows from the voltage power supply line Vdd through the drive transistor DRT to the reference voltage power supply line Vss via the parasitic capacitance Co of the organic EL element 16, and after this period, the drive transistor DRT The source potential is VINI−Vth + ΔV1, and the gate potential of the driving transistor is VINI−Vth + ΔV1. The absolute value of the ΔV1 potential increases as the mobility of the driving transistor DRT increases.

  In the signal writing operation, each video voltage signal potential Vsig (R, G, B) is written to each video signal line X (1 to n) of the RGB display pixels PX within one horizontal period. This signal writing operation is performed simultaneously with the pre-mobility correction operation.

  Subsequently, as shown in FIGS. 3, 5 and 8, 5) In the mobility correction period, the control signal SG turns on the pixel switch SST and the control signal IG turns off the initialization switch IST. The off-potential for setting the state and the control signal BG become the potential for turning on the output switch BCT and turning off the reset switch RST. Thereby, the initialization switch IST and the reset switch RST are turned off (non-conducting state), the pixel switch SST and the output switch BCT are turned on (conducting state), and the mobility correction operation is started.

In the mobility correction period, the video voltage signal Vsig is written from the video signal line X (1 to n) through the pixel switch SST to the gate of the drive transistor DRT. Further, a current flows from the voltage power supply line Vdd to the reference voltage power supply line Vss through the drive transistor DRT and the parasitic capacitance Co of the organic EL element 16. Immediately after the pixel switch SST is turned on, the gate potential of the drive transistor DRT is Vsig (R, G, B), and the source potential of the drive transistor DRT is
VINI−Vth + ΔV1 + Cs (Vsig−VINI−ΔV1) / (Cs + Co)
It becomes. Thereafter, a current flows to the reference voltage power supply line Vss via the parasitic capacitance Co of the organic EL element 16, and at the end of the mobility correction period, the gate potential of the drive transistor is Vsig (R, G, B), the drive transistor DRT. The source potential of
VINI−Vth + ΔV1 + ΔV2 + Cs (Vsig−VINI−ΔV1) / (Cs + Co)
It becomes. Thereby, the variation in mobility of the drive transistor DRT is corrected.
In the present embodiment, pre-mobility correction, signal writing, and mobility correction are performed in one horizontal period.

  Next, as shown in FIGS. 3, 4, and 9, the control signal SG is turned off (low level), and the pixel switch SST is turned off. Thereby, the gradation video voltage signal writing operation and the mobility correction operation are completed. At the same time or subsequently, the control signal BG becomes an on potential (high level) that turns the output switch BCT on and the reset switch RST off, and the control signal IG turns off the initialization switch IST off. It becomes a potential (low level). Accordingly, the reset switch RST, the initialization switch IST, and the pixel switch SST are turned off (non-conducting state), only the output switch BCT is turned on (conducting state), and the light emission operation is started.

  In the light emission period, a drive current flows from the voltage power supply line Vdd to the drive transistor DRT of each of the R, G, and B display pixels PX through the output switch BCT and the reset power supply wiring Vrst. The drive transistor DRT outputs a drive current Ie having a current amount corresponding to the gate control voltage written in the storage capacitor CS. This drive current Ie is supplied to the organic EL element 16. Thereby, the organic EL element 16 emits light with a luminance corresponding to the drive current Ie, and performs a light emission operation. The organic EL element 16 maintains the light emitting state until the control signal BG becomes the off potential again after one frame period.

  The above-described reset operation, offset cancel operation, pre-mobility correction operation, signal writing operation, mobility correction operation, and light emission operation are sequentially performed on each display pixel, thereby displaying a desired image.

According to the organic EL display device configured as described above, during the light emission period, the current Ie flowing through the organic EL element 16 is the current value in the saturation region of the drive transistor DRT.
Iel = β × {(Vsig−VINI−ΔV1) × Co / (Cs + Co) −ΔV2} ² ,
β = μ · CoxW / 2L, (W: channel width, L: channel length)
Thus, the value does not depend on the threshold value Vth of the drive transistor DRT. Therefore, it is possible to eliminate the influence due to the variation in the threshold value of the driving transistor. In addition, since ΔV1 and ΔV2 have larger absolute values as the mobility of the driving transistor is larger, the influence of the mobility can be compensated. Therefore, it is possible to suppress the occurrence of display defects, unevenness, and rough feeling due to these variations, and to perform high-quality image display.

  In addition, it is not necessary to switch a high-potential voltage power source to a plurality of potentials, so that the switching element can be downsized and the drive circuit can be upsized. Thereby, it is possible to narrow the frame of the display device. By providing the video signal line and the reset power supply wiring, the video signal line can be selectively driven, and the reset period and the offset cancel period can each take one horizontal period or more. Therefore, it is possible to prevent insufficient writing of the video signal or insufficient cancellation of the threshold value and suppress the occurrence of display unevenness. Similarly, it is possible to sufficiently perform the mobility correction of the driving transistor that constitutes the pixel, to prevent display unevenness and to improve display quality. Furthermore, it is sufficient that at least one output switch is provided in one row, so that the number of elements can be reduced and high definition of the display panel can be achieved. By forming the light emission time control gate wiring and the reset control gate wiring with a common scanning line, the number of wirings can be reduced. As described above, an active matrix display device with high definition and improved display quality and a driving method thereof can be obtained.

Next, an organic EL display device according to the second embodiment will be described. Note that in the second embodiment, the same components as those in the first embodiment described above are denoted by the same reference numerals, description thereof is omitted, and different components are described in detail.
The configuration of the display panel of the organic EL display device according to the second embodiment, the configuration of each display pixel, and the pixel circuit are the same as those of the first embodiment described above. In the second embodiment, the driving method of the organic EL display device is different from that of the first embodiment.

The operation of the organic EL display device according to the second embodiment will be described. FIG. 10 shows a timing chart of control signals of the scanning line drive circuits 14a and 14b during the operation display during the display operation.
The operation of the pixel circuit 18 is divided into 1) reset operation, 2) threshold offset cancel operation, 3) write operation, 4) mobility correction operation, and 5) light emission operation.

  As shown in FIGS. 10 and 11, first, 1) a reset operation is performed. In the reset operation, from the scanning line driving circuits 14a and 14b, the level at which the pixel switch SST is turned off (off potential), here, the low level control signal SG, and the level at which the initialization switch IST is turned on (on potential). Here, the high level control signal IG, the level at which the output switch BCT is turned off and the reset switch RST is turned on, here, the low level control signal BG are output. As a result, the output switch BCT and the pixel switch SST are turned off (non-conducting state), the initialization switch IST and the reset switch RST are turned on (conducting state), and the reset operation is started.

  In the reset period, the initialization voltage signal VINI output from the initialization power supply line Vini is applied to the gate of the drive transistor DRT through the initialization switch IST. As a result, the gate potential of the drive transistor DRT is reset to a potential corresponding to the initialization voltage signal VINI, and the information of the previous frame is initialized. The initialization voltage signal VINI is set to 2V, for example.

  In addition, the reset voltage signal VRST output from the reset power supply wiring Vrst is applied to the source and drain of the drive transistor DRT through the reset switch RST. As a result, the source and drain potentials of the drive transistor DRT are reset to a potential corresponding to the reset voltage signal VRST, for example, −2 V, and the information of the previous frame is initialized.

  Subsequently, as shown in FIGS. 10 and 12, the control signal BG is turned on (high level), the control signal IG is kept on, and the control signal SG is kept off. As a result, the pixel switch SST and the reset switch RST are turned off, the output switch BCT and the initialization switch IST are turned on, and 2) the threshold value offset cancel operation is started.

  In the offset cancel period, the gate potential of the drive transistor DRT is fixed to VINI. Further, the output switch BCT is in an ON state, and a current flows from the voltage power supply line Vdd to the drive transistor DRT. The source potential of the drive transistor DRT absorbs and compensates for variations in TFT characteristics of the drive transistor while gradually reducing the amount of current flowing through the drain-source of the drive transistor DRT, with VRST written during the reset period as an initial value. However, it shifts to the high potential side. At the end of the cancel period, the source potential of the drive transistor DRT becomes VINI−Vth (threshold voltage of the drive transistor). As a result, the gate-source voltage of the drive transistor DRT reaches the cancel point, and a potential difference corresponding to the cancel point is stored in the storage capacitor Cs.

  Simultaneously with the offset cancel period, 3) signal write operation is started. In the signal writing period, the control signal BG is turned on (high level), the control signal IG is kept on, and the control signal SG is kept off. As a result, the pixel switch SST and the reset switch RST are turned off, and the output switch BCT and the initialization switch IST are turned on. Also, the respective video voltage signal potentials Vsig (R, G, B) are written to the video signal lines X (1 to n) of the RGB display pixels PX. This signal writing operation is performed simultaneously with the offset cancel operation.

  Subsequently, as shown in FIGS. 10 and 13, in the 4) mobility correction period, the control signal SG is turned on to turn on the pixel switch SST, and the control signal IG is turned off to turn the initialization switch IST off. The potential and the control signal BG are the potentials for turning on the output switch BCT and turning off the reset switch RST. Thereby, the initialization switch IST and the reset switch RST are turned off (non-conducting state), the pixel switch SST and the output switch BCT are turned on (conducting state), and the mobility correction operation is started.

In the mobility correction period, the video voltage signal Vsig is written from the video signal line X (1 to n) through the pixel switch SST to the gate of the drive transistor DRT. Further, a current flows from the voltage power supply line Vdd to the reference voltage power supply line Vss through the drive transistor DRT and the parasitic capacitance Co of the organic EL element 16. Immediately after the pixel switch SST is turned on, the gate potential of the drive transistor DRT is Vsig (R, G, B), and the source potential of the drive transistor DRT is
VINI-Vth + Cs (Vsig-VINI) / (Cs + Co)
It becomes. Thereafter, a current flows to the reference voltage power supply line Vss via the parasitic capacitance Co of the organic EL element 16, and at the end of the mobility correction period, the gate potential of the drive transistor is Vsig (R, G, B), the drive transistor DRT. The source potential of
VINI−Vth + ΔV1 + Cs (Vsig−VINI) / (Cs + Co)
It becomes. The absolute value of the ΔV1 potential increases as the mobility of the driving transistor DRT increases. Thereby, the variation in mobility of the drive transistor DRT is corrected.
In this embodiment, reset, offset cancellation, signal writing, and mobility correction are performed in one horizontal period.

  Next, as shown in FIGS. 10 and 14, the control signal SG is turned off (low level), and the pixel switch SST is turned off. Thereby, the gradation video voltage signal writing operation and the mobility correction operation are completed. At the same time or subsequently, the control signal BG becomes an on potential (high level) that turns the output switch BCT on and the reset switch RST off, and the control signal IG turns off the initialization switch IST off. It becomes a potential (low level). Accordingly, the reset switch RST, the initialization switch IST, and the pixel switch SST are turned off (non-conducting state), only the output switch BCT is turned on (conducting state), and the light emission operation is started.

In the light emission period, a drive current flows from the voltage power supply line Vdd to the drive transistor DRT of each of the R, G, and B display pixels PX through the output switch BCT and the reset power supply wiring Vrst. The drive transistor DRT outputs a drive current Ie having a current amount corresponding to the gate control voltage written in the storage capacitor Cs. This drive current Ie is supplied to the organic EL element 16. Thereby, the organic EL element 16 emits light with a luminance corresponding to the drive current Ie, and performs a light emission operation. The organic EL element 16 maintains the light emitting state until the control signal BG becomes the off potential again after one frame period.
The above-described reset operation, offset cancel operation, signal writing operation, mobility correction operation, and light emission operation are sequentially performed on each display pixel to display a desired image.

According to the organic EL display device configured as described above, during the light emission period, the current Ie flowing through the organic EL element 16 is the current value in the saturation region of the drive transistor DRT.
Iel = β × {(Vsig−VINI) × Co / (Cs + Co) −ΔV1} ² ,
β = μ · CoxW / 2L, (W: channel width, L: channel length)
Thus, the value does not depend on the threshold value Vth of the drive transistor DRT. Therefore, it is possible to eliminate the influence due to the variation in the threshold value of the driving transistor. Further, since ΔV1 has a larger absolute value as the mobility of the driving transistor is larger, the influence of the mobility can be compensated. Therefore, it is possible to suppress the occurrence of display defects, unevenness, and rough feeling due to these variations, and to perform high-quality image display.

  In addition, it is not necessary to switch a high-potential voltage power source to a plurality of potentials, so that the switching element can be downsized and the drive circuit can be upsized. Thereby, it is possible to narrow the frame of the display device. By providing the video signal line and the reset power supply wiring, the video signal line can be selectively driven, and the reset period and the offset cancellation period can be arbitrarily set. Therefore, it is possible to prevent insufficient writing of the video signal or insufficient cancellation of the threshold value and suppress the occurrence of display unevenness. Similarly, it is possible to sufficiently perform the mobility correction of the driving transistor that constitutes the pixel, to prevent display unevenness and to improve display quality. Furthermore, it is sufficient that at least one output switch is provided in one row, so that the number of elements can be reduced and high definition of the display panel can be achieved. By forming the light emission time control gate wiring and the reset control gate wiring with a common scanning line, the number of wirings can be reduced. As described above, an active matrix display device with high definition and improved display quality and a driving method thereof can be obtained.

  Note that the present invention is not limited to the above-described embodiment as it is, and can be embodied by modifying the constituent elements without departing from the scope of the invention in the implementation stage. In addition, various inventions can be formed by appropriately combining a plurality of components disclosed in the embodiment. For example, some components may be deleted from all the components shown in the embodiment. Furthermore, constituent elements over different embodiments may be appropriately combined.

  In the above-described embodiment, the light emission time control gate wiring for controlling the output switch BCT and the reset control gate wiring for controlling the reset switch RST are formed by the common first scanning line Sga (1 to m). However, the present invention is not limited to this, and they may be formed by independent scanning ships and driven by independent control signals. The plurality of reset power supply lines and the plurality of initialization power supply lines are not limited to each row of the pixel portion, and may be provided for each column.

  The semiconductor layer of the thin film transistor is not limited to polysilicon but can be composed of amorphous silicon. The transistors constituting each switch and drive transistor are not limited to the N-channel type, but may be a P-channel type. Similarly, the reset switch is not limited to the P channel type and may be an N channel type. The shapes and dimensions of the transistors and switches are not limited to the above-described embodiments, and can be changed as necessary. Although one output switch is provided for three display pixels, the number of output switches is not limited to this, and the number of output switches can be increased or decreased as necessary. The self-luminous elements constituting the display pixels are not limited to organic EL elements, and various display elements capable of self-luminance are applicable.

FIG. 1 is a plan view schematically showing the organic EL display device according to the first embodiment. FIG. 2 is a plan view showing an equivalent circuit of display pixels in the organic EL display device. FIG. 3 is a timing chart showing the potential change of the control signal in the organic EL display device. FIG. 4 is a diagram illustrating an on / off state of each switch during each operation period of the organic EL display device. FIG. 5 is a plan view showing an equivalent circuit of the display pixel during the reset operation of the organic EL display device. FIG. 6 is a plan view showing an equivalent circuit of the display pixel during the offset cancel operation of the organic EL display device. FIG. 7 is a plan view showing an equivalent circuit of a display pixel during signal current writing and pre-mobility correction operation of the organic EL display device. FIG. 8 is a plan view showing an equivalent circuit of the display pixel during the mobility correction operation of the organic EL display device. FIG. 9 is a plan view showing an equivalent circuit of the display pixel during the light emitting operation of the organic EL display device. FIG. 10 is a timing chart showing potential changes of the control signal in the organic EL display device according to the second embodiment. FIG. 11 is a plan view showing an equivalent circuit of the display pixel during the reset operation of the organic EL display device according to the second embodiment. FIG. 11 is a plan view showing an equivalent circuit of a display pixel during an offset cancel operation and a signal write operation of the organic EL display device according to the second embodiment. FIG. 12 is a plan view showing an equivalent circuit of the display pixel during the mobility correction operation of the organic EL display device according to the second embodiment. FIG. 14 is a plan view showing an equivalent circuit of the display pixel during the light emitting operation of the organic EL display device.

Explanation of symbols

8 ... Insulating substrate, 10 ... Organic EL panel, 11 ... Display area, 12 ... Controller,
14a, 14b ... scanning line drive circuit, 15 ... signal line drive circuit, 16 ... organic EL element,
18 ... Pixel circuit, SST ... Pixel switch, DRT ... Drive transistor,
IST ... Initialization switch, RST ... Reset switch, BCT ... Output switch,
X: Video signal line, Vdd: Voltage power line, Vss: Reference voltage power line,
Vrst ... Reset power supply wiring, Vini ... Initialization power supply wiring Sga (1-m) ... First scanning line, Sgb (1-m) ... Second scanning line,
Sgc (1 to m) ... the third scanning line,

Claims (10)

A plurality of pixel portions including a display element and a pixel circuit for supplying a driving current to the display element, the pixel parts being arranged in a matrix on the substrate;
A plurality of scanning lines connected to each row of the pixel portion;
A plurality of video signal lines connected to each column of the pixel portion;
A plurality of reset power supply wires each connected to the pixel portion;
A plurality of initialization power supply lines each connected to the pixel portion;
A high potential voltage power line and a low potential voltage power line;
A scanning line driving circuit that sequentially supplies a control signal to the plurality of scanning lines to scan the pixel portion line by line in a row unit;
A signal line driving circuit for supplying a video voltage signal to the video signal line in accordance with the line sequential scanning,
The pixel circuit includes:
A drive transistor connected in series with the display element between the low potential voltage power supply line and the high potential voltage power supply line, a first terminal connected to the display element, and a second terminal connected to the reset power supply line; ,
An output switch formed by a transistor, having a first terminal connected to a high potential voltage power source, a second terminal connected to a second terminal of the driving transistor, and a control terminal connected to the scan line;
A storage capacitor connected between a first terminal and a control terminal of the drive transistor;
An initialization switch formed by a transistor, having a first terminal connected to the initialization power line, a second terminal connected to a control terminal of the driving transistor, and a control terminal connected to the scan line;
Formed by a transistor, having a first terminal connected to the video signal line, a second terminal connected to a control terminal of the driving transistor, a control terminal connected to the scanning line, and a video voltage signal from the video signal line. A pixel switch for capturing and holding in the holding capacitor;
The scanning line driving circuit is provided for each reset power supply line, each having a first terminal connected to the reset power supply, a second terminal connected to the reset power supply line, and a control terminal connected to the scan line. An active matrix display device having a reset switch.   The scanning line for reset control connected to the control terminal of the reset switch and the scanning line for light emission time control connected to the control terminal of the output switch are formed by a common scanning line. Active matrix organic EL display device.   The active matrix display device according to claim 1, wherein one output switch is provided in common for a plurality of pixel portions.   The plurality of pixel portions include a red display pixel portion, a green display pixel portion, and a blue display pixel portion that are alternately arranged along each row, and the output switch is for red display. 2. The active matrix display device according to claim 1, wherein one active matrix type display device is provided in common for the three pixel portions of the pixel portion, the pixel portion for green display, and the pixel portion for blue display.   5. The active matrix display device according to claim 1, wherein the output switch, the pixel switch, the initialization switch, and the reset switch are formed of N-channel or P-channel thin film transistors. 6. A driving method of an active matrix display device according to any one of claims 1 to 5,
A reset period in which an initialization potential is applied from the initialization power supply wiring to the control terminal of the drive transistor, and a reset potential is applied from the reset power supply wiring to the first terminal of the drive transistor to initialize the drive transistor;
An offset cancellation period in which a current is passed from the high-potential voltage power source to the drive transistor in a state where an initialization potential is applied to the control terminal of the drive transistor, and a threshold offset of the drive transistor is canceled.
A video signal writing period for writing a video voltage signal to the video signal line;
A pre-mobility correction period in which current flows from the high-potential voltage power supply line to the low-potential voltage power supply line through the drive transistor;
A mobility correction period in which the video voltage signal is written from the video signal line to the control terminal of the drive transistor, and a current is passed from the high potential voltage power supply line to the low potential voltage power supply line through the drive transistor, and
A light emission period for supplying a drive current corresponding to the video voltage signal from the high-potential voltage power line through the drive transistor to the display element;
For driving an active matrix display device comprising:   The method for driving an active matrix display device according to claim 6, wherein the video signal writing period and the pre-movement correction period are performed simultaneously. A driving method of an active matrix display device according to any one of claims 1 to 5,
A reset period in which an initialization potential is applied from the initialization power supply wiring to the control terminal of the drive transistor, and a reset potential is applied from the reset power supply wiring to the first terminal of the drive transistor to initialize the drive transistor;
An offset cancellation period in which a current is passed from the high-potential voltage power source to the drive transistor in a state where an initialization potential is applied to the control terminal of the drive transistor, and a threshold offset of the drive transistor is canceled.
A video signal writing period for writing a video voltage signal to the video signal line;
A mobility correction period in which the video voltage signal is written from the video signal line to the control terminal of the drive transistor, and a current is passed from the high potential voltage power supply line to the low potential voltage power supply line through the drive transistor, and
A light emission period for supplying a drive current corresponding to the video voltage signal from the high-potential voltage power line through the drive transistor to the display element;
For driving an active matrix display device comprising:   The method for driving an active matrix display device according to claim 8, wherein the video signal writing period and the offset cancel period are performed simultaneously.   10. The active matrix type according to claim 6, wherein a red video voltage signal, a green video voltage signal, and a blue video voltage signal are sequentially output from the signal line driving circuit within one horizontal period. A driving method of a display device.

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