JP2014174220A - Method of driving display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method of driving a high definition display device which can relieve restriction of writing of a video signal.SOLUTION: A method of driving a display device includes a source initializing operation, a gate initializing operation, an offset cancellation operation, a video signal writing operation, and a displaying operation. After giving an initializing signal to a video signal line during j horizontal scanning period, video signals of j lines or more are given sequentially; j is 2 or larger natural number.

Description

  Embodiments described herein relate generally to a display device driving method.

  In recent years, the demand for flat display devices typified by liquid crystal display devices has been rapidly increased by taking advantage of the features of thinness, light weight, and low power consumption. Among them, an active matrix display device in which each pixel is provided with a pixel switch having a function of electrically separating an on-pixel and an off-pixel and holding a video signal to the on-pixel includes various types of information including portable information devices. It is used for the display.

  As such a flat-type active matrix display device, an organic EL display device using a self-luminous element has attracted attention, and research and development have been actively conducted. The organic EL display device has characteristics that it does not require a backlight, is suitable for moving image reproduction because of high-speed responsiveness, and is suitable for use in a cold region because the luminance does not decrease at low temperatures.

  In general, an organic EL display device includes a plurality of pixels arranged in a plurality of rows and a plurality of columns. Each pixel includes an organic EL element that is a self-light emitting element and a pixel circuit that supplies a drive current to the organic EL element, and performs a display operation by controlling the light emission luminance of the organic EL element.

  As a pixel circuit driving method, a method using a voltage signal is known. In addition, by switching the voltage power supply, switching between low and high, and outputting both the video signal and the initialization signal from the video signal wiring, the number of pixel constituent elements and the number of wirings can be reduced, and the pixel layout area There has been proposed a display device that achieves higher definition by reducing the size of the screen.

US Pat. No. 6,229,506 JP 2007-310311 A JP 2011-145622 A

By the way, as the display device becomes higher in definition as described above, there is a problem that one horizontal scanning period becomes relatively short, and writing of a video signal is restricted. For example, it may be difficult to secure a sufficient video signal writing period, or it may be difficult to increase the number of video signal writes.
The present invention has been made in view of the above points, and an object of the present invention is to provide a driving method for a high-definition display device that can ease restrictions on writing video signals.

A driving method of a display device according to an embodiment is as follows:
A plurality of pixels are provided in a matrix along the row direction and the column direction, and each of the plurality of pixels is connected to a display element connected between a high potential power source and a low potential power source, and to the display element. A drive transistor having a source electrode, a drain electrode connected to a reset line, and a gate electrode; and a connection between the high potential power source and the drain electrode of the drive transistor; and conduction between the high potential power source and the drain electrode of the drive transistor. An output switch that switches between a video signal line and a gate electrode of the drive transistor, and a pixel switch that switches whether a signal supplied through the video signal line is taken into the gate electrode side of the drive transistor. And a storage capacitor connected between the source electrode and the gate electrode of the driving transistor. That, in the driving method of the display device,
In a source initialization period, a reset signal is given to the drain electrode of the driving transistor through the reset wiring,
In a state where the reset signal is applied to the drain electrode of the drive transistor in the gate initialization period following the source initialization period, an initialization signal is applied to the gate electrode of the drive transistor through the video signal line and the pixel switch, Initializing the drive transistor;
In an offset cancellation period following the gate initialization period, a current is passed from the high potential power source to the drive transistor through the output switch in a state where an initialization signal is applied to the gate electrode of the drive transistor, and a threshold value of the drive transistor Cancel the offset,
In a video signal writing period subsequent to the offset cancel period, a video signal is applied to the gate electrode of the driving transistor through the video signal line and the pixel switch, and the low potential is supplied from the high potential power source through the output switch, the driving transistor, and the display element. Apply current to the power supply
In a display period following the video signal writing period, a driving current corresponding to the video signal is supplied from the high potential power source to the display element through the output switch and the driving transistor,
Assuming that a natural number of 2 or more is j, the initialization signal is given to the video signal line within the j horizontal scanning period, and then the video signals for j rows or more are given in order.

FIG. 1 is a plan view schematically showing the display device according to the first embodiment. FIG. 2 is an equivalent circuit diagram of a pixel of the display device of FIG. FIG. 3 is a partial cross-sectional view schematically showing an example of a structure that can be employed in the display device of FIG. FIG. 4 is a schematic diagram illustrating an arrangement configuration of pixels of the display device of Example 1 according to the first embodiment. FIG. 5 is a schematic diagram illustrating a pixel arrangement configuration of the display device of Example 2 according to the first embodiment. FIG. 6 is a schematic diagram illustrating a pixel arrangement configuration of the display device of Example 3 according to the first embodiment. FIG. 7 is a schematic diagram illustrating a pixel arrangement configuration of the display device of Example 4 according to the first embodiment. FIG. 8 is an enlarged plan view showing a non-display area of the display device of Example 3, and is a circuit diagram showing a switching circuit. FIG. 9 is an enlarged plan view showing a non-display area of the display device according to the fourth embodiment, and is a circuit diagram showing a switching circuit. FIG. 10 is a plan view showing a pixel of the display device of the first and second embodiments. FIG. 11 shows the control signal of the scanning line driving circuit when the RGBW square pixel arrangement of the first embodiment is adopted and the initialization operation is performed once and the video signal writing operation is performed twice in two horizontal scanning periods. It is a timing chart which shows. FIG. 12 shows the control signal of the scanning line driving circuit when the RGBW square pixel arrangement of the second embodiment is adopted and the initialization operation is performed once and the video signal writing operation is performed four times in four horizontal scanning periods. It is a timing chart which shows. FIG. 13 shows the arrangement of the RGBW vertical stripe pixels of the third embodiment, and the control signal for the scanning line driving circuit when the initialization operation is performed once and the video signal writing operation is performed four times in two horizontal scanning periods. It is a timing chart which shows. FIG. 14 shows the control signal of the scanning line driving circuit in the case where the arrangement configuration of the RGB vertical stripe pixels of Example 4 is adopted and the initialization operation is performed once and the video signal writing operation is performed six times in two horizontal scanning periods. It is a timing chart which shows. FIG. 15 is an equivalent circuit diagram of a pixel of the display device according to the second embodiment. FIG. 16 shows the scanning line when the RGBW square pixel arrangement of Example 1 of the second embodiment is adopted, and the initialization operation is performed once and the video signal writing operation is performed twice in two horizontal scanning periods. It is a timing chart which shows the control signal of a drive circuit. FIG. 17 shows the scanning line in the case where the RGBW square pixel arrangement configuration of Example 2 of the second embodiment is adopted, and the initialization operation is performed once and the video signal writing operation is performed four times in four horizontal scanning periods. It is a timing chart which shows the control signal of a drive circuit. FIG. 18 shows the scanning in the case where the arrangement of RGBW vertical stripe pixels of Example 3 of the second embodiment is adopted, and the initialization operation is performed once and the video signal writing operation is performed four times in two horizontal scanning periods. It is a timing chart which shows the control signal of a line drive circuit. FIG. 19 shows the scanning when the RGB vertical stripe pixel arrangement configuration of Example 4 of the second embodiment is adopted, and the initialization operation is performed once and the video signal writing operation is performed six times in two horizontal scanning periods. It is a timing chart which shows the control signal of a line drive circuit.

  Hereinafter, the display device and the driving method of the display device according to the first embodiment will be described in detail with reference to the drawings. In this embodiment, the display device is an active matrix display device, more specifically, an active matrix organic EL (electroluminescence) display device.

  FIG. 1 is a plan view schematically showing the display device according to the present embodiment. FIG. 2 is an equivalent circuit diagram of a pixel of the display device of FIG. FIG. 3 is a partial cross-sectional view schematically showing an example of a structure that can be employed in the display device of FIG. In FIG. 3, the display device is drawn such that the display surface, that is, the front surface or the light emitting surface faces upward, and the back surface faces downward. This display device is a top emission type organic EL display device adopting an active matrix driving method. In the present embodiment, the organic EL display device is a top emission type organic EL display device, but the present embodiment can be easily applied to a bottom emission type organic EL display device.

  As shown in FIG. 1, the display device according to the present embodiment is configured as, for example, an active matrix type display device of type 2 or more, and includes a display panel DP and a controller 12 that controls the operation of the display panel DP. It is out. In this embodiment, the display panel DP is an organic EL panel.

  The display panel DP includes an insulating substrate SUB having light transmissivity such as a glass plate, m × n pixels PX arranged in a matrix on the display region R1 of the insulating substrate SUB, and a plurality (m / 2) of pixels. The first scanning line Sga (1 to m / 2), the plurality (m) of second scanning lines Sgb (1 to m), and the plurality of (m / 2) third scanning lines Sgc (1 to 1). m / 2), a plurality (m / 2) of reset wirings Sgr (1 to m / 2), and a plurality (n) of video signal lines VL (1 to n).

  The pixels PX are arranged m in the column direction Y and n in the row direction X. The first scanning line Sga, the second scanning line Sgb, and the reset wiring Sgr are provided to extend in the row direction X. The reset wiring Sgr is formed of a plurality of electrodes that are electrically connected to each other. The video signal line VL extends in the column direction Y.

  As shown in FIGS. 1 and 2, the display panel DP includes a high potential power supply line SLa fixed to the high potential Pvdd and a low potential power supply line SLb fixed to the low potential Pvss. The high potential power supply line SLa is connected to a high potential power supply, and the low potential power supply line SLb is connected to a low potential power supply (reference potential power supply).

  The display panel DP has scanning line driving circuits YDR1 and YDR2 that sequentially drive the first scanning line Sga, the second scanning line Sgb, and the third scanning line Sgc for each row of the pixels PX, and a signal line drive that drives the video signal line VL. A circuit XDR is provided. The scanning line drive circuits YDR1 and YDR2 and the signal line drive circuit XDR are integrally formed on the non-display area R2 outside the display area R1 of the insulating substrate SUB, and constitute the drive unit 10 together with the controller 12.

  Each pixel PX includes a display element and a pixel circuit that supplies a drive current to the display element. The display element is, for example, a self-luminous element. In this embodiment, an organic EL diode OLED (hereinafter simply referred to as a diode OLED) including at least an organic light emitting layer as a photoactive layer is used.

  As shown in FIG. 2, the pixel circuit of each pixel PX is a voltage signal type pixel circuit that controls light emission of the diode OLED in accordance with a video signal composed of a voltage signal, and includes a pixel switch SST, a drive transistor DRT, a storage capacitor Cs and auxiliary capacitance Cad are included. The holding capacitor Cs and the auxiliary capacitor Cad are capacitors. The auxiliary capacitor Cad is an element provided for adjusting the amount of light emission current, and may be unnecessary depending on circumstances. The capacitance part Cel is the capacitance of the diode OLED itself (parasitic capacitance of the diode OLED). The diode OLED also functions as a capacitor.

  Each pixel PX includes an output switch BCT. A plurality of pixels PX adjacent in the column direction Y share the output switch BCT. In this embodiment, four or six pixels PX adjacent in the row direction X and the column direction Y share one output switch BCT. The scanning line driving circuit YDR2 (or the scanning line driving circuit YDR1) is provided with a plurality of reset switches RST. The reset switch RST and the reset wiring Sgr are connected one to one.

  Here, the pixel switch SST, the drive transistor DRT, the output switch BCT, and the reset switch RST are composed of TFTs (thin film transistors) of the same conductivity type, for example, N-channel type.

  In the display device according to the present embodiment, the TFTs constituting each driving transistor and each switch are all formed in the same process and the same layer structure, and are top-gate thin film transistors using polysilicon as the semiconductor layer.

  Each of the pixel switch SST, the drive transistor DRT, the output switch BCT, and the reset switch RST has a first terminal, a second terminal, and a control terminal. In this embodiment, the first terminal is a source electrode, the second terminal is a drain electrode, and the control terminal is a gate electrode.

  In the pixel circuit of the pixel PX, the drive transistor DRT and the output switch BCT are connected in series with the diode OLED between the high potential power supply line SLa and the low potential power supply line SLb. The high potential power line SLa (high potential Pvdd) is set to a potential of 10 V, for example, and the low potential power line SLb (low potential Pvss) is set to a potential of 1.5 V, for example.

  In the output switch BCT, the drain electrode is connected to the high potential power supply line SLa, the source electrode is connected to the drain electrode of the drive transistor DRT, and the gate electrode is connected to the first scanning line Sga. Thus, the output switch BCT is controlled to be on (conductive state) and off (non-conductive state) by the control signal BG (1 to m / 2) from the first scanning line Sga. The output switch BCT controls the light emission time of the diode OLED in response to the control signal BG.

  In the drive transistor DRT, the drain electrode is connected to the source electrode of the output switch BCT and the reset wiring Sgr, and the source electrode is connected to one electrode (here, the anode) of the diode OLED. The other electrode (here, the cathode) of the diode OLED is connected to the low potential power line SLb. The drive transistor DRT outputs a drive current having a current amount corresponding to the video signal Vsig to the diode OLED.

  In the pixel switch SST, the source electrode is connected to the video signal line VL (1 to n), the drain electrode is connected to the gate electrode of the driving transistor DRT, and the gate electrode functions as a signal writing control gate wiring. It is connected to Sgb (1 to m). The pixel switch SST is on / off controlled by a control signal SG (1 to m) supplied from the second scanning line Sgb. The pixel switch SST controls connection / disconnection between the pixel circuit and the video signal line VL (1-n) in response to the control signal SG (1-m), and the corresponding video signal line VL (1 To n) capture the video signal Vsig into the pixel circuit.

  The reset switch RST is provided in the scanning line driving circuit YDR2 every two rows. The reset switch RST is connected between the drain electrode of the drive transistor DRT and the reset power supply. In the reset switch RST, the source electrode is connected to the reset power supply line SLc connected to the reset power supply, the drain electrode is connected to the reset wiring Sgr, and the gate electrode is connected to the third scanning line Sgc functioning as a reset control gate wiring. Has been. As described above, the reset power supply line SLc is connected to the reset power supply and is fixed to the reset potential Vrst that is a constant potential.

  The reset switch RST switches between the reset power supply line SLc and the reset wiring Sgr in a conductive state (ON) or a non-conductive state (OFF) in accordance with a control signal RG (1 to m / 2) given through the third scanning line Sgc. Switch. By switching the reset switch RST to the on state, the potential of the drain electrode (source electrode) of the drive transistor DRT is initialized.

  On the other hand, the controller 12 shown in FIG. 1 is formed on a printed circuit board (not shown) arranged outside the display panel DP, and controls the scanning line driving circuits YDR1 and YDR2 and the signal line driving circuit XDR. The controller 12 receives a digital video signal and a synchronization signal supplied from the outside, and generates a vertical scanning control signal for controlling the vertical scanning timing and a horizontal scanning control signal for controlling the horizontal scanning timing based on the synchronizing signal.

  The controller 12 supplies the vertical scanning control signal and the horizontal scanning control signal to the scanning line driving circuits YDR1 and YDR2 and the signal line driving circuit XDR, respectively, and the digital video signal and the initial stage are synchronized with the horizontal and vertical scanning timings. The signal is supplied to the signal line drive circuit XDR.

  The signal line drive circuit XDR converts the video signal sequentially obtained in each horizontal scanning period to the analog format under the control of the horizontal scanning control signal, and converts the video signal Vsig corresponding to the gradation to the plurality of video signal lines VL (1 to n). In parallel. The signal line drive circuit XDR supplies the initialization signal Vini to the video signal line VL.

The scanning line driving circuits YDR1 and YDR2 include a shift register, an output buffer, and the like (not shown), transfer a horizontal scanning start pulse supplied from the outside sequentially to the next stage, and three types of pixels PX in each row via the output buffer Control signals, that is, control signals BG (1 to m / 2), SG (1 to m), and RG (1 to m / 2) are supplied (FIG. 2). Note that the control signal RG is not directly supplied to the pixel PX, but a predetermined voltage is supplied from the reset power supply line SLc fixed to the reset potential Vrst at a predetermined timing according to the control signal RG.
Accordingly, the first scanning line Sga, the second scanning line Sgb, and the third scanning line Sgc are driven by the control signals BG, SG, and RG, respectively.

Next, the configuration of the drive transistor DRT and the diode OLED will be described in detail with reference to FIG.
The N-channel TFT in which the driving transistor DRT is formed includes a semiconductor layer SC. The semiconductor layer SC is formed on the undercoat layer UC formed on the insulating substrate SUB. The semiconductor layer SC is, for example, a polysilicon layer including a p-type region and an n-type region.

  The semiconductor layer SC is covered with a gate insulating film GI. On the gate insulating film GI, the gate electrode G of the drive transistor DRT is formed. The gate electrode G is opposed to the semiconductor layer SC. An interlayer insulating film II is formed on the gate insulating film GI and the gate electrode G.

  A source electrode SE and a drain electrode DE are further formed on the interlayer insulating film II. The source electrode SE and the drain electrode DE are connected to the source region and the drain region of the semiconductor layer SC through contact holes formed in the interlayer insulating film II and the gate insulating film GI, respectively. A passivation film PS is formed on the source electrode SE and the drain electrode DE.

  The diode OLED includes a pixel electrode PE, an organic layer ORG, and a counter electrode CE. In this embodiment, the pixel electrode PE is an anode, and the counter electrode CE is a cathode.

  A pixel electrode PE is formed on the passivation film PS. The pixel electrode PE is connected to the source electrode SE of the driving transistor DRT through a contact hole provided in the passivation film PS. In this example, the pixel electrode PE is a back electrode having light reflectivity.

  A partition insulating layer PI is further formed on the passivation film PS. In the partition insulating layer PI, a through hole is provided at a position corresponding to the pixel electrode PE, or a slit is provided at a position corresponding to a column or row formed by the pixel electrode PE. Here, as an example, the partition insulating layer PI has a through hole at a position corresponding to the pixel electrode PE.

  On the pixel electrode PE, an organic layer ORG including a light emitting layer is formed as an active layer. The light emitting layer is, for example, a thin film containing a luminescent organic compound whose emission color is red, green, blue, or achromatic. The organic layer ORG can further include a hole injection layer, a hole transport layer, a hole blocking layer, an electron transport layer, an electron injection layer, and the like in addition to the light emitting layer.

  Note that the light emission color of the diode OLED is not necessarily divided into red, green, blue, or achromatic color, and may be only achromatic color. In this case, the diode OLED can emit red, green, blue, or achromatic color by combining with red, green, and blue color filters.

  The partition insulating layer PI and the organic layer ORG are covered with the counter electrode CE. In this example, the counter electrode CE is an electrode connected to each other between the pixels PX, that is, a common electrode. In this example, the counter electrode CE is a cathode and a light-transmitting front electrode. For example, the counter electrode CE is electrically connected to an electrode wiring (not shown) formed in the same layer as the source electrode SE and the drain electrode DE through a contact hole provided in the passivation film PS and the partition insulating layer PI. Connected.

  In the diode OLED having such a structure, when the holes injected from the pixel electrode PE and the electrons injected from the counter electrode CE are recombined inside the organic layer ORG, the organic molecules constituting the organic layer ORG are changed. Excitons are generated by excitation. The excitons emit light in the process of radiation deactivation, and the light is emitted from the organic layer ORG to the outside through the transparent counter electrode CE.

  Next, the arrangement configuration of the plurality of pixels PX will be described. FIG. 4 is a schematic diagram showing the arrangement configuration of the pixels PX of Example 1 according to the present embodiment. FIG. 5 is a schematic diagram illustrating an arrangement configuration of the pixels PX of Example 2 according to the present embodiment. FIG. 6 is a schematic diagram showing the arrangement configuration of the pixels PX of Example 3 according to the present embodiment. FIG. 7 is a schematic diagram illustrating an arrangement configuration of the pixels PX of Example 3 according to the present embodiment.

  As shown in FIG. 4, the pixel PX is a so-called RGBW square pixel. The plurality of pixels PX include a first pixel, a second pixel adjacent to the first pixel in the column direction Y, a third pixel adjacent to the first pixel in the row direction X, and an adjacent second pixel in the row direction X. The third pixel is adjacent to the third pixel in the column direction Y. The first to fourth pixels include a pixel PX configured to display a red image, a pixel PX configured to display a green image, a pixel PX configured to display a blue image, And a pixel PX configured to display an achromatic image. The picture element P has first to fourth pixels.

  For example, any two of red, green, blue and achromatic pixels PX are arranged in even rows, and the remaining two are arranged in odd rows. In the first embodiment, red and green pixels PX are arranged in odd rows, and achromatic and blue pixels PX are arranged in even rows. The output switch BCT is shared by the first to fourth pixels.

  Here, the output switch BCT is shared by the pixels PX in the 2k−1 and 2k rows, and is shared by the pixels PX in the 2k + 1 and 2k + 2 rows. From the above, the number of first scanning lines Sga and reset lines Sgr is m / 2.

  The k-th output unit 30 is connected to the k-th first scanning line Sga and the k-th reset wiring Sgr. From the above, the number of output units 30 is m / 2. The k-th output unit 20 is connected to the 2k−1 (row) second scanning line Sgb and the 2kth (row) second scanning line Sgb. Since the output unit 20 is connected to the two second scanning lines Sgb, the number of the output units 20 is m / 2.

  As illustrated in FIG. 5, the k-th output unit 30 is connected to the 2k−1 and 2kth first scanning lines Sga, and is connected to the 2k−1 and 2kth reset lines Sgr. From the above, the number of output units 30 is m / 4.

  The k-th output unit 20 includes 4k-3rd (row), 4k-2th (row), 4k-1th (row), and 4kth (row) second scanning lines Sgb. It is connected. Since the output unit 20 is connected to the four second scanning lines Sgb, the number of the output units 20 is m / 4.

  As shown in FIG. 6, the pixel PX is a so-called vertical stripe pixel. In the row direction X, red pixels PX, green pixels PX, blue pixels PX, and achromatic pixels PX are alternately arranged. In the column direction Y, pixels PX configured to display the same color image are arranged.

  The red (R) pixel PX, the green (G) pixel PX, the blue (B) pixel PX, and the achromatic (W) pixel PX form a picture element P. In the third embodiment, the picture element P has four (four colors) pixels PX.

  The output switch BCT is shared by four adjacent pixels (two adjacent in the column direction Y and two adjacent in the row direction X). From the above, the number of first scanning lines Sga and third scanning lines Sgc is m / 2.

  As shown in FIG. 7, the pixel PX is a so-called vertical stripe pixel. In the row direction X, red pixels PX, green pixels PX, and blue pixels PX are alternately arranged. In the column direction Y, pixels PX configured to display the same color image are arranged.

  The red (R) pixel PX, the green (G) pixel PX, and the blue (B) pixel PX form a picture element P. In the third embodiment, the picture element P has three (three colors) pixels PX.

  The output switch BCT is shared by six adjacent pixels PX (two adjacent in the column direction Y and three adjacent in the row direction X). From the above, the number of first scanning lines Sga and third scanning lines Sgc is m / 2.

  Next, the switching circuit will be described. The display device may further include a switching circuit. In the present embodiment, the display devices of Examples 3 and 4 further include a switching circuit. Note that the display devices of Examples 1 and 2 do not have a switching circuit. FIG. 8 is an enlarged plan view showing the non-display area R2 of the display device of the third embodiment, and is a circuit diagram showing the switching circuit 13. As shown in FIG. FIG. 9 is an enlarged plan view showing the non-display area R2 of the display device of the fourth embodiment, and is a circuit diagram showing the switching circuit 13. As shown in FIG.

  As shown in FIG. 8, in the third embodiment, the switching circuit 13 includes a plurality of switching element groups 55, and each switching element group 55 includes a plurality of switching elements 56. Each switching element group 55 has two switching elements 56. The switching circuit 13 is a 1/2 multiplexer circuit. The switching element 56 is formed of, for example, a p-channel type TFT, but may be formed of an n-channel type TFT.

  The switching circuit 13 is connected to a plurality of video signal lines VL. The switching circuit 13 is connected to the signal line drive circuit XDR via the connection wiring 57. The number of connection wirings 57 is ½ of the number of video signal lines VL.

  The switching element 56 is turned on / off by the control signals ASW1 and ASW2 so that two video signal lines VL are time-division driven per output (connection wiring 57) of the signal line driving circuit XDR. These control signals ASW1 and ASW2 are respectively supplied to the switching element 56 via a plurality of control wirings 58. In the horizontal scanning period, the ON control signals ASW1 and ASW2 are given to the switching element 56 a plurality of times at a predetermined timing, and the initialization signal Vini and the desired video signal Vsig are written to the pixels PX arranged in the row direction X. It is. Here, j is a natural number of 2 or more.

  As shown in FIG. 9, in the fourth embodiment, each switching element group 55 has three switching elements 56. The switching circuit 13 is a 1/3 multiplexer circuit. The number of connection wirings 57 is 1/3 of the number of video signal lines VL.

  The switching element 56 is turned on / off by the control signals ASW1 to ASW3 so that three video signal lines VL are time-division driven per output (connection wiring 57) of the signal line driving circuit XDR. These control signals ASW 1 to ASW 3 are respectively supplied to the switching element 56 via a plurality of control wirings 58. Then, in the j horizontal scanning period, the ON control signals ASW1 to ASW3 are given to the switching element 56 a plurality of times at a predetermined timing, and the initialization signal Vini and the desired video signal Vsig are written to the pixels PX arranged in the row direction X. It is. In addition, the switching circuit 13 of the third embodiment is formed in the same manner as the switching circuit 13 of the second embodiment.

  Next, the planar structure of the pixel PX according to the present embodiment will be described. Here, an RGBW square arrangement pixel will be described as a representative example. FIG. 10 is a plan view showing the pixel PX of the display devices of Examples 1 and 2 according to this embodiment.

As shown in FIG. 10, the output switch BCT is shared by four pixels PX (one picture element P). In order to efficiently arrange the elements in the pixel circuit, the four pixels PX sharing (sharing) the output switch BCT include a drive transistor DRT, a pixel switch SST, a video signal line VL, a storage capacitor Cs, an auxiliary capacitor Cad, The two scanning lines Sgb are arranged so as to be substantially line symmetric in the column direction and the row direction with the output switch BCT as the center.
Here, in the present embodiment, the terminology of the pixel PX and the picture element P has been described, but the pixel can be rephrased as a sub-pixel. In this case, the picture element is a pixel.

  The arrangement of the picture elements P (pixels PX) is not limited to the example shown in FIG. 10 and can be variously modified. For example, two pixels PX adjacent in the column direction Y may share a contact hole. Specifically, the pixel switches SST of two pixels PX adjacent in the column direction Y may share a contact hole formed in the insulating film (gate insulating film GI, interlayer insulating film II). The two pixels PX form different picture elements P. By using the contact hole, the video signal line VL can be connected to the source region of the semiconductor layer of the pixel switch SST.

  Next, the operation of the display device (organic EL display device) configured as described above will be described. 11, FIG. 12, FIG. 13 and FIG. 14 are timing charts showing control signals of the scanning line driving circuits YDR1 and YDR2 during operation display, respectively.

  FIG. 11 adopts the RGBW square pixel arrangement configuration (FIG. 4) of Example 1 according to the first embodiment, and performs initialization operation once and video signal writing operation twice in two horizontal scanning periods. 6 is a timing chart showing a control signal of the scanning line driving circuit in the case of FIG. FIG. 12 adopts the RGBW square pixel arrangement configuration of Example 2 according to the first embodiment (FIG. 5), and performs initialization operation once and video signal writing operation four times in four horizontal scanning periods. 6 is a timing chart showing a control signal of the scanning line driving circuit in the case of FIG.

  FIG. 13 employs the RGBW vertical stripe pixel arrangement configuration of Example 3 according to the first embodiment described above (FIG. 6), with one initialization operation and four video signal writing operations in two horizontal scanning periods. 6 is a timing chart showing a control signal of the scanning line driving circuit in the case of performing. FIG. 14 adopts the arrangement configuration of RGB vertical stripe pixels (FIG. 7) of Example 4 according to the first embodiment, and performs initialization operation once and image signal writing operation six times in two horizontal scanning periods. 6 is a timing chart showing a control signal of the scanning line driving circuit in the case of performing.

  In the driving method of the display device of the first to fourth embodiments, the offset cancel operation is provided twice in order for the pixel PX to display (emit light) an image. However, the number of offset cancel operations is not limited to two, and may be one or three or more times.

  For example, the scanning line driving circuits YDR1 and YDR2 generate a pulse having a width of one horizontal scanning period (Tw-Starta) corresponding to each horizontal scanning period from a start signal (STV1 to STV3) and a clock (CKV1 to CKV3). The pulses are output as control signals BG, SG, RG. Here, one horizontal scanning period is set to 1H.

  The operation of the pixel circuit includes a source initialization operation performed during the source initialization period Pis, a gate initialization operation performed during the gate initialization period Pig, an offset cancellation (OC) operation performed during the offset cancellation period Po, It is divided into a video signal writing operation performed during the signal writing period Pw and a display operation (light emitting operation) performed during the display period Pd (light emission period).

  As shown in FIGS. 11 to 14, 1, and 2, the driving unit 10 first performs a source initialization operation. In the source initialization operation, the control signal SG turns off the pixel switch SST from the scanning line drive circuits YDR1 and YDR2, and the control signal BG turns off the output switch BCT. The level (off potential: low level here) and the control signal RG are set to a level (on potential: high level here) that turns on the reset switch RST.

  The output switch BCT and the pixel switch SST are turned off (non-conductive state), the reset switch RST is turned on (conductive state), and the source initialization operation is started. When the reset switch RST is turned on, the source electrode and drain electrode of the drive transistor DRT are reset to the same potential as the potential of the reset power supply (reset potential Vrst), and the source initialization operation is completed. Here, the reset power supply (reset potential Vrst) is set to −2 V, for example.

  Next, the driving unit 10 performs a gate initialization operation. In the gate initialization operation, the control signal SG turns on the pixel switch SST from the scanning line drive circuits YDR1 and YDR2 (on potential: high level here), and the control signal BG turns off the output switch BCT. The level and control signal RG is set to a level that turns on the reset switch RST. The output switch BCT is turned off, the pixel switch SST and the reset switch RST are turned on, and the gate initialization operation is started.

  In the gate initialization period Pig, the initialization signal Vini (initialization voltage) output from the video signal line VL is applied to the gate electrode of the driving transistor DRT through the pixel switch SST. As a result, the potential of the gate electrode of the drive transistor DRT is reset to a potential corresponding to the initialization signal Vini, and information of the previous frame is initialized. The voltage level of the initialization signal Vini is set to 2V, for example.

  In the display device having the switching circuit 13, all the switching elements 56 are switched on by the control signals (ASW1, ASW2, ASW3) in the gate initialization period Pig. As a result, the initialization signal Vini is given to all the video signal lines VL.

  Subsequently, the drive unit 10 performs an offset cancel operation. The control signal SG is turned on, the control signal BG is turned on (high level), and the control signal RG is turned off (low level). As a result, the reset switch RST is turned off, the pixel switch SST and the output switch BCT are turned on, and the threshold value offset cancel operation is started.

  In the offset cancel period Po, the initialization signal Vini is applied to the gate electrode of the drive transistor DRT through the video signal line VL and the pixel switch SST, and the potential of the gate electrode of the drive transistor DRT is fixed. In the offset cancel period Po, all the switching elements 56 of the display device having the switching circuit 13 are switched on.

  Further, the output switch BCT is in an ON state, and a current flows from the high potential power supply line SLa to the drive transistor DRT. The potential of the source electrode of the drive transistor DRT is initially set to the potential (reset potential Vrst) written in the source initialization period Pis, and the current flowing through between the drain electrode and the source electrode of the drive transistor DRT is gradually reduced. In the meantime, the TFT shifts to the high potential side while absorbing and compensating for the TFT characteristic variation of the drive transistor DRT. In the present embodiment, the offset cancellation period Po is set to a time of about 1 μsec, for example.

  At the end of the offset cancellation period Po, the potential of the source electrode of the drive transistor DRT becomes Vini−Vth. Vini is the voltage value of the initialization signal Vini, and Vth is the threshold voltage of the drive transistor DRT. As a result, the voltage between the gate electrode and the source electrode of the drive transistor DRT reaches the cancel point (Vgs = Vth), and the potential difference corresponding to the cancel point is stored (held) in the storage capacitor Cs. It should be noted that the offset cancellation period Po can be provided twice as in the examples shown in FIGS.

  Subsequently, in the video signal writing period Pw, the control signal SG sets the pixel switch SST to an on state, the control signal BG sets the output switch BCT to an on state, and the control signal RG sets the reset switch RST to an off state. Set to level. Then, the pixel switch SST and the output switch BCT are turned on, the reset switch RST is turned off, and the video signal writing operation is started.

In the video signal writing period Pw, the video signal Vsig is written from the video signal line VL through the pixel switch SST to the gate electrode of the drive transistor DRT. In addition, a current flows from the high potential power line SLa to the drive transistor DRT via the output switch BCT. Immediately after the pixel switch SST is turned on, the potential of the gate electrode of the driving transistor DRT is Vsig (R, G, B, W), and the potential of the source electrode of the driving transistor DRT is Vini−Vth + Cs (Vsig−Vini) / ( Cs + Cel + Cad).
Vsig is the voltage value of the video signal Vsig, Cs is the capacity of the storage capacitor Cs, Cel is the capacity of the capacitor part Cel, and Cad is the capacity of the auxiliary capacitor Cad.

Thereafter, a current flows through the low-potential power line SLb via the capacitor Cel of the diode OLED, and at the end of the video signal writing period Pw, the potential of the gate electrode of the drive transistor DRT is Vsig (R, G, B, W). The potential of the source electrode of the drive transistor DRT is Vini−Vth + ΔV1 + Cs (Vsig−Vini) / (Cs + Cel + Cad). The relationship between the current Idrt flowing through the driving transistor DRT and the capacitance Cs + Cel + Cad is expressed by the following equation, and ΔV1 corresponds to the voltage value of the video signal Vsig determined from the following equation, the video writing period Pw, and the transistor mobility. This is the displacement of the potential of the source electrode.

here,
Idrt = β × (Vgs−Vth) ²
= {(Vsig−Vini) × (Cel + Cad) / (Cs + Cel + Cad)} ²
It is.

  β is defined by the following equation.

β = μ × Cox × W / 2L
Here, W is the channel width of the drive transistor DRT, L is the channel length of the drive transistor DRT, μ is the carrier mobility, and Cox is the gate capacitance per unit area. Thereby, the variation in mobility of the drive transistor DRT is corrected.

  In the display device having the switching circuit 13, the switching element 56 of each switching element group 55 is sequentially turned on by the control signal (ASW1, ASW2, ASW3) during the video writing period Pw. By driving the video signal line VL in a time-sharing manner, the video signal Vsig is sequentially given to all the video signal lines VL.

  Finally, in the display period Pd, the control signal SG is at a level at which the pixel switch SST is turned off, the control signal BG is at a level at which the output switch BCT is turned on, and the control signal RG is at a level at which the reset switch RST is turned off. Is set. The output switch BCT is turned on, the pixel switch SST and the reset switch RST are turned off, and the display operation is started.

  The drive transistor DRT outputs a drive current Iel having a current amount corresponding to the gate control voltage written in the storage capacitor Cs. This drive current Iel is supplied to the diode OLED. As a result, the diode OLED emits light with a luminance corresponding to the drive current Iel, and a display operation is performed. The diode OLED maintains the light emitting state after one frame period until the control signal BG becomes the off potential again.

  The above-described source initialization operation, gate initialization operation, offset cancellation operation, video signal writing operation, and display operation are sequentially performed on each pixel PX, thereby displaying a desired image.

Next, the initialization signal and video signal writing operations in the driving methods of the display devices of the first to fourth embodiments will be described.
An initialization signal and video signal writing operation in the driving method of the display device of the first embodiment will be described.
As shown in FIG. 1, FIG. 2, FIG. 4 and FIG. Here, the one picture element P is in the 2k-1 and 2k rows and has four pixels PX located in the i and i + 1 columns. In the above driving method, the initialization operation is performed once in two horizontal scanning periods, and then the video signal writing operation is performed twice. Although not described, a plurality of picture elements P arranged in the row direction X are similarly driven in the two horizontal scanning periods.

  First, in the initialization operation, the signal line drive circuit XDR gives the initialization signal Vini to the video signal lines VL in the i and i + 1 columns, and the scan line drive circuit YDR1 in the second scan lines Sgb in the 2k-1 and 2k rows. Is supplied with a control signal SG at a level for turning on the pixel switch SST.

  Next, the signal line drive circuit XDR supplies the video signal Vsig for red display to the video signal line VL in the i-th column and the video signal Vsig for green display to the video signal line VL in the i + 1-th column. The scanning line drive circuit YDR1 supplies a control signal SG at a level for turning on the pixel switch SST to the second scanning line Sgb in the 2k-1 row, and turns off the pixel switch SST in the second scanning line Sgb in the 2k row. A control signal SG at a level to be brought into a state is given.

  Thereafter, the signal line drive circuit XDR gives the achromatic signal video signal Vsig to the i-th video signal line VL, and gives the blue display video signal Vsig to the i + 1-th video signal line VL. The scanning line driving circuit YDR1 supplies a control signal SG at a level for turning off the pixel switch SST to the second scanning line Sgb in the 2k-1 row, and turns on the pixel switch SST in the second scanning line Sgb in the 2k row. A control signal SG at a level to be brought into a state is given.

  By adopting the above driving method of the display device, the initialization signal Vini can be collectively applied to the pixels PX in two consecutive rows, and the number of initialization operations in two horizontal scanning periods can be reduced to one.

An initialization signal and video signal writing operation in the driving method of the display device of the second embodiment will be described.
As shown in FIG. 1, FIG. 2, FIG. 5 and FIG. Here, the two picture elements P are in the 4k-3, 4k-2, 4k-1, and 4k rows, and have eight pixels PX located in the i and i + 1 columns. In the above driving method, the initialization operation is performed once in four horizontal scanning periods, and then the video signal writing operation is performed four times. Although not described, a plurality of picture elements P arranged in the row direction X are similarly driven in the four horizontal scanning periods.

  First, in the initialization operation, the signal line driving circuit XDR gives the initialization signal Vini to the video signal lines VL in the i and i + 1 columns, and the scanning line driving circuit YDR1 is 4k-3, 4k-2, 4k-1 and 4k. A control signal SG at a level for turning on the pixel switch SST is applied to the second scanning line Sgb in the row.

  Next, the signal line drive circuit XDR supplies the video signal Vsig for red display to the video signal line VL in the i-th column and the video signal Vsig for green display to the video signal line VL in the i + 1-th column. The scanning line drive circuit YDR1 gives a control signal SG at a level for turning on the pixel switch SST to the second scanning line Sgb in the 4k-3 row, and the second scanning in the 4k-2, 4k-1, and 4k rows. A control signal SG at a level for turning off the pixel switch SST is applied to the line Sgb.

  Subsequently, the signal line drive circuit XDR gives the video signal Vsig for red display to the video signal line VL in the i-th column and the video signal Vsig for green display to the video signal line VL in the i + 1-th column. The scanning line driving circuit YDR1 gives a control signal SG at a level for turning on the pixel switch SST to the second scanning line Sgb in the 4k-1 row, and the second scanning in the 4k-3, 4k-2, and 4k rows. A control signal SG at a level for turning off the pixel switch SST is applied to the line Sgb.

  Next, the signal line driving circuit XDR gives the achromatic signal video signal Vsig to the i-th video signal line VL, and gives the blue color video signal Vsig to the i + 1-th video signal line VL. The scanning line drive circuit YDR1 supplies a control signal SG at a level for turning on the pixel switch SST to the second scanning line Sgb in the 4k-2 row, and the second scanning in the 4k-3, 4k-1, and 4k rows. A control signal SG at a level for turning off the pixel switch SST is applied to the line Sgb.

  Thereafter, the signal line drive circuit XDR gives the achromatic signal video signal Vsig to the i-th video signal line VL, and gives the blue display video signal Vsig to the i + 1-th video signal line VL. The scanning line driving circuit YDR1 gives a control signal SG at a level for turning on the pixel switch SST to the second scanning line Sgb in the 4k row, and the second scanning in the 4k-3, 4k-2, and 4k-1 rows. A control signal SG at a level for turning off the pixel switch SST is applied to the line Sgb.

  By adopting the above driving method of the display device, the initialization signal Vini can be collectively applied to the pixels PX in four consecutive rows, and the number of initialization operations in the four horizontal scanning periods can be reduced to one. Further, when the video signal Vsig is sequentially given, the video signal Vsig can be continuously given to a plurality of pixels PX that display the same color image.

An initialization signal and video signal writing operation in the driving method of the display device of the third embodiment will be described.
As shown in FIGS. 1, 2, 6, 8, and 13, attention is paid to a method for driving two picture elements P of the display device of the third embodiment. Here, the two picture elements P are in the 2k-1 and 2k rows and have eight pixels PX located in the i, i + 1, i + 2, and i + 3 columns. In the above driving method, the initialization operation is performed once in two horizontal scanning periods, and then the video signal writing operation is performed four times. Although not described, a plurality of picture elements P arranged in the row direction X are similarly driven in the two horizontal scanning periods.

  First, in the initialization operation, the control signals ASW1 and ASW2 to be turned on are supplied to the switching element 56, and all the switching elements 56 connected to the video signal lines VL in the i, i + 1, i + 2, and i + 3 columns are switched on. It is done. The signal line drive circuit XDR gives an initialization signal Vini to the video signal lines VL in the i, i + 1, i + 2 and i + 3 columns, and the scan line drive circuit YDR1 applies a pixel switch to the second scan lines Sgb in the 2k-1 and 2k rows. A control signal SG at a level for turning on SST is applied.

  Next, the control signal ASW1 to be turned on and the control signal ASW2 to be turned off are supplied to the switching element 56, the switching element 56 connected to the video signal lines VL in the i and i + 2th columns is turned on, and i + 1 and The switching element 56 connected to the video signal line VL in the i + 3th column is switched off. The signal line drive circuit XDR supplies the video signal Vsig for red display to the video signal line VL in the i-th column and the video signal Vsig for blue display to the video signal line VL in the i + 2th column. The scanning line drive circuit YDR1 supplies a control signal SG at a level for turning on the pixel switch SST to the second scanning line Sgb in the 2k-1 row, and turns off the pixel switch SST in the second scanning line Sgb in the 2k row. A control signal SG at a level to be brought into a state is given.

  Subsequently, the control signal ASW1 to be turned off and the control signal ASW2 to be turned on are supplied to the switching element 56, the switching element 56 connected to the video signal lines VL in the i + 1 and i + 3th columns is turned on, and i And the switching element 56 connected to the video signal line VL in the (i + 2) th column is switched off. The signal line driving circuit XDR gives the video signal Vsig for green display to the video signal line VL in the (i + 1) th column, and gives the video signal Vsig for achromatic color display to the video signal line VL in the (i + 3) th column. The scanning line drive circuit YDR1 supplies a control signal SG at a level for turning on the pixel switch SST to the second scanning line Sgb in the 2k-1 row, and turns off the pixel switch SST in the second scanning line Sgb in the 2k row. A control signal SG at a level to be brought into a state is given.

  Next, the control signal ASW1 to be turned on and the control signal ASW2 to be turned off are supplied to the switching element 56, the switching element 56 connected to the video signal lines VL in the i and i + 2th columns is turned on, and i + 1 and The switching element 56 connected to the video signal line VL in the i + 3th column is switched off. The signal line drive circuit XDR supplies the video signal Vsig for red display to the video signal line VL in the i-th column and the video signal Vsig for blue display to the video signal line VL in the i + 2th column. The scanning line driving circuit YDR1 supplies a control signal SG at a level for turning off the pixel switch SST to the second scanning line Sgb in the 2k-1 row, and turns on the pixel switch SST in the second scanning line Sgb in the 2k row. A control signal SG at a level to be brought into a state is given.

  Thereafter, the control signal ASW1 to be turned off and the control signal ASW2 to be turned on are supplied to the switching element 56, the switching element 56 connected to the video signal lines VL in the i + 1 and i + 3th columns is turned on, and i and The switching element 56 connected to the video signal line VL in the i + 2th column is switched off. The signal line driving circuit XDR gives the video signal Vsig for green display to the video signal line VL in the (i + 1) th column, and gives the video signal Vsig for achromatic color display to the video signal line VL in the (i + 3) th column. The scanning line driving circuit YDR1 supplies a control signal SG at a level for turning off the pixel switch SST to the second scanning line Sgb in the 2k-1 row, and turns on the pixel switch SST in the second scanning line Sgb in the 2k row. A control signal SG at a level to be brought into a state is given.

  By adopting the above driving method of the display device, the initialization signal Vini can be collectively applied to the pixels PX in two consecutive rows, and the number of initialization operations in two horizontal scanning periods can be reduced to one. Further, each pixel P can be driven with the voltage level of the control signal SG fixed.

An initialization signal and video signal writing operation in the driving method of the display device of the fourth embodiment will be described.
As shown in FIG. 1, FIG. 2, FIG. 7, FIG. 9, and FIG. Here, the two picture elements P are in the 2k-1 and 2k rows and have six pixels PX located in the i, i + 1 and i + 2 columns. In the driving method, the initialization operation is performed once in two horizontal scanning periods, and then the video signal writing operation is performed six times. Although not described, a plurality of picture elements P arranged in the row direction X are similarly driven in the two horizontal scanning periods.

  First, in the initialization operation, the control signals ASW1 to ASW3 to be turned on are supplied to the switching element 56, and all the switching elements 56 connected to the video signal lines VL in the i, i + 1 and i + 2 columns are turned on. The signal line driving circuit XDR gives an initialization signal Vini to the video signal lines VL in the i, i + 1 and i + 2 columns, and the scanning line driving circuit YDR1 applies a pixel switch SST to the second scanning lines Sgb in the 2k-1 and 2k rows. A control signal SG at a level to be turned on is applied.

  Next, the control signal ASW1 to be turned on and the control signals ASW2 and ASW3 to be turned off are supplied to the switching element 56, and the switching element 56 connected to the video signal line VL in the i-th column is turned on, and i + 1 and The switching element 56 connected to the video signal line VL in the i + 2th column is switched off. The signal line drive circuit XDR gives the video signal Vsig for red display to the video signal line VL in the i-th column. The scanning line drive circuit YDR1 supplies a control signal SG at a level for turning on the pixel switch SST to the second scanning line Sgb in the 2k-1 row, and turns off the pixel switch SST in the second scanning line Sgb in the 2k row. A control signal SG at a level to be brought into a state is given.

  Subsequently, the control signal ASW2 to be turned on and the control signals ASW1 and ASW3 to be turned off are supplied to the switching element 56, and the switching element 56 connected to the video signal line VL in the (i + 1) th column is turned on. And the switching element 56 connected to the video signal line VL in the (i + 2) th column is switched off. The signal line driving circuit XDR supplies the video signal Vsig for green display to the video signal line VL in the (i + 1) th column. The scanning line drive circuit YDR1 supplies a control signal SG at a level for turning on the pixel switch SST to the second scanning line Sgb in the 2k-1 row, and turns off the pixel switch SST in the second scanning line Sgb in the 2k row. A control signal SG at a level to be brought into a state is given.

  Thereafter, the control signal ASW3 to be turned on and the control signals ASW1 and ASW2 to be turned off are supplied to the switching element 56, and the switching element 56 connected to the video signal line VL in the (i + 2) th column is turned on, and i and The switching element 56 connected to the video signal line VL in the (i + 1) th column is switched off. The signal line driver circuit XDR supplies the video signal Vsig for blue display to the video signal line VL in the (i + 2) th column. The scanning line drive circuit YDR1 supplies a control signal SG at a level for turning on the pixel switch SST to the second scanning line Sgb in the 2k-1 row, and turns off the pixel switch SST in the second scanning line Sgb in the 2k row. A control signal SG at a level to be brought into a state is given.

  Next, the control signal ASW1 to be turned on and the control signals ASW2 and ASW3 to be turned off are supplied to the switching element 56, and the switching element 56 connected to the video signal line VL in the i-th column is turned on, and i + 1 and The switching element 56 connected to the video signal line VL in the i + 2th column is switched off. The signal line drive circuit XDR gives the video signal Vsig for red display to the video signal line VL in the i-th column. The scanning line driving circuit YDR1 supplies a control signal SG at a level for turning off the pixel switch SST to the second scanning line Sgb in the 2k-1 row, and turns on the pixel switch SST in the second scanning line Sgb in the 2k row. A control signal SG at a level to be brought into a state is given.

  Subsequently, the control signal ASW2 to be turned on and the control signals ASW1 and ASW3 to be turned off are supplied to the switching element 56, and the switching element 56 connected to the video signal line VL in the (i + 1) th column is turned on. And the switching element 56 connected to the video signal line VL in the (i + 2) th column is switched off. The signal line driving circuit XDR supplies the video signal Vsig for green display to the video signal line VL in the (i + 1) th column. The scanning line driving circuit YDR1 supplies a control signal SG at a level for turning off the pixel switch SST to the second scanning line Sgb in the 2k-1 row, and turns on the pixel switch SST in the second scanning line Sgb in the 2k row. A control signal SG at a level to be brought into a state is given.

  Thereafter, the control signal ASW3 to be turned on and the control signals ASW1 and ASW2 to be turned off are supplied to the switching element 56, and the switching element 56 connected to the video signal line VL in the (i + 2) th column is turned on, and i and The switching element 56 connected to the video signal line VL in the (i + 1) th column is switched off. The signal line driver circuit XDR supplies the video signal Vsig for blue display to the video signal line VL in the (i + 2) th column. The scanning line driving circuit YDR1 supplies a control signal SG at a level for turning off the pixel switch SST to the second scanning line Sgb in the 2k-1 row, and turns on the pixel switch SST in the second scanning line Sgb in the 2k row. A control signal SG at a level to be brought into a state is given.

  By adopting the above driving method of the display device, the initialization signal Vini can be collectively applied to the pixels PX in two consecutive rows, and the number of initialization operations in two horizontal scanning periods can be reduced to one. Further, each pixel P can be driven with the voltage level of the control signal SG fixed.

  According to the display device and the driving method of the display device according to the first embodiment configured as described above, the display device includes a plurality of video signal lines VL and a plurality of scanning lines (first scanning line Sga, first scanning line). 2 scanning lines Sgb, third scanning line Sgc), a plurality of reset lines Sgr, and a plurality of pixels PX. Each pixel PX includes a drive transistor DRT, a diode OLED, a pixel switch SST, an output switch BCT, a holding capacitor Cs, and an auxiliary capacitor Cad.

  The diode OLED is connected between the high potential power line SLa and the low potential power line SLb. The drive transistor DRT has a source electrode connected to the diode OLED, a drain electrode connected to the reset wiring Sgr, and a gate electrode. The output switch BCT is connected between the high potential power supply line SLa and the drain electrode of the drive transistor DRT, and switches between the high potential power supply line SLa and the drain electrode of the drive transistor DRT between a conductive state and a nonconductive state.

  The pixel switch SST is connected between the video signal line VL and the gate electrode of the drive transistor DRT, and switches whether the video signal Vsig supplied through the video signal line VL is taken into the gate electrode side of the drive transistor. The storage capacitor Cs is connected between the source electrode and the gate electrode of the drive transistor DRT.

  The display device driving method includes a source initialization operation, a gate initialization operation, an offset cancellation operation, a video signal writing operation, and a display operation (light emission operation). In the first embodiment, after the initialization signal Vini is given to the video signal line VL within two horizontal scanning periods, the video signals Vsig for two rows can be given in order. In the second embodiment, after the initialization signal Vini is given to the video signal line VL within the four horizontal scanning periods, the video signals Vsig for four rows can be given in order.

  In the third embodiment, after the initialization signal Vini is given to the video signal line VL within two horizontal scanning periods, the video signals Vsig for two rows can be given in order. In the fourth embodiment, the video signal Vsig for two rows can be sequentially applied after the initialization signal Vini is applied to the video signal line VL within two horizontal scanning periods.

  As described above, in this embodiment, after the initialization signal Vini is given to the video signal line VL within the j horizontal scanning period, the video signals Vsig for j rows can be given in order. The initialization signal Vini may not be provided every horizontal scanning period (in units of one row). For this reason, even if the display device has been improved in definition and the horizontal scanning period becomes relatively short, the restriction on writing of the video signal Vsig can be relaxed. For example, a sufficient video signal writing period can be secured, or the number of video signal Vsig writes can be increased.

  In the second embodiment, when the video signals Vsig for four rows are sequentially supplied, the video signal Vsig is continuously supplied to the two pixels PX that display the same color image. For this reason, it is possible to reduce the drive frequency of the video signal line VL (the frequency of the video signal Vsig). For this reason, the driving conditions of the video signal line VL can be relaxed, and the power consumption can be reduced.

  Among the plurality of pixels PX, the plurality of pixels PX adjacent in the column direction Y share the output switch BCT. In this embodiment, four or six pixels PX share one output switch BCT.

  Compared with the case where one output switch BCT is provided for each pixel PX, the number of output switches BCT can be reduced to 1/4 or 1/6, and the first scanning line Sga, the third scanning line Sgc, and the reset wiring. The number of Sgr can be reduced to ½, and the number of reset switches RST can be reduced to ½. In the second embodiment, the number of third scanning lines Sgc can be reduced to ¼. For this reason, the frame of the display device can be narrowed, and a high-definition display device can be obtained.

  In the display period Pd, the output current Iel in the saturation region of the drive transistor DRT is applied to the diode OLED to emit light. Here, when the gain coefficient of the driving transistor DRT is β, the output current Iel is expressed by the following equation.

Iel = β × {(Vsig−Vini−ΔV1) × (Cel + Cad) / (Cs + Cel + Cad)} ²
β is defined by the following equation.

β = μ × Cox × W / 2L
W is the channel width of the drive transistor DRT, L is the channel length of the drive transistor DRT, μ is the carrier mobility, and Cox is the gate capacitance per unit area.

  Therefore, the output current Iel becomes a value that does not depend on the threshold voltage Vth of the drive transistor DRT, and the influence of the variation of the threshold voltage of the drive transistor DRT on the output current Iel can be eliminated.

  In addition, since the absolute value of ΔV1 increases as the mobility μ of the driving transistor DRT increases, the influence of the mobility μ can be compensated. Therefore, it is possible to suppress the occurrence of display defects, unevenness, and rough feeling due to these variations, and to perform high-quality image display.

  From the above, it is possible to obtain a high-definition display device driving method capable of relaxing restrictions on writing of the video signal Vsig. In addition, a display device that can achieve a narrow frame can be obtained.

  Next, a display device and a driving method of the display device according to the second embodiment will be described. In this embodiment, the same functional parts as those of the first embodiment described above are denoted by the same reference numerals, and detailed description thereof is omitted.

  As shown in FIG. 15, the display panel DP includes a plurality (m / 2) of fourth scanning lines Sgd (1 to m / 2). Further, the scanning line driving circuit YDR2 (or the scanning line driving circuit YDR1) is provided with a plurality of reset switches RST2 as a plurality of other reset switches. The reset switch RST2 and the reset wiring Sgr are connected one to one.

  When the number of reset switches RST is m / 4 and the number of third scanning lines Sgc is m / 4, the number of reset switches RST2 is also m / 4 and the number of fourth scanning lines Sgd is m. / 4.

  The reset switch RST2 is composed of a TFT having the same conductivity type as that of the reset switch RST, for example, an N-channel TFT, and is formed in the same process and the same layer structure as the reset switch RST. Similarly to the reset switch RST and the like, the reset switch RST2 has a first terminal (source electrode), a second terminal (drain electrode), and a control terminal (gate electrode).

  The reset switch RST2 is provided in the scanning line driving circuit YDR2 every two rows, for example. The reset switch RST2 is connected between another reset power source and the reset wiring Sgr. In the reset switch RST2, the source electrode is connected to the reset power supply line SLd connected to another reset power supply, the drain electrode is connected to the reset wiring Sgr, and the gate electrode functions as a reset control gate wiring. It is connected to the. As described above, the reset power supply line SLd is connected to another reset power supply and is fixed to the reset potential Vrst2 that is a constant potential. Note that the value of the reset potential Vrst2 is different from the value of the reset potential Vrst. Here, the other reset power supply (reset potential Vrst2) is set to 5 V, for example.

  The reset switch RST2 switches between the reset power supply line SLd and the reset wiring Sgr between a conductive state and a non-conductive state according to a control signal RG2 (1 to m / 2) given through the fourth scanning line Sgd. By switching the reset switch RST2 to the on state, the potential of the drain electrode (source electrode) of the drive transistor DRT is initialized.

  The scanning line driving circuits YDR1 and YDR2 include a shift register, an output buffer, and the like (not shown), and sequentially transfer a horizontal scanning start pulse supplied from the outside to the next stage, and four types of pixels are supplied to the pixels PX in each row via the output buffer. Control signals, that is, control signals BG (1 to m / 2), SG (1 to m), RG (1 to m / 2), and RG2 (1 to m / 2) are supplied.

  Note that the control signal RG is not directly supplied to the pixel PX, but a predetermined voltage is supplied from the reset power supply line SLc fixed to the reset potential Vrst at a predetermined timing according to the control signal RG. Alternatively, a predetermined voltage is supplied to the pixel PX from the reset power supply line SLd fixed to the reset potential Vrst2 at a predetermined timing according to the control signal RG2.

  Accordingly, the first scanning line Sga, the second scanning line Sgb, the third scanning line Sgc, and the fourth scanning line Sgd are driven by the control signals BG, SG, RG, and RG2, respectively.

  Next, the operation of the display device (organic EL display device) configured as described above will be described. 16, FIG. 17, FIG. 18, and FIG. 19 are timing charts showing control signals of the scanning line drive circuits YDR1 and YDR2 during operation display, respectively.

  FIG. 16 shows the scanning in the case where the RGBW square pixel arrangement of Example 1 according to the second embodiment is adopted, and the initialization operation is performed once and the video signal writing operation is performed twice in two horizontal scanning periods. It is a timing chart which shows the control signal of a line drive circuit. The display device of Example 1 according to the present embodiment is obtained by adding the reset switch RST2, the fourth scanning line Sgd, and the reset power supply line SLd to the display device of Example 1 according to the first embodiment described above. Is formed.

  FIG. 17 shows an RGBW square pixel arrangement configuration of Example 2 according to the second embodiment, and scanning in the case where the initialization operation is performed once and the video signal writing operation is performed four times in four horizontal scanning periods. It is a timing chart which shows the control signal of a line drive circuit. Note that the display device of Example 2 according to the present embodiment is obtained by adding the reset switch RST2, the fourth scanning line Sgd, and the reset power supply line SLd to the display device of Example 2 according to the first embodiment described above. Is formed.

  FIG. 18 shows the arrangement of the RGBW vertical stripe pixels of Example 3 according to the second embodiment, and the initialization operation is performed once in two horizontal scanning periods and the video signal writing operation is performed four times. 3 is a timing chart showing control signals of a scanning line driving circuit. Note that the display device of Example 3 according to the present embodiment includes a reset switch RST2, a fourth scanning line Sgd, and a reset power supply line SLd added to the display device of Example 3 according to the first embodiment described above. Is formed.

  FIG. 19 shows the arrangement of RGB vertical stripe pixels of Example 4 according to the second embodiment, and the initialization operation is performed once in two horizontal scanning periods and the video signal writing operation is performed six times. 3 is a timing chart showing control signals of a scanning line driving circuit. Note that the display device of Example 4 according to the present embodiment includes a reset switch RST2, a fourth scanning line Sgd, and a reset power supply line SLd added to the display device of Example 4 according to the first embodiment described above. Is formed.

  In the driving method of the display device of the first to fourth embodiments, the offset cancel operation is provided twice in order for the pixel PX to display (emit light) an image. However, the number of offset cancel operations is not limited to two, and may be one or three or more times.

  For example, the scanning line driving circuits YDR1 and YDR2 generate a pulse having a width of one horizontal scanning period (Tw-Starta) corresponding to each horizontal scanning period from a start signal (STV1 to STV4) and a clock (CKV1 to CKV4). The pulses are output as control signals BG, SG, RG, RG2.

  The operation of the pixel circuit includes a source initialization operation performed during the source initialization period Pis, a gate initialization operation performed during the gate initialization period Pig, and an offset cancellation (OC) operation performed during the offset cancellation period Po. It is divided into a video signal writing operation performed during the video signal writing period Pw and a display operation (light emitting operation) performed during the display period Pd (light emission period).

As shown in FIGS. 16 to 19, 1, and 2, first, the driving unit 10 performs a source initialization operation. In the source initialization operation, from the scanning line drive circuits YDR1 and YDR2, the control signal SG is a level at which the pixel switch SST is turned off, the control signal BG is at a level at which the output switch BCT is turned off, and the control signal RG is the reset switch RST. Level that turns on
The control signal RG2 is set to a level that turns off the reset switch RST2 (off potential: low level here).

  The output switch BCT, the pixel switch SST, and the reset switch RST2 are turned off and the reset switch RST is turned on, and the source initialization operation is started. When the reset switch RST is turned on, the source electrode and drain electrode of the drive transistor DRT are reset to the same potential as the potential of the reset power supply (reset potential Vrst), and the source initialization operation is completed. Here, the reset power supply (reset potential Vrst) is set to −2 V, for example.

  Next, the driving unit 10 performs a gate initialization operation. In the gate initialization operation, from the scanning line driving circuits YDR1 and YDR2, the control signal SG is a level at which the pixel switch SST is turned on, the control signal BG is at a level at which the output switch BCT is turned off, and the control signal RG is the reset switch RST. Is set to a level that turns on the reset switch RST2, and the control signal RG2 is set to a level that turns off the reset switch RST2. The output switch BCT and the reset switch RST2 are turned off, the pixel switch SST and the reset switch RST are turned on, and the gate initialization operation is started.

  In the gate initialization period Pig, the initialization signal Vini (initialization voltage) output from the video signal line VL is applied to the gate electrode of the driving transistor DRT through the pixel switch SST. As a result, the potential of the gate electrode of the drive transistor DRT is reset to a potential corresponding to the initialization signal Vini, and information of the previous frame is initialized. The voltage level of the initialization signal Vini is set to 2V, for example.

  In the display device having the switching circuit 13, all the switching elements 56 are switched on by the control signals (ASW1, ASW2, ASW3) in the gate initialization period Pig. As a result, the initialization signal Vini is given to all the video signal lines VL.

  Subsequently, the drive unit 10 performs an offset cancel operation. The control signal SG is turned on, the control signal BG is turned off, the control signal RG is turned off, and the control signal RG2 is turned on. As a result, the reset switch RST and the output switch BCT are turned off, the pixel switch SST and the reset switch RST2 are turned on, and the threshold value offset cancel operation is started.

  In the offset cancel period Po, the initialization signal Vini is applied to the gate electrode of the drive transistor DRT through the video signal line VL and the pixel switch SST, and the potential of the gate electrode of the drive transistor DRT is fixed. In the offset cancel period Po, all the switching elements 56 of the display device having the switching circuit 13 are switched on.

  Further, the reset switch RST2 is in an on state, and a current flows into the drive transistor DRT from another reset power source through the reset switch RST2 and the reset wiring Sgr. Here, the other reset power supply (reset potential Vrst2) is set to 5 V, for example. The potential of the source electrode of the drive transistor DRT is initially set to the potential (reset potential Vrst) written in the source initialization period Pis, and the current flowing through between the drain electrode and the source electrode of the drive transistor DRT is gradually reduced. In the meantime, the TFT shifts to the high potential side while absorbing and compensating for the TFT characteristic variation of the drive transistor DRT. In the present embodiment, the offset cancellation period Po is set to a time of about 1 μsec, for example.

  At the end of the offset cancellation period Po, the potential of the source electrode of the drive transistor DRT becomes Vini−Vth. As a result, the voltage between the gate electrode and the source electrode of the drive transistor DRT reaches the cancel point (Vgs = Vth), and the potential difference corresponding to the cancel point is stored (held) in the storage capacitor Cs. Note that the offset cancellation period Po can be provided twice as in the example shown in FIGS.

  Subsequently, in the video signal writing period Pw, the control signal SG is at a level that turns on the pixel switch SST, the control signal BG is at a level that turns off the output switch BCT, and the control signal RG turns off the reset switch RST. The level and control signal RG2 is set to a level that turns on the reset switch RST2. Then, the pixel switch SST and the reset switch RST2 are turned on, the output switch BCT and the reset switch RST are turned off, and the video signal writing operation is started.

  In the video signal writing period Pw, the video signal Vsig is written from the video signal line VL through the pixel switch SST to the gate electrode of the drive transistor DRT. In addition, a current flows from the other reset power source to the drive transistor DRT via the reset switch RST2 and the reset wiring Sgr. Immediately after the pixel switch SST is turned on, the potential of the gate electrode of the driving transistor DRT is Vsig (R, G, B, W), and the potential of the source electrode of the driving transistor DRT is Vini−Vth + Cs (Vsig−Vini) / ( Cs + Cel + Cad).

  Thereafter, a current flows through the low-potential power line SLb via the capacitor Cel of the diode OLED, and at the end of the video signal writing period Pw, the potential of the gate electrode of the drive transistor DRT is Vsig (R, G, B, W). The potential of the source electrode of the drive transistor DRT is Vini−Vth + ΔV1 + Cs (Vsig−Vini) / (Cs + Cel + Cad). Thereby, the variation in mobility of the drive transistor DRT is corrected.

  In the display device having the switching circuit 13, the switching element 56 of each switching element group 55 is sequentially turned on by the control signal (ASW1, ASW2, ASW3) during the video writing period Pw. By driving the video signal line VL in a time-sharing manner, the video signal Vsig is sequentially given to all the video signal lines VL.

  Finally, in the display period Pd, the control signal SG is at a level at which the pixel switch SST is turned off, the control signal BG is at a level at which the output switch BCT is turned on, and the control signal RG is at a level at which the reset switch RST is turned off. The control signal RG2 is set to a level that turns off the reset switch RST2. The output switch BCT is turned on, the pixel switch SST, the reset switch RST, and the reset switch RST2 are turned off, and the display operation is started.

  The drive transistor DRT outputs a drive current Iel having a current amount corresponding to the gate control voltage written in the storage capacitor Cs. This drive current Iel is supplied to the diode OLED. As a result, the diode OLED emits light with a luminance corresponding to the drive current Iel, and a display operation is performed. The diode OLED maintains the light emitting state after one frame period until the control signal BG becomes the off potential again.

  The above-described source initialization operation, gate initialization operation, offset cancellation operation, video signal writing operation, and display operation are sequentially performed on each pixel PX, thereby displaying a desired image.

  According to the display device and the driving method of the display device according to the first embodiment configured as described above, the display device includes a plurality of video signal lines VL and a plurality of scanning lines (first scanning line Sga, first scanning line). 2 scanning line Sgb, 3rd scanning line Sgc, 4th scanning line Sgd), several reset wiring Sgr, and several pixel PX.

  The display device driving method includes a source initialization operation, a gate initialization operation, an offset cancellation operation, a video signal writing operation, and a display operation (light emission operation). In the first embodiment, after the initialization signal Vini is given to the video signal line VL within two horizontal scanning periods, the video signals Vsig for two rows can be given in order. In the second embodiment, after the initialization signal Vini is given to the video signal line VL within the four horizontal scanning periods, the video signals Vsig for four rows can be given in order.

  In the third embodiment, after the initialization signal Vini is given to the video signal line VL within two horizontal scanning periods, the video signals Vsig for two rows can be given in order. In the fourth embodiment, the video signal Vsig for two rows can be sequentially applied after the initialization signal Vini is applied to the video signal line VL within two horizontal scanning periods.

  As described above, in this embodiment, after the initialization signal Vini is given to the video signal line VL within the j horizontal scanning period, the video signals Vsig for j rows can be given in order. For this reason, the effect similar to 1st Embodiment mentioned above can be acquired.

  The scanning line driving circuit YDR2 has a reset switch RST2. In the offset cancel operation, the reset switch RST2 can switch the other reset power source and the drive transistor DRT to the conductive state. Thereby, the value of the voltage (Vds) between the drain electrode and the source electrode of the drive transistor DRT at the end of the offset cancel operation can be brought close to the value of the voltage (Vds) during the display operation (white display). For this reason, in this embodiment, it is possible to obtain a display device that is superior in display quality compared to the display device according to the first embodiment.

  From the above, it is possible to obtain a high-definition display device driving method capable of relaxing restrictions on writing of the video signal Vsig. In addition, a display device that can achieve a narrow frame can be obtained.

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

  For example, the driving method of the display device can sequentially apply the video signals Vsig for j rows or more after supplying the initialization signal Vini to the video signal lines VL within the j horizontal scanning period. Thereby, the effect of embodiment mentioned above can be acquired. J is a natural number of 2 or more.

  As shown in Examples 1 to 4 of the first embodiment and Examples 1 to 4 of the second embodiment, the initialization signal Vini is applied to the video signal line VL within the j horizontal scanning period. Thereafter, video signals Vsig for j rows may be given in order.

  In addition, as shown in Example 2 of the first embodiment and Example 2 of the second embodiment, when sequentially giving video signals Vsig for j rows, a plurality of images displaying the same color are displayed. The video signal Vsig may be continuously supplied to the pixel PX.

  Furthermore, after the initialization signal Vini is given to the video signal line VL within the j horizontal scanning period, the video signals Vsig for (2 × j) rows may be given in order. Alternatively, after the initialization signal Vini is given to the video signal line VL within the j horizontal scanning period, the video signals Vsig for (3 × j) rows may be given in order.

  The semiconductor layer of the TFT is not limited to polysilicon, but can be composed of amorphous silicon. The TFT and the drive transistor DRT constituting each switch are not limited to N-channel TFTs but may be formed of P-channel TFTs. Similarly, the reset switches RST and RST2 only need to be formed of P-channel or N-channel TFTs. The shapes and dimensions of the drive transistor DRT and the switch are not limited to the above-described embodiments, and can be changed as necessary.

Further, the output switch BCT is provided so as to be shared by four or six pixels PX. However, the present invention is not limited to this, and the number of output switches BCT can be increased or decreased as necessary. For example, two pixels PX provided in 2 rows and 1 column share one output switch BCT, or 8 pixels PX provided in 2 rows and 4 columns share one output switch BCT. It may be.
Furthermore, the self-light-emitting element constituting the pixel PX is not limited to the diode (organic EL diode) OLED and can be formed by applying various display elements capable of self-light emission.

The auxiliary capacitor Cad only needs to be connected between the source electrode of the driving transistor DRT and the constant potential wiring. Examples of the constant potential wiring include a high potential power supply line SLa, a low potential power supply line SLb, and a reset wiring Sgr.
Embodiments of the present invention are not limited to display devices and display device driving methods, and can be applied to various display devices and display device driving methods.

  DP ... display panel, 10 ... drive unit, 12 ... controller, YDR1, YDR2 ... scan line drive circuit, XDR ... signal line drive circuit, Sga ... first scan line, Sgb ... second scan line, Sgc ... third scan line , Sgd ... 4th scanning line, Sgr ... reset wiring, VL ... video signal line, P ... pixel, PX ... pixel, OLED ... diode, SST ... pixel switch, DRT ... drive transistor, BCT ... output switch, RST, RST2 ... Reset switch, Cs ... Retention capacitor, Cad ... Auxiliary capacitor, Pis ... Source initialization period, Pig ... Gate initialization period, Po ... Offset cancel period, Pw ... Video signal writing period, Pd ... Display period, Y ... Column direction , X ... row direction.

Claims (7)

A plurality of pixels are provided in a matrix along the row direction and the column direction, and each of the plurality of pixels is connected to a display element connected between a high potential power source and a low potential power source, and to the display element. A drive transistor having a source electrode, a drain electrode connected to a reset line, and a gate electrode; and a connection between the high potential power source and the drain electrode of the drive transistor; and conduction between the high potential power source and the drain electrode of the drive transistor. An output switch that switches between a video signal line and a gate electrode of the drive transistor, and a pixel switch that switches whether a signal supplied through the video signal line is taken into the gate electrode side of the drive transistor. And a storage capacitor connected between the source electrode and the gate electrode of the driving transistor. That, in the driving method of the display device,
In a source initialization period, a reset signal is given to the drain electrode of the driving transistor through the reset wiring,
In a state where the reset signal is applied to the drain electrode of the drive transistor in the gate initialization period following the source initialization period, an initialization signal is applied to the gate electrode of the drive transistor through the video signal line and the pixel switch, Initializing the drive transistor;
In an offset cancellation period following the gate initialization period, a current is passed from the high potential power source to the drive transistor through the output switch in a state where an initialization signal is applied to the gate electrode of the drive transistor, and a threshold value of the drive transistor Cancel the offset,
In a video signal writing period subsequent to the offset cancel period, a video signal is applied to the gate electrode of the driving transistor through the video signal line and the pixel switch, and the low potential is supplied from the high potential power source through the output switch, the driving transistor, and the display element. Apply current to the power supply
In a display period following the video signal writing period, a driving current corresponding to the video signal is supplied from the high potential power source to the display element through the output switch and the driving transistor,
A driving method of a display device, wherein j is a natural number of 2 or more, and the initialization signal is given to the video signal lines in the j horizontal scanning period, and then the video signals of j rows or more are sequentially given.   2. The driving method of the display device according to claim 1, wherein the video signals for j rows are sequentially given after the initialization signal is given to the video signal lines within the j horizontal scanning period.   The method of driving a display device according to claim 2, wherein when the video signals for j rows are sequentially given, the video signals are continuously given to a plurality of pixels displaying an image of the same color.   2. The method of driving a display device according to claim 1, wherein after the initialization signal is given to the video signal line within the j horizontal scanning period, the video signals for (2 × j) rows are given in order.   2. The method of driving a display device according to claim 1, wherein after the initialization signal is given to the video signal line within the j horizontal scanning period, the video signals for (3 × j) rows are given in order.   The method for driving a display device according to claim 2, wherein j is two.   The display device driving method according to claim 1, wherein a plurality of the offset cancel periods are provided between the gate initialization period and the video signal writing period.

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