JP6186127B2 - Display device - Google Patents

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JP6186127B2
JP6186127B2 JP2013012286A JP2013012286A JP6186127B2 JP 6186127 B2 JP6186127 B2 JP 6186127B2 JP 2013012286 A JP2013012286 A JP 2013012286A JP 2013012286 A JP2013012286 A JP 2013012286A JP 6186127 B2 JP6186127 B2 JP 6186127B2
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conductive layer
display device
insulating film
layer
potential power
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JP2014142560A5 (en
JP2014142560A (en
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誠 渋沢
誠 渋沢
一由 小俣
一由 小俣
木村 裕之
裕之 木村
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株式会社ジャパンディスプレイ
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  Embodiments described herein relate generally to a display device.

  In recent years, the demand for flat display devices typified by liquid crystal display devices has been rapidly increased by taking advantage of the features of thinness, light weight, and low power consumption. Among them, an active matrix display device in which each pixel is provided with a pixel switch having a function of electrically separating an on-pixel and an off-pixel and holding a video signal to the on-pixel includes various types of information including portable information devices. It is used for the display.

  As such a flat-type active matrix display device, an organic EL display device using a self-luminous element has attracted attention, and research and development have been actively conducted. The organic EL display device has characteristics that it does not require a backlight, is suitable for moving image reproduction because of high-speed responsiveness, and is suitable for use in a cold region because the luminance does not decrease at low temperatures.

  In general, an organic EL display device includes a plurality of pixels arranged in a plurality of rows and a plurality of columns. Each pixel includes an organic EL element that is a self-light emitting element and a pixel circuit that supplies a drive current to the organic EL element, and performs a display operation by controlling the light emission luminance of the organic EL element.

  As a pixel circuit driving method, a method using a voltage signal is known. In addition, by switching the voltage power supply, switching between low and high, and outputting both the video signal and the initialization signal from the video signal wiring, the number of pixel constituent elements and the number of wirings can be reduced, and the pixel layout area There has been proposed a display device that achieves higher definition by reducing the size of the screen.

US Pat. No. 6,229,506 JP 2007-310311 A JP 2011-145622 A

Incidentally, in recent years, there has been a further demand for higher definition of pixels. As the size of a pixel is reduced, it has become difficult to arrange a plurality of elements of each pixel within a predetermined region.
The present invention has been made in view of the above points, and an object thereof is to provide a high-definition display device.

A display device according to an embodiment includes :
A plurality of pixels provided in a matrix along the row direction and the column direction;
Each of the plurality of pixels is
A first conductive layer;
A first insulating film provided on the front Symbol first conductive layer,
A semi-conductor layer provided on the first insulating film,
A second insulating film provided on the first insulating film and before Symbol semiconductors layer,
On the second insulating film, a second conductive layer wherein the first conductive layer was set so as not to overlap vignetting,
Vignetting set to overlap the previous SL second conductive layer, and a table示素Ko connected between the high potential power source and a low potential power source,
Has a conductor layer part of the previous SL semi conductor layer,
Another part of the previous SL semi conductor layer, said second insulating film and the second conductive layer forms a connected drive transistor between the high potential power supply and the display device,
The second conductive layer constituting the gate electrode of the driving transistor and a part of the semiconductor layer form a first capacitor portion;
The first conductive layer and a part of the semiconductor layer form a second capacitor portion,
The other part of the semiconductor layer forming the driving transistor, the part of the semiconductor layer forming the first capacitor part, and the part of the semiconductor layer forming the second capacitor part are It consists of a series of island-like semiconductor layers.

FIG. 1 is a plan view schematically showing a display device according to an embodiment. FIG. 2 is an equivalent circuit diagram of a pixel of the display device of FIG. FIG. 3 is a partial cross-sectional view schematically showing an example of a structure that can be employed in the display device of FIG. FIG. 4 is a partial cross-sectional view illustrating the display device according to the embodiment, and is a diagram illustrating a drive transistor, a power supply line, a conductive layer, and a pixel electrode. FIG. 5 is a schematic diagram illustrating an example of an arrangement configuration of pixels according to the embodiment. FIG. 6 is a timing chart showing the control signal of the scanning line driving circuit when the pixel arrangement according to the embodiment is adopted and the offset cancel operation is performed once. FIG. 7 is a timing chart showing a control signal of the scanning line driving circuit when the pixel arrangement according to the embodiment is adopted and the offset cancel operation is performed twice. FIG. 8 is a partial cross-sectional view showing a modification of the display device according to the embodiment, and shows a drive transistor, a power supply line, a connection electrode, a conductive layer, and a pixel electrode.

  Hereinafter, a display device and a driving method of the display device according to an embodiment will be described in detail with reference to the drawings. In this embodiment, the display device is an active matrix display device, more specifically, an active matrix organic EL (electroluminescence) display device.

  FIG. 1 is a plan view schematically showing the display device according to the present embodiment. FIG. 2 is an equivalent circuit diagram of a pixel of the display device of FIG. FIG. 3 is a partial cross-sectional view schematically showing an example of a structure that can be employed in the display device of FIG. In FIG. 3, the display device is drawn such that the display surface, that is, the front surface or the light emitting surface faces upward, and the back surface faces downward. This display device is a top emission type organic EL display device adopting an active matrix driving method.

  As shown in FIG. 1, the display device according to the present embodiment is configured as, for example, an active matrix type display device of type 2 or more, and includes a display panel DP and a controller 12 that controls the operation of the display panel DP. It is out. In this embodiment, the display panel DP is an organic EL panel.

  The display panel DP includes an insulating substrate SUB having light transmissivity such as a glass plate, m × n pixels PX arranged in a matrix on the display region R1 of the insulating substrate SUB, and a plurality (m / 2) of pixels. The first scanning line Sga (1 to m / 2), the plurality (m) of second scanning lines Sgb (1 to m), and the plurality of (m / 2) third scanning lines Sgc (1 to 1). m / 2), a plurality (m / 2) of reset wirings Sgr (1 to m / 2), and a plurality (n) of video signal lines VL (1 to n).

  The pixels PX are arranged m in the column direction Y and n in the row direction X. The first scanning line Sga, the second scanning line Sgb, and the reset wiring Sgr are provided to extend in the row direction X. The reset wiring Sgr is formed of a plurality of electrodes that are electrically connected to each other. The video signal line VL extends in the column direction Y.

  As shown in FIGS. 1 and 2, the display panel DP includes a high-potential power line SLa that is fixed to a high potential Pvdd and a low-potential power electrode SLb that is fixed to a low potential Pvss. The high potential power supply line SLa is connected to a high potential power supply, and the low potential power supply electrode SLb is connected to a low potential power supply (reference potential power supply).

  The display panel DP has scanning line driving circuits YDR1 and YDR2 that sequentially drive the first scanning line Sga, the second scanning line Sgb, and the third scanning line Sgc for each row of the pixels PX, and a signal line drive that drives the video signal line VL. A circuit XDR is provided. The scanning line drive circuits YDR1 and YDR2 and the signal line drive circuit XDR are integrally formed on the non-display area R2 outside the display area R1 of the insulating substrate SUB, and constitute the drive unit 10 together with the controller 12.

  Each pixel PX includes a display element and a pixel circuit that supplies a drive current to the display element. The display element is, for example, a self-luminous element. In this embodiment, an organic EL diode OLED (hereinafter simply referred to as a diode OLED) including at least an organic light emitting layer as a photoactive layer is used.

  As shown in FIG. 2, the pixel circuit of each pixel PX is a voltage signal type pixel circuit that controls light emission of the diode OLED in accordance with a video signal composed of a voltage signal, and includes a pixel switch SST, a drive transistor DRT, a storage capacitor Cs and auxiliary capacitance Cad are included. The holding capacitor Cs and the auxiliary capacitor Cad are capacitors. The auxiliary capacitor Cad is an element provided for adjusting the light emission current amount. The capacitance part Cel is the capacitance of the diode OLED itself (parasitic capacitance of the diode OLED). The diode OLED also functions as a capacitor.

  Each pixel PX includes an output switch BCT. In this embodiment, the four pixels PX adjacent in the row direction X and the column direction Y share one output switch BCT.

  The scanning line driving circuit YDR2 (or the scanning line driving circuit YDR1) is provided with a plurality of reset switches RST. The reset switch RST and the reset wiring Sgr are connected one to one.

  Here, the pixel switch SST, the drive transistor DRT, the output switch BCT, and the reset switch RST are composed of TFTs (thin film transistors) of the same conductivity type, for example, N-channel type.

  In the display device according to the present embodiment, the TFTs constituting each driving transistor and each switch are all formed in the same process and the same layer structure, and are top-gate thin film transistors using polysilicon as the semiconductor layer.

  Each of the pixel switch SST, the drive transistor DRT, the output switch BCT, and the reset switch RST has a first terminal, a second terminal, and a control terminal. In this embodiment, the first terminal is a source electrode, the second terminal is a drain electrode, and the control terminal is a gate electrode. The source region and drain region of the semiconductor layer are conductor layers in which polysilicon is doped with an impurity at a high concentration.

  In the pixel circuit of the pixel PX, the drive transistor DRT and the output switch BCT are connected in series with the diode OLED between the high potential power line SLa and the low potential power electrode SLb. The high potential power supply line SLa (high potential Pvdd) is set to a potential of 10 V, for example, and the low potential power supply electrode SLb (low potential Pvss) is set to a potential of 1.5 V, for example.

  In the output switch BCT, the drain electrode is connected to the high potential power supply line SLa, the source electrode is connected to the drain electrode of the drive transistor DRT, and the gate electrode is connected to the first scanning line Sga. Thus, the output switch BCT is controlled to be on (conductive state) and off (non-conductive state) by the control signal BG (1 to m / 2) from the first scanning line Sga. The output switch BCT controls the light emission time of the diode OLED in response to the control signal BG.

  In the drive transistor DRT, the drain electrode is connected to the source electrode of the output switch BCT and the reset wiring Sgr, and the source electrode is connected to one electrode (here, the anode) of the diode OLED. The other electrode (here, the cathode) of the diode OLED is connected to the low potential power supply electrode SLb. The drive transistor DRT outputs a drive current having a current amount corresponding to the video signal Vsig to the diode OLED.

  In the pixel switch SST, the source electrode is connected to the video signal line VL (1 to n), the drain electrode is connected to the gate electrode of the driving transistor DRT, and the gate electrode functions as a signal writing control gate wiring. It is connected to Sgb (1 to m). The pixel switch SST is on / off controlled by a control signal SG (1 to m) supplied from the second scanning line Sgb. The pixel switch SST controls connection / disconnection between the pixel circuit and the video signal line VL (1-n) in response to the control signal SG (1-m), and the corresponding video signal line VL (1 To n), the video signal Vsig or the initialization signal Vini is taken into the pixel circuit.

  The reset switch RST is provided in the scanning line driving circuit YDR2. In this embodiment, since the pixels PX adjacent in the column direction Y share one output switch BCT, the reset switch RST is provided every two rows. The reset switch RST is connected between the drain electrode of the drive transistor DRT and the reset power supply.

  In the reset switch RST, the source electrode is connected to the reset power supply line SLc connected to the reset power supply, the drain electrode is connected to the reset wiring Sgr, and the gate electrode is connected to the third scanning line Sgc functioning as a reset control gate wiring. Has been. As described above, the reset power supply line SLc is connected to the reset power supply and is fixed to the reset potential Vrst that is a constant potential.

  The reset switch RST switches between the reset power supply line SLc and the reset wiring Sgr in a conductive state (ON) or a non-conductive state (OFF) in accordance with a control signal RG (1 to m / 2) given through the third scanning line Sgc. Switch. By switching the reset switch RST to the on state, the potential of the source electrode of the drive transistor DRT is initialized.

  On the other hand, the controller 12 shown in FIG. 1 is formed on a printed circuit board (not shown) arranged outside the display panel DP, and controls the scanning line driving circuits YDR1 and YDR2 and the signal line driving circuit XDR. The controller 12 receives a digital video signal and a synchronization signal supplied from the outside, and generates a vertical scanning control signal for controlling the vertical scanning timing and a horizontal scanning control signal for controlling the horizontal scanning timing based on the synchronizing signal.

  The controller 12 supplies the vertical scanning control signal and the horizontal scanning control signal to the scanning line driving circuits YDR1 and YDR2 and the signal line driving circuit XDR, respectively, and the digital video signal and the initial stage are synchronized with the horizontal and vertical scanning timings. The signal is supplied to the signal line drive circuit XDR.

  The signal line drive circuit XDR converts the video signal sequentially obtained in each horizontal scanning period to the analog format under the control of the horizontal scanning control signal, and converts the video signal Vsig corresponding to the gradation to the plurality of video signal lines VL (1 to n). In parallel. The signal line drive circuit XDR supplies the initialization signal Vini to the video signal line VL.

The scanning line driving circuits YDR1 and YDR2 include a shift register, an output buffer, and the like (not shown), transfer a horizontal scanning start pulse supplied from the outside sequentially to the next stage, and three types of pixels PX in each row via the output buffer Control signals, that is, control signals BG (1 to m / 2), SG (1 to m), and RG (1 to m / 2) are supplied (FIG. 2). Note that the control signal RG is not directly supplied to the pixel PX, but a predetermined voltage is supplied from the reset power supply line SLc fixed to the reset potential Vrst at a predetermined timing according to the control signal RG.
Accordingly, the first scanning line Sga, the second scanning line Sgb, and the third scanning line Sgc are driven by the control signals BG, SG, and RG, respectively.

Next, the configuration of the drive transistor DRT and the diode OLED will be described in detail with reference to FIG.
The N-channel TFT in which the driving transistor DRT is formed includes a semiconductor layer SC. The semiconductor layer SC is formed on the insulating film PL as the first insulating film. An undercoat layer UC is formed on the insulating substrate SUB, and the insulating film PL is formed on the undercoat layer UC. The semiconductor layer SC is, for example, a polysilicon layer including a p-type region and an n-type region.

  The semiconductor layer SC is covered with a gate insulating film GI as a second insulating film. On the gate insulating film GI, the gate electrode G of the drive transistor DRT is formed. The gate electrode G is opposed to the semiconductor layer SC. An interlayer insulating film II is formed on the gate insulating film GI and the gate electrode G.

  A source electrode SE and a drain electrode DE are further formed on the interlayer insulating film II. The source electrode SE and the drain electrode DE are connected to the source region and the drain region of the semiconductor layer SC through contact holes formed in the interlayer insulating film II and the gate insulating film GI, respectively. A passivation film PS is formed on the interlayer insulating film II, the source electrode SE, and the drain electrode DE. The passivation film PS functions as an insulating film.

  The diode OLED includes a pixel electrode PE, an organic layer ORG, and a counter electrode CE. In this embodiment, the pixel electrode PE is an anode, and the counter electrode CE is a cathode.

  A pixel electrode PE is formed on the passivation film PS. The pixel electrode PE is connected to the source electrode SE through a contact hole provided in the passivation film PS. The pixel electrode PE is a back electrode having light reflectivity. The pixel electrode PE is formed by laminating a transparent electrode layer (for example, ITO: indium tin oxide) and a light reflective electrode layer (for example, Al).

  When forming the pixel electrode PE, a transparent conductive material (for example, ITO) is deposited on the passivation film PS, and then a light-reflective conductive material (for example, Al) is deposited, and then a photolithography method is used. Then, the pixel electrode PE is formed by patterning.

  A partition insulating layer PI is further formed on the passivation film PS. In the partition insulating layer PI, a through hole is provided at a position corresponding to the pixel electrode PE, or a slit is provided at a position corresponding to a column or row formed by the pixel electrode PE. Here, as an example, the partition insulating layer PI has a through hole at a position corresponding to the pixel electrode PE.

  On the pixel electrode PE, an organic layer ORG including a light emitting layer is formed as an active layer. The light emitting layer is, for example, a thin film containing a luminescent organic compound whose emission color is red, green, blue, or achromatic. The organic layer ORG can further include a hole injection layer, a hole transport layer, a hole blocking layer, an electron transport layer, an electron injection layer, and the like in addition to the light emitting layer.

  Note that the light emission color of the diode OLED is not necessarily divided into red, green, blue, or achromatic color, and may be only achromatic color. In this case, the diode OLED can emit red, green, blue, or achromatic color by combining with red, green, and blue color filters.

  The partition insulating layer PI and the organic layer ORG are covered with the counter electrode CE. In this example, the counter electrode CE is an electrode connected to each other between the pixels PX, that is, a common electrode. In this example, the counter electrode CE is a cathode and a light-transmitting front electrode. For example, the counter electrode CE is electrically connected to an electrode wiring (not shown) formed in the same layer as the source electrode SE and the drain electrode DE through a contact hole provided in the passivation film PS and the partition insulating layer PI. Connected.

  In the diode OLED having such a structure, when the holes injected from the pixel electrode PE and the electrons injected from the counter electrode CE are recombined inside the organic layer ORG, the organic molecules constituting the organic layer ORG are changed. Excitons are generated by excitation. The excitons emit light in the process of radiation deactivation, and the light is emitted from the organic layer ORG to the outside through the transparent counter electrode CE.

  Next, the configuration of the drive transistor DRT, the storage capacitor Cs, and the auxiliary capacitor Cad will be described in detail with reference to FIGS. FIG. 4 is a partial cross-sectional view showing the display device according to the present embodiment, and is a view showing a drive transistor DRT, a power supply line PSH, a conductive layer AE, a conductive layer OE, and a pixel electrode PE.

  As shown in FIGS. 3 and 4, the plurality of conductive layers OE as the plurality of first conductive layers are provided in the display region R1 and are formed on the undercoat layer UC. The insulating film PL is provided on the undercoat layer UC and the conductive layer OE. The conductive layer OE is formed of a metal (for example, aluminum) as a conductor.

  In the non-display region R2 outside the display region R1, the conductive layer OE is connected to the power supply line PSH provided in the non-display region R2. The power supply line PSH is connected to a constant potential power supply. In this embodiment, the power supply line PSH is connected to a high potential power supply and is fixed at a high potential Pvdd. Thus, the conductive layer OE can be set so as not to be in an electrically floating state (so that the auxiliary capacitor Cad functions as a capacitor portion). Note that the power supply line PSH may be connected to a low potential power supply and fixed to the low potential Pvss.

  The conductive layer OE, the insulating film PL, and the conductor layer (source region of the semiconductor layer SC of the driving transistor DRT) facing each other form an auxiliary capacitance Cad (capacitance portion). The auxiliary capacitance Cad can be formed without using an electrode (conductive layer) above the semiconductor layer SC.

  The plurality of conductive layers AE as the plurality of second conductive layers are provided in the display region R1 and are formed on the gate insulating film GI. The diode OLED is provided above the conductive layer AE. The conductive layer AE is formed of a metal (for example, aluminum) as a conductor. The conductive layer AE is formed in the same layer as the gate electrode G. The conductive layer AE is connected to the gate electrode G.

  In this embodiment, since the display device is a top emission display device, the conductive layer OE and the conductive layer AE can be formed of metal. Note that in the case where the display device is a bottom emission display device or a light transmission display device such as a liquid crystal display device, it is not desirable to form the conductive layer OE and the conductive layer AE from metal.

  The conductive layer AE, the gate insulating film GI, and the conductor layer (source region of the semiconductor layer SC of the driving transistor DRT) facing each other form a storage capacitor Cs (capacitance portion). The semiconductor layer SC, the gate insulating film GI, and the gate electrode G form a top gate type TFT.

  The conductive layer OE and the conductive layer AE are formed in different layers. The conductive layer OE and the conductive layer AE may face each other. That is, since the auxiliary capacitor Cad and the storage capacitor Cs can be efficiently arranged, the space utilization efficiency can be improved.

Next, the arrangement configuration of the plurality of pixels PX will be described. FIG. 5 is a schematic diagram showing an arrangement configuration of the pixels PX according to the present embodiment.
As shown in FIG. 5, the pixel PX is a so-called vertical stripe pixel. In the row direction X, a pixel PX configured to display a red image, a pixel PX configured to display a green image, a pixel PX configured to display a blue image, and no pixel Pixels PX configured to display a chromatic image are alternately arranged. In the column direction Y, pixels PX configured to display the same color image are arranged.

  The red (R) pixel PX, the green (G) pixel PX, the blue (B) pixel PX, and the achromatic (W) pixel PX form a picture element P. In the first embodiment, the picture element P has four (four colors) pixels PX, but is not limited to this and can be variously modified. For example, when the achromatic pixel PX is not provided, the picture element P may include three (three colors) pixels PX of red, green, and blue.

  The output switch BCT is shared by four adjacent pixels (two adjacent in the column direction Y and two adjacent in the row direction X). From the above, the number of first scanning lines Sga and third scanning lines Sgc is m / 2.

The arrangement configuration of the pixels PX is not limited to the present embodiment (FIG. 5) and can be variously modified. For example, the pixel PX may be a so-called RGBW square pixel. In this case, for example, any two of red, green, blue and achromatic pixels PX are arranged in even rows, and the remaining two are arranged in odd rows.
Here, in the present embodiment, the terminology of the pixel PX and the picture element P has been described, but the pixel can be rephrased as a sub-pixel. In this case, the picture element is a pixel.

  Next, the operation of the display device (organic EL display device) configured as described above will be described. 6 and 7 are timing charts showing control signals of the scanning line drive circuits YDR1 and YDR2 during operation display, respectively.

  FIG. 6 shows a case in which the offset cancellation period is once for vertical stripe pixels, and FIG. 7 shows a case in which the offset cancellation period is multiple times (here, twice as a representative example) for vertical stripe pixels. Therefore, in this embodiment, the display device can be driven using the control signal in FIG. 6 or the control signal in FIG.

  For example, the scanning line drive circuits YDR1 and YDR2 generate a pulse having a width of one horizontal scanning period (Tw-Starta) corresponding to each horizontal scanning period from a start signal (STV1 to STV3) and a clock (CKV1 to CKV3). The pulses are output as control signals BG (1 to m / 2), SG (1 to m), and RG (1 to m / 2). Here, one horizontal scanning period is set to 1H.

  The operation of the pixel circuit includes a source initialization operation performed during the source initialization period Pis, a gate initialization operation performed during the gate initialization period Pig, and an offset cancellation (OC) operation performed during the offset cancellation period Po. It is divided into a video signal writing operation performed during the video signal writing period Pw and a display operation (light emitting operation) performed during the display period Pd (light emission period).

  As shown in FIGS. 6, 7, 1, and 2, first, the driving unit 10 performs a source initialization operation. In the source initialization operation, the control signal SG turns off the pixel switch SST from the scanning line drive circuits YDR1 and YDR2, and the control signal BG turns off the output switch BCT. The level (off potential: low level here) and the control signal RG are set to a level (on potential: high level here) that turns on the reset switch RST.

  The output switch BCT and the pixel switch SST are turned off (non-conductive state), the reset switch RST is turned on (conductive state), and the source initialization operation is started. When the reset switch RST is turned on, the source electrode and drain electrode of the drive transistor DRT are reset to the same potential as the potential of the reset power supply (reset potential Vrst), and the source initialization operation is completed. Here, the reset power supply (reset potential Vrst) is set to −2 V, for example.

  Next, the driving unit 10 performs a gate initialization operation. In the gate initialization operation, the control signal SG turns on the pixel switch SST from the scanning line drive circuits YDR1 and YDR2 (on potential: high level here), and the control signal BG turns off the output switch BCT. The level and control signal RG is set to a level that turns on the reset switch RST. The output switch BCT is turned off, the pixel switch SST and the reset switch RST are turned on, and the gate initialization operation is started.

  In the gate initialization period Pig, the initialization signal Vini (initialization voltage) output from the video signal line VL is applied to the gate electrode of the driving transistor DRT through the pixel switch SST. As a result, the potential of the gate electrode of the drive transistor DRT is reset to a potential corresponding to the initialization signal Vini, and information of the previous frame is initialized. The voltage level of the initialization signal Vini is set to 2V, for example.

  Subsequently, the drive unit 10 performs an offset cancel operation. The control signal SG is turned on, the control signal BG is turned on (high level), and the control signal RG is turned off (low level). As a result, the reset switch RST is turned off, the pixel switch SST and the output switch BCT are turned on, and the threshold value offset cancel operation is started.

  In the offset cancel period Po, the initialization signal Vini is applied to the gate electrode of the drive transistor DRT through the video signal line VL and the pixel switch SST, and the potential of the gate electrode of the drive transistor DRT is fixed.

  Further, the output switch BCT is in an ON state, and a current flows from the high potential power supply line SLa to the drive transistor DRT. The potential of the source electrode of the drive transistor DRT is initially set to the potential (reset potential Vrst) written in the source initialization period Pis, and the current flowing through between the drain electrode and the source electrode of the drive transistor DRT is gradually reduced. In the meantime, the TFT shifts to the high potential side while absorbing and compensating for the TFT characteristic variation of the drive transistor DRT. In the present embodiment, the offset cancellation period Po is set to a time of about 1 μsec, for example.

  At the end of the offset cancellation period Po, the potential of the source electrode of the drive transistor DRT becomes Vini−Vth. Vini is the voltage value of the initialization signal Vini, and Vth is the threshold voltage of the drive transistor DRT. As a result, the voltage between the gate electrode and the source electrode of the drive transistor DRT reaches the cancel point (Vgs = Vth), and the potential difference corresponding to the cancel point is stored (held) in the storage capacitor Cs. Note that, as in the example shown in FIG. 7, the offset cancellation period Po can be provided a plurality of times as necessary.

  Subsequently, in the video signal writing period Pw, the control signal SG sets the pixel switch SST to an on state, the control signal BG sets the output switch BCT to an on state, and the control signal RG sets the reset switch RST to an off state. Set to level. Then, the pixel switch SST and the output switch BCT are turned on, the reset switch RST is turned off, and the video signal writing operation is started.

In the video signal writing period Pw, the video signal Vsig is written from the video signal line VL through the pixel switch SST to the gate electrode of the drive transistor DRT. In addition, a current flows from the high potential power supply line SLa to the low potential power supply electrode SLb through the output switch BCT and the driving transistor DRT, and via the capacitance portion (parasitic capacitance) Cel of the diode OLED. Immediately after the pixel switch SST is turned on, the potential of the gate electrode of the drive transistor DRT is Vsig (R, G, B), and the potential of the source electrode of the drive transistor DRT is Vini−Vth + Cs (Vsig−Vini) / (Cs + Cel + Cad). It becomes.
Vsig is the voltage value of the video signal Vsig, Cs is the capacity of the storage capacitor Cs, Cel is the capacity of the capacitor part Cel, and Cad is the capacity of the auxiliary capacitor Cad.

Thereafter, a current flows to the low-potential power supply electrode SLb via the capacitance part Cel of the diode OLED, and at the end of the video signal writing period Pw, the potential of the gate electrode of the drive transistor DRT is Vsig (R, G, B), drive The potential of the source electrode of the transistor DRT is Vini−Vth + ΔV1 + Cs (Vsig−Vini) / (Cs + Cel + Cad). The relationship between the current Idrt flowing through the driving transistor DRT and the capacitance Cs + Cel + Cad is expressed by the following equation, and ΔV1 corresponds to the voltage value of the video signal Vsig determined from the following equation, the video writing period Pw, and the transistor mobility. This is the displacement of the potential of the source electrode.

here,
Idrt = β × (Vgs−Vth) 2
= Β × [(Vsig−Vini) × (Cel + Cad) / (Cs + Cel + Cad)] 2
If the channel width of the driving transistor DRT is W, the channel length of the driving transistor DRT is L, the carrier mobility is μ, and the gate capacitance per unit area is Cox, β is defined by the following equation.

β = μ × Cox × W / 2L
Therefore, ΔV1 is proportional to the carrier mobility μ, and ΔV1 increases as the mobility increases. Vgs at the end of the video signal writing period Pw is Vsig− [Vini−Vth + ΔV1 + (Vsig−Vini) × Cs / (Cs + Cel + Cad)]
= Vth− (Vsig−Vini) × (Cel + Cad) / (Cs + Cel + Cad) −ΔV1
When ΔV1 is large, that is, when the mobility is large, Vgs is further lowered, and the current flowing through the driving transistor is suppressed, so that the current variation due to the magnitude of the mobility can be reduced.

  Finally, in the display period Pd, the control signal SG is at a level at which the pixel switch SST is turned off, the control signal BG is at a level at which the output switch BCT is turned on, and the control signal RG is at a level at which the reset switch RST is turned off. Is set. The output switch BCT is turned on, the pixel switch SST and the reset switch RST are turned off, and the display operation is started.

  The drive transistor DRT outputs a drive current Ie having a current amount corresponding to the gate control voltage written in the storage capacitor Cs. This drive current Ie is supplied to the diode OLED. As a result, the diode OLED emits light with a luminance corresponding to the drive current Ie, and a display operation is performed. The diode OLED maintains the light emitting state after one frame period until the control signal BG becomes the off potential again.

  The above-described source initialization operation, gate initialization operation, offset cancellation operation, video signal writing operation, and display operation are sequentially performed on each pixel PX, thereby displaying a desired image.

  According to the display device and the display device driving method according to the first embodiment configured as described above, the display device includes a plurality of conductive layers OE (a plurality of first conductive layers) and an insulating film PL (a first film). 1 insulating film), a plurality of semiconductor layers SC (including a conductor layer which is a source region and a drain region), a gate insulating film GI (second insulating film), a plurality of gate electrodes G and a plurality of conductive layers AE ( A plurality of second conductive layers) and a plurality of diodes OLED (a plurality of display elements). The semiconductor layer SC, the gate insulating film GI, and the gate electrode G form a top gate type TFT. The conductive layer OE, the insulating film PL, and the conductor layer (source region of the semiconductor layer SC) form an auxiliary capacitance Cad (capacitance portion).

  A conductive layer OE and an insulating film PL are formed on the lower layer side of the semiconductor layer SC, and an auxiliary capacitor Cad is formed. The auxiliary capacitor Cad can be formed without being affected by the layout on the upper layer side of the semiconductor layer SC. For this reason, an increase in the size of the pixel can be suppressed, and in some cases, the size of the pixel can be reduced.

  The conductive layer OE and the conductive layer AE are formed in different layers. The conductive layer OE and the conductive layer AE may face each other. Since the auxiliary capacitor Cad and the holding capacitor Cs can be efficiently arranged, the space utilization efficiency can be improved. And it can contribute to high definition of the pixel PX.

In addition, by providing the conductive layer OE on the lower layer side of the semiconductor layer SC, it is possible to expect an effect of blocking light incident on the semiconductor layer SC by the conductive layer OE. In this case, the amount of leakage current in the semiconductor layer SC can be suppressed.
Furthermore, compared to the case where the conductive layer is formed on the upper layer side of the semiconductor layer SC, the manufacturing (manufacturing process) is easier when the conductive layer is formed on the lower layer side of the semiconductor layer SC.

  In the display period Pd, the output current Iel in the saturation region of the drive transistor DRT is applied to the diode OLED to emit light. Here, when the gain coefficient of the driving transistor DRT is β, the output current Iel is expressed by the following equation.

Iel = β × {(Vsig−Vini−ΔV1) × (Cel + Cad) / (Cs + Cel + Cad)} 2
β is defined by the following equation.

β = μ × Cox × W / 2L
W is the channel width of the drive transistor DRT, L is the channel length of the drive transistor DRT, μ is the carrier mobility, and Cox is the gate capacitance per unit area.

  Therefore, the output current Iel becomes a value that does not depend on the threshold voltage Vth of the drive transistor DRT, and the influence of the variation of the threshold voltage of the drive transistor DRT on the output current Iel can be eliminated.

In addition, since the absolute value of ΔV1 increases as the mobility μ of the driving transistor DRT increases, the influence of the mobility μ can be compensated. Therefore, it is possible to suppress the occurrence of display defects, unevenness, and rough feeling due to these variations, and to perform high-quality image display.
From the above, a high-definition display device and a driving method of the display device can be obtained.

  Next, a modification of the display device according to the above embodiment will be described. FIG. 8 is a partial cross-sectional view showing a modification of the display device according to the embodiment, and includes a drive transistor DRT, a power supply line PSH, a connection electrode AE, a connection electrode GE, a conductive layer OE, a conductive layer HE, and a pixel electrode PE. FIG.

  As shown in FIG. 8, the conductive layer OE is formed on the undercoat layer UC and covered with the insulating film PL. The conductive layer OE faces the conductor layer (the source region of the semiconductor layer SC). The conductive layer OE, the insulating film PL, and the conductor layer form a storage capacitor Cs. Note that the conductive layer AE shown in FIG. 4 is not provided.

  On the interlayer insulating film II, the connection electrode GE and the conductive layer HE are formed in addition to the drain electrode DE and the source electrode SE (not shown). The connection electrode GE and the conductive layer HE are simultaneously formed of the same material as the drain electrode DE and the source electrode SE.

  One of the connection electrodes GE is connected to the gate electrode G through a contact hole provided in the interlayer insulating film II. The other of the connection electrodes GE is connected to the conductive layer OE through a contact hole provided in the insulating film PL, the gate insulating film GI, and the interlayer insulating film II. This contact hole is located inside an opening formed in the conductor layer (source region of the semiconductor layer SC) or located away from the conductor layer.

The conductive layer HE is opposed to the conductor layer (the source region of the semiconductor layer SC). The conductor layer (source region of the semiconductor layer SC), the gate insulating film GI, the interlayer insulating film II, and the conductive layer HE form an auxiliary capacitor Cad. Here, the conductive layer OE and the conductive layer HE are opposed to each other with a conductor layer or the like interposed therebetween.
As described above, the storage capacitor Cs may be formed on the lower side, and the auxiliary capacitor Cad may be formed on the upper side.

  In the non-display area R2 outside the display area R1, the conductive layer HE is connected to the power supply line PSH provided in the non-display area R2. As described above, the power supply line PSH is connected to a constant potential power supply. Here, the power supply line PSH is connected to a high potential power supply and is fixed to the high potential Pvdd. Thereby, it can set so that the conductive layer HE may not be in an electrically floating state. Note that the power supply line PSH may be connected to a low potential power supply and fixed to the low potential Pvss.

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

  For example, the semiconductor layer of the TFT is not limited to polysilicon, but can be composed of amorphous silicon. The TFT and the drive transistor DRT constituting each switch are not limited to N-channel TFTs but may be formed of P-channel TFTs. Similarly, the reset switch RST may be formed of a P-channel or N-channel TFT. The shapes and dimensions of the drive transistor DRT and the switch are not limited to the above-described embodiments, and can be changed as necessary.

  Further, the output switch BCT is provided so as to be shared by four pixels PX. However, the present invention is not limited to this, and the number of output switches BCT can be increased or decreased as necessary. For example, one output switch BCT may be provided for each pixel PX. In addition, two pixels PX provided in one row and two columns or two rows and one column share one output switch BCT, or eight pixels PX provided in two rows and four columns output one. The switch BCT may be shared.

Furthermore, all the pixels PX in one row may share one output switch BCT. In this case, the output switch BCT and the first scanning line Sga may be provided in the scanning line driving circuit YDR2 (YDR1). That is, in the output switch BCT, the source electrode is connected to the high potential power supply, the drain electrode is connected to the reset wiring Sgr, and the gate electrode is connected to the first scanning line Sga.
Furthermore, the self-light-emitting element constituting the pixel PX is not limited to the diode (organic EL diode) OLED and can be formed by applying various display elements capable of self-light emission.

The auxiliary capacitor Cad only needs to be connected between the source electrode of the driving transistor DRT and the constant potential wiring. Examples of the constant potential wiring include a high potential power supply line SLa, a low potential power supply line SLb, and a reset wiring Sgr.
Embodiments of the present invention are not limited to display devices and display device driving methods, and can be applied to various display devices and display device driving methods .
Hereinafter, the invention described in the scope of claims of the present application will be appended.
[1] A plurality of first conductive layers;
A first insulating film provided on the plurality of conductive layers;
A plurality of conductor layers provided on the first insulating film;
A second insulating film provided on the first insulating film and the plurality of conductor layers;
A plurality of second conductive layers provided on the second insulating film;
A plurality of display elements provided above the plurality of second conductive layers,
The conductor layer, the second insulating film, and the second conductive layer form a top gate type thin film transistor,
The first conductive layer, the first insulating film, and the conductor layer are display devices that form a capacitor.
[2] It further includes a plurality of pixels provided in a matrix along the row direction and the column direction,
Each of the plurality of pixels is
The display element connected between a high potential power source and a low potential power source;
A drive transistor having a source electrode connected to the display element, a drain electrode connected to a reset wiring, and a gate electrode;
An output switch connected between the high-potential power supply and the drain electrode of the drive transistor, and switching between the high-potential power supply and the drain electrode of the drive transistor to a conductive state or a non-conductive state;
A pixel switch connected between a video signal line and a gate electrode of the driving transistor, and switching whether to take in a signal given through the video signal line to the gate electrode side of the driving transistor;
A storage capacitor connected between a source electrode of the driving transistor and the gate electrode,
The driving transistor is formed of the thin film transistor,
The display device according to [1], wherein the storage capacitor is formed by the capacitor unit.
[3] It further includes a plurality of pixels provided in a matrix along the row direction and the column direction,
Each of the plurality of pixels is
The display element connected between a high potential power source and a low potential power source;
A drive transistor having a source electrode connected to the display element, a drain electrode connected to a reset wiring, and a gate electrode;
An output switch connected between the high-potential power supply and the drain electrode of the drive transistor, and switching between the high-potential power supply and the drain electrode of the drive transistor to a conductive state or a non-conductive state;
A pixel switch connected between a video signal line and a gate electrode of the driving transistor, and switching whether to take in a signal given through the video signal line to the gate electrode side of the driving transistor;
An auxiliary capacitor connected between the display element and the high-potential power source,
The driving transistor is formed of the thin film transistor,
The display device according to [1], wherein the auxiliary capacitor is formed by the capacitor unit.
[4] The display device according to [1], in which the conductor layer, the second insulating film, and the second conductive layer facing each other form another capacitor in addition to the thin film transistor.
[5] A plurality of pixels further provided in a matrix along the row direction and the column direction,
Each of the plurality of pixels is
The display element connected between a high potential power source and a low potential power source;
A drive transistor having a source electrode connected to the display element, a drain electrode connected to a reset wiring, and a gate electrode;
An output switch connected between the high-potential power supply and the drain electrode of the drive transistor, and switching between the high-potential power supply and the drain electrode of the drive transistor to a conductive state or a non-conductive state;
A pixel switch connected between a video signal line and a gate electrode of the driving transistor, and switching whether to take in a signal given through the video signal line to the gate electrode side of the driving transistor;
A storage capacitor connected between a source electrode of the driving transistor and the gate electrode;
An auxiliary capacitor connected between the display element and the high-potential power source,
The driving transistor is formed of the thin film transistor,
One of the storage capacitor and the auxiliary capacitor is formed by the capacitor part,
The display device according to [4], wherein the other of the storage capacitor and the auxiliary capacitor is formed by the other capacitor unit.
[6] The display device according to any one of [2], [3], and [5], wherein the output switch is shared by the plurality of pixels.
[7] The display device according to [1], wherein the first conductive layer is made of metal.
[8] The display device according to [1], wherein the first conductive layer is connected to a power supply line connected to a constant-potential power supply outside the display region.
[9] The display device according to [6], wherein the constant potential power source is the high potential power source or the low potential power source.

  DP ... display panel, 10 ... drive unit, 12 ... controller, YDR1, YDR2 ... scan line drive circuit, XDR ... signal line drive circuit, Sga ... first scan line, Sgb ... second scan line, Sgc ... third scan line , Sgr ... reset wiring, VL ... video signal line, PX ... pixel, OLED ... diode, SST ... pixel switch, DRT ... drive transistor, BCT ... output switch, RST ... reset switch, Cs ... holding capacitor, Cad ... auxiliary capacitor, PL ... insulating film, SC ... semiconductor layer, GI ... gate insulating film, G ... gate electrode, II ... interlayer insulating film, OE, AE, HE ... conductive layer, PE ... pixel electrode, PSH ... power supply line, X ... row direction , Y: Column direction.

Claims (6)

  1. A plurality of pixels provided in a matrix along the row direction and the column direction;
    Each of the plurality of pixels is
    A first conductive layer;
    A first insulating film provided on the front Symbol first conductive layer,
    A semi-conductor layer provided on the first insulating film,
    A second insulating film provided on the first insulating film and before Symbol semiconductors layer,
    On the second insulating film, a second conductive layer wherein the first conductive layer was set so as not to overlap vignetting,
    Vignetting set to overlap the previous SL second conductive layer, and a table示素Ko connected between the high potential power source and a low potential power source,
    Has a conductor layer part of the previous SL semi conductor layer,
    Another part of the previous SL semi conductor layer, said second insulating film and the second conductive layer forms a connected drive transistor between the high potential power supply and the display device,
    The second conductive layer constituting the gate electrode of the driving transistor and a part of the semiconductor layer form a first capacitor portion;
    The first conductive layer and a part of the semiconductor layer form a second capacitor portion,
    The other part of the semiconductor layer forming the driving transistor, the part of the semiconductor layer forming the first capacitor part, and the part of the semiconductor layer forming the second capacitor part are It becomes an island-shaped semiconductor layer of the continuation, the display apparatus.
  2. Each of the plurality of pixels,
    An output switch connected between the high-potential power supply and the drain electrode of the drive transistor, and switches between the high-potential power supply and the drain electrode of the drive transistor between a conductive state and a non-conductive state;
    Is connected between the gate electrode of the driving transistor and the video signal line, further comprising, a pixel switch which switches whether incorporated into the gate electrode of the driving transistor a signal supplied through the video signal line,請 Motomeko The display device according to 1.
  3. Wherein the first conductive layer, the high potential power source and are electrically connected, the display device according to Motomeko 1.
  4. The display device according to claim 2, wherein the output switch is shared by the plurality of pixels.
  5.   The display device according to claim 1, wherein the first conductive layer is made of metal.
  6. The display device according to claim 3, wherein the first conductive layer is connected to the high potential power source outside a display region.
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US14/056,282 US9368058B2 (en) 2012-10-19 2013-10-17 Display apparatus
KR1020130124052A KR101580719B1 (en) 2012-10-19 2013-10-17 Display device
CN201310487901.3A CN103779385B (en) 2012-10-19 2013-10-17 Display device
US15/167,401 US9542888B2 (en) 2012-10-19 2016-05-27 Display apparatus
US15/365,428 US10096283B2 (en) 2012-10-19 2016-11-30 Display apparatus
US16/119,655 US10573239B2 (en) 2012-10-19 2018-08-31 Display apparatus
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