CN218632044U - Pixel circuit and display panel - Google Patents
Pixel circuit and display panel Download PDFInfo
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- CN218632044U CN218632044U CN202222972505.7U CN202222972505U CN218632044U CN 218632044 U CN218632044 U CN 218632044U CN 202222972505 U CN202222972505 U CN 202222972505U CN 218632044 U CN218632044 U CN 218632044U
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Abstract
The utility model relates to a pixel circuit and display panel. The pixel circuit includes: a first thin film transistor; a second thin film transistor (T2) having a gate connected to a second global signal (G2); a third thin film transistor (T3) having a gate connected to the first global signal (G1); a fourth thin film transistor (T4) having a gate connected to the second global signal (G2); a fifth thin film transistor (T5) having a gate connected to the third global signal (G3); a sixth thin film transistor (T6) having a gate connected to the third global signal (G3); a seventh thin film transistor (T7) having a gate connected to the control signal (Scan); a first capacitor (C1), a second capacitor (C2), and an Organic Light Emitting Diode (OLED). The utility model also provides a corresponding display panel. The utility model discloses a pixel circuit and display panel provide the pixel circuit that has the internal compensation and only need a set of GOA circuit, do benefit to display panel's narrow frame design, do benefit to micro display panel's concatenation.
Description
Technical Field
The utility model relates to a show technical field, especially relate to a pixel circuit and display panel.
Background
As a new generation of display technology, microled has higher contrast, faster response speed and wider viewing angle compared with the traditional LCD, and is widely applied to the fields of smart phones and TVs. In a driving mode, unlike an LCD, an LED belongs to a current driving type, and is sensitive to electrical variation of a Thin Film Transistor (TFT), and both uniformity of threshold voltage Vth of a TFT of a pixel circuit of a panel and drift of Vth under stress (stress) affect accuracy and uniformity of image display. The traditional compensation circuit needs a large number of line scanning signals, which is not beneficial to the narrowing of the frame of the panel.
As shown in fig. 1a and 1b, fig. 1a is a schematic diagram of a conventional pixel circuit with internal compensation, fig. 1b is a schematic diagram of a panel structure using the pixel circuit shown in fig. 1a, three sets of signals Scan1, scan2 and Scan3 are required, three sets of GOA circuits are required for the pixel circuit, and three sets of GOA circuits, GOA1, GOA2 and GOA3 are arranged on a panel using the conventional pixel circuit, so that the width of the frame of the panel is wide, which is not conducive to micro-rolled splicing, and the seams are obvious. Because micro panels need to be spliced into large-size panels, the narrower the width of the frame of the panel is, the better the frame width is, and the existing pixel circuit is not favorable for the narrow frame design requirement of the panel.
SUMMERY OF THE UTILITY MODEL
Therefore, an object of the present invention is to provide a pixel circuit suitable for a narrow frame design requirement of a display panel.
Another object of the present invention is to provide a display panel, which is suitable for the narrow frame design requirement of the display panel.
To achieve the above object, the present invention provides a pixel circuit, including:
a first thin film transistor, wherein the grid electrode of the first thin film transistor is connected with a first node, and the source electrode and the drain electrode of the first thin film transistor are respectively connected with a second node and a third node;
a second thin film transistor, wherein the grid electrode of the second thin film transistor is connected with a second global signal, and the source electrode and the drain electrode of the second thin film transistor are respectively connected with a direct current high voltage and a third node;
a third thin film transistor, a grid electrode of which is connected with the first global signal, and a source electrode and a drain electrode of which are respectively connected with the first node and the third node;
a fourth thin film transistor, a grid electrode of which is connected with the second global signal, and a source electrode and a drain electrode of which are respectively connected with the second node and the fourth node;
a fifth thin film transistor, a grid electrode of which is connected with the third global signal, and a source electrode and a drain electrode of which are respectively connected with the fourth node and the direct current low voltage;
a sixth thin film transistor, a gate of which is connected to the third global signal, and a source and a drain of which are connected to the first node and the fifth node, respectively;
a seventh thin film transistor, a gate of which is connected to the control signal, and a source and a drain of which are connected to the data signal and the fifth node, respectively;
a first capacitor connected between the fifth node and the dc low voltage;
a second capacitor connected between the first node and the fourth node; and
and the anode of the organic light emitting diode is connected with the second node, and the cathode of the organic light emitting diode is connected with the direct-current low voltage.
Wherein the control signal is a shift register signal.
The first global signal, the second global signal and the third global signal are alternating current signals.
The first global signal, the second global signal and the third global signal are from an alternating current signal source fixed on the periphery of the display panel.
The utility model also provides a display panel, include as aforementioned any one the pixel circuit.
To sum up, the utility model discloses a pixel circuit and display panel provide the pixel circuit that has the internal compensation and only need a set of GOA circuit, do benefit to display panel's narrow frame design, do benefit to the concatenation of micro rolled display panel.
Drawings
The technical solution and other advantages of the present invention will become apparent from the following detailed description of the embodiments of the present invention, which is to be read in connection with the accompanying drawings.
In the drawings, there is shown in the drawings,
FIG. 1a is a diagram of a conventional pixel circuit;
FIG. 1b is a schematic diagram of a panel structure using the pixel circuit shown in FIG. 1 a;
FIG. 2a is a circuit diagram of a pixel circuit according to a preferred embodiment of the present invention;
FIG. 2b is a schematic diagram of a panel structure using the pixel circuit shown in FIG. 2 a;
FIG. 3a is a schematic diagram of a driving timing sequence of a display panel using the pixel circuit of FIG. 2 a;
FIG. 3b is a timing diagram of signals in the pixel circuit of FIG. 2 a;
FIG. 4 is a timing diagram of the pixel circuit of FIG. 2a during internal compensation
Fig. 5 is a schematic diagram of an operation process of the pixel circuit of fig. 2 a.
Detailed Description
Fig. 2a is a circuit diagram of a pixel circuit according to a preferred embodiment of the present invention. The utility model provides a pixel circuit has the internal compensation function, and only needs a set of GOA circuit cooperation to drive, because micro rolled needs to become the jumbo size panel through splicing, therefore the frame width of panel is more narrow better, the utility model discloses a pixel circuit does benefit to display panel's narrow frame design and micro rolled display panel's concatenation.
In the preferred embodiment, the pixel circuit mainly includes:
a first thin film transistor T1, the grid electrode of which is connected with a first node M, and the source electrode and the drain electrode of which are respectively connected with a second node N and a third node P;
a second thin film transistor T2, a grid electrode of which is connected with a second global signal G2, and a source electrode and a drain electrode of which are respectively connected with a direct current high voltage VDD and a third node P;
a third thin film transistor T3 having a gate connected to the first global signal G1, and a source and a drain connected to the first node M and the third node P, respectively;
a fourth thin film transistor T4 having a gate connected to the second global signal G2, and a source and a drain connected to the second node N and the fourth node F, respectively;
a fifth thin film transistor T5 having a gate connected to the third global signal G3, and a source and a drain connected to the fourth node F and the dc low voltage VSS, respectively;
a sixth thin film transistor T6 having a gate connected to the third global signal G3, and a source and a drain connected to the first node M and the fifth node K, respectively;
a seventh thin film transistor T7 having a gate connected to the control signal Scan, and a source and a drain connected to the Data signal Data and the fifth node K, respectively;
a first capacitor C1 connected between the fifth node K and the dc low voltage VSS;
a second capacitor C2 connected between the first node M and the fourth node F; and
and the anode of the organic light emitting diode OLED is connected with the second node N, and the cathode of the organic light emitting diode OLED is connected with the direct-current low voltage VSS.
Referring to fig. 2b, which is a schematic diagram of a panel structure using the pixel circuit shown in fig. 2a, it can be seen from fig. 2a that the pixel circuit of the preferred embodiment only needs one group of GOA signals, i.e., the control signal Scan, and G1, G2, and G3 global signals, so that only one group of GOA circuits is needed to provide the signal Scan, and accordingly, the frame of the display panel using the pixel circuit of the preferred embodiment is relatively narrow, which is beneficial to the splicing of a micro-rolled display panel.
Referring to fig. 3a and 3b, fig. 3a is a timing diagram of driving a display panel using the pixel circuit of fig. 2a, and fig. 3b is a timing diagram of signals in the pixel circuit of fig. 2 a. With reference to fig. 3a and 3b, the display panel performs frame-by-frame (frame) sequential display under the coordination of the GOA circuit, and performs line-by-line scanning on the pixels on the display panel in coordination with the GOA circuit within a frame time, where each frame time is divided into a Compensation phase (Compensation) and an OLED Emission phase (Emission), and the Compensation phase displays that the display panel does not emit light; the Scan signal is a shift register signal from the GOA circuit, a control signal Scan (n) of the current frame received by the frame (n), and a control signal Scan (n + 1) of the current frame received by the frame (n + 1); in each frame time, the Scan signals received by the pixel circuits in each row change line by line according to the characteristics of a shift register in the GOA circuit; g1 And G2 and G3 are global Alternating Current (AC) signals, and the global signals G1, G2 and G3 in each pixel circuit are all connected to an AC signal source fixed on the periphery of the display panel. Thus, the utility model discloses a pixel circuit only needs a set of GOA circuit to cooperate, and has the internal compensation function. Correspondingly, through inciting somebody to action the utility model provides a pixel circuit is applied to display panel, does benefit to display panel's narrow frame design, does benefit to micro rolled display panel's concatenation.
Referring to fig. 4, a timing diagram of the pixel circuit of fig. 2a for performing internal compensation is shown, wherein the amplitude of the signal can be set according to the following table.
Table I, signal voltage amplitude
Referring to fig. 5, it is a schematic diagram of the operation process of the pixel circuit of fig. 2 a. With reference to fig. 2a and the following table two, the working process of the pixel circuit of the present invention is described as follows, taking a single-stage pixel as an example.
The internal compensation operation of the pixel circuit is mainly divided into five stages.
1, A1-Signal Data storage phase: the signal Scan is raised to high potential, T7 is turned on, data is written into the storage capacitor C1 at the point K, meanwhile, the signal G1 is low potential, T6 is turned off, and the current I of the OLED at the moment OLED The OLED current generated for the previous frame data.
2, A2-M point reset phase: the signal G1 rises to a high level, T3 is turned on, and the potential at the point M is consistent with that at the point P.
3, A3-threshold Voltage Vth extraction phase: when the signal G2 is lowered to a low potential, T2 is turned off, the potential at the N point of the source of T1 starts to rise, and theoretically, the potential at the N point stops rising to Vth1 (threshold voltage of the OLED), and when the potential at the S point is greater than Vth1, the OLED is turned on, and the potential at the S point decreases. When the potentials at the M and P points theoretically rise to Vth1+ Vth2 (T1 threshold voltage), the TFT is turned off, and at this time VM-VN = Vth2, the TFT is turned off.
4, A4-Data writing phase, signal G3 is raised to high potential, T6 is turned on, and the Data potential of signal is written to M point.
5, A5-in the light-emitting stage, the signal G2 is raised to high potential, T2 is turned on, VDD potential is written into the point P, current flows through T1, and the OLED is turned on.
Second table, pixel circuit working state
To sum up, the utility model discloses a pixel circuit and display panel provide the pixel circuit that has the internal compensation and only need a set of GOA circuit, do benefit to display panel's narrow frame design, do benefit to the concatenation of micro rolled display panel.
From the above, it is obvious to those skilled in the art that various other changes and modifications can be made according to the technical solution and the technical idea of the present invention, and all such changes and modifications should fall within the protective scope of the appended claims.
Claims (5)
1. A pixel circuit, comprising:
a first thin film transistor (T1) having a gate connected to a first node (M), and a source and a drain connected to a second node (N) and a third node (P), respectively;
a second thin film transistor (T2) having a gate connected to a second global signal (G2), and a source and a drain connected to a direct current high Voltage (VDD) and a third node (P), respectively;
a third thin film transistor (T3) having a gate connected to the first global signal (G1), and a source and a drain connected to the first node (M) and the third node (P), respectively;
a fourth thin film transistor (T4) having a gate connected to the second global signal (G2), and a source and a drain connected to the second node (N) and the fourth node (F), respectively;
a fifth thin film transistor (T5) having a gate connected to the third global signal (G3), and a source and a drain connected to the fourth node (F) and the direct current low Voltage (VSS), respectively;
a sixth thin film transistor (T6) having a gate connected to the third global signal (G3), and a source and a drain connected to the first node (M) and the fifth node (K), respectively;
a seventh thin film transistor (T7) having a gate connected to the control signal (Scan), and a source and a drain connected to the Data signal (Data) and the fifth node (K), respectively;
a first capacitor (C1) connected between the fifth node (K) and a DC low Voltage (VSS);
a second capacitor (C2) connected between the first node (M) and a fourth node (F); and
and an Organic Light Emitting Diode (OLED) having an anode connected to the second node (N) and a cathode connected to a DC low Voltage (VSS).
2. A pixel circuit as claimed in claim 1, characterized in that the control signal (Scan) is a shift register signal.
3. The pixel circuit according to claim 1, wherein the first global signal (G1), the second global signal (G2), and the third global signal (G3) are alternating current signals.
4. The pixel circuit according to claim 1, wherein the first global signal (G1), the second global signal (G2), and the third global signal (G3) are from an ac signal source fixed at the periphery of the display panel.
5. A display panel comprising the pixel circuit according to any one of claims 1 to 4.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202222972505.7U CN218632044U (en) | 2022-11-08 | 2022-11-08 | Pixel circuit and display panel |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202222972505.7U CN218632044U (en) | 2022-11-08 | 2022-11-08 | Pixel circuit and display panel |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN218632044U true CN218632044U (en) | 2023-03-14 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202222972505.7U Expired - Fee Related CN218632044U (en) | 2022-11-08 | 2022-11-08 | Pixel circuit and display panel |
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| Country | Link |
|---|---|
| CN (1) | CN218632044U (en) |
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- 2022-11-08 CN CN202222972505.7U patent/CN218632044U/en not_active Expired - Fee Related
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Granted publication date: 20230314 |