CN218632044U - Pixel circuit and display panel - Google Patents

Abstract

The utility model relates to a pixel circuit and display panel. The pixel circuit includes: a first thin film transistor; a second thin film transistor (T2) having a gate connected to a second global signal (G2); a third thin film transistor (T3) having a gate connected to the first global signal (G1); a fourth thin film transistor (T4) having a gate connected to the second global signal (G2); a fifth thin film transistor (T5) having a gate connected to the third global signal (G3); a sixth thin film transistor (T6) having a gate connected to the third global signal (G3); a seventh thin film transistor (T7) having a gate connected to the control signal (Scan); a first capacitor (C1), a second capacitor (C2), and an Organic Light Emitting Diode (OLED). The utility model also provides a corresponding display panel. The utility model discloses a pixel circuit and display panel provide the pixel circuit that has the internal compensation and only need a set of GOA circuit, do benefit to display panel's narrow frame design, do benefit to micro display panel's concatenation.

Description

Pixel circuit and display panel

technical field

The utility model relates to the field of display technology, in particular to a pixel circuit and a display panel.

Background technique

As a new generation of display technology, Microled has higher contrast ratio, faster response speed and wider viewing angle than traditional LCD, and is widely used in smart phones and TV fields. In terms of driving methods, unlike LCDs, LEDs are current-driven and are sensitive to electrical variations of thin-film transistors (TFTs). The uniformity of the TFT threshold voltage Vth of the panel pixel circuit and the drift of Vth under stress (stress) both affect The accuracy and uniformity of the screen display, in order to solve this problem, a pixel compensation circuit is introduced. The traditional compensation circuit requires a large number of row scanning signals, which is not conducive to the narrow border of the panel.

As shown in Figure 1a and Figure 1b, Figure 1a is a schematic diagram of a traditional pixel circuit with internal compensation, and Figure 1b is a schematic diagram of a panel structure using the pixel circuit shown in Figure 1a, since three sets of signals Scan1, For Scan2 and Scan3, the pixel circuit needs three sets of GOA circuits. The panel using the traditional pixel circuit has three sets of GOA circuits: GOA1, GOA2 and GOA3. Therefore, the frame width of the panel is wider, which is not conducive to the splicing of microled. obvious. Since microleds need to be spliced into large-sized panels, the narrower the frame width of the panel, the better. The existing pixel circuit is not conducive to the narrow frame design requirements of the panel.

Utility model content

Therefore, the purpose of the present invention is to provide a pixel circuit, which is suitable for the narrow frame design requirements of the display panel.

Another object of the present invention is to provide a display panel, which is suitable for the narrow frame design requirements of the display panel.

In order to achieve the above purpose, the utility model provides a pixel circuit, comprising:

a first thin film transistor, the gate of which is connected to the first node, and the source and drain are respectively connected to the second node and the third node;

The gate of the second thin film transistor is connected to the second global signal, and the source and drain are respectively connected to the DC high voltage and the third node;

a third thin film transistor, the gate of which is connected to the first global signal, and the source and drain are respectively connected to the first node and the third node;

The gate of the fourth thin film transistor is connected to the second global signal, and the source and drain are respectively connected to the second node and the fourth node;

The gate of the fifth thin film transistor is connected to the third global signal, and the source and drain are respectively connected to the fourth node and the DC low voltage;

The sixth thin film transistor, the gate of which is connected to the third global signal, and the source and drain of which are respectively connected to the first node and the fifth node;

The seventh thin film transistor, the gate of which is connected to the control signal, and the source and drain of which are respectively connected to the data signal and the fifth node;

a first capacitor connected between the fifth node and the DC low voltage;

a second capacitor connected between the first node and the fourth node; and

An organic light emitting diode, the anode of which is connected to the second node, and the cathode is connected to a direct current low voltage.

Wherein, the control signal is a shift register signal.

Wherein, the first global signal, the second global signal and the third global signal are AC signals.

Wherein, the first global signal, the second global signal and the third global signal come from a fixed AC signal source around the display panel.

The utility model also provides a display panel, comprising the pixel circuit as described in any one of the foregoing items.

In summary, the pixel circuit and display panel of the present invention provide a pixel circuit with internal compensation and only need a set of GOA circuits, which is beneficial to the narrow frame design of the display panel and the splicing of microled display panels.

Description of drawings

The technical solution and other beneficial effects of the utility model will be apparent through the detailed description of the specific implementation of the utility model in conjunction with the accompanying drawings.

In the attached picture,

FIG. 1a is a schematic diagram of a conventional pixel circuit;

FIG. 1b is a schematic diagram of a panel structure using the pixel circuit shown in FIG. 1a;

Fig. 2a is a schematic circuit diagram of a preferred embodiment of the pixel circuit of the present invention;

FIG. 2b is a schematic diagram of a panel structure using the pixel circuit shown in FIG. 2a;

Fig. 3a is a schematic diagram of driving timing of a display panel using the pixel circuit in Fig. 2a;

Fig. 3b is a schematic timing diagram of signals in the pixel circuit in Fig. 2a;

Figure 4 is a timing diagram of the pixel circuit in Figure 2a performing internal compensation

FIG. 5 is a schematic diagram of the working process of the pixel circuit in FIG. 2a.

Detailed ways

Referring to FIG. 2 a , it is a schematic circuit diagram of a preferred embodiment of the pixel circuit of the present invention. The pixel circuit proposed by the utility model has an internal compensation function, and only needs a group of GOA circuits to drive it. Since the microled needs to be spliced into a large-size panel, the narrower the frame width of the panel, the better. The pixel of the utility model The circuit is beneficial to the narrow frame design of the display panel and the splicing of the microled display panel.

In this preferred embodiment, the pixel circuit mainly includes:

The gate of the first thin film transistor T1 is connected to the first node M, and the source and drain are respectively connected to the second node N and the third node P;

The gate of the second thin film transistor T2 is connected to the second global signal G2, and the source and drain are respectively connected to the DC high voltage VDD and the third node P;

The gate of the third thin film transistor T3 is connected to the first global signal G1, and the source and drain are respectively connected to the first node M and the third node P;

The gate of the fourth thin film transistor T4 is connected to the second global signal G2, and the source and drain are respectively connected to the second node N and the fourth node F;

The gate of the fifth thin film transistor T5 is connected to the third global signal G3, and the source and drain are respectively connected to the fourth node F and the DC low voltage VSS;

The gate of the sixth thin film transistor T6 is connected to the third global signal G3, and the source and drain are respectively connected to the first node M and the fifth node K;

The gate of the seventh thin film transistor T7 is connected to the control signal Scan, and the source and drain are respectively connected to the data signal Data and the fifth node K;

a first capacitor C1, which is connected between the fifth node K and the DC low voltage VSS;

a second capacitor C2 connected between the first node M and the fourth node F; and

The anode of the organic light emitting diode OLED is connected to the second node N, and the cathode is connected to the DC low voltage VSS.

Referring to Fig. 2b, it is a schematic diagram of the panel structure using the pixel circuit shown in Fig. 2a. Combining with Fig. 2a, it can be seen that the pixel circuit in this preferred embodiment only needs a set of GOA signals, namely the control signal Scan, and G1, G2, G3 global signals Therefore, only one set of GOA circuits is needed to cooperate to provide the signal Scan, and correspondingly, the frame of the display panel adopting the pixel circuit of this preferred embodiment is also narrower, which is beneficial to the splicing of microled display panels.

Referring to FIG. 3a and FIG. 3b, FIG. 3a is a schematic diagram of the driving timing of the display panel using the pixel circuit of FIG. 2a, and FIG. 3b is a schematic diagram of the timing of each signal in the pixel circuit of FIG. 2a. Combining Figure 3a and Figure 3b, the display panel is displayed frame by frame with the cooperation of the GOA circuit. Within a frame time, the pixels on the display panel are scanned line by line with the GOA circuit, and each frame time is divided into In the compensation stage (Compensation) and the OLED light emission stage (Emission), the display panel does not emit light in the compensation stage; the Scan signal is the shift register signal from the GOA circuit, the control signal Scan(n) of the current frame received by the frame (n), and the frame ( n+1) the control signal Scan(n+1) of the current frame received; within each frame time, the Scan signal received by each row of pixel circuits changes row by row according to the characteristics of the shift register in the GOA circuit; G1, G2, G3 It is a global alternating current (AC) signal, and the global signals G1, G2, G3 in each pixel circuit are connected to a fixed AC signal source around the display panel. Therefore, the pixel circuit of the present invention only needs a group of GOA circuits to cooperate, and has an internal compensation function. Correspondingly, by applying the pixel circuit provided by the present invention to the display panel, it is beneficial to the narrow frame design of the display panel and the splicing of the microled display panel.

Referring to FIG. 4 , it is a timing diagram of the internal compensation of the pixel circuit in FIG. 2 a , where the amplitude of the signal can be set with reference to the following table 1.

Table 1. Signal voltage amplitude

Referring to FIG. 5 , it is a schematic diagram of the working process of the pixel circuit in FIG. 2 a . Combining FIG. 2a and Table 2 below, taking a single-level pixel as an example, the working process of the pixel circuit of the present invention is illustrated as follows.

The internal compensation process of the pixel circuit is mainly divided into five stages.

1. A1——Signal Data storage stage: the signal Scan rises to a high potential, T7 is turned on, and the data is written into the storage capacitor C1 at point K, while the signal G1 is at a low potential, T6 is turned off, and the OLED current I _OLED is up at this time OLED current generated by one frame of data.

2. A2——M point reset stage: signal G1 rises to high potential, T3 is turned on, and the potential of M point is consistent with that of P point.

3. A3——threshold voltage Vth extraction stage: the signal G2 drops to a low potential, T2 is turned off, and the potential of the source N point of T1 starts to rise. In theory, the potential of the N point rises to Vth1 (OLED threshold voltage). When the potential is greater than Vth1, the OLED turns on and the potential of point S decreases. When the potentials of point M and point P theoretically rise to Vth1+Vth2 (T1 threshold voltage), the TFT is turned off. At this time, VM−VN=Vth2, so the TFT is turned off.

4. A4——In the data writing stage, the signal G3 rises to a high potential, T6 is turned on, and the signal Data potential is written to point M.

5. A5——In the light-emitting stage, the signal G2 rises to a high potential, T2 is turned on, the P point is written into the VDD potential, the current flows through T1, and the OLED turns on.

Table 2. Pixel circuit working status

In summary, the pixel circuit and display panel of the present invention provide a pixel circuit with internal compensation and only need a set of GOA circuits, which is beneficial to the narrow frame design of the display panel and the splicing of microled display panels.

As mentioned above, for those of ordinary skill in the art, various other corresponding changes and deformations can be made according to the technical scheme and technical concept of the present utility model, and all these changes and deformations should belong to the appendix of the utility model. The scope of the claims.

Claims (5)

1. A pixel circuit, comprising:

a first thin film transistor (T1) having a gate connected to a first node (M), and a source and a drain connected to a second node (N) and a third node (P), respectively;

a second thin film transistor (T2) having a gate connected to a second global signal (G2), and a source and a drain connected to a direct current high Voltage (VDD) and a third node (P), respectively;

a third thin film transistor (T3) having a gate connected to the first global signal (G1), and a source and a drain connected to the first node (M) and the third node (P), respectively;

a fourth thin film transistor (T4) having a gate connected to the second global signal (G2), and a source and a drain connected to the second node (N) and the fourth node (F), respectively;

a fifth thin film transistor (T5) having a gate connected to the third global signal (G3), and a source and a drain connected to the fourth node (F) and the direct current low Voltage (VSS), respectively;

a sixth thin film transistor (T6) having a gate connected to the third global signal (G3), and a source and a drain connected to the first node (M) and the fifth node (K), respectively;

a seventh thin film transistor (T7) having a gate connected to the control signal (Scan), and a source and a drain connected to the Data signal (Data) and the fifth node (K), respectively;

a first capacitor (C1) connected between the fifth node (K) and a DC low Voltage (VSS);

a second capacitor (C2) connected between the first node (M) and a fourth node (F); and

and an Organic Light Emitting Diode (OLED) having an anode connected to the second node (N) and a cathode connected to a DC low Voltage (VSS).

2. A pixel circuit as claimed in claim 1, characterized in that the control signal (Scan) is a shift register signal.

3. The pixel circuit according to claim 1, wherein the first global signal (G1), the second global signal (G2), and the third global signal (G3) are alternating current signals.

4. The pixel circuit according to claim 1, wherein the first global signal (G1), the second global signal (G2), and the third global signal (G3) are from an ac signal source fixed at the periphery of the display panel.

5. A display panel comprising the pixel circuit according to any one of claims 1 to 4.

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