WO2020186933A1 - Pixel circuit, method for driving same, electroluminescent display panel, and display device - Google Patents

Pixel circuit, method for driving same, electroluminescent display panel, and display device Download PDF

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Publication number
WO2020186933A1
WO2020186933A1 PCT/CN2020/074363 CN2020074363W WO2020186933A1 WO 2020186933 A1 WO2020186933 A1 WO 2020186933A1 CN 2020074363 W CN2020074363 W CN 2020074363W WO 2020186933 A1 WO2020186933 A1 WO 2020186933A1
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Prior art keywords
transistor
circuit
signal
coupled
signal terminal
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PCT/CN2020/074363
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French (fr)
Chinese (zh)
Inventor
王志冲
李付强
冯京
刘鹏
栾兴龙
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京东方科技集团股份有限公司
鄂尔多斯市源盛光电有限责任公司
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Publication of WO2020186933A1 publication Critical patent/WO2020186933A1/en

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]

Definitions

  • the present disclosure relates to the field of display technology, in particular to a pixel circuit, a driving method thereof, an electroluminescent display panel and a display device.
  • Electroluminescent displays are one of the hot spots in the field of flat panel display research. Compared with liquid crystal displays, electroluminescent devices have the advantages of low energy consumption, low production cost, self-luminescence, wide viewing angle and fast response speed. At present, in the field of flat panel displays such as mobile phones, PDAs, and digital cameras, electroluminescent displays have begun to replace traditional liquid crystal displays. Among them, pixel circuit design is the core technology of electroluminescent displays, which has important research significance.
  • the embodiment of the present disclosure provides a pixel circuit including: an initialization circuit, a data writing circuit, a drive control circuit, a light emission control circuit, and a light emitting device; wherein,
  • the initialization circuit is configured to respond to the signals provided by the reset signal terminal and the scan signal terminal to provide the drive control circuit and the anode of the light emitting device with the signal of the initialization signal terminal;
  • the data writing circuit is configured to write the signal provided by the data signal terminal to the drive control circuit in response to the signal provided by the scan signal terminal;
  • the light emission control circuit is configured to provide a signal of a first voltage signal terminal to the drive control circuit in response to a signal provided by the light emission control terminal; the signal provided by the light emission control terminal and the signal level provided by the scan signal terminal in contrast;
  • the driving control circuit is configured to generate a driving current for driving the light emitting device.
  • the drive control circuit includes: a second transistor and a first capacitor;
  • the gate and the first electrode of the second transistor are respectively coupled to the initialization circuit, and the second electrode of the second transistor is respectively coupled to the data writing circuit and the light emission control circuit;
  • the first electrode of the first capacitor is coupled to the gate of the second transistor, and the second electrode of the first capacitor is coupled to the first voltage signal terminal.
  • the initialization circuit includes: a first initialization circuit, a second initialization circuit, and an anode control circuit;
  • the first initialization circuit is configured to provide the signal of the initialization signal terminal to the second initialization circuit in response to the signal provided by the reset signal terminal;
  • the second initialization circuit is configured to turn on the gate and the first electrode of the second transistor in response to the signal provided by the scan signal terminal;
  • the anode control circuit is configured to turn on the first electrode of the second transistor and the anode of the light emitting device in response to the signal provided by the reset signal terminal.
  • the first initialization circuit includes: a fourth transistor;
  • the gate of the fourth transistor is coupled to the reset signal terminal, the first pole of the fourth transistor is coupled to the initialization signal terminal, and the second pole of the fourth transistor is coupled to the second initialization circuit Pick up.
  • the second initialization circuit includes: a sixth transistor and a seventh transistor;
  • the gate of the sixth transistor is coupled to the scan signal terminal, the first electrode of the sixth transistor is coupled to the second electrode of the fourth transistor, and the second electrode of the sixth transistor is coupled to the The gate of the second transistor is coupled;
  • the gate of the seventh transistor is coupled to the scan signal terminal, the first pole of the seventh transistor is coupled to the second pole of the fourth transistor, and the second pole of the seventh transistor is coupled to the The first pole of the second transistor is coupled.
  • the anode control circuit includes: a third transistor
  • the gate of the third transistor is coupled to the reset signal terminal, the first pole of the third transistor is coupled to the first pole of the second transistor, and the second pole of the third transistor is coupled to the reset signal terminal.
  • the cathode of the light emitting device is coupled to the second voltage signal terminal.
  • the data writing circuit includes: a fifth transistor;
  • the gate of the fifth transistor is coupled to the scan signal terminal, the first electrode of the fifth transistor is coupled to the data signal terminal, and the second electrode of the fifth transistor is coupled to the second transistor The second pole is coupled.
  • the light emission control circuit includes: a first transistor
  • the gate of the first transistor is coupled to the light-emitting control terminal; the first electrode of the first transistor is coupled to the first voltage signal terminal, and the second electrode of the first transistor is coupled to the first voltage signal terminal.
  • the second poles of the two transistors are coupled.
  • all transistors in the pixel circuit are P-type transistors, or all transistors in the pixel circuit are N-type transistors.
  • An embodiment of the present disclosure provides a method for driving a pixel circuit according to any one of the above embodiments, including:
  • the scan signal terminal and the reset signal terminal both provide a first level signal
  • the light-emitting control terminal provides a second level signal
  • the data signal terminal and the initialization signal terminal provide initialization signals ;
  • the scan signal terminal provides the first level signal
  • the reset signal terminal and the light emitting control terminal provide the second level signal
  • the data signal terminal provides a data signal
  • both the scan signal terminal and the reset signal terminal provide the second level signal, and the light-emitting control terminal provides the first level signal;
  • the scan signal terminal provides the second level signal
  • both the light-emitting control terminal and the reset signal terminal provide the first level signal
  • the embodiments of the present disclosure also provide an electroluminescent display panel, including the pixel circuit provided in any of the above-mentioned embodiments located in the display area and the driving circuit located in the non-display area;
  • the driving circuit includes a plurality of cascaded shift registers, each stage of the shift register includes a first output terminal and a second output terminal, and the signal provided by the first output terminal is the same as that provided by the second output terminal.
  • the signal level is opposite;
  • the first output terminal of the shift register of this stage is coupled to the scan signal terminal of the pixel circuit of this row, and the second output terminal of the shift register of this stage is coupled to the light emitting control terminal of the pixel circuit of this row.
  • the reset signal terminal of the pixel circuit of the current row is coupled to the second output terminal of the shift register of the next stage.
  • the embodiment of the present disclosure also provides a display device, including the above-mentioned electroluminescent display panel provided by the embodiment of the present disclosure.
  • FIG. 1 is a schematic diagram of a circuit structure in a related art electroluminescence display panel
  • FIG. 2 is a schematic structural diagram of a pixel circuit provided by an embodiment of the disclosure.
  • FIG. 3 is a schematic diagram of a specific structure of a pixel circuit provided by an embodiment of the disclosure.
  • FIG. 4 is a timing diagram of a pixel circuit provided by an embodiment of the disclosure.
  • FIG. 5 is a flowchart of a pixel circuit driving method provided by an embodiment of the disclosure.
  • the circuit structure of the electroluminescent display panel in the related art configured to drive the pixel display is shown in FIG. 1.
  • the pixel circuit Pixel includes a scanning signal terminal and a light-emitting control terminal (the specific structure of the pixel circuit is not shown), and because The design of the Pixel structure of the pixel circuit.
  • the signal of the scanning signal terminal and the signal of the light-emitting control terminal in the pixel circuit Pixel cannot be provided by the same driving circuit. Therefore, two driving circuits (light-emitting control driving circuit) are required in the non-display area of the electroluminescent display.
  • EM and gate drive circuit Gate can realize the control of the pixel circuit Pixel.
  • the two driving circuits occupy a larger area of the non-display area, which is not conducive to achieving a narrow frame design.
  • the embodiments of the present disclosure provide a pixel circuit, a driving method thereof, an electroluminescence display panel, and a display device.
  • a driving circuit can be used to provide driving signals to the scanning signal terminal and the light-emitting control terminal at the same time, which reduces the number of driving circuits and facilitates the narrow frame design of the electroluminescent display panel.
  • an embodiment of the present disclosure provides a pixel circuit, as shown in FIG. 2, comprising: an initialization circuit 0, a data writing circuit 4, a drive control circuit 5, a light emission control circuit 6, and a light emitting device O;
  • the initialization circuit 0 is configured to respond to the signals provided by the reset signal terminal EM_n+1 and the scan signal terminal G_n to provide the signal of the initialization signal terminal V to the driving control circuit 5 and the anode of the light emitting device O;
  • the data writing circuit 4 is configured to write the signal provided by the data signal terminal D to the drive control circuit 5 in response to the signal provided by the scan signal terminal G_n;
  • the light emission control circuit 6 is configured to provide a first voltage signal terminal ELVDD signal to the drive control circuit 5 in response to the signal provided by the light emission control terminal EM_n; the signal level provided by the light emission control terminal EM_n is opposite to the signal level provided by the scan signal terminal G_n ;
  • the drive control circuit 5 is configured to generate a drive current that drives the light emitting device O.
  • the initialization circuit 0, the data writing circuit 4, the drive control circuit 5, the light emission control circuit 6 and the light emitting device O are arranged so that the scan signal terminal G_n of the pixel circuit provides The signal level is opposite to the signal provided by the light-emitting control terminal EM_n, so a driving circuit can provide driving signals to the scanning signal terminal G_n and the light-emitting control terminal EM_n at the same time, which reduces the setting of the driving circuit and is beneficial to realize the electroluminescence display The narrow frame design of the panel.
  • the above-mentioned pixel circuit can also implement compensation for the threshold voltage of the driving transistor in the driving control circuit 5, that is, the second transistor, so as to ensure the uniformity of light emission of each pixel in the display panel.
  • the initialization circuit 0 may specifically include: a first initialization circuit 1, a second initialization circuit 2 and an anode control circuit 3;
  • the first initialization circuit 1 is configured to provide the signal of the initialization signal terminal V to the second initialization circuit 2 in response to the signal provided by the reset signal terminal EM_n+1, that is, to provide the signal of the initialization signal terminal V to the first node A (first node A).
  • Node A is the signal input terminal of the second initialization circuit 2);
  • the second initialization circuit 2 is configured to turn on the gate and the first pole of the second transistor M2 in response to the signal provided by the scan signal terminal Gate_n, even if the first node A (the first node A is the second initialization circuit 2
  • the signal input terminal is connected to the second node G (the second node G is the gate of the second transistor M2) and the third node D (the third node D is the first pole of the second transistor M2);
  • the anode control circuit 3 is configured to turn on the first electrode of the second transistor M2 and the anode of the light emitting device O in response to the signal provided by the reset signal terminal EM_n+1, that is, the third node D (the third node D is the second The potential of the first pole of the transistor M2) is supplied to the anode of the light emitting device O.
  • the setting of the above initialization circuit 0 can cooperate with the data writing circuit 4 to provide the signal of the data signal terminal D to the fourth node S under the control of the scan signal terminal G_n (the fourth node S is the second electrode of the second transistor M2 ), the drive control circuit 5 determines the magnitude of the drive current for driving the light-emitting device OLED under the control of the potential of the second node G (the second node G is the gate of the second transistor M2) and the potential of the fourth node S, The light emission control circuit 6 provides the signal of the first voltage signal terminal ELVDD to the fourth node S under the control of the light emission control terminal EM_n, which can compensate the threshold voltage of the driving transistor in the driving control circuit 5, that is, the second transistor. Ensure the uniformity of light emission of each pixel in the display panel.
  • the first initialization circuit 1 may specifically include: a fourth transistor M4;
  • the gate of the fourth transistor M4 is coupled to the reset signal terminal EM_n+1, the first pole of the fourth transistor M4 is coupled to the initialization signal terminal V, and the second pole of the fourth transistor M4 is coupled to the first node A, that is, the second initialization The signal input terminal of the circuit 2 is coupled.
  • the fourth transistor M4 may be a P-type transistor.
  • the fourth transistor M4 When the signal provided by the reset signal terminal EM_n+1 is low, the fourth transistor M4 is in a conducting state. When the signal provided by the signal terminal EM_n+1 is at a high level, the fourth transistor M4 is in an off state; the fourth transistor M4 may also be an N-type transistor (not specifically shown in the figure).
  • the signal terminal EM_n+ is reset
  • the fourth transistor M4 is in an on state, and when the signal provided by the reset signal terminal EM_n+1 is at a low level, the fourth transistor M4 is in an off state; there is no specific limitation here.
  • the second initialization circuit 2 may specifically include: a sixth transistor M6 and a seventh transistor M7;
  • the gate of the sixth transistor M6 is coupled to the scan signal terminal G_n, the first electrode of the sixth transistor M6 is coupled to the first node A, that is, the second electrode of the fourth transistor M4, and the second electrode of the sixth transistor M6 is coupled to the The second node G is coupled to the gate of the second transistor M2;
  • the gate of the seventh transistor M7 is coupled to the scan signal terminal G_n, the first electrode of the seventh transistor M7 is coupled to the first node A, that is, the second electrode of the fourth transistor M4, and the second electrode of the seventh transistor M7 is coupled to the The three-node D is coupled to the first pole of the second transistor M2.
  • the sixth transistor M6 may be a P-type transistor.
  • the sixth transistor M6 When the signal provided by the scan signal terminal G_n is low, the sixth transistor M6 is in a conducting state. When the signal provided by G_n is at a high level, the sixth transistor M6 is in an off state; the sixth transistor M6 may also be an N-type transistor (not specifically shown in the figure).
  • the signal provided by the scan signal terminal G_n when the signal provided by the scan signal terminal G_n is high When the voltage level is high, the sixth transistor M6 is in the on state, and when the signal provided by the scan signal terminal G_n is low, the sixth transistor M6 is in the off state; there is no specific limitation here.
  • the seventh transistor M7 can be a P-type transistor.
  • the seventh transistor M7 When the signal provided by the scan signal terminal G_n is low level, the seventh transistor M7 is in the conducting state. When the signal provided by the scan signal terminal G_n is high level, the seventh transistor M7 The transistor M7 is in an off state; the seventh transistor M7 can also be an N-type transistor (not specifically shown in the figure).
  • the seventh transistor M7 when the signal provided by the scan signal terminal G_n is at a high level, the seventh transistor M7 is in an on state When the signal provided by the scan signal terminal G_n is at a low level, the seventh transistor M7 is in an off state; it is not specifically limited here.
  • control terminals of the sixth transistor M6 and the seventh transistor M7 are the same, and both are the scan signal terminal G_n, and the types of the transistors are also the same, and they are either N-type transistors or It is a P-type transistor at the same time, ensuring that the sixth transistor M6 and the seventh transistor M7 are simultaneously turned on or turned off at the same stage.
  • the sixth transistor M6 is turned on to provide the potential of the first node A to the second node G, and initialize the second node G, the gate of the second transistor M2;
  • the transistor M7 is turned on to provide the potential of the first node A to the third node D, and provide an initialization signal for the anode of the light emitting device O.
  • the sixth transistor M6 and the seventh transistor M7 are turned on at the same time to write the data signal and the threshold voltage of the second transistor M2 to the gate of the second transistor M2, thereby realizing the threshold voltage Fetching and data writing.
  • the anode control circuit 3 may specifically include: a third transistor M3;
  • the gate of the third transistor M3 is coupled to the reset signal terminal EM_n+1, the first pole of the third transistor M3 is coupled to the third node D, that is, the first pole of the second transistor M2, and the second pole of the third transistor M3 Coupled with the anode of the light-emitting device O;
  • the cathode of the light emitting device O is coupled to the second voltage signal terminal ELVSS.
  • the third transistor M3 may be a P-type transistor.
  • the third transistor M3 When the signal provided by the reset signal terminal EM_n+1 is low, the third transistor M3 is in a conducting state. When the signal provided by the signal terminal EM_n+1 is at a high level, the third transistor M3 is in an off state; the third transistor M3 may also be an N-type transistor (not specifically shown in the figure).
  • the signal terminal EM_n+ is reset
  • the signal provided by 1 is at a high level
  • the third transistor M3 is in an on state, and when the signal provided by the reset signal terminal EM_n+1 is at a low level, the third transistor M3 is in an off state; there is no specific limitation here.
  • the data writing circuit 4 may specifically include: a fifth transistor M5;
  • the gate of the fifth transistor M5 is coupled to the scan signal terminal G_n, the first electrode of the fifth transistor M5 is coupled to the data signal terminal D, and the second electrode of the fifth transistor M5 is connected to the fourth node S of the second transistor M2.
  • the second pole is coupled.
  • the fifth transistor M5 may be a P-type transistor.
  • the fifth transistor M5 When the signal provided by the scan signal terminal G_n is low, the fifth transistor M5 is in a conducting state. When the signal provided by G_n is at a high level, the fifth transistor M5 is in an off state; the fifth transistor M5 can also be an N-type transistor (not specifically shown in the figure).
  • the signal provided by the scan signal terminal G_n when the signal provided by the scan signal terminal G_n is high When the voltage level, the fifth transistor M5 is in the on state, and when the signal provided by the scan signal terminal G_n is low, the fifth transistor M5 is in the off state; there is no specific limitation here.
  • the signal provided by the data signal terminal D is the same as the signal provided by the initialization signal terminal V, the fifth transistor M5 is turned on, and the initialization signal provided by the data signal terminal D is provided to the fourth node S, so that the second The potentials of the node G and the fourth node S are the same, ensuring that the second transistor M2 is in the off state.
  • the signal provided by the data signal terminal D is a data signal for driving the light-emitting device to emit light
  • the fifth transistor M5 is turned on to provide the data signal to the fourth node S to achieve data writing and threshold at the same time Of crawling.
  • the driving control circuit 5 may specifically include: a second transistor M2 and a first capacitor C1;
  • the gate and the first electrode of the second transistor M2 are respectively coupled to the initialization circuit 0, and the second electrode of the second transistor M2 is respectively coupled to the data writing circuit 4 and the light emission control circuit 6, specifically, the second transistor M2
  • the gate is coupled to the second node G, the first pole of the second transistor M2 is coupled to the fourth node S, and the second pole of the second transistor M2 is coupled to the third node D;
  • the first electrode of the first capacitor C1 is coupled to the second node G, that is, the gate of the second transistor, and the second electrode of the first capacitor C1 is coupled to the first voltage signal terminal ELVDD.
  • the second transistor M2 is a P-type transistor.
  • the voltage provided by the corresponding first voltage signal terminal ELVDD is generally It is a positive voltage
  • the voltage of the second voltage signal terminal ELVSS is generally grounded or negative.
  • the light emission control circuit 6 may specifically include: a first transistor M1;
  • the gate of the first transistor M1 is coupled to the emission control terminal EM_n; the first electrode of the first transistor M1 is coupled to the first voltage signal terminal ELVDD, and the second electrode of the first transistor M1 is coupled to the fourth node S, that is, the second transistor The second pole of M2 is coupled.
  • the first transistor M1 may be a P-type transistor.
  • the first transistor M1 When the signal provided by the light-emitting control terminal EM_n is low, the first transistor M1 is in a conducting state. When the signal provided by EM_n is at a high level, the first transistor M1 is in an off state; the first transistor M1 may also be an N-type transistor (not specifically shown in the figure).
  • the signal provided by the light-emitting control terminal EM_n is high
  • the first transistor M1 is in the on state, and when the signal provided by the light-emitting control terminal EM_n is in the low level, the first transistor M1 is in the off state; it is not specifically limited here.
  • each circuit in the pixel circuit is not limited to the above-mentioned structure provided by the embodiment of the present disclosure, and may also be other structures known to those skilled in the art. Make a limit.
  • all transistors are P-type transistors, or all transistors are N-type transistors.
  • the transistors mentioned in the above-mentioned pixel circuit provided by the embodiment of the present disclosure can all adopt P-type transistor design, which can simplify the manufacturing process of the pixel circuit.
  • the driving transistor is a P-type transistor as an example.
  • the case where the driving transistor is an N-type transistor and adopts the same design principle also belongs to the protection scope of the present disclosure.
  • the driving transistor and the switching transistor may be thin film transistors (TFT, Thin Film Transistor), or metal oxide semiconductor field effect transistors (MOS, Metal Oxide Semiconductor), which are not limited here.
  • TFT Thin Film Transistor
  • MOS Metal Oxide Semiconductor
  • the functions of the first pole and the second pole of these transistors can be interchanged according to the transistor type and the input signal, and no specific distinction is made here.
  • the pixel circuit shown in FIG. 3 and the timing sequence shown in FIG. 4 are respectively taken as examples to describe the working process of the pixel circuit provided by the embodiment of the present disclosure.
  • the signal provided by the initialization signal terminal V is a low-level signal
  • the signal provided by the first voltage signal ELVDD terminal is a high-level signal
  • the signal provided by the second voltage signal terminal ELVSS is a low-level signal
  • all transistors are P-type Transistor.
  • the reset signal terminal EM_n+1 is at low level
  • the fourth transistor M4 is turned on, and the initialization signal of the initialization signal terminal V is provided to the first node A to initialize the first node A
  • the scan signal terminal G_n is Low level
  • the sixth transistor M6 is turned on to provide the initialization signal of the first node A to the second node G (ie the gate of the second transistor M2)
  • the seventh transistor M7 is turned on to provide the initialization signal of the first node A To the third node D
  • the third transistor M3 is turned on, the initialization signal of the third node D is provided to the anode of the light-emitting device O, and the anode of the light-emitting device O is initialized;
  • the scan signal terminal G_n is a low-level signal
  • the fifth transistor M5 is also in the conducting state, at this time the signal provided by the data signal terminal D is the same initialization signal as the initialization signal terminal V, and the turned-on fifth transistor
  • the scan signal terminal G_n is a low-level signal
  • the fifth transistor M5, the sixth transistor M6, and the seventh transistor M7 are turned on
  • the turned-on fifth transistor M5 provides the data signal Vdata provided by the data signal terminal D to
  • the potential of the fourth node S up to the second node G is Vdata+Vth, where Vth represents the threshold voltage of the second transistor.
  • the scanning signal terminal G_n is at a high level
  • the fifth transistor M5, the sixth transistor M6, and the seventh transistor M7 are turned off
  • the light-emitting control terminal EM_n is at a low level
  • the first transistor M1 is turned on to turn on the first voltage signal terminal
  • the signal of ELVDD is provided to the fourth node S, and the second transistor M2 is turned on to provide the third node D with a voltage for driving the light emitting device O to emit light.
  • the third transistor M3 Since the gate of the third transistor M3 is coupled to the reset signal terminal EM_n+1, the signal of the reset signal terminal EM_n+1 is opposite to the level of the scan signal terminal G_n+1 in the pixel circuit configured to drive the next row of pixels Therefore, at this stage, the third transistor M3 is in an off state, and a driving current cannot be formed to drive the light-emitting device O to emit light.
  • the light-emitting control terminal EM_n and the reset signal terminal EM_n+1 are both low-level signals, and the first transistor M1 and the third transistor M3 are both turned on to form a current for driving the light-emitting device O to make the light-emitting device O emit light.
  • the signals of the light-emitting control terminal EM_n and the scanning signal terminal G_n can be provided by the same driving circuit, reducing the drive
  • the number of circuits facilitates the realization of the narrow frame design of the electroluminescent display panel.
  • the data signal terminal D provides the initialization signal in the first stage, and the data signal in the second stage, and in order to avoid the data signal when the second stage and the third stage alternate due to the delay of the data signal The change occurs, so the intermediate moment of providing the data signal (that is, the peak value of the data signal) is set at the alternate moment of the second stage and the third stage.
  • an embodiment of the present disclosure also provides a driving method of a pixel circuit, including:
  • both the scan signal terminal and the reset signal terminal provide a first level signal
  • the light-emitting control terminal provides a second level signal
  • the signal provided by the data signal terminal is the same as the signal provided by the initialization signal terminal, that is, the initialization signal
  • the scan signal terminal provides a first level signal
  • the reset signal terminal and the light emitting control terminal provide a second level signal
  • the data signal terminal provides a data signal for lighting the light emitting device
  • both the scan signal terminal and the reset signal terminal provide a second level signal, and the light-emitting control terminal provides a first level signal;
  • the scanning signal terminal provides a second level signal
  • both the light emitting control terminal and the reset signal terminal provide the first level signal
  • the first level signal and the second level signal can be either a high level signal or a low level signal.
  • the second level signal The signal is a low level signal; when the first level signal is a low level signal, the second level signal is a high level signal.
  • the first level signal is a low-level signal
  • the second level signal is a high level signal.
  • each transistor is a P-type transistor
  • the first level signal is a low-level signal
  • the second level signal is a high-level signal
  • the first level signal is high Level signal
  • the second level signal is a low level signal.
  • the specific working principle of the driving method of the pixel circuit has been described in detail in the specific embodiment of the above-mentioned pixel circuit. Therefore, the driving method of the pixel circuit can be implemented with reference to the above-described embodiment of the pixel circuit, which will not be omitted here. Repeat.
  • an embodiment of the present disclosure also provides an electroluminescent display panel, including a pixel circuit provided in any of the above-mentioned embodiments in a display area and a driving circuit in a non-display area;
  • the driving circuit includes a plurality of cascaded shift registers, each stage of shift register includes a first output terminal and a second output terminal, and the signal provided by the first output terminal is opposite to the signal provided by the second output terminal;
  • the first output terminal of the shift register of the current stage is coupled to the scan signal terminal of the pixel circuit of the current stage, and the second output terminal of the shift register of the current stage is coupled to the light emission control terminal of the pixel circuit of the current stage;
  • the reset signal terminal of the pixel circuit of the current row is coupled to the second output terminal of the next stage shift register.
  • only one driving circuit can be provided in the non-display area to provide driving signals to each signal terminal of the pixel circuit, which reduces the area occupied by the non-display area by the driving circuit. Conducive to the realization of a narrow frame design.
  • the embodiments of the present disclosure also provide a display device, including the above-mentioned electroluminescent display panel provided by the embodiments of the present disclosure.
  • the display device can be a monitor, a mobile phone, a TV, a notebook computer, an electronic paper, a digital photo frame, a navigator, an all-in-one machine, etc., and other indispensable components of the display device should be understood by those of ordinary skill in the art. It will not be repeated here, nor should it be used as a limitation to the present disclosure.
  • Embodiments of the present disclosure provide a pixel circuit, a driving method thereof, an electroluminescent display panel, and a display device.
  • the pixel circuit includes: a first initialization circuit, a second initialization circuit, an anode control circuit, a data writing circuit, and a drive control
  • the first initialization circuit provides the signal of the initialization signal terminal to the first node under the control of the reset signal terminal;
  • the second initialization circuit makes the first node and the second node and the first node under the control of the scan signal terminal
  • the three nodes are turned on;
  • the anode control circuit provides the potential of the third node to the anode of the light-emitting device under the control of the reset signal terminal;
  • the data writing circuit provides the signal of the data signal terminal to the fourth node under the control of the scan signal terminal; drive control
  • the circuit determines the magnitude of the driving current for driving the light emitting device under the control of the potential of the second node and the potential of the fourth node; the light
  • the level of the signal provided by the scan signal terminal of the pixel circuit and the signal provided by the light-emitting control terminal are opposite, so a driving circuit can be used to provide driving signals to the scan signal terminal and the light-emitting control terminal, reducing
  • the arrangement of the driving circuit is beneficial to realize the narrow frame design of the electroluminescent display panel.

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Abstract

Disclosed are a pixel circuit, a method for driving same, an electroluminescent display panel, and a display device. The pixel circuit comprises: an initialization circuit (0), a data write-in circuit (4), a driving control circuit (5), a light-emitting control circuit (6) and a light-emitting device (O), wherein by means of designing a structure of the pixel circuit, the level of a signal provided by a scanning signal end (G_n) of the pixel circuit and the level of a signal provided by a light-emitting control end (EM_n) of the pixel circuit can be the reverse; therefore, driving signals can be provided to the scanning signal end (G_n) and the light-emitting control end (EM_n) by means of one driving circuit, thus reducing the arrangement of the driving circuit, and facilitating the narrow frame design of the electroluminescent display panel.

Description

像素电路、其驱动方法、电致发光显示面板及显示装置Pixel circuit, driving method thereof, electroluminescence display panel and display device
相关申请的交叉引用Cross references to related applications
本公开要求在2019年03月20日提交中国专利局、申请号为201910210941.0、申请名称为“一种像素电路、其驱动方法及电致发光显示面板”的中国专利申请的优先权，其全部内容通过引用结合在本公开中。This disclosure requires the priority of a Chinese patent application filed with the Chinese Patent Office, the application number is 201910210941.0, and the application name is "a pixel circuit, its driving method, and an electroluminescent display panel" on March 20, 2019, and its entire contents Incorporated in this disclosure by reference.
技术领域Technical field
本公开涉及显示技术领域，尤指一种像素电路、其驱动方法、电致发光显示面板及显示装置。The present disclosure relates to the field of display technology, in particular to a pixel circuit, a driving method thereof, an electroluminescent display panel and a display device.
背景技术Background technique
电致发光显示器是当今平板显示器研究领域的热点之一，与液晶显示器相比，电致发光器件具有低能耗、生产成本低、自发光、宽视角及响应速度快等优点。目前，在手机、PDA、数码相机等平板显示领域，电致发光显示器已经开始取代传统的液晶显示屏。其中，像素电路设计是电致发光显示器的核心技术，具有重要的研究意义。Electroluminescent displays are one of the hot spots in the field of flat panel display research. Compared with liquid crystal displays, electroluminescent devices have the advantages of low energy consumption, low production cost, self-luminescence, wide viewing angle and fast response speed. At present, in the field of flat panel displays such as mobile phones, PDAs, and digital cameras, electroluminescent displays have begun to replace traditional liquid crystal displays. Among them, pixel circuit design is the core technology of electroluminescent displays, which has important research significance.
发明内容Summary of the invention
本公开实施例提供了一种像素电路，包括：初始化电路，数据写入电路，驱动控制电路，发光控制电路以及发光器件；其中，The embodiment of the present disclosure provides a pixel circuit including: an initialization circuit, a data writing circuit, a drive control circuit, a light emission control circuit, and a light emitting device; wherein,
所述初始化电路被配置为响应于复位信号端和扫描信号端提供的信号，对所述驱动控制电路和所述发光器件的阳极提供初始化信号端的信号；The initialization circuit is configured to respond to the signals provided by the reset signal terminal and the scan signal terminal to provide the drive control circuit and the anode of the light emitting device with the signal of the initialization signal terminal;
所述数据写入电路被配置为响应于所述扫描信号端提供的信号，对所述驱动控制电路写入数据信号端提供的信号；The data writing circuit is configured to write the signal provided by the data signal terminal to the drive control circuit in response to the signal provided by the scan signal terminal;
所述发光控制电路被配置为响应于发光控制端提供的信号，对所述驱动控制电路提供第一电压信号端的信号；所述发光控制端提供的信号与所述扫 描信号端提供的信号电平相反；The light emission control circuit is configured to provide a signal of a first voltage signal terminal to the drive control circuit in response to a signal provided by the light emission control terminal; the signal provided by the light emission control terminal and the signal level provided by the scan signal terminal in contrast;
所述驱动控制电路被配置为产生驱动所述发光器件的驱动电流。The driving control circuit is configured to generate a driving current for driving the light emitting device.
在一种可能的实施方式中，在本公开实施例提供的像素电路中，所述驱动控制电路包括：第二晶体管和第一电容；In a possible implementation manner, in the pixel circuit provided by the embodiment of the present disclosure, the drive control circuit includes: a second transistor and a first capacitor;
所述第二晶体管的栅极和第一极分别与所述初始化电路耦接，所述第二晶体管的第二极分别与所述数据写入电路和所述发光控制电路耦接；The gate and the first electrode of the second transistor are respectively coupled to the initialization circuit, and the second electrode of the second transistor is respectively coupled to the data writing circuit and the light emission control circuit;
所述第一电容的第一电极与所述第二晶体管的栅极耦接，所述第一电容的第二电极与所述第一电压信号端耦接。The first electrode of the first capacitor is coupled to the gate of the second transistor, and the second electrode of the first capacitor is coupled to the first voltage signal terminal.
在一种可能的实施方式中，在本公开实施例提供的像素电路中，所述初始化电路包括：第一初始化电路、第二初始化电路和阳极控制电路；In a possible implementation manner, in the pixel circuit provided in the embodiment of the present disclosure, the initialization circuit includes: a first initialization circuit, a second initialization circuit, and an anode control circuit;
所述第一初始化电路被配置为响应于所述复位信号端提供的信号，对所述第二初始化电路提供所述初始化信号端的信号；The first initialization circuit is configured to provide the signal of the initialization signal terminal to the second initialization circuit in response to the signal provided by the reset signal terminal;
所述第二初始化电路被配置为响应于所述扫描信号端提供的信号，导通所述第二晶体管的栅极和第一极；The second initialization circuit is configured to turn on the gate and the first electrode of the second transistor in response to the signal provided by the scan signal terminal;
所述阳极控制电路被配置为响应于所述复位信号端提供的信号，导通所述第二晶体管的第一极和所述发光器件的阳极。The anode control circuit is configured to turn on the first electrode of the second transistor and the anode of the light emitting device in response to the signal provided by the reset signal terminal.
在一种可能的实施方式中，在本公开实施例提供的像素电路中，所述第一初始化电路包括：第四晶体管；In a possible implementation manner, in the pixel circuit provided by the embodiment of the present disclosure, the first initialization circuit includes: a fourth transistor;
所述第四晶体管的栅极与所述复位信号端耦接，所述第四晶体管的第一极与初始化信号端耦接，所述第四晶体管的第二极与所述第二初始化电路耦接。The gate of the fourth transistor is coupled to the reset signal terminal, the first pole of the fourth transistor is coupled to the initialization signal terminal, and the second pole of the fourth transistor is coupled to the second initialization circuit Pick up.
在一种可能的实施方式中，在本公开实施例提供的像素电路中，所述第二初始化电路包括：第六晶体管和第七晶体管；In a possible implementation manner, in the pixel circuit provided by the embodiment of the present disclosure, the second initialization circuit includes: a sixth transistor and a seventh transistor;
所述第六晶体管的栅极与所述扫描信号端耦接，所述第六晶体管的第一极与所述第四晶体管的第二极耦接，所述第六晶体管的第二极与所述第二晶体管的栅极耦接；The gate of the sixth transistor is coupled to the scan signal terminal, the first electrode of the sixth transistor is coupled to the second electrode of the fourth transistor, and the second electrode of the sixth transistor is coupled to the The gate of the second transistor is coupled;
所述第七晶体管的栅极与所述扫描信号端耦接，所述第七晶体管的第一 极与所述第四晶体管的第二极耦接，所述第七晶体管的第二极与所述第二晶体管的第一极耦接。The gate of the seventh transistor is coupled to the scan signal terminal, the first pole of the seventh transistor is coupled to the second pole of the fourth transistor, and the second pole of the seventh transistor is coupled to the The first pole of the second transistor is coupled.
在一种可能的实施方式中，在本公开实施例提供的像素电路中，所述阳极控制电路包括：第三晶体管；In a possible implementation manner, in the pixel circuit provided by the embodiment of the present disclosure, the anode control circuit includes: a third transistor;
所述第三晶体管的栅极与所述复位信号端耦接，所述第三晶体管的第一极与所述第二晶体管的第一极耦接，所述第三晶体管的第二极与所述发光器件的阳极耦接；The gate of the third transistor is coupled to the reset signal terminal, the first pole of the third transistor is coupled to the first pole of the second transistor, and the second pole of the third transistor is coupled to the reset signal terminal. The anode coupling of the light-emitting device;
所述发光器件的阴极与第二电压信号端耦接。The cathode of the light emitting device is coupled to the second voltage signal terminal.
在一种可能的实施方式中，在本公开实施例提供的像素电路中，所述数据写入电路包括：第五晶体管；In a possible implementation manner, in the pixel circuit provided by the embodiment of the present disclosure, the data writing circuit includes: a fifth transistor;
所述第五晶体管的栅极与所述扫描信号端耦接，所述第五晶体管的第一极与所述数据信号端耦接，所述第五晶体管的第二极与所述第二晶体管的第二极耦接。The gate of the fifth transistor is coupled to the scan signal terminal, the first electrode of the fifth transistor is coupled to the data signal terminal, and the second electrode of the fifth transistor is coupled to the second transistor The second pole is coupled.
在一种可能的实施方式中，在本公开实施例提供的像素电路中，所述发光控制电路包括：第一晶体管；In a possible implementation manner, in the pixel circuit provided by the embodiment of the present disclosure, the light emission control circuit includes: a first transistor;
所述第一晶体管的栅极与所述发光控制端耦接；所述第一晶体管的第一极与所述第一电压信号端耦接，所述第一晶体管的第二极与所述第二晶体管的第二极耦接。The gate of the first transistor is coupled to the light-emitting control terminal; the first electrode of the first transistor is coupled to the first voltage signal terminal, and the second electrode of the first transistor is coupled to the first voltage signal terminal. The second poles of the two transistors are coupled.
在一种可能的实施方式中，在本公开实施例提供的像素电路中，所述像素电路中的所有晶体管均为P型晶体管，或，所述像素电路中的所有晶体管均为N型晶体管。In a possible implementation manner, in the pixel circuit provided in the embodiment of the present disclosure, all transistors in the pixel circuit are P-type transistors, or all transistors in the pixel circuit are N-type transistors.
本公开实施例提供了一种上述任一实施例所述的像素电路的驱动方法，包括：An embodiment of the present disclosure provides a method for driving a pixel circuit according to any one of the above embodiments, including:
第一阶段，所述扫描信号端和所述复位信号端均提供第一电平信号，所述发光控制端提供第二电平信号，所述数据信号端与所述初始化信号端提供的初始化信号；In the first stage, the scan signal terminal and the reset signal terminal both provide a first level signal, the light-emitting control terminal provides a second level signal, and the data signal terminal and the initialization signal terminal provide initialization signals ；
第二阶段，所述扫描信号端提供所述第一电平信号，所述复位信号端和 所述发光控制端提供所述第二电平信号，所述数据信号端提供数据信号；In the second stage, the scan signal terminal provides the first level signal, the reset signal terminal and the light emitting control terminal provide the second level signal, and the data signal terminal provides a data signal;
第三阶段，所述扫描信号端和所述复位信号端均提供所述第二电平信号，所述发光控制端提供所述第一电平信号；In the third stage, both the scan signal terminal and the reset signal terminal provide the second level signal, and the light-emitting control terminal provides the first level signal;
第四阶段，所述扫描信号端提供所述第二电平信号，所述发光控制端和所述复位信号端均提供所述第一电平信号。In the fourth stage, the scan signal terminal provides the second level signal, and both the light-emitting control terminal and the reset signal terminal provide the first level signal.
本公开实施例还提供了一种电致发光显示面板，包括位于显示区域的如上述任一实施例提供的像素电路和位于非显示区域的驱动电路；The embodiments of the present disclosure also provide an electroluminescent display panel, including the pixel circuit provided in any of the above-mentioned embodiments located in the display area and the driving circuit located in the non-display area;
所述驱动电路包括多个级联的移位寄存器，每级所述移位寄存器包括第一输出端和第二输出端，所述第一输出端提供的信号与所述第二输出端提供的信号的电平相反；The driving circuit includes a plurality of cascaded shift registers, each stage of the shift register includes a first output terminal and a second output terminal, and the signal provided by the first output terminal is the same as that provided by the second output terminal. The signal level is opposite;
本级所述移位寄存器的第一输出端与本行所述像素电路的扫描信号端耦接，本级所述移位寄存器的第二输出端与本行所述像素电路的发光控制端耦接；The first output terminal of the shift register of this stage is coupled to the scan signal terminal of the pixel circuit of this row, and the second output terminal of the shift register of this stage is coupled to the light emitting control terminal of the pixel circuit of this row. Connect
本行所述像素电路的复位信号端与下一级所述移位寄存器的第二输出端耦接。The reset signal terminal of the pixel circuit of the current row is coupled to the second output terminal of the shift register of the next stage.
本公开实施例还提供了一种显示装置，包括本公开实施例提供的上述电致发光显示面板。The embodiment of the present disclosure also provides a display device, including the above-mentioned electroluminescent display panel provided by the embodiment of the present disclosure.
附图说明Description of the drawings
图1为相关技术的电致发光显示面板中的电路结构的示意图；FIG. 1 is a schematic diagram of a circuit structure in a related art electroluminescence display panel;
图2为本公开实施例提供的像素电路的结构示意图；2 is a schematic structural diagram of a pixel circuit provided by an embodiment of the disclosure;
图3为本公开实施例提供的像素电路的具体结构示意图；3 is a schematic diagram of a specific structure of a pixel circuit provided by an embodiment of the disclosure;
图4为本公开实施例提供的像素电路的时序图；4 is a timing diagram of a pixel circuit provided by an embodiment of the disclosure;
图5为本公开实施例提供的像素电路驱动方法的流程图。FIG. 5 is a flowchart of a pixel circuit driving method provided by an embodiment of the disclosure.
具体实施方式detailed description
相关技术中电致发光显示面板中的被配置为驱动像素显示的电路结构如 图1所示，该像素电路Pixel包括扫描信号端和发光控制端(像素电路的具体结构未示出)，且由于像素电路Pixel结构的设计，该像素电路Pixel中扫描信号端的信号和发光控制端的信号并不能通过同一驱动电路提供，因此需要在电致发光显示器的非显示区域设置两个驱动电路(发光控制驱动电路EM和栅极驱动电路Gate)，才能实现对像素电路Pixel进行控制。但是两个驱动电路占据了非显示区域的较大面积，不利于实现窄边框设计。The circuit structure of the electroluminescent display panel in the related art configured to drive the pixel display is shown in FIG. 1. The pixel circuit Pixel includes a scanning signal terminal and a light-emitting control terminal (the specific structure of the pixel circuit is not shown), and because The design of the Pixel structure of the pixel circuit. The signal of the scanning signal terminal and the signal of the light-emitting control terminal in the pixel circuit Pixel cannot be provided by the same driving circuit. Therefore, two driving circuits (light-emitting control driving circuit) are required in the non-display area of the electroluminescent display. EM and gate drive circuit Gate) can realize the control of the pixel circuit Pixel. However, the two driving circuits occupy a larger area of the non-display area, which is not conducive to achieving a narrow frame design.
针对上述问题，本公开实施例提供了一种像素电路、其驱动方法、电致发光显示面板及显示装置，通过对像素电路的结构进行设计，使扫描信号端的信号和发光控制端的信号的电平相反，从而实现可以利用一个驱动电路同时向扫描信号端和发光控制端提供驱动信号，减少了驱动电路的个数，有利于电致发光显示面板的窄边框设计。In response to the above problems, the embodiments of the present disclosure provide a pixel circuit, a driving method thereof, an electroluminescence display panel, and a display device. By designing the structure of the pixel circuit, the level of the signal at the scanning signal terminal and the signal at the light emitting control terminal On the contrary, it is realized that a driving circuit can be used to provide driving signals to the scanning signal terminal and the light-emitting control terminal at the same time, which reduces the number of driving circuits and facilitates the narrow frame design of the electroluminescent display panel.
为了使本公开的目的，技术方案和优点更加清楚，下面结合附图，对本公开实施例提供的像素电路、其驱动方法、电致发光显示面板及显示装置的具体实施方式进行详细地说明。应当理解，下面所描述的优选实施例仅被配置为说明和解释本公开，并不被配置为限定本公开。并且在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互组合。In order to make the objectives, technical solutions and advantages of the present disclosure clearer, specific implementations of the pixel circuit, its driving method, the electroluminescent display panel and the display device provided by the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. It should be understood that the preferred embodiments described below are only configured to illustrate and explain the present disclosure, and are not configured to limit the present disclosure. And in the case of no conflict, the embodiments in the present disclosure and the features in the embodiments can be combined with each other.
具体地，本公开实施例提供了一种像素电路，如图2所示，包括：初始化电路0，数据写入电路4，驱动控制电路5，发光控制电路6以及发光器件O；Specifically, an embodiment of the present disclosure provides a pixel circuit, as shown in FIG. 2, comprising: an initialization circuit 0, a data writing circuit 4, a drive control circuit 5, a light emission control circuit 6, and a light emitting device O;
初始化电路0被配置为响应于复位信号端EM_n+1和扫描信号端G_n提供的信号，对驱动控制电路5和发光器件O的阳极提供初始化信号端V的信号；The initialization circuit 0 is configured to respond to the signals provided by the reset signal terminal EM_n+1 and the scan signal terminal G_n to provide the signal of the initialization signal terminal V to the driving control circuit 5 and the anode of the light emitting device O;
数据写入电路4被配置为响应于扫描信号端G_n提供的信号，对驱动控制电路5写入数据信号端D提供的信号；The data writing circuit 4 is configured to write the signal provided by the data signal terminal D to the drive control circuit 5 in response to the signal provided by the scan signal terminal G_n;
发光控制电路6被配置为响应于发光控制端EM_n提供的信号，对驱动控制电路5提供第一电压信号端ELVDD的信号；发光控制端EM_n提供的信号与扫描信号端G_n提供的信号电平相反；The light emission control circuit 6 is configured to provide a first voltage signal terminal ELVDD signal to the drive control circuit 5 in response to the signal provided by the light emission control terminal EM_n; the signal level provided by the light emission control terminal EM_n is opposite to the signal level provided by the scan signal terminal G_n ；
驱动控制电路5被配置为产生驱动发光器件O的驱动电流。The drive control circuit 5 is configured to generate a drive current that drives the light emitting device O.
具体地，在本公开实施例提供的像素电路中，通过初始化电路0，数据写入电路4，驱动控制电路5，发光控制电路6以及发光器件O的设置，使像素电路的扫描信号端G_n提供的信号和发光控制端EM_n提供的信号的电平相反，因此可以通过一个驱动电路同时向扫描信号端G_n和发光控制端EM_n提供驱动信号，减少了驱动电路的设置，有利于实现电致发光显示面板的窄边框设计。Specifically, in the pixel circuit provided by the embodiment of the present disclosure, the initialization circuit 0, the data writing circuit 4, the drive control circuit 5, the light emission control circuit 6 and the light emitting device O are arranged so that the scan signal terminal G_n of the pixel circuit provides The signal level is opposite to the signal provided by the light-emitting control terminal EM_n, so a driving circuit can provide driving signals to the scanning signal terminal G_n and the light-emitting control terminal EM_n at the same time, which reduces the setting of the driving circuit and is beneficial to realize the electroluminescence display The narrow frame design of the panel.
除上述之外，上述像素电路还可以实现对驱动控制电路5中的驱动晶体管即第二晶体管的阈值电压进行补偿，以保证显示面板中各像素发光的均一性。In addition to the above, the above-mentioned pixel circuit can also implement compensation for the threshold voltage of the driving transistor in the driving control circuit 5, that is, the second transistor, so as to ensure the uniformity of light emission of each pixel in the display panel.
具体地，在本公开实施例提供的上述像素电路中，如图2所示，初始化电路0具体可以包括：第一初始化电路1，第二初始化电路2和阳极控制电路3；Specifically, in the aforementioned pixel circuit provided by the embodiment of the present disclosure, as shown in FIG. 2, the initialization circuit 0 may specifically include: a first initialization circuit 1, a second initialization circuit 2 and an anode control circuit 3;
第一初始化电路1被配置为响应于复位信号端EM_n+1提供的信号，对第二初始化电路2提供初始化信号端V的信号，即将初始化信号端V的信号提供给第一节点A(第一节点A即为第二初始化电路2的信号输入端)；The first initialization circuit 1 is configured to provide the signal of the initialization signal terminal V to the second initialization circuit 2 in response to the signal provided by the reset signal terminal EM_n+1, that is, to provide the signal of the initialization signal terminal V to the first node A (first node A). Node A is the signal input terminal of the second initialization circuit 2);
第二初始化电路2被配置为响应于扫描信号端Gate_n提供的信号，导通第二晶体管M2的栅极和第一极，即使第一节点A(第一节点A即为第二初始化电路2的信号输入端)与第二节点G(第二节点G即为第二晶体管M2的栅极)和第三节点D(第三节点D即为第二晶体管M2的第一极)导通；The second initialization circuit 2 is configured to turn on the gate and the first pole of the second transistor M2 in response to the signal provided by the scan signal terminal Gate_n, even if the first node A (the first node A is the second initialization circuit 2 The signal input terminal) is connected to the second node G (the second node G is the gate of the second transistor M2) and the third node D (the third node D is the first pole of the second transistor M2);
阳极控制电路3被配置为响应于复位信号端EM_n+1提供的信号，导通第二晶体管M2的第一极和发光器件O的阳极，即将第三节点D(第三节点D即为第二晶体管M2的第一极)的电位提供给发光器件O的阳极。The anode control circuit 3 is configured to turn on the first electrode of the second transistor M2 and the anode of the light emitting device O in response to the signal provided by the reset signal terminal EM_n+1, that is, the third node D (the third node D is the second The potential of the first pole of the transistor M2) is supplied to the anode of the light emitting device O.
上述初始化电路0的设置，可以配合数据写入电路4在扫描信号端G_n的控制下将数据信号端D的信号提供给第四节点S(第四节点S即为第二晶体管M2的第二极)，驱动控制电路5在第二节点G(第二节点G即为第二晶体管M2的栅极)的电位和第四节点S的电位的控制下，确定驱动发光器件 OLED的驱动电流的大小，发光控制电路6在发光控制端EM_n的控制下将第一电压信号端ELVDD的信号提供给第四节点S，可以实现对驱动控制电路5中的驱动晶体管即第二晶体管的阈值电压进行补偿，以保证显示面板中各像素发光的均一性。The setting of the above initialization circuit 0 can cooperate with the data writing circuit 4 to provide the signal of the data signal terminal D to the fourth node S under the control of the scan signal terminal G_n (the fourth node S is the second electrode of the second transistor M2 ), the drive control circuit 5 determines the magnitude of the drive current for driving the light-emitting device OLED under the control of the potential of the second node G (the second node G is the gate of the second transistor M2) and the potential of the fourth node S, The light emission control circuit 6 provides the signal of the first voltage signal terminal ELVDD to the fourth node S under the control of the light emission control terminal EM_n, which can compensate the threshold voltage of the driving transistor in the driving control circuit 5, that is, the second transistor. Ensure the uniformity of light emission of each pixel in the display panel.
下面结合具体实施例，对本公开进行详细说明。需要说明的是，本实施例中是为了更好的解释本公开，但不限制本公开。The disclosure will be described in detail below in conjunction with specific embodiments. It should be noted that the purpose of this embodiment is to better explain the present disclosure, but does not limit the present disclosure.
可选地，在本公开实施例提供的像素电路中，如图3所示，第一初始化电路1具体可以包括：第四晶体管M4；Optionally, in the pixel circuit provided by the embodiment of the present disclosure, as shown in FIG. 3, the first initialization circuit 1 may specifically include: a fourth transistor M4;
第四晶体管M4的栅极与复位信号端EM_n+1耦接，第四晶体管M4的第一极与初始化信号端V耦接，第四晶体管M4的第二极与第一节点A即第二初始化电路2的信号输入端耦接。The gate of the fourth transistor M4 is coupled to the reset signal terminal EM_n+1, the first pole of the fourth transistor M4 is coupled to the initialization signal terminal V, and the second pole of the fourth transistor M4 is coupled to the first node A, that is, the second initialization The signal input terminal of the circuit 2 is coupled.
具体地，在本公开实施例提供的像素电路中，第四晶体管M4可以为P型晶体管，当复位信号端EM_n+1提供的信号为低电平时，第四晶体管M4处于导通状态，当复位信号端EM_n+1提供的信号为高电平时，第四晶体管M4处于截止状态；第四晶体管M4也可以为N型晶体管(在图中未具体示出)，此时，当复位信号端EM_n+1提供的信号为高电平时，第四晶体管M4处于导通状态，当复位信号端EM_n+1提供的信号为低电平时，第四晶体管M4处于截止状态；在此不作具体限定。Specifically, in the pixel circuit provided by the embodiment of the present disclosure, the fourth transistor M4 may be a P-type transistor. When the signal provided by the reset signal terminal EM_n+1 is low, the fourth transistor M4 is in a conducting state. When the signal provided by the signal terminal EM_n+1 is at a high level, the fourth transistor M4 is in an off state; the fourth transistor M4 may also be an N-type transistor (not specifically shown in the figure). At this time, when the signal terminal EM_n+ is reset When the signal provided by 1 is at a high level, the fourth transistor M4 is in an on state, and when the signal provided by the reset signal terminal EM_n+1 is at a low level, the fourth transistor M4 is in an off state; there is no specific limitation here.
可选地，在本公开实施例提供的像素电路中，如图3所示，第二初始化电路2具体可以包括：第六晶体管M6和第七晶体管M7；Optionally, in the pixel circuit provided by the embodiment of the present disclosure, as shown in FIG. 3, the second initialization circuit 2 may specifically include: a sixth transistor M6 and a seventh transistor M7;
第六晶体管M6的栅极与扫描信号端G_n耦接，第六晶体管M6的第一极与第一节点A即第四晶体管M4的第二极耦接，第六晶体管M6的第二极与第二节点G即第二晶体管M2的栅极耦接；The gate of the sixth transistor M6 is coupled to the scan signal terminal G_n, the first electrode of the sixth transistor M6 is coupled to the first node A, that is, the second electrode of the fourth transistor M4, and the second electrode of the sixth transistor M6 is coupled to the The second node G is coupled to the gate of the second transistor M2;
第七晶体管M7的栅极与扫描信号端G_n耦接，第七晶体管M7的第一极与第一节点A即第四晶体管M4的第二极耦接，第七晶体管M7的第二极与第三节点D即第二晶体管M2的第一极耦接。The gate of the seventh transistor M7 is coupled to the scan signal terminal G_n, the first electrode of the seventh transistor M7 is coupled to the first node A, that is, the second electrode of the fourth transistor M4, and the second electrode of the seventh transistor M7 is coupled to the The three-node D is coupled to the first pole of the second transistor M2.
具体地，在本公开实施例提供的像素电路中，第六晶体管M6可以为P 型晶体管，当扫描信号端G_n提供的信号为低电平时，第六晶体管M6处于导通状态，当扫描信号端G_n提供的信号为高电平时，第六晶体管M6处于截止状态；第六晶体管M6也可以为N型晶体管(在图中未具体示出)，此时，当扫描信号端G_n提供的信号为高电平时，第六晶体管M6处于导通状态，当扫描信号端G_n提供的信号为低电平时，第六晶体管M6处于截止状态；在此不作具体限定。Specifically, in the pixel circuit provided by the embodiment of the present disclosure, the sixth transistor M6 may be a P-type transistor. When the signal provided by the scan signal terminal G_n is low, the sixth transistor M6 is in a conducting state. When the signal provided by G_n is at a high level, the sixth transistor M6 is in an off state; the sixth transistor M6 may also be an N-type transistor (not specifically shown in the figure). At this time, when the signal provided by the scan signal terminal G_n is high When the voltage level is high, the sixth transistor M6 is in the on state, and when the signal provided by the scan signal terminal G_n is low, the sixth transistor M6 is in the off state; there is no specific limitation here.
同理，第七晶体管M7可以为P型晶体管，当扫描信号端G_n提供的信号为低电平时，第七晶体管M7处于导通状态，当扫描信号端G_n提供的信号为高电平时，第七晶体管M7处于截止状态；第七晶体管M7也可以为N型晶体管(在图中未具体示出)，此时，当扫描信号端G_n提供的信号为高电平时，第七晶体管M7处于导通状态，当扫描信号端G_n提供的信号为低电平时，第七晶体管M7处于截止状态；在此不作具体限定。Similarly, the seventh transistor M7 can be a P-type transistor. When the signal provided by the scan signal terminal G_n is low level, the seventh transistor M7 is in the conducting state. When the signal provided by the scan signal terminal G_n is high level, the seventh transistor M7 The transistor M7 is in an off state; the seventh transistor M7 can also be an N-type transistor (not specifically shown in the figure). At this time, when the signal provided by the scan signal terminal G_n is at a high level, the seventh transistor M7 is in an on state When the signal provided by the scan signal terminal G_n is at a low level, the seventh transistor M7 is in an off state; it is not specifically limited here.
需要说明的是，在本公开实施例提供的像素电路中，第六晶体管M6和第七晶体管M7的控制端相同，均为扫描信号端G_n，且晶体管的类型也相同，同时为N型晶体管或者同时为P型晶体管，保证第六晶体管M6和第七晶体管M7在同一阶段内，同时导通或同时截止。例如，在第一阶段，即节点初始化阶段，第六晶体管M6导通将第一节点A的电位提供给第二节点G，对第二节点G即第二晶体管M2的栅极进行初始化；第七晶体管M7导通将第一节点A的电位提供给第三节点D，为发光器件O的阳极提供初始化信号。在第二阶段，即数据写入阶段，第六晶体管M6和第七晶体管M7同时导通将数据信号和第二晶体管M2的阈值电压写入到第二晶体管M2的栅极，从而实现阈值电压的抓取和数据写入。It should be noted that in the pixel circuit provided by the embodiment of the present disclosure, the control terminals of the sixth transistor M6 and the seventh transistor M7 are the same, and both are the scan signal terminal G_n, and the types of the transistors are also the same, and they are either N-type transistors or It is a P-type transistor at the same time, ensuring that the sixth transistor M6 and the seventh transistor M7 are simultaneously turned on or turned off at the same stage. For example, in the first stage, the node initialization stage, the sixth transistor M6 is turned on to provide the potential of the first node A to the second node G, and initialize the second node G, the gate of the second transistor M2; The transistor M7 is turned on to provide the potential of the first node A to the third node D, and provide an initialization signal for the anode of the light emitting device O. In the second stage, that is, the data writing stage, the sixth transistor M6 and the seventh transistor M7 are turned on at the same time to write the data signal and the threshold voltage of the second transistor M2 to the gate of the second transistor M2, thereby realizing the threshold voltage Fetching and data writing.
可选地，在本公开实施例提供的像素电路中，如图3所示，阳极控制电路3具体可以包括：第三晶体管M3；Optionally, in the pixel circuit provided by the embodiment of the present disclosure, as shown in FIG. 3, the anode control circuit 3 may specifically include: a third transistor M3;
第三晶体管M3的栅极与复位信号端EM_n+1耦接，第三晶体管M3的第一极与第三节点D即第二晶体管M2的第一极耦接，第三晶体管M3的第二极与发光器件O的阳极耦接；The gate of the third transistor M3 is coupled to the reset signal terminal EM_n+1, the first pole of the third transistor M3 is coupled to the third node D, that is, the first pole of the second transistor M2, and the second pole of the third transistor M3 Coupled with the anode of the light-emitting device O;
发光器件O的阴极与第二电压信号端ELVSS耦接。The cathode of the light emitting device O is coupled to the second voltage signal terminal ELVSS.
具体地，在本公开实施例提供的像素电路中，第三晶体管M3可以为P型晶体管，当复位信号端EM_n+1提供的信号为低电平时，第三晶体管M3处于导通状态，当复位信号端EM_n+1提供的信号为高电平时，第三晶体管M3处于截止状态；第三晶体管M3也可以为N型晶体管(在图中未具体示出)，此时，当复位信号端EM_n+1提供的信号为高电平时，第三晶体管M3处于导通状态，当复位信号端EM_n+1提供的信号为低电平时，第三晶体管M3处于截止状态；在此不作具体限定。Specifically, in the pixel circuit provided by the embodiment of the present disclosure, the third transistor M3 may be a P-type transistor. When the signal provided by the reset signal terminal EM_n+1 is low, the third transistor M3 is in a conducting state. When the signal provided by the signal terminal EM_n+1 is at a high level, the third transistor M3 is in an off state; the third transistor M3 may also be an N-type transistor (not specifically shown in the figure). At this time, when the signal terminal EM_n+ is reset When the signal provided by 1 is at a high level, the third transistor M3 is in an on state, and when the signal provided by the reset signal terminal EM_n+1 is at a low level, the third transistor M3 is in an off state; there is no specific limitation here.
可选地，在本公开实施例提供的像素电路中，如图3所示，数据写入电路4具体可以包括：第五晶体管M5；Optionally, in the pixel circuit provided by the embodiment of the present disclosure, as shown in FIG. 3, the data writing circuit 4 may specifically include: a fifth transistor M5;
第五晶体管M5的栅极与扫描信号端G_n耦接，第五晶体管M5的第一极与数据信号端D耦接，第五晶体管M5的第二极与第四节点S即第二晶体管M2的第二极耦接。The gate of the fifth transistor M5 is coupled to the scan signal terminal G_n, the first electrode of the fifth transistor M5 is coupled to the data signal terminal D, and the second electrode of the fifth transistor M5 is connected to the fourth node S of the second transistor M2. The second pole is coupled.
具体地，在本公开实施例提供的像素电路中，第五晶体管M5可以为P型晶体管，当扫描信号端G_n提供的信号为低电平时，第五晶体管M5处于导通状态，当扫描信号端G_n提供的信号为高电平时，第五晶体管M5处于截止状态；第五晶体管M5也可以为N型晶体管(在图中未具体示出)，此时，当扫描信号端G_n提供的信号为高电平时，第五晶体管M5处于导通状态，当扫描信号端G_n提供的信号为低电平时，第五晶体管M5处于截止状态；在此不作具体限定。Specifically, in the pixel circuit provided by the embodiment of the present disclosure, the fifth transistor M5 may be a P-type transistor. When the signal provided by the scan signal terminal G_n is low, the fifth transistor M5 is in a conducting state. When the signal provided by G_n is at a high level, the fifth transistor M5 is in an off state; the fifth transistor M5 can also be an N-type transistor (not specifically shown in the figure). At this time, when the signal provided by the scan signal terminal G_n is high When the voltage level, the fifth transistor M5 is in the on state, and when the signal provided by the scan signal terminal G_n is low, the fifth transistor M5 is in the off state; there is no specific limitation here.
其中，在第一阶段，数据信号端D提供的信号与初始化信号端V提供的信号相同，第五晶体管M5导通，将数据信号端D提供的初始化信号提供给第四节点S，使第二节点G与第四节点S的电位相同，保证第二晶体管M2处于截止状态。而在第二阶段，数据信号端D提供的信号为用于驱动发光器件发光的数据信号，第五晶体管M5导通，将数据信号提供给第四节点S，以同时实现数据的写入和阈值的抓取。In the first stage, the signal provided by the data signal terminal D is the same as the signal provided by the initialization signal terminal V, the fifth transistor M5 is turned on, and the initialization signal provided by the data signal terminal D is provided to the fourth node S, so that the second The potentials of the node G and the fourth node S are the same, ensuring that the second transistor M2 is in the off state. In the second stage, the signal provided by the data signal terminal D is a data signal for driving the light-emitting device to emit light, and the fifth transistor M5 is turned on to provide the data signal to the fourth node S to achieve data writing and threshold at the same time Of crawling.
可选地，在本公开实施例提供的像素电路中，如图3所示，驱动控制电 路5具体可以包括：第二晶体管M2和第一电容C1；Optionally, in the pixel circuit provided by the embodiment of the present disclosure, as shown in FIG. 3, the driving control circuit 5 may specifically include: a second transistor M2 and a first capacitor C1;
第二晶体管M2的栅极和第一极分别与初始化电路0耦接，第二晶体管M2的第二极分别与数据写入电路4和发光控制电路6耦接，具体地，第二晶体管M2的栅极与第二节点G耦接，第二晶体管M2的第一极与第四节点S耦接，第二晶体管M2的第二极与第三节点D耦接；The gate and the first electrode of the second transistor M2 are respectively coupled to the initialization circuit 0, and the second electrode of the second transistor M2 is respectively coupled to the data writing circuit 4 and the light emission control circuit 6, specifically, the second transistor M2 The gate is coupled to the second node G, the first pole of the second transistor M2 is coupled to the fourth node S, and the second pole of the second transistor M2 is coupled to the third node D;
第一电容C1的第一电极与第二节点G即第二晶体管的栅极耦接，第一电容C1的第二电极与第一电压信号端ELVDD耦接。The first electrode of the first capacitor C1 is coupled to the second node G, that is, the gate of the second transistor, and the second electrode of the first capacitor C1 is coupled to the first voltage signal terminal ELVDD.
具体地，在本公开实施例提供的像素电路中，第二晶体管M2为P型晶体管，为了保证第二晶体管M2(即驱动晶体管)能正常工作，对应的第一电压信号端ELVDD提供的电压一般为正电压，第二电压信号端ELVSS的电压一般接地或为负值。Specifically, in the pixel circuit provided by the embodiment of the present disclosure, the second transistor M2 is a P-type transistor. In order to ensure that the second transistor M2 (that is, the driving transistor) can work normally, the voltage provided by the corresponding first voltage signal terminal ELVDD is generally It is a positive voltage, and the voltage of the second voltage signal terminal ELVSS is generally grounded or negative.
可选地，在本公开实施例提供的像素电路中，如图3所示，发光控制电路6具体可以包括：第一晶体管M1；Optionally, in the pixel circuit provided by the embodiment of the present disclosure, as shown in FIG. 3, the light emission control circuit 6 may specifically include: a first transistor M1;
第一晶体管M1的栅极与发光控制端EM_n耦接；第一晶体管M1的第一极与第一电压信号端ELVDD耦接，第一晶体管M1的第二极与第四节点S即第二晶体管M2的第二极耦接。The gate of the first transistor M1 is coupled to the emission control terminal EM_n; the first electrode of the first transistor M1 is coupled to the first voltage signal terminal ELVDD, and the second electrode of the first transistor M1 is coupled to the fourth node S, that is, the second transistor The second pole of M2 is coupled.
具体地，在本公开实施例提供的像素电路中，第一晶体管M1可以为P型晶体管，当发光控制端EM_n提供的信号为低电平时，第一晶体管M1处于导通状态，当发光控制端EM_n提供的信号为高电平时，第一晶体管M1处于截止状态；第一晶体管M1也可以为N型晶体管(在图中未具体示出)，此时，当发光控制端EM_n提供的信号为高电平时，第一晶体管M1处于导通状态，当发光控制端EM_n提供的信号为低电平时，第一晶体管M1处于截止状态；在此不作具体限定。Specifically, in the pixel circuit provided by the embodiment of the present disclosure, the first transistor M1 may be a P-type transistor. When the signal provided by the light-emitting control terminal EM_n is low, the first transistor M1 is in a conducting state. When the signal provided by EM_n is at a high level, the first transistor M1 is in an off state; the first transistor M1 may also be an N-type transistor (not specifically shown in the figure). At this time, when the signal provided by the light-emitting control terminal EM_n is high When the voltage level, the first transistor M1 is in the on state, and when the signal provided by the light-emitting control terminal EM_n is in the low level, the first transistor M1 is in the off state; it is not specifically limited here.
以上仅是举例说明像素电路中各电路的具体结构，在具体实施时，各电路的具体结构不限于本公开实施例提供的上述结构，还可以是本领域技术人员可知的其他结构，在此不做限定。The foregoing is only an example of the specific structure of each circuit in the pixel circuit. In specific implementation, the specific structure of each circuit is not limited to the above-mentioned structure provided by the embodiment of the present disclosure, and may also be other structures known to those skilled in the art. Make a limit.
可选地，在本公开实施例提供的像素电路中，所有晶体管均为P型晶体 管，或，所有晶体管均为N型晶体管。Optionally, in the pixel circuit provided by the embodiment of the present disclosure, all transistors are P-type transistors, or all transistors are N-type transistors.
最佳地，本公开实施例提供的上述像素电路中提到的各晶体管可以全部采用P型晶体管设计，这样可以简化像素电路的制作工艺流程。Preferably, the transistors mentioned in the above-mentioned pixel circuit provided by the embodiment of the present disclosure can all adopt P-type transistor design, which can simplify the manufacturing process of the pixel circuit.
需要说明的是本公开上述实施例中是以驱动晶体管为P型晶体管为例进行说明的，对于驱动晶体管为N型晶体管且采用相同设计原理的情况也属于本公开保护的范围。It should be noted that in the above-mentioned embodiments of the present disclosure, the driving transistor is a P-type transistor as an example. The case where the driving transistor is an N-type transistor and adopts the same design principle also belongs to the protection scope of the present disclosure.
在具体实施时，驱动晶体管和开关晶体管可以是薄膜晶体管(TFT，Thin Film Transistor)，也可以是金属氧化物半导体场效应管(MOS，Metal Oxide Semiconductor)，在此不做限定。在具体实施中，这些晶体管的第一极和第二极根据晶体管类型以及输入信号的不同，其功能可以互换，在此不做具体区分。In specific implementation, the driving transistor and the switching transistor may be thin film transistors (TFT, Thin Film Transistor), or metal oxide semiconductor field effect transistors (MOS, Metal Oxide Semiconductor), which are not limited here. In specific implementation, the functions of the first pole and the second pole of these transistors can be interchanged according to the transistor type and the input signal, and no specific distinction is made here.
下面分别以图3所示的像素电路，图4所示的时序为例对本公开实施例提供的像素电路的工作过程作以描述。其中，初始化信号端V提供的信号为低电平信号，第一电压信号ELVDD端提供的信号为高电平信号，第二电压信号端ELVSS提供的信号为低电平信号，所有晶体管为P型晶体管。The pixel circuit shown in FIG. 3 and the timing sequence shown in FIG. 4 are respectively taken as examples to describe the working process of the pixel circuit provided by the embodiment of the present disclosure. Among them, the signal provided by the initialization signal terminal V is a low-level signal, the signal provided by the first voltage signal ELVDD terminal is a high-level signal, the signal provided by the second voltage signal terminal ELVSS is a low-level signal, and all transistors are P-type Transistor.
第一阶段，G_n＝0，EM_n＝1，EM_n+1＝0，D＝0；In the first stage, G_n=0, EM_n=1, EM_n+1=0, D=0;
在该阶段，复位信号端EM_n+1为低电平，第四晶体管M4导通，将初始化信号端V的初始化信号提供给第一节点A，对第一节点A进行初始化；扫描信号端G_n为低电平，第六晶体管M6导通将第一节点A的初始化信号提供给第二节点G(即第二晶体管M2的栅极)，第七晶体管M7导通将第一节点A的初始化信号提供给第三节点D，并且第三晶体管M3导通，将第三节点D的初始化信号提供给发光器件O的阳极，对发光器件O的阳极进行初始化；同时由于扫描信号端G_n为低电平信号，第五晶体管M5也处于导通状态，此时数据信号端D提供的信号为与初始化信号端V相同的初始化信号，导通的第五晶体管M5将数据信号端D提供的初始化信号提供给第四节点S，保持第二节点G的电位与第四节点S的电位相同，以保证第二晶体管M2在该阶段处于截止状态。At this stage, the reset signal terminal EM_n+1 is at low level, the fourth transistor M4 is turned on, and the initialization signal of the initialization signal terminal V is provided to the first node A to initialize the first node A; the scan signal terminal G_n is Low level, the sixth transistor M6 is turned on to provide the initialization signal of the first node A to the second node G (ie the gate of the second transistor M2), and the seventh transistor M7 is turned on to provide the initialization signal of the first node A To the third node D, and the third transistor M3 is turned on, the initialization signal of the third node D is provided to the anode of the light-emitting device O, and the anode of the light-emitting device O is initialized; at the same time, since the scan signal terminal G_n is a low-level signal , The fifth transistor M5 is also in the conducting state, at this time the signal provided by the data signal terminal D is the same initialization signal as the initialization signal terminal V, and the turned-on fifth transistor M5 provides the initialization signal provided by the data signal terminal D to the first The fourth node S keeps the potential of the second node G the same as the potential of the fourth node S to ensure that the second transistor M2 is in the off state at this stage.
第二阶段，G_n＝0，EM_n＝1，EM_n+1＝1，D＝1；In the second stage, G_n=0, EM_n=1, EM_n+1=1, D=1;
在该阶段，扫描信号端G_n为低电平信号，第五晶体管M5、第六晶体管M6和第七晶体管M7导通，导通的第五晶体管M5将数据信号端D提供的数据信号Vdata提供给第四节点S，直到第二节点G的电位为Vdata+Vth，其中Vth表示第二晶体管的阈值电压。At this stage, the scan signal terminal G_n is a low-level signal, the fifth transistor M5, the sixth transistor M6, and the seventh transistor M7 are turned on, and the turned-on fifth transistor M5 provides the data signal Vdata provided by the data signal terminal D to The potential of the fourth node S up to the second node G is Vdata+Vth, where Vth represents the threshold voltage of the second transistor.
第三阶段，G_n＝1，EM_n＝0，EM_n+1＝1，D＝0；In the third stage, G_n=1, EM_n=0, EM_n+1=1, D=0;
在该阶段，扫描信号端G_n为高电平，第五晶体管M5、第六晶体管M6和第七晶体管M7截止；发光控制端EM_n为低电平，第一晶体管M1导通将第一电压信号端ELVDD的信号提供给第四节点S，第二晶体管M2导通将驱动发光器件O发光的电压提供给第三节点D。由于第三晶体管M3的栅极与复位信号端EM_n+1耦接，而复位信号端EM_n+1的信号于被配置为驱动下一行像素的像素电路中的扫描信号端G_n+1的电平相反，因此该阶段第三晶体管M3处于截止状态，不能形成驱动电流驱动发光器件O发光。At this stage, the scanning signal terminal G_n is at a high level, the fifth transistor M5, the sixth transistor M6, and the seventh transistor M7 are turned off; the light-emitting control terminal EM_n is at a low level, and the first transistor M1 is turned on to turn on the first voltage signal terminal The signal of ELVDD is provided to the fourth node S, and the second transistor M2 is turned on to provide the third node D with a voltage for driving the light emitting device O to emit light. Since the gate of the third transistor M3 is coupled to the reset signal terminal EM_n+1, the signal of the reset signal terminal EM_n+1 is opposite to the level of the scan signal terminal G_n+1 in the pixel circuit configured to drive the next row of pixels Therefore, at this stage, the third transistor M3 is in an off state, and a driving current cannot be formed to drive the light-emitting device O to emit light.
第四阶段，G_n＝1，EM_n＝0，EM_n+1＝0，D＝0；In the fourth stage, G_n=1, EM_n=0, EM_n+1=0, D=0;
在该阶段，发光控制端EM_n和复位信号端EM_n+1均为低电平信号，第一晶体管M1和第三晶体管M3均导通，形成驱动发光器件O的电流，使发光器件O发光。At this stage, the light-emitting control terminal EM_n and the reset signal terminal EM_n+1 are both low-level signals, and the first transistor M1 and the third transistor M3 are both turned on to form a current for driving the light-emitting device O to make the light-emitting device O emit light.
其中，发光电流为I＝1/2K(Vgs-Vth) 2＝1/2K(V elvdd-Vdata) 2，其中K为系数，Vgs表示第二晶体管M2的栅极与第二晶体管M2的源极的电压差，Vth表示第二晶体管M2的阈值电压，V elvdd表示第一电压信号端ELVDD的电压，Vdata表示数据信号。可见，上述像素电路实现了对第二晶体管M2(即驱动晶体管)Vth的补偿，提高了显示面板均一性，同时发光控制端EM_n和扫描信号端G_n的信号可以由同一驱动电路提供，减少了驱动电路的个数，有利于实现电致发光显示面板的窄边框设计。 Among them, the light-emitting current is I=1/2K(Vgs-Vth) 2 =1/2K(V elvdd -Vdata) 2 , where K is a coefficient, and Vgs represents the gate of the second transistor M2 and the source of the second transistor M2 Vth represents the threshold voltage of the second transistor M2, Velvdd represents the voltage of the first voltage signal terminal ELVDD, and Vdata represents the data signal. It can be seen that the above-mentioned pixel circuit realizes the compensation of the second transistor M2 (that is, the driving transistor) Vth, and improves the uniformity of the display panel. At the same time, the signals of the light-emitting control terminal EM_n and the scanning signal terminal G_n can be provided by the same driving circuit, reducing the drive The number of circuits facilitates the realization of the narrow frame design of the electroluminescent display panel.
需要说明的是，数据信号端D在第一阶段提供的为初始化信号，在第二阶段提供的是数据信号，且为了避免由于数据信号的延迟产生在第二阶段和第三阶段交替时数据信号产生变化，因此将提供数据信号的中间时刻(即数 据信号的峰值)设置在了第二阶段和第三阶段交替时刻。It should be noted that the data signal terminal D provides the initialization signal in the first stage, and the data signal in the second stage, and in order to avoid the data signal when the second stage and the third stage alternate due to the delay of the data signal The change occurs, so the intermediate moment of providing the data signal (that is, the peak value of the data signal) is set at the alternate moment of the second stage and the third stage.
基于同一发明构思，如图5所示，本公开实施例还提供了一种像素电路的驱动方法，包括：Based on the same inventive concept, as shown in FIG. 5, an embodiment of the present disclosure also provides a driving method of a pixel circuit, including:
S501、第一阶段，扫描信号端和复位信号端均提供第一电平信号，发光控制端提供第二电平信号，数据信号端提供的信号与初始化信号端提供的信号相同即初始化信号；S501. In the first stage, both the scan signal terminal and the reset signal terminal provide a first level signal, the light-emitting control terminal provides a second level signal, and the signal provided by the data signal terminal is the same as the signal provided by the initialization signal terminal, that is, the initialization signal;
S502、第二阶段，扫描信号端提供第一电平信号，复位信号端和发光控制端提供第二电平信号，数据信号端提供用于点亮发光器件的数据信号；S502. In the second stage, the scan signal terminal provides a first level signal, the reset signal terminal and the light emitting control terminal provide a second level signal, and the data signal terminal provides a data signal for lighting the light emitting device;
S503、第三阶段，扫描信号端和复位信号端均提供第二电平信号，发光控制端提供第一电平信号；S503. In the third stage, both the scan signal terminal and the reset signal terminal provide a second level signal, and the light-emitting control terminal provides a first level signal;
S504、第四阶段，扫描信号端提供第二电平信号，发光控制端和复位信号端均提供第一电平信号。S504. In the fourth stage, the scanning signal terminal provides a second level signal, and both the light emitting control terminal and the reset signal terminal provide the first level signal.
需要说明的是，第一电平信号和第二电平信号可以为高电平信号，也可以为低电平信号，但是，当第一电平信号为高电平信号时，第二电平信号为低电平信号；第一电平信号为低电平信号时，第二电平信号为高电平信号。具体地，当各晶体管为P型晶体管时，第一电平信号为低电平信号，第二电平信号为高电平信号；当各晶体管为N型晶体管时，第一电平信号为高电平信号，第二电平信号为低电平信号。It should be noted that the first level signal and the second level signal can be either a high level signal or a low level signal. However, when the first level signal is a high level signal, the second level signal The signal is a low level signal; when the first level signal is a low level signal, the second level signal is a high level signal. Specifically, when each transistor is a P-type transistor, the first level signal is a low-level signal, and the second level signal is a high-level signal; when each transistor is an N-type transistor, the first level signal is high Level signal, the second level signal is a low level signal.
其中，像素电路的驱动方法的具体工作原理已经在上述像素电路的具体实施例中进行了详细阐述，因此该像素电路的驱动方法可以参见对上述描述像素电路的实施例进行实施，在此不再赘述。Among them, the specific working principle of the driving method of the pixel circuit has been described in detail in the specific embodiment of the above-mentioned pixel circuit. Therefore, the driving method of the pixel circuit can be implemented with reference to the above-described embodiment of the pixel circuit, which will not be omitted here. Repeat.
基于同一发明构思，本公开实施例还提供了一种电致发光显示面板，包括位于显示区域的如上述任一实施例提供的像素电路和位于非显示区域的驱动电路；Based on the same inventive concept, an embodiment of the present disclosure also provides an electroluminescent display panel, including a pixel circuit provided in any of the above-mentioned embodiments in a display area and a driving circuit in a non-display area;
驱动电路包括多个级联的移位寄存器，每级移位寄存器包括第一输出端和第二输出端，第一输出端提供的信号与第二输出端提供的信号的电平相反；The driving circuit includes a plurality of cascaded shift registers, each stage of shift register includes a first output terminal and a second output terminal, and the signal provided by the first output terminal is opposite to the signal provided by the second output terminal;
本级移位寄存器的第一输出端与本行像素电路的扫描信号端耦接，本级 移位寄存器的第二输出端与本行像素电路的发光控制端耦接；The first output terminal of the shift register of the current stage is coupled to the scan signal terminal of the pixel circuit of the current stage, and the second output terminal of the shift register of the current stage is coupled to the light emission control terminal of the pixel circuit of the current stage;
本行像素电路的复位信号端与下一级移位寄存器的第二输出端耦接。The reset signal terminal of the pixel circuit of the current row is coupled to the second output terminal of the next stage shift register.
具体地，在本公开实施例提供的电致发光显示面板中，在非显示区域可以仅设置一个驱动电路向像素电路的各信号端提供驱动信号，减少了驱动电路占用非显示区域的面积，有利于实现窄边框设计。Specifically, in the electroluminescent display panel provided by the embodiments of the present disclosure, only one driving circuit can be provided in the non-display area to provide driving signals to each signal terminal of the pixel circuit, which reduces the area occupied by the non-display area by the driving circuit. Conducive to the realization of a narrow frame design.
基于同一发明构思，本公开实施例还提供了一种显示装置，包括本公开实施例提供的上述电致发光显示面板。该显示装置可以是显示器、手机、电视、笔记本电脑、电子纸、数码相框、导航仪、一体机等，对于显示装置的其它必不可少的组成部分均为本领域的普通技术人员应该理解具有的，在此不做赘述，也不应作为对本公开的限制。Based on the same inventive concept, the embodiments of the present disclosure also provide a display device, including the above-mentioned electroluminescent display panel provided by the embodiments of the present disclosure. The display device can be a monitor, a mobile phone, a TV, a notebook computer, an electronic paper, a digital photo frame, a navigator, an all-in-one machine, etc., and other indispensable components of the display device should be understood by those of ordinary skill in the art. It will not be repeated here, nor should it be used as a limitation to the present disclosure.
本公开实施例提供的一种像素电路、其驱动方法、电致发光显示面板及显示装置，该像素电路包括：第一初始化电路，第二初始化电路，阳极控制电路，数据写入电路，驱动控制电路，发光控制电路以及发光器件；第一初始化电路在复位信号端的控制下将初始化信号端的信号提供给第一节点；第二初始化电路在扫描信号端的控制下使第一节点与第二节点和第三节点导通；阳极控制电路在复位信号端的控制下将第三节点的电位提供给发光器件的阳极；数据写入电路在扫描信号端的控制下将数据信号端的信号提供给第四节点；驱动控制电路在第二节点的电位和第四节点的电位的控制下，确定驱动发光器件的驱动电流的大小；发光控制电路在发光控制端的控制下将第一电压信号端的信号提供给第四节点。通过对像素电路结构的设计，使像素电路的扫描信号端提供的信号和发光控制端提供的信号的电平相反，因此可以通过一个驱动电路向扫描信号端和发光控制端提供驱动信号，减少了驱动电路的设置，有利于实现电致发光显示面板的窄边框设计。Embodiments of the present disclosure provide a pixel circuit, a driving method thereof, an electroluminescent display panel, and a display device. The pixel circuit includes: a first initialization circuit, a second initialization circuit, an anode control circuit, a data writing circuit, and a drive control The first initialization circuit provides the signal of the initialization signal terminal to the first node under the control of the reset signal terminal; the second initialization circuit makes the first node and the second node and the first node under the control of the scan signal terminal The three nodes are turned on; the anode control circuit provides the potential of the third node to the anode of the light-emitting device under the control of the reset signal terminal; the data writing circuit provides the signal of the data signal terminal to the fourth node under the control of the scan signal terminal; drive control The circuit determines the magnitude of the driving current for driving the light emitting device under the control of the potential of the second node and the potential of the fourth node; the light emitting control circuit provides the signal of the first voltage signal terminal to the fourth node under the control of the light emitting control terminal. Through the design of the pixel circuit structure, the level of the signal provided by the scan signal terminal of the pixel circuit and the signal provided by the light-emitting control terminal are opposite, so a driving circuit can be used to provide driving signals to the scan signal terminal and the light-emitting control terminal, reducing The arrangement of the driving circuit is beneficial to realize the narrow frame design of the electroluminescent display panel.
显然，本领域的技术人员可以对本公开进行各种改动和变型而不脱离本公开的精神和范围。这样，倘若本公开的这些修改和变型属于本公开权利要求及其等同技术的范围之内，则本公开也意图包含这些改动和变型在内。Obviously, those skilled in the art can make various changes and modifications to the present disclosure without departing from the spirit and scope of the present disclosure. In this way, if these modifications and variations of the present disclosure fall within the scope of the claims of the present disclosure and equivalent technologies, the present disclosure also intends to include these modifications and variations.

Claims (12)

  1. 一种像素电路，其中，包括：初始化电路，数据写入电路，驱动控制电路，发光控制电路以及发光器件；其中，A pixel circuit, which includes: an initialization circuit, a data writing circuit, a drive control circuit, a light-emitting control circuit, and a light-emitting device; wherein,
    所述初始化电路被配置为响应于复位信号端和扫描信号端提供的信号，对所述驱动控制电路和所述发光器件的阳极提供初始化信号端的信号；The initialization circuit is configured to respond to the signals provided by the reset signal terminal and the scan signal terminal to provide the drive control circuit and the anode of the light emitting device with the signal of the initialization signal terminal;
    所述数据写入电路被配置为响应于所述扫描信号端提供的信号，对所述驱动控制电路写入数据信号端提供的信号；The data writing circuit is configured to write the signal provided by the data signal terminal to the drive control circuit in response to the signal provided by the scan signal terminal;
    所述发光控制电路被配置为响应于发光控制端提供的信号，对所述驱动控制电路提供第一电压信号端的信号；所述发光控制端提供的信号与所述扫描信号端提供的信号电平相反；The light emission control circuit is configured to provide a signal of a first voltage signal terminal to the drive control circuit in response to a signal provided by the light emission control terminal; the signal provided by the light emission control terminal and the signal level provided by the scan signal terminal in contrast;
    所述驱动控制电路被配置为产生驱动所述发光器件的驱动电流。The driving control circuit is configured to generate a driving current for driving the light emitting device.
  2. 如权利要求1所述的像素电路，其中，所述驱动控制电路包括：第二晶体管和第一电容；8. The pixel circuit of claim 1, wherein the drive control circuit comprises: a second transistor and a first capacitor;
    所述第二晶体管的栅极和第一极分别与所述初始化电路耦接，所述第二晶体管的第二极分别与所述数据写入电路和所述发光控制电路耦接；The gate and the first electrode of the second transistor are respectively coupled to the initialization circuit, and the second electrode of the second transistor is respectively coupled to the data writing circuit and the light emission control circuit;
    所述第一电容的第一电极与所述第二晶体管的栅极耦接，所述第一电容的第二电极与所述第一电压信号端耦接。The first electrode of the first capacitor is coupled to the gate of the second transistor, and the second electrode of the first capacitor is coupled to the first voltage signal terminal.
  3. 如权利要求2所述的像素电路，其中，所述初始化电路包括：第一初始化电路、第二初始化电路和阳极控制电路；3. The pixel circuit of claim 2, wherein the initialization circuit comprises: a first initialization circuit, a second initialization circuit, and an anode control circuit;
    所述第一初始化电路被配置为响应于所述复位信号端提供的信号，对所述第二初始化电路提供所述初始化信号端的信号；The first initialization circuit is configured to provide the signal of the initialization signal terminal to the second initialization circuit in response to the signal provided by the reset signal terminal;
    所述第二初始化电路被配置为响应于所述扫描信号端提供的信号，导通所述第二晶体管的栅极和第一极；The second initialization circuit is configured to turn on the gate and the first electrode of the second transistor in response to the signal provided by the scan signal terminal;
    所述阳极控制电路被配置为响应于所述复位信号端提供的信号，导通所述第二晶体管的第一极和所述发光器件的阳极。The anode control circuit is configured to turn on the first electrode of the second transistor and the anode of the light emitting device in response to the signal provided by the reset signal terminal.
  4. 如权利要求3所述的像素电路，其中，所述第一初始化电路包括：第 四晶体管；The pixel circuit of claim 3, wherein the first initialization circuit comprises: a fourth transistor;
    所述第四晶体管的栅极与所述复位信号端耦接，所述第四晶体管的第一极与所述初始化信号端耦接，所述第四晶体管的第二极与所述第二初始化电路耦接。The gate of the fourth transistor is coupled to the reset signal terminal, the first pole of the fourth transistor is coupled to the initialization signal terminal, and the second pole of the fourth transistor is coupled to the second initialization signal terminal. Circuit coupling.
  5. 如权利要求4所述的像素电路，其中，所述第二初始化电路包括：第六晶体管和第七晶体管；8. The pixel circuit of claim 4, wherein the second initialization circuit comprises: a sixth transistor and a seventh transistor;
    所述第六晶体管的栅极与所述扫描信号端耦接，所述第六晶体管的第一极与所述第四晶体管的第二极耦接，所述第六晶体管的第二极与所述第二晶体管的栅极耦接；The gate of the sixth transistor is coupled to the scan signal terminal, the first electrode of the sixth transistor is coupled to the second electrode of the fourth transistor, and the second electrode of the sixth transistor is coupled to the The gate of the second transistor is coupled;
    所述第七晶体管的栅极与所述扫描信号端耦接，所述第七晶体管的第一极与所述第四晶体管的第二极耦接，所述第七晶体管的第二极与所述第二晶体管的第一极耦接。The gate of the seventh transistor is coupled to the scan signal terminal, the first electrode of the seventh transistor is coupled to the second electrode of the fourth transistor, and the second electrode of the seventh transistor is coupled to the The first pole of the second transistor is coupled.
  6. 如权利要求3所述的像素电路，其中，所述阳极控制电路包括：第三晶体管；5. The pixel circuit of claim 3, wherein the anode control circuit comprises: a third transistor;
    所述第三晶体管的栅极与所述复位信号端耦接，所述第三晶体管的第一极与所述第二晶体管的第一极耦接，所述第三晶体管的第二极与所述发光器件的阳极耦接；The gate of the third transistor is coupled to the reset signal terminal, the first pole of the third transistor is coupled to the first pole of the second transistor, and the second pole of the third transistor is coupled to the reset signal terminal. The anode coupling of the light-emitting device;
    所述发光器件的阴极与第二电压信号端耦接。The cathode of the light emitting device is coupled to the second voltage signal terminal.
  7. 如权利要求2所述的像素电路，其中，所述数据写入电路包括：第五晶体管；3. The pixel circuit of claim 2, wherein the data writing circuit comprises: a fifth transistor;
    所述第五晶体管的栅极与所述扫描信号端耦接，所述第五晶体管的第一极与所述数据信号端耦接，所述第五晶体管的第二极与所述第二晶体管的第二极耦接。The gate of the fifth transistor is coupled to the scan signal terminal, the first electrode of the fifth transistor is coupled to the data signal terminal, and the second electrode of the fifth transistor is coupled to the second transistor The second pole is coupled.
  8. 如权利要求1所述的像素电路，其中，所述发光控制电路包括：第一晶体管；8. The pixel circuit of claim 1, wherein the light emission control circuit comprises: a first transistor;
    所述第一晶体管的栅极与所述发光控制端耦接；所述第一晶体管的第一极与所述第一电压信号端耦接，所述第一晶体管的第二极与所述第二晶体管 的第二极耦接。The gate of the first transistor is coupled to the light-emitting control terminal; the first electrode of the first transistor is coupled to the first voltage signal terminal, and the second electrode of the first transistor is coupled to the first voltage signal terminal. The second poles of the two transistors are coupled.
  9. 如权利要求1-7任一项所述的像素电路，其中，所述像素电路中的所有晶体管均为P型晶体管，或，所述像素电路中的所有晶体管均为N型晶体管。8. The pixel circuit according to any one of claims 1-7, wherein all transistors in the pixel circuit are P-type transistors, or all transistors in the pixel circuit are N-type transistors.
  10. 一种如权利要求1-9任一项所述的像素电路的驱动方法，其中，包括：A method for driving a pixel circuit according to any one of claims 1-9, which comprises:
    第一阶段，所述扫描信号端和所述复位信号端均提供第一电平信号，所述发光控制端提供第二电平信号，所述数据信号端与所述初始化信号端提供初始化信号；In the first stage, the scan signal terminal and the reset signal terminal both provide a first level signal, the light control terminal provides a second level signal, and the data signal terminal and the initialization signal terminal provide an initialization signal;
    第二阶段，所述扫描信号端提供所述第一电平信号，所述复位信号端和所述发光控制端提供所述第二电平信号，所述数据信号端提供数据信号；In the second stage, the scan signal terminal provides the first level signal, the reset signal terminal and the light-emitting control terminal provide the second level signal, and the data signal terminal provides a data signal;
    第三阶段，所述扫描信号端和所述复位信号端均提供所述第二电平信号，所述发光控制端提供所述第一电平信号；In the third stage, both the scan signal terminal and the reset signal terminal provide the second level signal, and the light-emitting control terminal provides the first level signal;
    第四阶段，所述扫描信号端提供所述第二电平信号，所述发光控制端和所述复位信号端均提供所述第一电平信号。In the fourth stage, the scan signal terminal provides the second level signal, and both the light-emitting control terminal and the reset signal terminal provide the first level signal.
  11. 一种电致发光显示面板，其中，包括位于显示区域的如权利要求1-9任一项所述的像素电路和位于非显示区域的驱动电路；An electroluminescent display panel, which comprises the pixel circuit according to any one of claims 1-9 located in a display area and a drive circuit located in a non-display area;
    所述驱动电路包括多个级联的移位寄存器，每级所述移位寄存器包括第一输出端和第二输出端，所述第一输出端提供的信号与所述第二输出端提供的信号电平相反；The driving circuit includes a plurality of cascaded shift registers, and each stage of the shift register includes a first output terminal and a second output terminal. The signal provided by the first output terminal and the signal provided by the second output terminal The signal level is opposite;
    本级所述移位寄存器的第一输出端与本行所述像素电路的扫描信号端耦接，本级所述移位寄存器的第二输出端与本行所述像素电路的发光控制端耦接；The first output terminal of the shift register of this stage is coupled to the scan signal terminal of the pixel circuit of this row, and the second output terminal of the shift register of this stage is coupled to the light emitting control terminal of the pixel circuit of this row. Connect
    本行所述像素电路的复位信号端与下一级所述移位寄存器的第二输出端耦接。The reset signal terminal of the pixel circuit of the current row is coupled to the second output terminal of the shift register of the next stage.
  12. 一种显示装置，其中，包括如权利要求11所述的电致发光显示面板。A display device comprising the electroluminescence display panel according to claim 11.
PCT/CN2020/074363 2019-03-20 2020-02-05 Pixel circuit, method for driving same, electroluminescent display panel, and display device WO2020186933A1 (en)

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