WO2020186933A1 - Circuit de pixels et son procédé d'attaque, panneau d'affichage électroluminescent, et dispositif d'affichage - Google Patents

Circuit de pixels et son procédé d'attaque, panneau d'affichage électroluminescent, et dispositif d'affichage Download PDF

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WO2020186933A1
WO2020186933A1 PCT/CN2020/074363 CN2020074363W WO2020186933A1 WO 2020186933 A1 WO2020186933 A1 WO 2020186933A1 CN 2020074363 W CN2020074363 W CN 2020074363W WO 2020186933 A1 WO2020186933 A1 WO 2020186933A1
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Prior art keywords
transistor
circuit
signal
coupled
signal terminal
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PCT/CN2020/074363
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English (en)
Chinese (zh)
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王志冲
李付强
冯京
刘鹏
栾兴龙
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京东方科技集团股份有限公司
鄂尔多斯市源盛光电有限责任公司
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Publication of WO2020186933A1 publication Critical patent/WO2020186933A1/fr

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]

Definitions

  • the present disclosure relates to the field of display technology, in particular to a pixel circuit, a driving method thereof, an electroluminescent display panel and a display device.
  • Electroluminescent displays are one of the hot spots in the field of flat panel display research. Compared with liquid crystal displays, electroluminescent devices have the advantages of low energy consumption, low production cost, self-luminescence, wide viewing angle and fast response speed. At present, in the field of flat panel displays such as mobile phones, PDAs, and digital cameras, electroluminescent displays have begun to replace traditional liquid crystal displays. Among them, pixel circuit design is the core technology of electroluminescent displays, which has important research significance.
  • the embodiment of the present disclosure provides a pixel circuit including: an initialization circuit, a data writing circuit, a drive control circuit, a light emission control circuit, and a light emitting device; wherein,
  • the initialization circuit is configured to respond to the signals provided by the reset signal terminal and the scan signal terminal to provide the drive control circuit and the anode of the light emitting device with the signal of the initialization signal terminal;
  • the data writing circuit is configured to write the signal provided by the data signal terminal to the drive control circuit in response to the signal provided by the scan signal terminal;
  • the light emission control circuit is configured to provide a signal of a first voltage signal terminal to the drive control circuit in response to a signal provided by the light emission control terminal; the signal provided by the light emission control terminal and the signal level provided by the scan signal terminal in contrast;
  • the driving control circuit is configured to generate a driving current for driving the light emitting device.
  • the drive control circuit includes: a second transistor and a first capacitor;
  • the gate and the first electrode of the second transistor are respectively coupled to the initialization circuit, and the second electrode of the second transistor is respectively coupled to the data writing circuit and the light emission control circuit;
  • the first electrode of the first capacitor is coupled to the gate of the second transistor, and the second electrode of the first capacitor is coupled to the first voltage signal terminal.
  • the initialization circuit includes: a first initialization circuit, a second initialization circuit, and an anode control circuit;
  • the first initialization circuit is configured to provide the signal of the initialization signal terminal to the second initialization circuit in response to the signal provided by the reset signal terminal;
  • the second initialization circuit is configured to turn on the gate and the first electrode of the second transistor in response to the signal provided by the scan signal terminal;
  • the anode control circuit is configured to turn on the first electrode of the second transistor and the anode of the light emitting device in response to the signal provided by the reset signal terminal.
  • the first initialization circuit includes: a fourth transistor;
  • the gate of the fourth transistor is coupled to the reset signal terminal, the first pole of the fourth transistor is coupled to the initialization signal terminal, and the second pole of the fourth transistor is coupled to the second initialization circuit Pick up.
  • the second initialization circuit includes: a sixth transistor and a seventh transistor;
  • the gate of the sixth transistor is coupled to the scan signal terminal, the first electrode of the sixth transistor is coupled to the second electrode of the fourth transistor, and the second electrode of the sixth transistor is coupled to the The gate of the second transistor is coupled;
  • the gate of the seventh transistor is coupled to the scan signal terminal, the first pole of the seventh transistor is coupled to the second pole of the fourth transistor, and the second pole of the seventh transistor is coupled to the The first pole of the second transistor is coupled.
  • the anode control circuit includes: a third transistor
  • the gate of the third transistor is coupled to the reset signal terminal, the first pole of the third transistor is coupled to the first pole of the second transistor, and the second pole of the third transistor is coupled to the reset signal terminal.
  • the cathode of the light emitting device is coupled to the second voltage signal terminal.
  • the data writing circuit includes: a fifth transistor;
  • the gate of the fifth transistor is coupled to the scan signal terminal, the first electrode of the fifth transistor is coupled to the data signal terminal, and the second electrode of the fifth transistor is coupled to the second transistor The second pole is coupled.
  • the light emission control circuit includes: a first transistor
  • the gate of the first transistor is coupled to the light-emitting control terminal; the first electrode of the first transistor is coupled to the first voltage signal terminal, and the second electrode of the first transistor is coupled to the first voltage signal terminal.
  • the second poles of the two transistors are coupled.
  • all transistors in the pixel circuit are P-type transistors, or all transistors in the pixel circuit are N-type transistors.
  • An embodiment of the present disclosure provides a method for driving a pixel circuit according to any one of the above embodiments, including:
  • the scan signal terminal and the reset signal terminal both provide a first level signal
  • the light-emitting control terminal provides a second level signal
  • the data signal terminal and the initialization signal terminal provide initialization signals ;
  • the scan signal terminal provides the first level signal
  • the reset signal terminal and the light emitting control terminal provide the second level signal
  • the data signal terminal provides a data signal
  • both the scan signal terminal and the reset signal terminal provide the second level signal, and the light-emitting control terminal provides the first level signal;
  • the scan signal terminal provides the second level signal
  • both the light-emitting control terminal and the reset signal terminal provide the first level signal
  • the embodiments of the present disclosure also provide an electroluminescent display panel, including the pixel circuit provided in any of the above-mentioned embodiments located in the display area and the driving circuit located in the non-display area;
  • the driving circuit includes a plurality of cascaded shift registers, each stage of the shift register includes a first output terminal and a second output terminal, and the signal provided by the first output terminal is the same as that provided by the second output terminal.
  • the signal level is opposite;
  • the first output terminal of the shift register of this stage is coupled to the scan signal terminal of the pixel circuit of this row, and the second output terminal of the shift register of this stage is coupled to the light emitting control terminal of the pixel circuit of this row.
  • the reset signal terminal of the pixel circuit of the current row is coupled to the second output terminal of the shift register of the next stage.
  • the embodiment of the present disclosure also provides a display device, including the above-mentioned electroluminescent display panel provided by the embodiment of the present disclosure.
  • FIG. 1 is a schematic diagram of a circuit structure in a related art electroluminescence display panel
  • FIG. 2 is a schematic structural diagram of a pixel circuit provided by an embodiment of the disclosure.
  • FIG. 3 is a schematic diagram of a specific structure of a pixel circuit provided by an embodiment of the disclosure.
  • FIG. 4 is a timing diagram of a pixel circuit provided by an embodiment of the disclosure.
  • FIG. 5 is a flowchart of a pixel circuit driving method provided by an embodiment of the disclosure.
  • the circuit structure of the electroluminescent display panel in the related art configured to drive the pixel display is shown in FIG. 1.
  • the pixel circuit Pixel includes a scanning signal terminal and a light-emitting control terminal (the specific structure of the pixel circuit is not shown), and because The design of the Pixel structure of the pixel circuit.
  • the signal of the scanning signal terminal and the signal of the light-emitting control terminal in the pixel circuit Pixel cannot be provided by the same driving circuit. Therefore, two driving circuits (light-emitting control driving circuit) are required in the non-display area of the electroluminescent display.
  • EM and gate drive circuit Gate can realize the control of the pixel circuit Pixel.
  • the two driving circuits occupy a larger area of the non-display area, which is not conducive to achieving a narrow frame design.
  • the embodiments of the present disclosure provide a pixel circuit, a driving method thereof, an electroluminescence display panel, and a display device.
  • a driving circuit can be used to provide driving signals to the scanning signal terminal and the light-emitting control terminal at the same time, which reduces the number of driving circuits and facilitates the narrow frame design of the electroluminescent display panel.
  • an embodiment of the present disclosure provides a pixel circuit, as shown in FIG. 2, comprising: an initialization circuit 0, a data writing circuit 4, a drive control circuit 5, a light emission control circuit 6, and a light emitting device O;
  • the initialization circuit 0 is configured to respond to the signals provided by the reset signal terminal EM_n+1 and the scan signal terminal G_n to provide the signal of the initialization signal terminal V to the driving control circuit 5 and the anode of the light emitting device O;
  • the data writing circuit 4 is configured to write the signal provided by the data signal terminal D to the drive control circuit 5 in response to the signal provided by the scan signal terminal G_n;
  • the light emission control circuit 6 is configured to provide a first voltage signal terminal ELVDD signal to the drive control circuit 5 in response to the signal provided by the light emission control terminal EM_n; the signal level provided by the light emission control terminal EM_n is opposite to the signal level provided by the scan signal terminal G_n ;
  • the drive control circuit 5 is configured to generate a drive current that drives the light emitting device O.
  • the initialization circuit 0, the data writing circuit 4, the drive control circuit 5, the light emission control circuit 6 and the light emitting device O are arranged so that the scan signal terminal G_n of the pixel circuit provides The signal level is opposite to the signal provided by the light-emitting control terminal EM_n, so a driving circuit can provide driving signals to the scanning signal terminal G_n and the light-emitting control terminal EM_n at the same time, which reduces the setting of the driving circuit and is beneficial to realize the electroluminescence display The narrow frame design of the panel.
  • the above-mentioned pixel circuit can also implement compensation for the threshold voltage of the driving transistor in the driving control circuit 5, that is, the second transistor, so as to ensure the uniformity of light emission of each pixel in the display panel.
  • the initialization circuit 0 may specifically include: a first initialization circuit 1, a second initialization circuit 2 and an anode control circuit 3;
  • the first initialization circuit 1 is configured to provide the signal of the initialization signal terminal V to the second initialization circuit 2 in response to the signal provided by the reset signal terminal EM_n+1, that is, to provide the signal of the initialization signal terminal V to the first node A (first node A).
  • Node A is the signal input terminal of the second initialization circuit 2);
  • the second initialization circuit 2 is configured to turn on the gate and the first pole of the second transistor M2 in response to the signal provided by the scan signal terminal Gate_n, even if the first node A (the first node A is the second initialization circuit 2
  • the signal input terminal is connected to the second node G (the second node G is the gate of the second transistor M2) and the third node D (the third node D is the first pole of the second transistor M2);
  • the anode control circuit 3 is configured to turn on the first electrode of the second transistor M2 and the anode of the light emitting device O in response to the signal provided by the reset signal terminal EM_n+1, that is, the third node D (the third node D is the second The potential of the first pole of the transistor M2) is supplied to the anode of the light emitting device O.
  • the setting of the above initialization circuit 0 can cooperate with the data writing circuit 4 to provide the signal of the data signal terminal D to the fourth node S under the control of the scan signal terminal G_n (the fourth node S is the second electrode of the second transistor M2 ), the drive control circuit 5 determines the magnitude of the drive current for driving the light-emitting device OLED under the control of the potential of the second node G (the second node G is the gate of the second transistor M2) and the potential of the fourth node S, The light emission control circuit 6 provides the signal of the first voltage signal terminal ELVDD to the fourth node S under the control of the light emission control terminal EM_n, which can compensate the threshold voltage of the driving transistor in the driving control circuit 5, that is, the second transistor. Ensure the uniformity of light emission of each pixel in the display panel.
  • the first initialization circuit 1 may specifically include: a fourth transistor M4;
  • the gate of the fourth transistor M4 is coupled to the reset signal terminal EM_n+1, the first pole of the fourth transistor M4 is coupled to the initialization signal terminal V, and the second pole of the fourth transistor M4 is coupled to the first node A, that is, the second initialization The signal input terminal of the circuit 2 is coupled.
  • the fourth transistor M4 may be a P-type transistor.
  • the fourth transistor M4 When the signal provided by the reset signal terminal EM_n+1 is low, the fourth transistor M4 is in a conducting state. When the signal provided by the signal terminal EM_n+1 is at a high level, the fourth transistor M4 is in an off state; the fourth transistor M4 may also be an N-type transistor (not specifically shown in the figure).
  • the signal terminal EM_n+ is reset
  • the fourth transistor M4 is in an on state, and when the signal provided by the reset signal terminal EM_n+1 is at a low level, the fourth transistor M4 is in an off state; there is no specific limitation here.
  • the second initialization circuit 2 may specifically include: a sixth transistor M6 and a seventh transistor M7;
  • the gate of the sixth transistor M6 is coupled to the scan signal terminal G_n, the first electrode of the sixth transistor M6 is coupled to the first node A, that is, the second electrode of the fourth transistor M4, and the second electrode of the sixth transistor M6 is coupled to the The second node G is coupled to the gate of the second transistor M2;
  • the gate of the seventh transistor M7 is coupled to the scan signal terminal G_n, the first electrode of the seventh transistor M7 is coupled to the first node A, that is, the second electrode of the fourth transistor M4, and the second electrode of the seventh transistor M7 is coupled to the The three-node D is coupled to the first pole of the second transistor M2.
  • the sixth transistor M6 may be a P-type transistor.
  • the sixth transistor M6 When the signal provided by the scan signal terminal G_n is low, the sixth transistor M6 is in a conducting state. When the signal provided by G_n is at a high level, the sixth transistor M6 is in an off state; the sixth transistor M6 may also be an N-type transistor (not specifically shown in the figure).
  • the signal provided by the scan signal terminal G_n when the signal provided by the scan signal terminal G_n is high When the voltage level is high, the sixth transistor M6 is in the on state, and when the signal provided by the scan signal terminal G_n is low, the sixth transistor M6 is in the off state; there is no specific limitation here.
  • the seventh transistor M7 can be a P-type transistor.
  • the seventh transistor M7 When the signal provided by the scan signal terminal G_n is low level, the seventh transistor M7 is in the conducting state. When the signal provided by the scan signal terminal G_n is high level, the seventh transistor M7 The transistor M7 is in an off state; the seventh transistor M7 can also be an N-type transistor (not specifically shown in the figure).
  • the seventh transistor M7 when the signal provided by the scan signal terminal G_n is at a high level, the seventh transistor M7 is in an on state When the signal provided by the scan signal terminal G_n is at a low level, the seventh transistor M7 is in an off state; it is not specifically limited here.
  • control terminals of the sixth transistor M6 and the seventh transistor M7 are the same, and both are the scan signal terminal G_n, and the types of the transistors are also the same, and they are either N-type transistors or It is a P-type transistor at the same time, ensuring that the sixth transistor M6 and the seventh transistor M7 are simultaneously turned on or turned off at the same stage.
  • the sixth transistor M6 is turned on to provide the potential of the first node A to the second node G, and initialize the second node G, the gate of the second transistor M2;
  • the transistor M7 is turned on to provide the potential of the first node A to the third node D, and provide an initialization signal for the anode of the light emitting device O.
  • the sixth transistor M6 and the seventh transistor M7 are turned on at the same time to write the data signal and the threshold voltage of the second transistor M2 to the gate of the second transistor M2, thereby realizing the threshold voltage Fetching and data writing.
  • the anode control circuit 3 may specifically include: a third transistor M3;
  • the gate of the third transistor M3 is coupled to the reset signal terminal EM_n+1, the first pole of the third transistor M3 is coupled to the third node D, that is, the first pole of the second transistor M2, and the second pole of the third transistor M3 Coupled with the anode of the light-emitting device O;
  • the cathode of the light emitting device O is coupled to the second voltage signal terminal ELVSS.
  • the third transistor M3 may be a P-type transistor.
  • the third transistor M3 When the signal provided by the reset signal terminal EM_n+1 is low, the third transistor M3 is in a conducting state. When the signal provided by the signal terminal EM_n+1 is at a high level, the third transistor M3 is in an off state; the third transistor M3 may also be an N-type transistor (not specifically shown in the figure).
  • the signal terminal EM_n+ is reset
  • the signal provided by 1 is at a high level
  • the third transistor M3 is in an on state, and when the signal provided by the reset signal terminal EM_n+1 is at a low level, the third transistor M3 is in an off state; there is no specific limitation here.
  • the data writing circuit 4 may specifically include: a fifth transistor M5;
  • the gate of the fifth transistor M5 is coupled to the scan signal terminal G_n, the first electrode of the fifth transistor M5 is coupled to the data signal terminal D, and the second electrode of the fifth transistor M5 is connected to the fourth node S of the second transistor M2.
  • the second pole is coupled.
  • the fifth transistor M5 may be a P-type transistor.
  • the fifth transistor M5 When the signal provided by the scan signal terminal G_n is low, the fifth transistor M5 is in a conducting state. When the signal provided by G_n is at a high level, the fifth transistor M5 is in an off state; the fifth transistor M5 can also be an N-type transistor (not specifically shown in the figure).
  • the signal provided by the scan signal terminal G_n when the signal provided by the scan signal terminal G_n is high When the voltage level, the fifth transistor M5 is in the on state, and when the signal provided by the scan signal terminal G_n is low, the fifth transistor M5 is in the off state; there is no specific limitation here.
  • the signal provided by the data signal terminal D is the same as the signal provided by the initialization signal terminal V, the fifth transistor M5 is turned on, and the initialization signal provided by the data signal terminal D is provided to the fourth node S, so that the second The potentials of the node G and the fourth node S are the same, ensuring that the second transistor M2 is in the off state.
  • the signal provided by the data signal terminal D is a data signal for driving the light-emitting device to emit light
  • the fifth transistor M5 is turned on to provide the data signal to the fourth node S to achieve data writing and threshold at the same time Of crawling.
  • the driving control circuit 5 may specifically include: a second transistor M2 and a first capacitor C1;
  • the gate and the first electrode of the second transistor M2 are respectively coupled to the initialization circuit 0, and the second electrode of the second transistor M2 is respectively coupled to the data writing circuit 4 and the light emission control circuit 6, specifically, the second transistor M2
  • the gate is coupled to the second node G, the first pole of the second transistor M2 is coupled to the fourth node S, and the second pole of the second transistor M2 is coupled to the third node D;
  • the first electrode of the first capacitor C1 is coupled to the second node G, that is, the gate of the second transistor, and the second electrode of the first capacitor C1 is coupled to the first voltage signal terminal ELVDD.
  • the second transistor M2 is a P-type transistor.
  • the voltage provided by the corresponding first voltage signal terminal ELVDD is generally It is a positive voltage
  • the voltage of the second voltage signal terminal ELVSS is generally grounded or negative.
  • the light emission control circuit 6 may specifically include: a first transistor M1;
  • the gate of the first transistor M1 is coupled to the emission control terminal EM_n; the first electrode of the first transistor M1 is coupled to the first voltage signal terminal ELVDD, and the second electrode of the first transistor M1 is coupled to the fourth node S, that is, the second transistor The second pole of M2 is coupled.
  • the first transistor M1 may be a P-type transistor.
  • the first transistor M1 When the signal provided by the light-emitting control terminal EM_n is low, the first transistor M1 is in a conducting state. When the signal provided by EM_n is at a high level, the first transistor M1 is in an off state; the first transistor M1 may also be an N-type transistor (not specifically shown in the figure).
  • the signal provided by the light-emitting control terminal EM_n is high
  • the first transistor M1 is in the on state, and when the signal provided by the light-emitting control terminal EM_n is in the low level, the first transistor M1 is in the off state; it is not specifically limited here.
  • each circuit in the pixel circuit is not limited to the above-mentioned structure provided by the embodiment of the present disclosure, and may also be other structures known to those skilled in the art. Make a limit.
  • all transistors are P-type transistors, or all transistors are N-type transistors.
  • the transistors mentioned in the above-mentioned pixel circuit provided by the embodiment of the present disclosure can all adopt P-type transistor design, which can simplify the manufacturing process of the pixel circuit.
  • the driving transistor is a P-type transistor as an example.
  • the case where the driving transistor is an N-type transistor and adopts the same design principle also belongs to the protection scope of the present disclosure.
  • the driving transistor and the switching transistor may be thin film transistors (TFT, Thin Film Transistor), or metal oxide semiconductor field effect transistors (MOS, Metal Oxide Semiconductor), which are not limited here.
  • TFT Thin Film Transistor
  • MOS Metal Oxide Semiconductor
  • the functions of the first pole and the second pole of these transistors can be interchanged according to the transistor type and the input signal, and no specific distinction is made here.
  • the pixel circuit shown in FIG. 3 and the timing sequence shown in FIG. 4 are respectively taken as examples to describe the working process of the pixel circuit provided by the embodiment of the present disclosure.
  • the signal provided by the initialization signal terminal V is a low-level signal
  • the signal provided by the first voltage signal ELVDD terminal is a high-level signal
  • the signal provided by the second voltage signal terminal ELVSS is a low-level signal
  • all transistors are P-type Transistor.
  • the reset signal terminal EM_n+1 is at low level
  • the fourth transistor M4 is turned on, and the initialization signal of the initialization signal terminal V is provided to the first node A to initialize the first node A
  • the scan signal terminal G_n is Low level
  • the sixth transistor M6 is turned on to provide the initialization signal of the first node A to the second node G (ie the gate of the second transistor M2)
  • the seventh transistor M7 is turned on to provide the initialization signal of the first node A To the third node D
  • the third transistor M3 is turned on, the initialization signal of the third node D is provided to the anode of the light-emitting device O, and the anode of the light-emitting device O is initialized;
  • the scan signal terminal G_n is a low-level signal
  • the fifth transistor M5 is also in the conducting state, at this time the signal provided by the data signal terminal D is the same initialization signal as the initialization signal terminal V, and the turned-on fifth transistor
  • the scan signal terminal G_n is a low-level signal
  • the fifth transistor M5, the sixth transistor M6, and the seventh transistor M7 are turned on
  • the turned-on fifth transistor M5 provides the data signal Vdata provided by the data signal terminal D to
  • the potential of the fourth node S up to the second node G is Vdata+Vth, where Vth represents the threshold voltage of the second transistor.
  • the scanning signal terminal G_n is at a high level
  • the fifth transistor M5, the sixth transistor M6, and the seventh transistor M7 are turned off
  • the light-emitting control terminal EM_n is at a low level
  • the first transistor M1 is turned on to turn on the first voltage signal terminal
  • the signal of ELVDD is provided to the fourth node S, and the second transistor M2 is turned on to provide the third node D with a voltage for driving the light emitting device O to emit light.
  • the third transistor M3 Since the gate of the third transistor M3 is coupled to the reset signal terminal EM_n+1, the signal of the reset signal terminal EM_n+1 is opposite to the level of the scan signal terminal G_n+1 in the pixel circuit configured to drive the next row of pixels Therefore, at this stage, the third transistor M3 is in an off state, and a driving current cannot be formed to drive the light-emitting device O to emit light.
  • the light-emitting control terminal EM_n and the reset signal terminal EM_n+1 are both low-level signals, and the first transistor M1 and the third transistor M3 are both turned on to form a current for driving the light-emitting device O to make the light-emitting device O emit light.
  • the signals of the light-emitting control terminal EM_n and the scanning signal terminal G_n can be provided by the same driving circuit, reducing the drive
  • the number of circuits facilitates the realization of the narrow frame design of the electroluminescent display panel.
  • the data signal terminal D provides the initialization signal in the first stage, and the data signal in the second stage, and in order to avoid the data signal when the second stage and the third stage alternate due to the delay of the data signal The change occurs, so the intermediate moment of providing the data signal (that is, the peak value of the data signal) is set at the alternate moment of the second stage and the third stage.
  • an embodiment of the present disclosure also provides a driving method of a pixel circuit, including:
  • both the scan signal terminal and the reset signal terminal provide a first level signal
  • the light-emitting control terminal provides a second level signal
  • the signal provided by the data signal terminal is the same as the signal provided by the initialization signal terminal, that is, the initialization signal
  • the scan signal terminal provides a first level signal
  • the reset signal terminal and the light emitting control terminal provide a second level signal
  • the data signal terminal provides a data signal for lighting the light emitting device
  • both the scan signal terminal and the reset signal terminal provide a second level signal, and the light-emitting control terminal provides a first level signal;
  • the scanning signal terminal provides a second level signal
  • both the light emitting control terminal and the reset signal terminal provide the first level signal
  • the first level signal and the second level signal can be either a high level signal or a low level signal.
  • the second level signal The signal is a low level signal; when the first level signal is a low level signal, the second level signal is a high level signal.
  • the first level signal is a low-level signal
  • the second level signal is a high level signal.
  • each transistor is a P-type transistor
  • the first level signal is a low-level signal
  • the second level signal is a high-level signal
  • the first level signal is high Level signal
  • the second level signal is a low level signal.
  • the specific working principle of the driving method of the pixel circuit has been described in detail in the specific embodiment of the above-mentioned pixel circuit. Therefore, the driving method of the pixel circuit can be implemented with reference to the above-described embodiment of the pixel circuit, which will not be omitted here. Repeat.
  • an embodiment of the present disclosure also provides an electroluminescent display panel, including a pixel circuit provided in any of the above-mentioned embodiments in a display area and a driving circuit in a non-display area;
  • the driving circuit includes a plurality of cascaded shift registers, each stage of shift register includes a first output terminal and a second output terminal, and the signal provided by the first output terminal is opposite to the signal provided by the second output terminal;
  • the first output terminal of the shift register of the current stage is coupled to the scan signal terminal of the pixel circuit of the current stage, and the second output terminal of the shift register of the current stage is coupled to the light emission control terminal of the pixel circuit of the current stage;
  • the reset signal terminal of the pixel circuit of the current row is coupled to the second output terminal of the next stage shift register.
  • only one driving circuit can be provided in the non-display area to provide driving signals to each signal terminal of the pixel circuit, which reduces the area occupied by the non-display area by the driving circuit. Conducive to the realization of a narrow frame design.
  • the embodiments of the present disclosure also provide a display device, including the above-mentioned electroluminescent display panel provided by the embodiments of the present disclosure.
  • the display device can be a monitor, a mobile phone, a TV, a notebook computer, an electronic paper, a digital photo frame, a navigator, an all-in-one machine, etc., and other indispensable components of the display device should be understood by those of ordinary skill in the art. It will not be repeated here, nor should it be used as a limitation to the present disclosure.
  • Embodiments of the present disclosure provide a pixel circuit, a driving method thereof, an electroluminescent display panel, and a display device.
  • the pixel circuit includes: a first initialization circuit, a second initialization circuit, an anode control circuit, a data writing circuit, and a drive control
  • the first initialization circuit provides the signal of the initialization signal terminal to the first node under the control of the reset signal terminal;
  • the second initialization circuit makes the first node and the second node and the first node under the control of the scan signal terminal
  • the three nodes are turned on;
  • the anode control circuit provides the potential of the third node to the anode of the light-emitting device under the control of the reset signal terminal;
  • the data writing circuit provides the signal of the data signal terminal to the fourth node under the control of the scan signal terminal; drive control
  • the circuit determines the magnitude of the driving current for driving the light emitting device under the control of the potential of the second node and the potential of the fourth node; the light
  • the level of the signal provided by the scan signal terminal of the pixel circuit and the signal provided by the light-emitting control terminal are opposite, so a driving circuit can be used to provide driving signals to the scan signal terminal and the light-emitting control terminal, reducing
  • the arrangement of the driving circuit is beneficial to realize the narrow frame design of the electroluminescent display panel.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Electroluminescent Light Sources (AREA)
  • Control Of El Displays (AREA)

Abstract

L'invention concerne un circuit de pixels et son procédé d'attaque, un panneau d'affichage électroluminescent, et un dispositif d'affichage. Le circuit de pixels comprend : un circuit d'initialisation (0), un circuit d'écriture de données (4), un circuit de commande d'attaque (5), un circuit de commande d'émission de lumière (6) et un dispositif électroluminescent (O) ; selon l'invention, au moyen de la conception d'une structure du circuit de pixels, le niveau d'un signal fourni par une extrémité de signal de balayage (G_n) du circuit de pixels et le niveau d'un signal fourni par une extrémité de commande d'émission de lumière (EM_n) du circuit de pixels peuvent être l'inverse l'un de l'autre ; par conséquent, des signaux de commande peuvent être fournis à l'extrémité de signal de balayage (G_n) et à l'extrémité de commande d'émission de lumière (EM_n) au moyen d'un circuit d'attaque, ce qui permet de réduire l'agencement du circuit d'attaque, et de faciliter la conception de cadre étroit du panneau d'affichage électroluminescent.
PCT/CN2020/074363 2019-03-20 2020-02-05 Circuit de pixels et son procédé d'attaque, panneau d'affichage électroluminescent, et dispositif d'affichage WO2020186933A1 (fr)

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CN113963668B (zh) * 2020-07-21 2023-04-07 京东方科技集团股份有限公司 一种显示装置及其驱动方法
CN113963667B (zh) 2020-07-21 2023-04-18 京东方科技集团股份有限公司 一种显示装置及其驱动方法
CN112116896B (zh) * 2020-10-20 2021-12-03 武汉华星光电半导体显示技术有限公司 像素驱动电路
CN112419967B (zh) * 2020-11-19 2022-04-12 京东方科技集团股份有限公司 像素电路及其驱动方法、显示装置
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