CN111916018A - Display panel and driving method thereof - Google Patents
Display panel and driving method thereof Download PDFInfo
- Publication number
- CN111916018A CN111916018A CN202010832943.6A CN202010832943A CN111916018A CN 111916018 A CN111916018 A CN 111916018A CN 202010832943 A CN202010832943 A CN 202010832943A CN 111916018 A CN111916018 A CN 111916018A
- Authority
- CN
- China
- Prior art keywords
- scanning
- circuit
- display panel
- clock signal
- scan
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 21
- 238000010586 diagram Methods 0.000 description 27
- 239000003990 capacitor Substances 0.000 description 18
- 206010047571 Visual impairment Diseases 0.000 description 7
- 230000000694 effects Effects 0.000 description 6
- 230000009286 beneficial effect Effects 0.000 description 3
- 101000805729 Homo sapiens V-type proton ATPase 116 kDa subunit a 1 Proteins 0.000 description 2
- 101000854879 Homo sapiens V-type proton ATPase 116 kDa subunit a 2 Proteins 0.000 description 2
- 101000854873 Homo sapiens V-type proton ATPase 116 kDa subunit a 4 Proteins 0.000 description 2
- 102100020737 V-type proton ATPase 116 kDa subunit a 4 Human genes 0.000 description 2
- 238000009825 accumulation Methods 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 1
- 230000014759 maintenance of location Effects 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
- 230000008707 rearrangement Effects 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
The embodiment of the invention discloses a display panel and a driving method thereof, wherein the display panel comprises m scanning circuits, wherein in the m scanning circuits, the jth scanning circuit is electrically connected with the mth + jth scanning line along the second direction, and m is more than or equal to 2; the driving chip controls any one scanning circuit in the m scanning circuits to output scanning pulse signals in each frame under the display mode of m times of basic refresh frequency, so that only 1/m pixel circuits in the display panel write in data signals and emit light in each frame under the display mode of m times of basic refresh frequency.
Description
Technical Field
The embodiment of the invention relates to the technical field of display, in particular to a display panel and a driving method thereof.
Background
With the development of display technology, the requirements on display quality are higher and higher.
The display panels are refreshed at different frequencies, and the display effects are usually different. The existing display panel is usually low in refreshing frequency, so that the display panel is easy to have poor display phenomena such as flicker, afterimage and the like, and the improvement of the refreshing frequency can be helpful for improving the poor display.
However, the conventional display panel has a problem that it is difficult to increase the refresh frequency.
Disclosure of Invention
The invention provides a display panel and a driving method thereof, which are used for improving the refreshing frequency of the display panel, improving the bad display phenomenon of the display panel and improving the display effect.
In a first aspect, an embodiment of the present invention provides a display panel, including:
the pixel circuit comprises m scanning circuits, a plurality of scanning lines extending along a first direction and a plurality of data lines extending along a second direction, wherein each data line is connected with at least one column of pixel circuits, and the first direction and the second direction are intersected;
in the m scanning circuits, the jth scanning circuit is electrically connected with the mth + jth scanning line along the second direction, and the mth + jth scanning line is electrically connected with at least the mth + jth row of pixel circuits along the second direction, wherein m is more than or equal to 2, j is more than or equal to 1 and less than or equal to m, and d is more than or equal to 0;
the display panel also comprises a driving chip which is respectively and electrically connected with the m scanning circuits and is respectively and electrically connected with each data line; the driving chip is used for controlling any scanning circuit in the m scanning circuits to output scanning pulse signals in each frame under a display mode of m times of basic refresh frequency; and a data line for outputting a data signal to the data line connected to the pixel circuit for controlling data writing by the scan pulse signal when the scan circuit outputs the scan pulse signal; wherein the basic refresh frequency is determined by the clock signal frequency of the driving chip.
In a second aspect, an embodiment of the present invention further provides a driving method of a display panel, for driving the display panel of the first aspect, where the driving method of the display panel includes:
in a display mode of m times of basic refresh frequency, in each frame, controlling any one of m scanning circuits to output a scanning pulse signal; and a data line for outputting a data signal to the data line connected to the pixel circuit for controlling data writing by the scan pulse signal when the scan circuit outputs the scan pulse signal; wherein the basic refresh frequency is determined by the clock signal frequency of the driving chip.
In the display panel and the driving method thereof provided by the embodiment, the display panel includes m scanning circuits, wherein in the m scanning circuits, the jth scanning circuit is electrically connected with the mth + jth scanning line along the second direction, wherein m is greater than or equal to 2, j is greater than or equal to 1 and less than or equal to m, and d is greater than or equal to 0; the display panel also comprises a driving chip, and the driving chip controls any scanning circuit in the m scanning circuits to output scanning pulse signals in each frame under a display mode of m times of basic refresh frequency; and when the scanning circuit outputs the scanning pulse signal, outputting the data signal to the data line connected with the pixel circuit which controls data writing by the scanning pulse signal, so that only 1/m of the pixel circuits in the display panel write the data signal and emit light in each frame in a display mode of m times of the basic refresh frequency, and further, compared with the pixel circuit which works at the basic refresh frequency and writes the data signal, the corresponding data writing time of the pixel circuit does not change, correspondingly, the charging time of a capacitor in the pixel circuit does not change, and further the capacitor of the pixel circuit can be fully charged. In addition, in 1s, the total number of the data signals provided by the driving chip when the display panel works in the working mode corresponding to the basic refresh frequency is equal to the total number of the data signals provided by the driving chip when the display panel works in the working mode corresponding to the m times of the basic refresh frequency, so that the bandwidth of the driving chip can not be changed. Therefore, the display panel of the embodiment can improve the refresh frequency of the display panel on the basis of not changing the bandwidth of the driving chip and ensuring the charging time of the capacitor in the pixel circuit, thereby improving the problems of flicker and afterimage of the display panel.
Drawings
Fig. 1 is a schematic structural diagram of a display panel according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of a scan circuit according to an embodiment of the present invention;
fig. 3 is a schematic diagram of a prior art 2T1C pixel circuit;
FIG. 4 is a schematic structural diagram of another display panel provided in the embodiment of the present invention;
FIG. 5 is a schematic structural diagram of another display panel according to an embodiment of the present invention;
FIG. 6 is a timing diagram of driving a pixel circuit in a display panel according to an embodiment of the present invention;
FIG. 7 is a timing diagram illustrating another driving method for a pixel circuit in a display panel according to an embodiment of the present invention;
fig. 8 is a schematic diagram of a 7T1C pixel circuit in the prior art;
FIG. 9 is a timing diagram illustrating another driving method for a pixel circuit of a display panel according to an embodiment of the present invention;
FIG. 10 is a schematic structural diagram of another display panel according to an embodiment of the present invention;
FIG. 11 is a schematic structural diagram of another display panel according to an embodiment of the present invention;
fig. 12 is another driving timing diagram for a pixel circuit in a display panel according to an embodiment of the present invention;
fig. 13 is a flowchart of a driving method of a display panel according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.
As described in the background art, the conventional refresh frequency of the display panel is generally low, so that the display panel is prone to display defects such as flicker and afterimage, and increasing the refresh frequency can help to improve the display defects. However, the conventional display panel has a problem that it is difficult to increase the refresh frequency. The inventors have found that the above problem is caused by that, when the refresh frequency of the display panel is low, the time required for holding each frame of picture is long, and the holding capability of the capacitor included in the pixel circuit is limited, so that the display panel is easy to generate the flicker phenomenon. In addition, in the working process of the pixel circuit in the display panel, most of the time works in the light-emitting stage, and the driving transistor in the pixel circuit is in a bias state for a long time in the light-emitting stage, so that the longer the time of one frame is, the more serious the charge accumulation in the driving transistor is, and the more obvious the afterimage phenomenon is caused. The refresh rate is increased to shorten the time of one frame, and accordingly, the charge retention time of the capacitor included in the pixel circuit in one frame is shortened, thereby being beneficial to reducing the flicker phenomenon of the display panel. And the one-frame time is shortened, so that the charge accumulation in the driving transistor in each frame can be reduced, and the afterimage problem can be improved. However, the charging time of the pixel circuit in the existing display panel is limited, that is, the capacitor in the pixel circuit can be charged only if the charging time is long enough, and the capacitor in the pixel circuit cannot be charged completely due to too short charging time; and the bandwidth of the driving chip in the existing display panel is also limited, wherein the bandwidth of the driving chip is related to the resolution of the display panel and the refresh frequency, and on the premise of the same resolution, the bandwidth of the driving chip is required to be correspondingly increased when the refresh frequency is increased, but the bandwidth increase of the existing driving chip is difficult to realize. In summary, the limitation of the capacitor charging time and the limitation of the bandwidth of the driving chip in the pixel circuit make it difficult to improve the refresh frequency of the display panel.
For the above reasons, an embodiment of the present invention provides a display panel, fig. 1 is a schematic structural diagram of a display panel provided in an embodiment of the present invention, fig. 2 is a schematic structural diagram of a scan circuit provided in an embodiment of the present invention, and referring to fig. 1 and fig. 2, the display panel includes:
m scan circuits 110, a plurality of scan lines (S1, S2, S3, S4, S5, S6 … …) extending in a first direction x, and a plurality of data lines (D1, D2, D3, D4, D5 … …) extending in a second direction y, each data line connecting at least one column of pixel circuits 130, the first direction x and the second direction y intersecting;
in the m scanning circuits 110, the jth scanning circuit is electrically connected with the mth + jth scanning line along the second direction y, and the mth + jth scanning line is electrically connected with at least the mth + jth row of pixel circuits 130 along the second direction y, wherein m is greater than or equal to 2, j is greater than or equal to 1 and less than or equal to m, and d is greater than or equal to 0;
the display panel further includes a driving chip 140, and the driving chip 140 is electrically connected to the m scanning circuits 110 and each data line; the driving chip 140 is configured to control any one of the m scanning circuits 110 to output a scanning pulse signal in each frame in a display mode with m times of the basic refresh frequency; and a data line for outputting a data signal to which the pixel circuit 130 is connected, the data writing of which is controlled by the scan pulse signal, when the scan circuit 110 outputs the scan pulse signal; wherein the base refresh frequency is determined by the clock signal frequency of the driving chip 140.
The row direction of the pixel circuits 130 is along a first direction x, and the column direction of the pixel circuits 130 is along a second direction y.
Specifically, each scan circuit 110 may include a plurality of output terminals, and each output terminal may be connected to one scan line. The scan circuit 110 is configured to generate scan signals, which include scan pulse signals, and the scan pulse signals are transmitted to the pixel circuits 130 through the scan lines. The scan lines connected to different scan circuits 110 are different, and specifically, the scan line connected to the jth scan circuit includes the dm + jth scan line along the second direction y. Fig. 1 exemplarily shows a case where m is 2, and referring to fig. 1, the display panel includes 2 scan circuits 110, where the 2 scan circuits 110 are a 1 st scan circuit 111 and a 2 nd scan circuit 112, respectively, i.e., j is 1, 2; where j is 1, dm + j is 1(d is 0), 3(d is 1),5(d is 2),7(d is 3) … …; when j is 2, dm + j is 2(d is 0),4(d is 1),6(d is 2),8(d is 3) … …. Any one of the 2 scan circuits 110 may serve as the 1 st scan circuit 111, and the remaining one scan circuit 110 serves as the 2 nd scan circuit 112. When m takes another value, the same as the case where m is 2, that is, any one of the m scan circuits 110 serves as the 1 st scan circuit 111, and any one of the remaining (m-1) scan circuits 110 serves as the last remaining 1 scan circuit 110 of the 2 nd scan circuit 112 … … as the m-th scan circuit.
When the display panel displays, the display panel can have different display modes and different required refreshing frequencies. For example, when the display panel displays a static page, the required refresh frequency is low; when the display panel displays the dynamic page, the required refreshing frequency is higher. As described in the background, it is difficult to increase the refresh frequency due to the limitation of the capacitor charging time in the pixel circuit 130 and the limitation of the bandwidth of the driving chip 140 in the conventional display panel. In the display panel of the present embodiment, the improvement of the refresh frequency can be realized by controlling any one of the m scanning circuits 110 to output the scanning pulse signal by the driving chip 140 in each frame in the display mode of m times the basic refresh frequency. Specifically, the basic refresh frequency is determined by the clock signal frequency of the driver chip 140, and optionally, the basic refresh frequency may be equal to the clock signal frequency of the driver chip 140, where the clock signal frequency is adjustable, that is, the basic refresh frequency is adjustable. When there is a need to increase the refresh frequency, for example, when the display panel needs to operate in a display mode with m times of the basic refresh frequency, in each frame, the driving chip 140 controls only one scanning circuit 110 of the m scanning circuits 110 to output a scanning pulse signal, and one scanning circuit 110 of the m scanning circuits 110 may be any one, correspondingly, only the scanning line connected to the scanning circuit 110 that outputs the scanning pulse signal may receive the scanning pulse signal, and at the same time, the driving chip 140 outputs a data signal to the data line connected to the pixel circuit 130 whose data is controlled to be written by the scanning pulse signal, thereby completing the writing of the data signal. Therefore, when the display panel operates in a display mode with m times of the basic refresh frequency, only 1/m of the scan lines in the display panel can receive the scan pulse signal, and accordingly, only 1/m of the pixel circuits 130 in the display panel perform data signal writing and emit light after data writing. Moreover, since the j-th scan circuit of the m scan circuits 110 is electrically connected to the dm + j-th scan line along the second direction y, that is, the scan lines connected to each scan circuit 110 are uniformly distributed in the second direction y, and the dm + j scan lines are electrically connected to the dm + j row pixel circuits, accordingly, the pixel circuits 130 driven by each scan circuit 110 are uniformly distributed in the second direction y, so that even if only 1/m of the pixel circuits 130 in the display panel are lighted (i.e., the resolution of each frame line is reduced to 1/m in the display mode corresponding to the basic display frequency) in the display mode of m times of the basic refresh frequency, a relatively complete display screen can be formed, and a good display effect can be ensured.
As can be seen from the above-mentioned driving process of the display panel in the display mode with m times of the basic refresh frequency, in each frame, by controlling any one of the m scanning circuits 110 to output the scanning signal, only 1/m of the pixel circuits 130 in the display panel perform writing of the data signal and emit light, so that for the pixel circuits 130 writing the data signal, compared with the pixel circuits 130 operating at the basic refresh frequency, the data writing time corresponding to the pixel circuits 130 does not change, and accordingly, the charging time of the capacitor in the pixel circuits 130 does not change, thereby ensuring that the capacitor of the pixel circuits 130 can be fully charged. In the display mode with m times of the basic refresh frequency, the driving chip 140 outputs the data signal to the data line connected to the pixel circuit 130 controlled by the scan pulse signal to write data in each frame, i.e., the driving chip 140 only needs to output the data signal to 1/m of the pixel circuits 130 in the display panel in each frame. Taking the number of the pixel circuits 130 included in the display panel as LF (where L may represent the total number of the pixel circuits 130 included in each row of the pixel circuits, and F may represent the total number of the pixel circuits 130 included in each row of the pixel circuits), and the basic refresh frequency is 60Hz as an example, when the display panel operates in the operating mode corresponding to the basic refresh frequency, the number of the data signals that the driving chip 140 needs to provide in each frame is LF, and then the total number of the data signals that the driving chip 140 provides in 1s is 60 LF. When the display panel operates in the operating mode corresponding to the m times of the basic refresh frequency, the number of the data signals that the driving chip 140 needs to provide is LF/m in each frame, and then in 1s, the total number of the data signals that the driving chip 140 provides is (LF/m) × 60 ═ 60LF, so in 1s, the total number of the data signals that the driving chip 140 provides when the display panel operates in the operating mode corresponding to the basic refresh frequency is equal to the total number of the data signals that the driving chip 140 provides when the display panel operates in the operating mode corresponding to the m times of the basic refresh frequency, and therefore although the refresh frequency is increased, the number of the data signals that the driving chip 140 needs to provide to the display panel in each frame is reduced, and therefore the bandwidth of the driving chip 140 may not be changed. Therefore, the display panel of the embodiment can increase the refresh frequency of the display panel without changing the bandwidth of the driving chip 140 and ensuring the charging time of the capacitor in the pixel circuit 130, thereby improving the problems of the flicker and the afterimage of the display panel.
Optionally, m is greater than or equal to 2 and less than or equal to 4, so that under the premise of ensuring that the refresh rate can be improved, the resolution of each frame line is not reduced too much in a display mode with m times of the basic refresh frequency, so that human eyes cannot perceive non-luminous pixels, and a good display effect is ensured. Optionally, m is 2, that is, in correspondence to the structure shown in the display panel shown in fig. 1, on the premise of ensuring that the refresh rate is increased, the resolution of each frame line is reduced to the minimum, and a better display effect is ensured. Optionally, m is 4, so that the number of data signals required to be provided by the display panel in each frame is smaller, which is more beneficial to increasing the refresh frequency of the display panel. Optionally, m is 3, fig. 2 is a schematic structural diagram of another display panel provided in an embodiment of the present invention, and the display panel shown in fig. 2 may correspond to the case where m is 3. When m is 3, the 3 scan circuits are the 1 st scan circuit 111, the 2 nd scan circuit 112, and the third scan circuit 113, respectively. When m is 3, on one hand, the resolution of each frame can not be reduced too much, and further, a good display effect is ensured; on the other hand, the number of data signals required to be provided by the display panel in each frame is less, so that the refresh frequency of the display panel is more favorably improved.
It should be noted that, the display panel shown in fig. 1 is exemplarily illustrated in that each scan line is connected to one row of pixel circuits 130, and each data line is connected to one column of pixel circuits 130, and in other embodiments of the present invention, a part of the scan lines may be connected to two rows of pixel circuits 130. The pixel circuit 130 in the display panel shown in fig. 1 may be a 2T1C pixel circuit in the prior art, and fig. 3 is a schematic structural diagram of a 2T1C pixel circuit in the prior art.
The display panel provided by the embodiment includes m scanning circuits, wherein in the m scanning circuits, the jth scanning circuit is electrically connected with the mth + jth scanning line along the second direction, wherein m is greater than or equal to 2, j is greater than or equal to 1 and less than or equal to m, and d is greater than or equal to 0; the display panel also comprises a driving chip, and the driving chip controls any scanning circuit in the m scanning circuits to output scanning pulse signals in each frame under a display mode of m times of basic refresh frequency; and when the scanning circuit outputs the scanning pulse signal, outputting the data signal to the data line connected with the pixel circuit which controls data writing by the scanning pulse signal, so that only 1/m of the pixel circuits in the display panel write the data signal and emit light in each frame in a display mode of m times of the basic refresh frequency, and further, compared with the pixel circuit which works at the basic refresh frequency and writes the data signal, the corresponding data writing time of the pixel circuit does not change, correspondingly, the charging time of a capacitor in the pixel circuit does not change, and further the capacitor of the pixel circuit can be fully charged. In addition, in 1s, the total number of the data signals provided by the driving chip when the display panel works in the working mode corresponding to the basic refresh frequency is equal to the total number of the data signals provided by the driving chip when the display panel works in the working mode corresponding to the m times of the basic refresh frequency, so that the bandwidth of the driving chip can not be changed. Therefore, the display panel of the embodiment can improve the refresh frequency of the display panel on the basis of not changing the bandwidth of the driving chip and ensuring the charging time of the capacitor in the pixel circuit, thereby being beneficial to improving the problems of flicker and ghost of the display panel.
With continuing reference to fig. 1 and fig. 2, based on the above technical solution, optionally, the driving chip 140 includes m starting signal ends, the display panel further includes m starting signal lines 120, the starting signal ends are electrically connected to the starting signal lines 120 in a one-to-one correspondence, and each starting signal line 120 is connected to one scanning circuit 110;
the driving chip 140 is specifically configured to provide a start signal to any one of the m start signal terminals in each frame in a display mode in which the display panel is at m times the basic refresh frequency.
Specifically, each of the scan circuits 110 is electrically connected to a start signal terminal through one start signal line 120, and the case where m is 2 in fig. 1 is taken as an example for explanation, the driving chip 140 includes two start signal terminals, which are respectively denoted as a first start signal terminal STV1 and a second start signal terminal STV2, and correspondingly, the display panel includes two start signal lines 120, which are respectively denoted as a first start signal line 121 and a second start signal line 122, where the start signal terminals are electrically connected to the start signal lines in a one-to-one correspondence, the first start signal terminal STV1 is connected to the first start signal line 121, and the second start signal terminal STV2 is connected to the second start signal line 122. The scan circuit 110 may include a start signal input terminal IN, the first start signal line 121 is connected to the start signal input terminal IN of the first scan circuit 110, and the second start signal line 122 is connected to the start signal input terminal IN of the second scan circuit 110. Corresponding to the display panel with m-3 shown in fig. 2, the driving chip further includes a third start signal terminal STV3, and correspondingly, the display panel further includes a third start signal line 123.
Whether the scanning circuit 110 outputs the scanning pulse signal is controlled by the start signal, after the scanning circuit 110 receives the start signal, the scanning pulse signal can be output according to the start signal, and the scanning circuit 110 which does not receive the start signal does not output the scanning pulse signal. Therefore, in the display panel of the embodiment, in the display mode in which the display panel is at m times of the basic refresh frequency, the start signal is provided to any one of the m start signal terminals in each frame, so that one scan circuit 110 of the m scan circuits 110 outputs the scan pulse signal, and further, in the display mode in which the display panel is at m times of the basic refresh frequency, the driving chip 140 only needs to provide the data signal to 1/m of the pixel circuits 130 of the display panel.
Based on the above technical solution, optionally, the driving chip 140 is further configured to sequentially provide the start signals to the m start signal terminals in m adjacent frames in a display mode in which the display panel is at m times of the basic refresh frequency, so that the m scanning circuits 110 output the scanning pulse signals one by one in the m adjacent frames.
Specifically, the driving chip 140 sequentially provides the start signal to the m start signal terminals in m frames adjacent to each other in the display mode of the display panel with the basic refresh frequency m times that of the display panel means that the driving chip 140 provides the start signal to one start signal terminal in m frames adjacent to each other in the display mode of the display panel with the basic refresh frequency m times that of the display panel, and the start signal terminals of the driving chip 140 providing the start signal to each frame in m frames adjacent to each other are different, so that the m scanning circuits 110 output the scanning signals one by one in m frames adjacent to each other, correspondingly, the pixel circuits 130 connected to the scanning circuits 110 in the m scanning circuits 110 alternately operate in m frames adjacent to each other, further the total operating time of the pixel circuits 130 in the display panel is relatively consistent, and the service lives of the pixel circuits 130 in the display panel can be relatively average.
In other embodiments of the present invention, in the display mode of the display panel with m times of the basic refresh frequency, the driving chip 140 provides the start signal to one start signal terminal in each of the adjacent m frames, and the start signal terminals of the driving chip 140 providing the start signal in any two frames of the adjacent m frames may be the same, which is not limited herein in the embodiments of the present invention.
With continued reference to fig. 1, optionally, the scan circuit 110 includes a plurality of cascaded first shift registers 10, where, in the m scan circuits 110, the ith-stage first shift register 10 of the jth scan circuit is electrically connected to the (i-1) m + j scan lines along the second direction y, where m is greater than or equal to 2, j is greater than or equal to 1 and less than or equal to m, i is greater than or equal to 1 and less than or equal to n, and n represents the total number of stages of the first shift registers 10 included in the scan circuit 110 where the first shift register 10 is located.
Taking the case where m is 2 as shown in fig. 1 as an example, j may take a value of 1, 2. When j is 1, that is, for the 1 st scan circuit 111, the 1 st stage first shift register of the 1 st scan circuit 111 is electrically connected to the (1-1) × 2+1 ═ 1 st scan line in the second direction y, and the 2 nd stage first shift register of the 1 st scan circuit 111 is electrically connected to the (2-1) × 2+1 ═ 3 st scan line in the second direction y; when j is 2, that is, for the 2 nd scan circuit 112, the 1 st stage first shift register of the 2 nd scan circuit 112 is electrically connected to the (1-1) × 2+2 ═ 2 th scan line in the second direction y, and the 2 nd stage first shift register 10 of the 2 nd scan circuit 112 is electrically connected to the (2-1) × 2+2 ═ 4 th scan line in the second direction y. For the case where m takes other values, similar to the case where m is 2, the description thereof is omitted.
Optionally, the driving chip 140 is further configured to, in a display mode with a basic refresh frequency of k times, sequentially control m/k scanning circuits 110 of the m scanning circuits 110 to output scanning pulse signals in each frame, where, in the m/k scanning circuits 110, a scanning pulse signal output by the first stage first shift register 10 of the q +1 th scanning circuit 110 is after a scanning pulse signal output by the first stage first shift register 10 of the q-th scanning circuit 110, where q is greater than or equal to 1 and is less than or equal to m/k-1; and the scanning pulse signal output by the second stage first shift register 10 of the 1 st scanning circuit 111 follows the scanning pulse signal output by the first stage first shift register 10 of the m/k-th scanning circuit 110; wherein k is more than or equal to 1 and less than m, and m/k is an integer.
Specifically, when k is 1, the basic refresh frequency is k times equal to the basic refresh frequency, and m/k is m, and in the display mode of the basic refresh frequency, m scan circuits 110 are sequentially controlled to output scan pulse signals for each frame.
When k is greater than or equal to 2 and less than m, m/k is less than m, therefore, when k is greater than or equal to 2 and less than m, not all m scan circuits 110 output scan pulse signals, but only m/k scan circuits 110 output scan pulse signals, correspondingly, only (m/k)/m is 1/k pixel circuits 130 in the display panel perform data signal writing, so that the data writing time of the pixel circuits 130 is not shortened and correspondingly the bandwidth of the driving chip 140 is kept unchanged relative to the display mode in which the display panel operates at the basic refresh frequency, thereby increasing the refresh frequency and further improving the flicker and image sticking phenomenon of the display panel on the basis of not changing the bandwidth of the driving chip 140 and ensuring the sufficient data writing time of the pixel circuits 130, the specific principle is the same as that of the display mode in which the basic refresh frequency is m times as in the above embodiment, this embodiment is not described herein.
It should be noted that in this embodiment, it is necessary to ensure that the value of k is an integer, and for example, when m is 4, the value of k may be 1 and 2, and m is 4, 2 is taken as an example, and in the display mode with 2 times the basic refresh frequency, two of the 4 scan circuits 110 are controlled to output the scan pulse signal every frame.
Fig. 4 is a schematic structural diagram of another display panel provided in an embodiment of the present invention, fig. 5 is a schematic structural diagram of another display panel provided in an embodiment of the present invention, and referring to fig. 4 and 5, optionally, the display panel further includes m light emission control driving circuits 150 and a plurality of light emission control signal lines (E1, E2, E3, E4, E5, E6 … …), each of the light emission control signal lines is connected to one row of pixel circuits 130, the light emission control driving circuit 150 includes a plurality of cascaded second shift registers 20, among the m light emission control driving circuits 150, the ith-stage second shift register 20 of the jth light emission control drive circuit 150 is electrically connected to the (i-1) th m + j-th light emission control signal line in the second direction y, wherein m is more than or equal to 2, j is more than or equal to 1 and less than or equal to m, i is more than or equal to 1 and less than or equal to n, and n represents the total stage number of the second shift register 20 included in the scanning circuit 110 where the second shift register 20 is located;
the driving chip 140 is further configured to control the second shift register 20 of the light-emitting control driving circuit 150, which is connected to the same pixel circuit 130 as the scanning circuit 110 that outputs the scanning pulse signal, to output the light-emitting control pulse signal step by step in the display mode in which the display panel is at m times the basic refresh frequency;
wherein, the r-th stage second shift register 20 of the light emission control driving circuit 150 outputting the light emission control pulse signal outputs the light emission control pulse signal, and r is more than or equal to 1 and less than or equal to m after the r-th stage first shift register 10 of the scanning circuit 110 outputting the scanning pulse signal outputs the scanning pulse signal.
Among them, fig. 4 and 5 schematically show a case where m is 2, that is, two scanning circuits 110 (1 st scanning circuit 111 and 2 nd scanning circuit 112) and two light emission control driving circuits 150 (1 st light emission control driving circuit 151 and 2 nd light emission control driving circuit 152) are included in the display panel.
Among them, the jth scanning circuit and the jth emission control driving circuit may be connected to the same pixel circuit 130 row. The ith stage second shift register 20 of the jth light emission control driving circuit 150 is electrically connected to the (i-1) th m + j light emission control signal lines in the second direction y, and the (i-1) th m + j light emission control signal lines may be connected to the (i-1) m + j rows of pixel circuits in the second direction y. In the display mode with m times of basic refresh frequency, if the jth scan circuit outputs the scan pulse signal in a frame, the jth light-emitting control driving circuit 150 outputs the light-emitting control pulse signal in the frame, so as to ensure that the pixel circuit 130 can drive the light-emitting device to emit light under the control of the light-emitting control pulse signal after data writing is performed under the control of the scan pulse signal.
FIG. 6 is a driving timing diagram for a pixel circuit in a display panel according to an embodiment of the present invention, in which FIG. 6 schematically shows the r-th scan signal Scanj _ r outputted from the r-th stage of the first shift register (1. ltoreq. r. ltoreq. n) in the j-th scan circuit, the r + 1-th scan signal Scanj _ r +1 outputted from the r + 1-th stage of the first shift register in the j-th scan circuit, and the r-th emission control signal EMj _ r outputted from the r-th stage of the second shift register in the j-th emission control drive circuit. Referring to fig. 6, fig. 6 schematically shows that the light emitting control pulse signal (taking a low level pulse as an example) of the r-th light emitting control signal EMj _ r is after the scan pulse signal (taking a low level pulse as an example) of the r-th scan signal Scanj _ r, the driving timing shown in fig. 6 can be applied to driving the 2T1C pixel circuit 130 in the prior art, the pixel circuit 130 included in the display panel shown in fig. 4 can be the 2T1C pixel circuit 130, and in combination with fig. 4, when the pixel circuit 130 included in the display panel is the 2T1C pixel circuit 130, each row of the pixel circuits 130 is connected to one scan line, and the scan pulse signal on the scan line connected to each row of the pixel circuits 130 can be used to control the pixel circuit 130 to write row data. Each row of pixel circuits 130 is connected to a light emission control signal line that can be used to control the light emitting devices of the row of pixel circuits 130 to emit light. Specifically, referring to fig. 4 and fig. 6, when the display panel includes 2T1C pixel circuits 130, the first shift register 10 of the r-th stage in the j-th scan circuit and the second shift register 20 of the r-th stage in the j-th light emission control driving circuit 150 are connected to the same row of pixel circuits 130 (the (r-1) th row of m + j pixel circuits), the scan pulse signal in the r-th scan signal Scanj _ r output by the first shift register 10 of the r-th stage in the j-th scan circuit can be used to control the (r-1) th row of m + j pixel circuits to perform data writing, after the data writing, the low-level pulse (light emission control pulse signal) in the r-th light emission control signal EMj _ r output from the r-th stage second shift register 20 in the j-th light emission control drive circuit 150 can be used to control the light emission of the light emitting devices in the (r-1) th row m + j of pixel circuits. The 2T1C pixel circuit shown in fig. 3 can be a pixel circuit in the (i-1) th m + j row in the second direction in the display panel, and the data signal writing of the pixel circuit is controlled by the scan pulse signal in the r scan signal Scanj _ r output by the r-th stage first shift register of the j scan circuit.
Fig. 7 is another driving timing diagram for the pixel circuit in the display panel according to the embodiment of the invention, and referring to fig. 7, fig. 7 schematically shows that the light emitting control pulse signal (low level pulse) of the r-th light emitting control signal EMj _ r is after the scan pulse signal (low level pulse) of the r + 1-th scan signal Scanj _ r +1, and the driving timing shown in fig. 7 is applicable to the driving of the 7T1C pixel circuit 130 in the prior art. Specifically, the display panel shown in fig. 5 may correspond to the case where the pixel circuit 130 included in the display panel is the 7T1C pixel circuit 130. Fig. 8 is a schematic diagram of a 7T1C pixel circuit in the prior art.
Specifically, referring to fig. 5, when the pixel circuits 130 included in the display panel are 7T1C pixel circuits 130, two scan lines are connected to each row of pixel circuits 130, where fig. 5 only schematically illustrates the connection between two rows of pixel circuits 130 and each scan line, each emission control signal line, and each data line in the second direction y. In the first direction x, the first row of pixel circuits 130 may be electrically connected to a first scan line and a third scan line in the second direction y, and the second row of pixel circuits 130 may be electrically connected to a second scan line and a fourth scan line in the second direction y, that is, the r-th stage first shift register 10 of the j-th scan circuit is electrically connected to the (r-1) m + j-th row of pixel circuits 130 through the (r-1) m + j scan lines in the second direction y, and the (r-1) m + j row of pixel circuits 130 is also electrically connected to the rm + j scan lines, where the rm + j scan lines are connected to the r + 1-th stage first shift register 10 in the j scan circuit. In conjunction with fig. 5 and 7, each row of pixel circuits 130 is connected to a light emission control signal line that can be used to control the light emitting devices of the row of pixel circuits 130 to emit light. Optionally, when the display panel includes 7T1C pixel circuits, after the r +1 st stage first shift register 10 of the scan circuit 110 outputting the scan pulse signal outputs the scan pulse signal, the jth scan circuit outputs the scan pulse signal, the jth light emission control drive circuit 150 outputs the light emission control pulse signal, the jth scan circuit outputs the light emission control pulse signal, the r th stage first shift register 10 and the r +1 th stage first shift register 10 in the jth scan circuit are connected to the (r-1) m + j row pixel circuits 130 in the display panel, and the data signal writing of the (r-1) m + j row pixel circuits 130 is controlled by the r +1 th scan signal Scanj _ r +1 in combination with fig. 8, so that the r th stage second shift register 20 of the light emission control drive circuit 150 outputting the light emission control pulse signal outputs the light emission control pulse signal After the r +1 th stage first shift register 10 of the scan circuit 110 outputting the scan pulse signal outputs the scan pulse signal, it can be ensured that the light emitting device is controlled to emit light after the data writing is completed by the pixel circuits 130 of each row. The pixel circuit 7T1C shown in fig. 8 can be a pixel circuit in the (i-1) th m + j row in the second direction in the display panel, and the data signal writing of the pixel circuit is controlled by the scan pulse signal in the r +1 th scan signal Scanj _ r +1 output by the r +1 th stage first shift register of the j-th scan circuit; the scan pulse signal of the r-th scan signal Scanj _ r output from the first shift register of the r-th stage of the j-th scan circuit can control the initialization of the pixel circuit.
The driving timing shown in fig. 6 and 7 is applied to a display mode corresponding to m (corresponding to the case where m is 2) times the base refresh frequency.
Fig. 9 is another driving timing diagram for pixel circuits in a display panel according to an embodiment of the present invention, where the driving timing diagram shown in fig. 9 is applicable to a display mode corresponding to a basic refresh frequency, and can be used to drive the display panel shown in fig. 5, which includes a 7T1C pixel circuit, and m is 2. Fig. 9 shows an r Scan signal Scan1_ r output from the r-th stage first shift register of the 1 st Scan circuit, an r +1 Scan signal Scan1_ r +1 output from the r + 1-th stage first shift register of the 1 st Scan circuit, an r Scan signal Scan2_ r output from the r-th stage first shift register of the 2 nd Scan circuit, an r +1 Scan signal Scan2_ r +1 output from the r + 1-th stage first shift register of the 2 nd Scan circuit, an r emission control signal EM1_ r output from the r-th second shift register of the 1 st emission control drive circuit, and an r emission control signal EM2_ r output from the r-th second shift register of the 2 nd emission control drive circuit. The first phase e1 is the non-emitting phase of the pixel circuit row connected to the r-th stage second shift register of the 1 st emission control driving circuit, and the second phase e2 is the non-emitting phase of the pixel circuit row connected to the r-th stage second shift register of the 2 nd emission control driving circuit.
The display panel of the embodiment, by arranging the display panel to include the light-emitting control driving circuits with the same number as the scanning circuits, enables the pixel circuits in each row to enter the light-emitting stage immediately after completing data writing, and ensures that the light-emitting devices in the pixel circuits have longer light-emitting time.
Fig. 10 is a schematic structural diagram of another display panel according to an embodiment of the present invention, and fig. 11 is a schematic structural diagram of another display panel according to an embodiment of the present invention, where the display panel shown in fig. 10 includes a pixel circuit that may be a 2T1C pixel circuit, and the display panel shown in fig. 11 includes a pixel circuit that may be a 7T1C pixel circuit. Referring to fig. 10 and fig. 11, optionally, the display panel further includes a light emission control driving circuit 150, the light emission control driving circuit 150 includes a plurality of cascaded second shift registers 20, an output end of the t-th stage of second shift registers 20 is connected to the (t-1) m _ +1 to tm rows of pixel circuits 130 along the second direction y, 1 ≦ t ≦ n, n represents a total number of second shift registers included in the light emission control driving circuit in which the second shift register 20 is located; the driving chip 140 is further configured to control the second shift register 20 of the light emission control driving circuit 150 to output the light emission control pulse signal step by step in a display mode in which the display panel is at m times of the basic refresh frequency;
the r-th stage second shift register 20 of the light emission control driving circuit 150 outputs the light emission control pulse signal, and after the r-stage first shift register 10 of the scanning circuit 110 outputting the scanning pulse signal outputs the scanning pulse signal, r is more than or equal to 1 and less than or equal to m.
Referring to fig. 10, when only one light emission control driving circuit 150 is included in the display panel, the second shift register 20 in each light emission control driving circuit 150 is connected to m rows of pixel circuits 130, specifically, when the output end of the t-th stage second shift register 20 is connected to the (t-1) m _ +1 to tm rows of pixel circuits 130 in the second direction y (for example, when m is 2, each stage second shift register 20 is connected to two rows of pixel circuits, exemplarily, each stage second shift register 20 is connected to one light emission control signal line, and further, when the display panel operates in an operation mode corresponding to the basic refresh frequency, each second shift register 20 controls light emission of light emitting devices in the m rows of pixel circuits 130; when the display panel operates in an operation mode corresponding to m times the basic refresh frequency, each of the second shift registers 20 controls the light emitting devices in one row of the pixel circuits 130 to emit light. When the display panel operates in the operating mode corresponding to m times of the basic refresh frequency, the driving timings shown in fig. 6 and fig. 7 are also applicable (wherein the driving timing shown in fig. 6 is suitable for driving the 2T1C pixel circuit in the display panel shown in fig. 10, and the driving timing shown in fig. 7 is suitable for driving the 7T1C pixel circuit in the display panel shown in fig. 11), and are not described herein again.
Fig. 12 is another driving timing diagram for pixel circuits in a display panel according to an embodiment of the present invention, where the driving timing diagram shown in fig. 12 is applicable to a display mode corresponding to a basic refresh frequency, and can be used to drive the display panel shown in fig. 11, which includes the 7T1C pixel circuits, and m is 2. Fig. 9 shows an r-th Scan signal Scan1_ r output from the r-th stage first shift register of the 1 st Scan circuit, an r + 1-th Scan signal Scan1_ r +1 output from the r + 1-th stage first shift register of the 1 st Scan circuit, an r-th Scan signal Scan2_ r output from the r-th stage first shift register of the 2 nd Scan circuit, an r + 1-th Scan signal Scan2_ r +1 output from the r + 1-th stage first shift register of the 2 nd Scan circuit, and an r-th emission control signal EM _ r output from the r-th second shift register of the emission control drive circuit. The first phase e1 is the non-emitting phase of the pixel circuit row connected to the r-th stage second shift register of the 1 st emission control driving circuit, and the second phase e2 is the non-emitting phase of the pixel circuit row connected to the r-th stage second shift register of the 2 nd emission control driving circuit. As can be seen from the driving timing sequence shown in fig. 9, each stage of the second shift register can control the light emitting state of the light emitting devices in the m rows of pixel circuits, and the scan circuit 110 and the light emitting control circuit are usually disposed in the non-display region of the display panel, so that the display panel of this embodiment includes only one light emitting control circuit, so that the area of the frame occupied by the scan circuit 110 and the light emitting control drive circuit 150 is reduced, and the narrow frame is further facilitated to be implemented.
Based on the above technical solution, taking the display panel shown in fig. 3 as an example, optionally, the display panel includes a display area AA and a first non-display area NAA and a second non-display area NAA located at two opposite sides of the display area AA, and no matter the display panel includes m light-emitting control driving circuits 150 or one light-emitting control circuit, in this embodiment, the scanning circuit 110 and the light-emitting control circuit may be uniformly disposed in the first display area AA and the second display area AA, specifically, the m scanning circuits 110 may be disposed in the first non-display area NAA, and the light-emitting control driving circuit 150 is disposed in the second non-display area NAA; or a part of the m scanning circuits 110 is disposed in the first display area AA, and another part of the scanning circuits 110 is disposed in the second display area AA; when the display panel includes m light emission control driving circuits 150, b light emission control driving circuits 150 of the m light emission control driving circuits 150 may be disposed in the first non-display area NAA, and m-b light emission control driving circuits 150 may be disposed in the second non-display area NAA, where b is greater than or equal to 1 and less than or equal to m-1. Or the scanning circuit 110 includes a first sub-scanning circuit 110 and a second sub-scanning circuit 110, where the first sub-scanning circuit 110 and the second sub-scanning circuit 110 each include a plurality of stages of first shift registers 10 connected in cascade; the light emission control driving circuit 150 includes a first sub light emission control driving circuit 150 and a second sub light emission control driving circuit 150, and the first sub light emission control driving circuit 150 and the second sub light emission control driving circuit 150 each include a plurality of stages of second shift registers 20 connected in cascade; the first sub-scanning circuit 110 and the first sub-emission control driving circuit 150 are located in the first non-display area NAA, and the second sub-scanning circuit 110 and the second sub-emission control driving circuit 150 are located in the second non-display area NAA. And then the areas of the first display area AA and the second display area AA are relatively consistent, and the frames on the two sides of the display area AA can be relatively narrow.
Optionally, the driving chip further includes a first clock signal output end and a second clock signal output end, the first shift register includes a first clock signal input end and a second clock signal input end, the display panel further includes a first clock signal line and a second clock signal line, the first clock signal line is electrically connected to the first clock signal output end, and the second clock signal line is electrically connected to the second clock signal output end; wherein, a first clock signal input end in the (2p-1) th scanning circuit is electrically connected with the first clock signal line, and a second clock signal input end in the (2p-1) th scanning circuit is electrically connected with the second clock signal line; a first clock signal input end in the 2 p-th scanning circuit is electrically connected with a second clock signal line, and a second clock signal input end in the 2 p-th scanning circuit is electrically connected with the first clock signal line; wherein p is more than or equal to 1;
the clock signal frequency is equal to the frequency of the first clock signal output by the first clock signal output end, and the clock signal frequency is equal to the frequency of the second clock signal output by the second clock signal output end.
Specifically, the output of the scan circuit is controlled by a first clock signal and a second clock signal, wherein the frequencies of the first clock signal and the second clock signal are equal, and a first pulse signal in the first clock signal and a first pulse signal in the second clock signal are not overlapped, wherein the first pulse signal is an effective signal of the pixel circuit, for example, when a thin film transistor included in the pixel circuit is a P-type transistor, the first pulse signal is a low-level pulse signal; when the thin film transistor included in the pixel circuit is an N-type transistor, the first pulse signal is a high-level pulse signal. The m scanning circuits can be controlled by a first clock signal and a second clock signal, but a first clock signal input end in the (2p-1) th scanning circuit is electrically connected with the first clock signal line, and a second clock signal input end in the (2p-1) th scanning circuit is electrically connected with the second clock signal line; a first clock signal input end in the 2p scanning circuit is electrically connected with a second clock signal line, and a second clock signal input end in the 2p scanning circuit is electrically connected with the first clock signal line, so that the scanning pulse signal output by the 2p scanning circuit can be ensured to be different from the scanning pulse signal output by the (2p-1) scanning circuit, and the progressive scanning of a pixel circuit in the display panel is completed.
It should be noted that, in the embodiment of the present invention, more clock signal ports and clock signal lines corresponding to the clock signal ports one to one may also be provided, and the embodiment is not specifically limited herein, for example, the driving chip may be configured to include a first clock signal output end, a second clock signal output end, a third clock signal output end and a fourth clock signal output end, where the clock signal output by the third clock signal output end is the same as the clock signal output by the second clock signal output end, and the clock signal output by the first clock signal output end and the clock signal output by the fourth clock signal output end are the same; the first shift register comprises a first clock signal input end and a second clock signal input end, wherein the first clock signal input end in the (2p-1) th scanning circuit is electrically connected with the first clock signal output end, and the second clock signal input end in the (2p-1) th scanning circuit is electrically connected with the second clock signal output end; a first clock signal input end in the 2 p-th scanning circuit is electrically connected with a third clock signal output end, and a second clock signal input end in the 2 p-th scanning circuit is electrically connected with a fourth clock signal output end; wherein p is more than or equal to 1.
In addition, the letters (including m, j, d, i, n, k, r, t, p, q, a, and b) in any of the above-described embodiments, i.e., in the following embodiments of the present invention must be an integer in addition to satisfying the conditions defined in the embodiments.
It should be noted that, in the above embodiments of the present invention, Data in fig. 6, fig. 7, fig. 9, and fig. 12 all represent Data signals.
An embodiment of the present invention further provides a driving method of a display panel, and fig. 13 is a flowchart of the driving method of the display panel provided in the embodiment of the present invention, where the driving method can be used to drive the display panel provided in any of the above embodiments of the present invention, and referring to fig. 13, the driving method of the display panel includes:
step 210, in a display mode with m times of basic refresh frequency, in each frame, controlling any one of m scanning circuits to output a scanning pulse signal; and a data line for outputting a data signal to the data line connected to the pixel circuit for controlling data writing by the scan pulse signal when the scan circuit outputs the scan pulse signal; wherein the basic refresh frequency is determined by the clock signal frequency of the driving chip.
According to the driving method of the display panel provided by the embodiment of the invention, in a display mode of m times of basic refresh frequency, any one scanning circuit in m scanning circuits is controlled to output a scanning pulse signal in each frame; and when the scanning circuit outputs the scanning pulse signal, outputting the data signal to the data line connected with the pixel circuit which controls data writing by the scanning pulse signal, so that only 1/m of the pixel circuits in the display panel write the data signal and emit light in each frame in a display mode of m times of the basic refresh frequency, and further, compared with the pixel circuit which works at the basic refresh frequency and writes the data signal, the corresponding data writing time of the pixel circuit does not change, correspondingly, the charging time of a capacitor in the pixel circuit does not change, and further the capacitor of the pixel circuit can be fully charged. In addition, in 1s, the total number of the data signals provided by the driving chip when the display panel works in the working mode corresponding to the basic refresh frequency is equal to the total number of the data signals provided by the driving chip when the display panel works in the working mode corresponding to the m times of the basic refresh frequency, so that the bandwidth of the driving chip can not be changed. Therefore, the display panel of the embodiment can improve the refresh frequency of the display panel on the basis of not changing the bandwidth of the driving chip and ensuring the charging time of the capacitor in the pixel circuit, thereby improving the problems of flicker and afterimage of the display panel.
On the basis of the foregoing technical solution, optionally, the step 210 may include:
providing a start signal to any one of m start signal terminals in each frame in a display mode in which the display panel is at m times the basic refresh frequency; when the scanning circuit outputs a scanning pulse signal, a data signal is output to a data line connected to a pixel circuit to which data writing is controlled by the scanning pulse signal.
Optionally, the driving method of the display panel further includes:
step 220, the display panel sequentially provides starting signals to m starting signal ends in m adjacent frames in a display mode of m times of basic refresh frequency, so that m scanning circuits output scanning pulse signals one by one in the m adjacent frames; and then m scanning circuits output scanning signals one by one in adjacent m frames, correspondingly, pixel circuits connected with all the scanning circuits in the m scanning circuits through scanning lines work alternately in the adjacent m frames, so that the total working time of all the pixel circuits in the display panel is consistent, and the service lives of the pixel circuits in the display panel can be relatively average.
It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.
Claims (10)
1. A display panel, comprising:
the pixel circuit comprises m scanning circuits, a plurality of scanning lines extending along a first direction and a plurality of data lines extending along a second direction, wherein each data line is connected with at least one column of pixel circuits, and the first direction and the second direction are intersected;
in the m scanning circuits, the jth scanning circuit is electrically connected with the mth + jth scanning line along the second direction, and the mth + jth scanning line is electrically connected with at least the mth + jth row of pixel circuits along the second direction, wherein m is more than or equal to 2, j is more than or equal to 1 and less than or equal to m, and d is more than or equal to 0;
the display panel also comprises a driving chip which is respectively and electrically connected with the m scanning circuits and the data lines; the driving chip is used for controlling any one scanning circuit in the m scanning circuits to output scanning pulse signals in each frame under a display mode of m times of basic refresh frequency; and a data line for outputting a data signal to a data line connected to a pixel circuit to which data is controlled to be written by the scan pulse signal when the scan circuit outputs the scan pulse signal; wherein the basic refresh frequency is determined by the clock signal frequency of the driving chip.
2. The display panel according to claim 1, wherein the driving chip comprises m start signal terminals, the display panel further comprises m start signal lines, the start signal terminals are electrically connected to the start signal lines in a one-to-one correspondence, and each start signal line is connected to one of the scanning circuits;
the driving chip is specifically configured to provide a start signal to any one of the m start signal terminals in each frame in a display mode in which the display panel is at m times the basic refresh frequency.
3. The display panel according to claim 2, wherein the driving chip is further configured to sequentially provide the start signals to the m start signal terminals in m adjacent frames in a display mode of the display panel at m times of the basic refresh frequency, so that the m scanning circuits output the scanning pulse signals one by one in the m adjacent frames.
4. The display panel according to claim 1,
the scanning circuit comprises a plurality of cascaded first shift registers, wherein in m scanning circuits, the ith stage first shift register of the jth scanning circuit is electrically connected with the (i-1) m + j scanning lines along the second direction, wherein m is more than or equal to 2, j is more than or equal to 1 and less than or equal to m, i is more than or equal to 1 and less than or equal to n, and n represents the total stage number of the first shift registers included in the scanning circuit where the first shift register is located.
5. The display panel according to claim 4, wherein the driver chip is further configured to sequentially control m/k of the m scan circuits to output scan pulse signals every frame in a display mode of k times the basic refresh frequency, wherein, of the m/k scan circuits, a scan pulse signal output by the first stage first shift register of the q +1 th scan circuit follows a scan pulse signal output by the first stage first shift register of the q-th scan circuit, where 1 ≦ q ≦ m/k-1; and the scanning pulse signal output by the second stage first shift register of the 1 st scanning circuit is behind the scanning pulse signal output by the first stage first shift register of the m/k scanning circuit; wherein k is more than or equal to 1 and less than m, and m/k is an integer.
6. The display panel according to claim 4, wherein the display panel further comprises m emission control driver circuits and a plurality of emission control signal lines, each of the emission control signal lines is connected to one row of the pixel circuits, the emission control driver circuit comprises a plurality of cascade-connected second shift registers, and of the m emission control driver circuits, an i-th stage second shift register of a j-th emission control driver circuit is electrically connected to an (i-1) m + j-th emission control signal line in the second direction, wherein m is greater than or equal to 2, 1 is greater than or equal to j is less than or equal to m, 1 is greater than or equal to i is less than or equal to n, and n represents a total number of second shift registers included in a scanning circuit in which the second shift register is located;
the driving chip is also used for controlling the second shift register of the light-emitting control driving circuit connected with the same pixel circuit as the scanning circuit outputting the scanning pulse signal to output the light-emitting control pulse signal step by step in a display mode that the display panel is m times of the basic refresh frequency;
wherein r is not less than 1 and not more than m after the r-th stage of the scan circuit that outputs the scan pulse signal outputs the light emission control pulse signal from the second shift register of the r-th stage of the light emission control drive circuit that outputs the light emission control pulse signal.
7. The display panel according to claim 4, wherein the display panel further comprises a light emission control driving circuit, the light emission control driving circuit comprises a plurality of cascaded second shift registers, an output end of the t-th stage of the second shift register is connected to the (t-1) m _ +1 to tm-th rows of the pixel circuits along the second direction, 1 ≦ t ≦ n, n represents a total number of second shift registers included in the light emission control driving circuit in which the second shift register is located; the driving chip is also used for controlling the second shift register of the light-emitting control driving circuit to output light-emitting control pulse signals step by step in a display mode that the display panel is m times of the basic refresh frequency;
the r-th stage of the light-emitting control drive circuit outputs a light-emitting control pulse signal after the r-th stage of the scanning circuit which outputs a scanning pulse signal) and the first shift register outputs a scanning pulse signal, wherein r is more than or equal to 1 and less than or equal to m.
8. The display panel according to claim 4, wherein the driver chip further comprises a first clock signal output terminal and a second clock signal output terminal, the display panel further comprises a first clock signal line and a second clock signal line, the first clock signal line is electrically connected to the first clock signal output terminal, and the second clock signal line is electrically connected to the second clock signal output terminal; the first shift register comprises a first clock signal input end and a second clock signal input end, wherein the first clock signal input end in the (2p-1) th scanning circuit is electrically connected with the first clock signal line, and the second clock signal input end in the (2p-1) th scanning circuit is electrically connected with the second clock signal line; a first clock signal input end in the 2 p-th scanning circuit is electrically connected with the second clock signal line, and a second clock signal input end in the 2 p-th scanning circuit is electrically connected with the first clock signal line; wherein p is more than or equal to 1;
the clock signal frequency is equal to the frequency of a first clock signal output by a first clock signal output end, and the clock signal frequency is equal to the frequency of a second clock signal output by a second clock signal output end.
9. The display panel according to any one of claims 1 to 8, wherein 2 ≦ m ≦ 4;
preferably, m is 2.
10. A driving method of a display panel for driving the display panel according to any one of claims 1 to 9, the driving method comprising:
in a display mode of m times of basic refresh frequency, in each frame, controlling any one of m scanning circuits to output a scanning pulse signal; and a data line for outputting a data signal to a data line connected to a pixel circuit to which data is controlled to be written by the scan pulse signal when the scan circuit outputs the scan pulse signal; wherein the basic refresh frequency is determined by the clock signal frequency of the driving chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010832943.6A CN111916018A (en) | 2020-08-18 | 2020-08-18 | Display panel and driving method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010832943.6A CN111916018A (en) | 2020-08-18 | 2020-08-18 | Display panel and driving method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN111916018A true CN111916018A (en) | 2020-11-10 |
Family
ID=73279719
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010832943.6A Pending CN111916018A (en) | 2020-08-18 | 2020-08-18 | Display panel and driving method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN111916018A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2023123035A1 (en) * | 2021-12-29 | 2023-07-06 | Boe Technology Group Co., Ltd. | Scan circuit, display apparatus, method of driving scan circuit |
| CN116682346A (en) * | 2023-06-21 | 2023-09-01 | 重庆惠科金渝光电科技有限公司 | Driving circuit, circuit driving method and display panel |
Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1766972A (en) * | 2004-10-28 | 2006-05-03 | 三星Sdi株式会社 | Scan driver, light emitting display using the same, and driving method thereof |
| CN101256735A (en) * | 2007-03-02 | 2008-09-03 | 三星Sdi株式会社 | Organic light emitting display and driving circuit thereof |
| US20140184484A1 (en) * | 2012-12-28 | 2014-07-03 | Semiconductor Energy Laboratory Co., Ltd. | Display device |
| CN105405385A (en) * | 2015-12-31 | 2016-03-16 | 京东方科技集团股份有限公司 | GOA (Gate Driver on Array) circuit, GOA (Gate Driver on Array) circuit scanning method, display panel and display apparatus |
| CN106652878A (en) * | 2017-02-24 | 2017-05-10 | 厦门天马微电子有限公司 | Display panel driving method and display panel |
| US20170206837A1 (en) * | 2016-01-18 | 2017-07-20 | Samsung Display Co., Ltd. | Display device and related operating method |
| CN107464539A (en) * | 2017-09-21 | 2017-12-12 | 京东方科技集团股份有限公司 | Shift register cell, drive device, display device and driving method |
| CN109064963A (en) * | 2018-09-05 | 2018-12-21 | 京东方科技集团股份有限公司 | Display device and driving method, shift register, driving circuit |
| CN110148373A (en) * | 2019-05-31 | 2019-08-20 | 上海天马有机发光显示技术有限公司 | A kind of driving method of display panel, display device and display panel |
-
2020
- 2020-08-18 CN CN202010832943.6A patent/CN111916018A/en active Pending
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1766972A (en) * | 2004-10-28 | 2006-05-03 | 三星Sdi株式会社 | Scan driver, light emitting display using the same, and driving method thereof |
| CN101256735A (en) * | 2007-03-02 | 2008-09-03 | 三星Sdi株式会社 | Organic light emitting display and driving circuit thereof |
| US20140184484A1 (en) * | 2012-12-28 | 2014-07-03 | Semiconductor Energy Laboratory Co., Ltd. | Display device |
| CN105405385A (en) * | 2015-12-31 | 2016-03-16 | 京东方科技集团股份有限公司 | GOA (Gate Driver on Array) circuit, GOA (Gate Driver on Array) circuit scanning method, display panel and display apparatus |
| US20170206837A1 (en) * | 2016-01-18 | 2017-07-20 | Samsung Display Co., Ltd. | Display device and related operating method |
| CN106652878A (en) * | 2017-02-24 | 2017-05-10 | 厦门天马微电子有限公司 | Display panel driving method and display panel |
| CN107464539A (en) * | 2017-09-21 | 2017-12-12 | 京东方科技集团股份有限公司 | Shift register cell, drive device, display device and driving method |
| CN109064963A (en) * | 2018-09-05 | 2018-12-21 | 京东方科技集团股份有限公司 | Display device and driving method, shift register, driving circuit |
| CN110148373A (en) * | 2019-05-31 | 2019-08-20 | 上海天马有机发光显示技术有限公司 | A kind of driving method of display panel, display device and display panel |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2023123035A1 (en) * | 2021-12-29 | 2023-07-06 | Boe Technology Group Co., Ltd. | Scan circuit, display apparatus, method of driving scan circuit |
| GB2622733A (en) * | 2021-12-29 | 2024-03-27 | Boe Technology Group Co Ltd | Scan circuit, display apparatus, method of driving scan circuit |
| CN116682346A (en) * | 2023-06-21 | 2023-09-01 | 重庆惠科金渝光电科技有限公司 | Driving circuit, circuit driving method and display panel |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN110148384B (en) | Array substrate, display panel and driving method of pixel driving circuit | |
| CN109461407B (en) | Organic light-emitting display panel and organic light-emitting display device | |
| CN108399895B (en) | Display panel, driving method thereof and display device | |
| US7825878B2 (en) | Active matrix display device | |
| CN112530351B (en) | Display panel driving method, display panel and display device | |
| US8497855B2 (en) | Scan driving apparatus and driving method for the same | |
| CN112562589B (en) | Pixel driving circuit, display panel and driving method of pixel driving circuit | |
| CN111179849B (en) | Control unit, control circuit, display device and control method thereof | |
| CN113689825A (en) | Driving circuit, driving method and display device | |
| US7161574B2 (en) | Liquid crystal display element driving method and liquid crystal display using the same | |
| CN111028781B (en) | Driving method and driving device of display panel and display equipment | |
| CN110322827B (en) | Digital driving method of display panel and display panel | |
| CN111916018A (en) | Display panel and driving method thereof | |
| CN115731839A (en) | Display driving circuit and display device | |
| CN115798382A (en) | Display driving circuit, control method thereof and display device | |
| CN113628588B (en) | Display driving module, display device and display method | |
| CN110800038B (en) | Display driving circuit, display device and display method based on time division data output | |
| KR101350622B1 (en) | Electro-Luminescence Pixel, Panel with the Pixels, and Device and Method of driving the Panel | |
| CN113971936B (en) | Display panel and driving method thereof | |
| CN110930926A (en) | Display panel driving method, display driving device and electronic equipment | |
| US11810514B2 (en) | Display panel, method for driving the same, and display apparatus | |
| US11328660B2 (en) | Display device and driving method thereof | |
| US10600363B2 (en) | Method for driving an array substrate having a plurality of light emitting components | |
| KR20220022526A (en) | Gate driver and display apparatus having the same | |
| CN114863875B (en) | Display panel, driving method thereof and display device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20201110 |
|
| RJ01 | Rejection of invention patent application after publication |