CN114863875B - Display panel, driving method thereof and display device - Google Patents
Display panel, driving method thereof and display device Download PDFInfo
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- CN114863875B CN114863875B CN202210577713.9A CN202210577713A CN114863875B CN 114863875 B CN114863875 B CN 114863875B CN 202210577713 A CN202210577713 A CN 202210577713A CN 114863875 B CN114863875 B CN 114863875B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3266—Details of drivers for scan electrodes
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/02—Improving the quality of display appearance
- G09G2320/0257—Reduction of after-image effects
Abstract
The invention discloses a display panel, a driving method thereof and a display device, wherein the display panel comprises: the array arrangement sub-pixels, the data line group and the control module are respectively and electrically connected with the 1 st data line to the M data line and used for controlling the 1 st data line to the M data line to transmit first data signals before row scanning, and the first data signals are used for resetting a first pole of the driving transistor and a second pole of the driving transistor. The first data signal is transmitted to the sub-pixels before the line scanning, so that the first pole of the driving transistor and the second pole of the driving transistor are reset at first when the line scanning starts, the problems of hysteresis effect and residual shadow caused by the driving transistor are avoided, and the display quality is improved.
Description
Technical Field
The invention relates to the technical field of display, in particular to a display panel, a driving method thereof and a display device.
Background
Among display technologies, an Organic Light-emitting diode (Organic Light-Emitting Display OLED) display panel has the advantages of self-luminescence, high luminous efficiency, short response time, low power consumption, wide viewing angle, rich colors, high brightness, wide use temperature range, capability of realizing flexible display and the like, and is considered as the display panel with the most development potential in the industry.
The sub-pixels of the organic light emitting diode display panel are provided with pixel driving circuits, the pixel driving circuits are provided with driving transistors for driving the organic light emitting diodes to emit light, the duration of the organic light emitting diode display panel is prolonged, or other factors may cause the threshold voltage of the driving transistors to deviate, and when the threshold voltage of the driving transistors deviates, the display effect of the organic light emitting diode display panel is reduced, so that the threshold voltage of the driving transistors needs to be reset when the organic light emitting diode display panel is used, and the display quality of the organic light emitting diode display panel is prevented from being reduced.
Accordingly, there is a need for a display panel capable of achieving threshold voltage reset, a driving method thereof, and a display device.
Disclosure of Invention
In view of the above, the present invention provides a display panel, a driving method thereof, and a display device for resetting a threshold voltage, so as to avoid the problem of hysteresis of a driving transistor.
In one aspect, the present invention provides a display panel including:
the array arrangement comprises sub-pixels, wherein the sub-pixels comprise pixel driving units, and the pixel driving units comprise driving transistors; the sub-pixels are arranged along a first direction to form pixel rows, the sub-pixels are arranged along a second direction to form pixel columns, and the first direction and the second direction are intersected; the pixel rows comprise row repeating groups which are arranged along the second direction, the row repeating groups comprise 1 st pixel row to M th pixel row which are sequentially arranged along the second direction, M is a positive integer, and M is more than or equal to 2;
The data line group is arranged corresponding to the sub-pixel columns and comprises 1 st to M data lines which are sequentially arranged along the first direction, the 1 st data line is electrically connected … with the sub-pixels of the 1 st pixel row, and the M data line is electrically connected with the sub-pixels of the M pixel row;
the control module is respectively and electrically connected with the 1 st data line to the M data line and is used for controlling the 1 st data line to the M data line to transmit a first data signal before line scanning, and the first data signal is used for resetting a first pole of the driving transistor and a second pole of the driving transistor.
In another aspect, the present invention also provides a driving method of a display panel, the display panel including:
the array arrangement comprises sub-pixels, wherein the sub-pixels comprise pixel driving units, and the pixel driving units comprise driving transistors; the sub-pixels are arranged along a first direction to form pixel rows, the sub-pixels are arranged along a second direction to form pixel columns, and the first direction and the second direction are intersected; the pixel rows comprise row repeating groups which are arranged along the second direction, the row repeating groups comprise 1 st pixel row to M th pixel row which are sequentially arranged along the second direction, M is a positive integer, and M is more than or equal to 2;
The data line group is arranged corresponding to the sub-pixel columns and comprises 1 st to M data lines which are sequentially arranged along the first direction, the 1 st data line is electrically connected … with the sub-pixels of the 1 st pixel row, and the M data line is electrically connected with the sub-pixels of the M pixel row;
the control module is respectively and electrically connected with the 1 st data line to the M data line;
the time for driving one row of the pixel rows comprises row scanning time and a first time period before the row scanning time, and in the first time period, the control module controls the 1 st data line to the M data line to transmit a first data signal, wherein the first data signal is used for resetting a first pole of the driving transistor and a second pole of the driving transistor.
In still another aspect, the present invention further provides a display device, including the display panel.
Compared with the prior art, the display panel provided by the invention has the advantages that at least the following beneficial effects are realized:
and the control module is respectively and electrically connected with the 1 st data line to the M data line and is used for controlling the 1 st data line to the M data line to transmit a first data signal before row scanning, and the first data signal is used for resetting the first pole of the driving transistor and the second pole of the driving transistor. The offset of the threshold voltage may be due to the formation of the gate bias of the driving transistor or due to the formation of the forward current in the driving transistor, and the first data signal is provided before the row scanning, so as to reset the first pole of the driving transistor and the second pole of the driving transistor at the beginning of the row scanning, thereby being beneficial to avoiding the problems of hysteresis effect and residual image of the driving transistor and improving the display quality.
Of course, it is not necessary for any one product embodying the invention to achieve all of the technical effects described above at the same time.
Other features of the present invention and its advantages will become apparent from the following detailed description of exemplary embodiments of the invention, which proceeds with reference to the accompanying drawings.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description, serve to explain the principles of the invention.
FIG. 1 is a schematic diagram of a prior art display panel;
FIG. 2 is a schematic diagram of a display panel according to the present invention;
FIG. 3 is a schematic diagram of a pixel driving unit according to the present invention;
FIG. 4 is a schematic structural diagram of another display panel according to the present invention;
FIG. 5 is a schematic view of a structure of another display panel according to the present invention;
FIG. 6 is a schematic diagram of another pixel driving unit according to the present invention;
FIG. 7 is a schematic diagram of a pixel driving unit according to another embodiment of the present invention;
FIG. 8 is a timing diagram of the pixel driving unit of FIG. 3;
FIG. 9 is a timing diagram of the pixel driving unit of FIG. 6;
FIG. 10 is another timing diagram of the pixel driving unit of FIG. 6;
Fig. 11 is a schematic structural diagram of a display device according to the present invention.
Detailed Description
Various exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be noted that: the relative arrangement of the components and steps, numerical expressions and numerical values set forth in these embodiments do not limit the scope of the present invention unless it is specifically stated otherwise.
The following description of at least one exemplary embodiment is merely exemplary in nature and is in no way intended to limit the invention, its application, or uses.
Techniques, methods, and apparatus known to one of ordinary skill in the relevant art may not be discussed in detail, but are intended to be part of the specification where appropriate.
In all examples shown and discussed herein, any specific values should be construed as merely illustrative, and not a limitation. Thus, other examples of exemplary embodiments may have different values.
It should be noted that: like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further discussion thereof is necessary in subsequent figures.
Referring to fig. 1, fig. 1 is a schematic structural diagram of a display panel in the prior art, in which a display panel 000 includes a plurality of scan lines (G1 '… GI') extending along a first direction X and arranged along a second direction Y, a plurality of data lines (D1 '… DJ') extending along the second direction Y and arranged along the first direction X, and the scan lines (G1 '… GI') and the data lines (D1 '… DJ') cross each other to define a pixel unit 01. In driving the display panel 000, the pixel units 01 are driven row by row, specifically, a scan signal is supplied to the scan line G1 'of the first row, the data line (D1' … DJ ') charges the pixel units 01 of the first row, then a scan signal is supplied to the scan line G2' of the second row, the data line (D1 '… DJ') charges the pixel units 01 of the second row, and so on. As the display panel 000 is advanced toward high resolution, the number of pixel units 01 increases, resulting in a shortened time for scanning one row of pixel units 01, and a reduced threshold voltage compensation time when driving the pixel units 01, resulting in insufficient threshold compensation and reduced display quality.
In view of the above, the present invention provides a display panel, a driving method thereof, and a display device for resetting a threshold voltage, so as to avoid a hysteresis problem of a driving transistor.
Referring to fig. 2 and 3, fig. 2 is a schematic structural diagram of a display panel according to the present invention, and fig. 3 is a schematic structural diagram of a pixel driving unit according to the present invention, where the display panel 100 includes:
the sub-pixels 02 are arranged in an array, the sub-pixels 02 comprise pixel driving units 03, and the pixel driving units 03 comprise driving transistors 04; the sub-pixels 02 are arranged along a first direction X to form a pixel row 05, the sub-pixels 02 are arranged along a second direction Y to form a pixel column 06, and the first direction X is intersected with the second direction Y; the pixel row 05 comprises a row repeating group 07 arranged along the second direction Y, the row repeating group 07 comprises 1 st pixel row L1 to M th pixel row LM which are sequentially arranged along the second direction Y, M is a positive integer, and M is more than or equal to 2;
the data line group 08 is arranged corresponding to the sub-pixel 02 column and comprises 1 st data lines D1 to M data lines DM which are sequentially arranged along the first direction X, wherein the 1 st data line D1 is electrically connected … with the sub-pixels 02 of the 1 st pixel row L1, and the M data line DM is electrically connected with the sub-pixels 02 of the M pixel row LM;
the control module 09 is electrically connected to the 1 st data line D1 to the M data line DM, and is used for controlling the 1 st data line D1 to the M data line DM to transmit a first data signal before row scanning, wherein the first data signal is used for resetting the first pole N1 of the driving transistor 04 and the second pole N2 of the driving transistor 04.
It should be noted that, in fig. 2, only the row repeating group 07 includes three pixel rows 05, the data line group 08 includes 3 data lines, the control module 09 is located at the lower edge of the sub-pixels 02 arranged in an array, specifically, the number of the sub-pixels 02, the array arrangement mode of the sub-pixels 02, the number of the row repeating group 07, the number of the data line group 08, and the number of the pixel rows 05 in the row repeating group 07, and the number of the data lines in the data line group 08 and the position of the control module 09 can be adjusted according to the actual requirement, which is not limited thereto.
Referring to fig. 2, the control module 09 is electrically connected to the 1 st data line D1 to the M data line DM, that is, the control module 09 can control the 1 st data line D1 to the M data line DM to simultaneously transmit data signals, and can also control the 1 st data line D1 to the M data line DM to transmit data signals in a time-sharing manner, because the pixel row 05 in the row repeating group 07 and the data line 08 in the data line group 08 are correspondingly arranged and connected, that is, data signals can be transmitted to the sub-pixels 02 in the row repeating group 07 simultaneously, or data signals can be transmitted to the sub-pixels 02 in the row repeating group 07 in a time-sharing manner, and the data signals include the first data signals.
Specifically, the line period H is the time required for scanning one line of pixel lines 05, and the calculation method of the line period H is calculated according to the following method:
H= (1 s/refresh frequency)/(number of rows of pixel rows+front and rear channels);
where H is a row period, s is a time unit, and in this embodiment, the row period H includes a row scanning time, which is a time for providing a signal to the gate driving circuit. The first case of the shift of the threshold voltage is formed due to the gate bias of the driving transistor 04, the second case is formed due to the forward current in the driving transistor 04, the control module 09 controls the 1 st data line D1 to the M data line DM to transmit the first data signal before the row scanning, the first data signal is transmitted to the first pole N1 (source) of the driving transistor 04 before the row scanning, when the row scanning starts, the first data signal can reset the first pole N1 of the driving transistor 04 and the second pole N2 of the driving transistor 04 immediately, the first pole N1 of the driving transistor 04 and the second pole N2 of the driving transistor 04 are the source and the drain of the driving transistor, that is, the threshold voltage is compensated for the second case, so that the problems of hysteresis effect, residual image and the like of the driving transistor 04 can be improved, noise point can be avoided when the picture is displayed, and the display effect is improved.
Compared with the prior art, the display panel 100 provided by the invention has the following beneficial effects:
The control module 09 is electrically connected to the 1 st data line D1 to the M data line DM, and is used for controlling the 1 st data line D1 to the M data line DM to transmit a first data signal before row scanning, wherein the first data signal is used for resetting the first pole N1 of the driving transistor 04 and the second pole N2 of the driving transistor 04. The offset of the threshold voltage may be due to the formation of the gate bias of the driving transistor 04 or due to the formation of the forward current in the driving transistor 04, and the first data signal is provided before the row scanning, so as to reset the first pole N1 of the driving transistor 04 and the second pole N2 of the driving transistor 04 at the beginning of the row scanning, thereby helping to avoid the problems of hysteresis effect and residual image of the driving transistor 04, and improving the display quality.
In some alternative embodiments, referring to fig. 4, fig. 4 is a schematic structural diagram of another display panel provided by the present invention, and the control module 09 includes:
the switch group 10 comprises 1 st switches K1 to M th switches KM, wherein the output end of the 1 st switch K1 is electrically connected … with the 1 st data line D1, and the output end of the M th switch KM is electrically connected with the M th data line DM;
The signal line group 11 includes 1 st signal line CKH1 to M signal line CKHM, where the 1 st signal line CKH1 is electrically connected to the control terminal of the 1 st switch K1 and the M signal line CKHM is electrically connected to the control terminal of the M switch KM.
Note that, in fig. 3, only the row repetition group 07 is illustrated as including two pixel rows 05, the data line group 08 includes two data lines, and the switch group 10 includes two switches, and of course, the number of pixel rows 05 in the row repetition group 07, the number of data lines in the data line group 08, and the number of switches in the switch group 10 may be adjusted as long as the number of pixel rows 05 in the row repetition group 07, the number of data lines in the data line group 08, and the number of switches in the switch group 10 are set correspondingly.
It can be understood that taking M >2 as an example, when the data line group 08 is controlled to simultaneously transmit data signals to the sub-pixels 02, the 1 st switch K1 to the M switch KM are simultaneously turned on, and the 1 st data line D1 to the M data line DM simultaneously transmit data signals to the sub-pixels 02; when the control data line group 08 transmits data signals to the sub-pixels 02 in the row repeating units in a time sharing mode, the 1 st switch K1 is turned on, the 1 st data line D1 transmits data signals to the 1 st pixel row L1, then the 2 nd switch is turned on, the 2 nd data line transmits data signals to the second pixel row 05, and so on. The switches in the switch group 10 are controlled to be simultaneously turned on or turned on in a time-sharing manner through the signal line group 11, so that the data line group 08 is controlled to simultaneously transmit data signals to the sub-pixels 02 in the row repeating units, or the data line group 08 is controlled to simultaneously transmit data signals to the sub-pixels 02 in the row repeating units in a time-sharing manner.
In some alternative embodiments, with continued reference to fig. 4, the display panel 100 provided in this embodiment further includes: a driving chip 12; the 1 st switch K1 to the M th switch KM are all first transistors M1, a first pole of each first transistor M1 is electrically connected with an N data line, N is an integer and is more than or equal to 1 and less than or equal to M, a grid electrode of each first transistor M1 is electrically connected with the N signal line, and a second pole of each first transistor M1 is electrically connected with the driving chip 12.
It should be noted that, in fig. 4, only the driving chip 12 is shown at the lower edge of the sub-pixels 02 arranged in an array, and in fig. 4, the second pole of the first transistor M1 is electrically connected to the driving chip 12 after being connected in parallel in a group of switch groups 10, but not limited thereto. The transistors may be divided into N-type transistors and P-type transistors according to the characteristics of the transistors, the active level of the N-type transistors is high, the active level of the P-type transistors is low, and only the first transistor M1 is illustrated as a P-type transistor in fig. 4, the first transistor M1 has a first electrode as a drain, and the second electrode of the first transistor M1 has a source, but the present invention is not limited thereto.
It will be appreciated that the driver chip 12 is arranged to provide a data signal to the driver transistor 04 during a row period H. When the gate of the first transistor M1 of the nth switch receives the enable signal transmitted by the nth signal line, the first transistor M1 of the nth switch is turned on, the nth data line receives the data signal provided by the driving chip 12, and the nth data line transmits the data signal to the corresponding sub-pixel 02, so as to realize precise control of data signal transmission.
In some alternative embodiments, referring to fig. 5, fig. 5 is a schematic structural diagram of another display panel provided by the present invention, and the display panel 100 provided by this embodiment further includes:
the first gate driving circuit 14 and the second gate driving circuit 15, the first gate driving circuit 14 includes a plurality of first shift registers Scan1, the second gate driving circuit 15 includes a plurality of second shift registers Scan2, and the row repeating group 07 is respectively and electrically connected to the first shift registers Scan1 and the second shift registers Scan2 in one-to-one correspondence.
It should be understood that only one row repeating group 07 is illustrated in fig. 5 as including two pixel rows 05, the first gate driving circuit 14 and the second gate driving circuit 15 are located on the same side of the sub-pixels 02 arranged in the array, however, it is also possible to provide that one row repeating group 07 includes a plurality of pixel rows 05, and the first gate driving circuit 14 and the second gate driving circuit 15 are located on two sides of the sub-pixels 02 arranged in the array, respectively, and the invention is not limited thereto.
Specifically, one line repetition group 07 is electrically connected to the first shift register Scan1 and the second shift register Scan2 in a one-to-one correspondence manner, that is, one line repetition group 07 is electrically connected to one first shift register Scan1 and one line repetition group 07 is electrically connected to one second shift register Scan2. In the display process, the first shift register Scan1 and the second shift register Scan2 provide different scanning driving signals, when the first shift register Scan1 and the second shift register Scan2 provide the scanning driving signals, the scanning driving signals can be simultaneously transmitted to M pixel rows 05, on the basis, the data signals are provided in a time sharing way in cooperation with the data line group 08, the row-by-row lighting of the M pixel rows 05 is realized, the first shift register Scan1 and the second shift register Scan2 are respectively in one-to-one correspondence with one row repetition group 07 and are electrically connected, the number of the first shift register Scan1 and the second shift register Scan2 required for driving the sub-pixels 02 is reduced, the wiring and the connection of the edges of the sub-pixels 02 arranged in an array are simplified, and the frame reduction is facilitated.
In some alternative embodiments, with continued reference to fig. 5, the display panel 100 provided in this embodiment further includes:
arranging a scanning line group 18 along a second direction Y, wherein the scanning line group 18 is arranged corresponding to the pixel row 05, the scanning line group 18 comprises a first scanning line 19 and a second scanning line 20 which are sequentially arranged along the second direction Y, one end of the first scanning line 19 is electrically connected with a first shift register Scan1, and the first scanning line 19 is electrically connected with all sub-pixels 02 of the pixel row 05; one end of the second Scan line 20 is electrically connected to the second shift register Scan2, and the second Scan line 20 is electrically connected to all the sub-pixels 02 of the pixel row 05.
It will be appreciated that in fig. 5, only one wiring manner of the Scan line group 18 is provided, but not limited thereto, since the first and second shift registers Scan1 and Scan2 provide different Scan driving signals, the sub-pixel 02 is electrically connected to the first shift register Scan1 through the first Scan line 19 and the second shift register Scan2 through the second Scan line 20, which is reasonable, and crosstalk between the Scan driving signals provided by the first shift register 16 and the Scan driving signals provided by the second shift register Scan2 is avoided.
In some alternative embodiments, with continued reference to fig. 2 and 3, the pixel driving unit 03 further comprises:
The first power supply voltage signal end PVDD is used for providing a first power supply voltage;
the second power supply voltage signal end PVEE is used for providing a second power supply voltage which is smaller than the first power supply voltage;
a driving transistor 04 and a light emitting element 21 connected in series to the first power voltage signal terminal PVDD and the second power voltage signal terminal PVEE;
a first initializing module 22, configured to initialize the gate of the driving transistor 04;
a data writing module 23 for writing the first data signal and the second data signal into the driving transistor 04, respectively;
the light-emitting control module 24 is used for controlling the light-emitting element 21 to emit light.
It should be noted that, in fig. 3, only one schematic structure of the pixel driving unit 03 is illustrated, and in some other embodiments of the present application, the schematic structure of the pixel driving circuit 03 may also be embodied as other structures, which is not specifically limited herein.
It is understood that the driving transistor 04 shown in fig. 3 is a P-type transistor, but not limited thereto, and the stage of driving the pixel driving unit 03 includes a data writing stage in which the pixel driving unit 03 is prepared for, for example, initializing and writing data to the gate of the driving transistor 04 in the pixel driving unit 03, and a stage of maintaining the light emitting element 21 to emit light. Before the data writing stage, the signal line group 11 provides a first data signal for resetting the first pole N1 of the driving transistor 04 and the second pole N2 of the driving transistor 04 in the pixel driving circuit, and initializes the gate of the driving transistor 04 in the pixel driving circuit during the data writing stage, and by compensating the threshold voltage twice, the problems of hysteresis effect, residual image and the like of the driving transistor 04 can be further improved, noise is avoided when a picture is displayed, and the display effect is improved.
In some alternative embodiments, referring to fig. 5 and 6, fig. 6 is a schematic diagram of another pixel driving unit structure provided by the present invention, the data writing module 23 includes a second transistor M2, a gate of the second transistor M2 is electrically connected to the second scan line 20, a first pole of the second transistor M2 is electrically connected to the nth data line, N is an integer and 1N M, and a second pole of the second transistor M2 is electrically connected to the first pole N1 of the driving transistor 04;
the light-emitting control module 24 includes a third transistor M3, a gate of the third transistor M3 is electrically connected to the light-emitting signal input terminal 13, a first pole of the third transistor M3 is electrically connected to a second pole N2 of the driving transistor 04, and a second pole of the third transistor M3 is electrically connected to an anode of the light-emitting element 21;
the first initialization module 22 includes a fourth transistor M4, a gate of the fourth transistor M4 is electrically connected to the first scan line 19, a first pole of the fourth transistor M4 is electrically connected to the first reference voltage signal terminal Vref1, and a second pole of the fourth transistor M4 is electrically connected to the gate of the driving transistor 04.
Note that, in fig. 6, only the second transistor M2, the third transistor M3, and the fourth transistor M4 are illustrated as P-type transistors, and only one transistor is included in the data writing module 23, the light emitting control module 24, and the first initialization module 22, but not limited thereto, the light emitting control module 24 may further include a seventh transistor M7, a first pole of the seventh transistor M7 is electrically connected to the first power voltage signal terminal PVDD, a second pole of the seventh transistor M7 is electrically connected to the first pole N1 of the driving transistor 04, a gate of the seventh transistor M7 is electrically connected to the light emitting signal input terminal 13, and of course, a storage capacitor 16 may also be included, one pole of the storage capacitor 16 is electrically connected to the first power voltage signal terminal PVDD, and another pole of the storage capacitor 16 is electrically connected to the gate of the driving transistor 04. Fig. 6 only illustrates that the first electrode of the second transistor M2 is the source and that the second electrode of the second transistor M2 is the drain; the first electrode of the third transistor M3 is the source, and the second electrode of the third transistor M3 is the drain; the first electrode of the fourth transistor M4 is the source, and the second electrode of the fourth transistor M4 is the drain; the first electrode of the seventh transistor M7 is the source, and the second electrode of the seventh transistor M7 is the drain.
It can be understood that, before the line scanning, the signal line group 11 controls the data line group 08 to simultaneously transmit the first data signal, the nth data line outputs the first data signal to the first pole of the second transistor M2, and when the line scanning starts, the second Scan line 20 transmits the enable signal provided by the second shift register Scan2, the gate of the second transistor M2 receives the second enable signal to be turned on, the first data signal is input to the first pole N1 of the driving transistor 04, resets the first pole N1 of the driving transistor 04 and the second pole N2 of the driving transistor 04, i.e. the line scanning starts, immediately resets the threshold voltage of the driving transistor 04, more fully compensates the threshold voltage of the driving transistor 04, avoids the hysteresis effect, causes the ghost and improves the display effect.
In some alternative embodiments, referring to fig. 5 and 7, fig. 7 is a schematic structural diagram of a pixel driving unit provided by the present invention, and the pixel driving unit 03 further includes:
the threshold compensation module 25 includes a fifth transistor M5, wherein a gate of the fifth transistor M5 is electrically connected to the second scan line 20, a first pole of the fifth transistor M5 is electrically connected to a second pole N2 of the driving transistor 04, and a second pole of the fifth transistor M5 is electrically connected to a gate of the driving transistor 04;
The second initialization module 26 includes a sixth transistor M6, a gate of the sixth transistor M6 is electrically connected to the first scan line 19, a first pole of the sixth transistor M6 is electrically connected to the input terminal of the second reference voltage signal Vref2, and a second pole of the sixth transistor M6 is electrically connected to the anode of the light emitting element 21.
It can be understood that the first electrode of the fifth transistor M5 is the source, and the second electrode of the fifth transistor M5 is the drain; the first electrode of the sixth transistor M6 is a drain electrode, the second electrode of the sixth transistor M6 is a source electrode, the threshold compensation module 25 in this embodiment can raise the potential of the gate electrode of the driving transistor 04, and has a better effect on maintaining the potential of the gate electrode of the driving transistor 04, especially when the pixel driving unit 03 includes the storage capacitor 16, the drain current of the storage capacitor 16 may cause the potential of the gate electrode of the driving transistor 04 to drop, the threshold compensation module 25 is configured to improve the potential drop of the gate electrode of the driving transistor 04 to cause the display panel 100 to flicker, and the second initialization module 26 is configured to reset the anode electrode of the light emitting element 21.
In some alternative embodiments, referring to fig. 2, 3 and 8, fig. 8 is a timing chart of the pixel driving unit in fig. 3, and the display panel 100 in this embodiment includes:
The sub-pixels 02 are arranged in an array, the sub-pixels 02 comprise pixel driving units 03, and the pixel driving units 03 comprise driving transistors 04; the sub-pixels 02 are arranged along a first direction X to form a pixel row 05, the sub-pixels 02 are arranged along a second direction Y to form a pixel column 06, and the first direction X is intersected with the second direction Y; the pixel row 05 comprises a row repeating group 07 arranged along the second direction Y, the row repeating group 07 comprises 1 st pixel row L1 to M th pixel row LM which are sequentially arranged along the second direction Y, M is a positive integer, and M is more than or equal to 2;
the data line group 08 is arranged corresponding to the sub-pixel 02 column and comprises 1 st data lines D1 to M data lines DM which are sequentially arranged along the first direction X, wherein the 1 st data line D1 is electrically connected … with the sub-pixels 02 of the 1 st pixel row L1, and the M data line DM is electrically connected with the sub-pixels 02 of the M pixel row LM;
the control module 09 is electrically connected with the 1 st data line D1 to the M data line DM respectively;
the driving time of the pixel row 05 includes a row scanning time and a first period T1 before the row scanning time, and the control module 09 controls the 1 st data line D1 to the M data line DM to transmit a first data signal for resetting the first pole N1 of the driving transistor 04 and the second pole N2 of the driving transistor 04 during the first period T1.
It can be understood that the structure of the display panel 100 in this embodiment has been described in detail above, and not described in detail herein, the time for driving one row of pixel rows 05 is one row period H, the row scanning time is the time for providing signals for the gate driving circuit, and before the gate driving circuit provides signals, the control module 09 controls the 1 st data line D1 to the M data line DM to transmit the first data signal, so that when the row scanning time is on, i.e. when the scanning line transmits signals, the first data signal is transmitted to the driving transistor 04 immediately, and the first pole N1 of the driving transistor 04 and the second pole N2 of the driving transistor 04 are reset, thereby realizing the threshold voltage compensation of the driving transistor 04, avoiding the occurrence of hysteresis effect and affecting the display effect.
In some alternative embodiments, with continued reference to fig. 3, 5, and 8, the display panel 100 further includes:
a driving chip 12;
the switch group 10 comprises 1 st switches K1 to M th switches KM, wherein the output end of the 1 st switch K1 is electrically connected … with the 1 st data line D1, and the output end of the M th switch KM is electrically connected with the M th data line DM;
the signal line group 11 includes 1 st signal line CKH1 to M signal line CKHM, the 1 st signal line CKH1 is electrically connected … to the control end of the 1 st switch K1, and the M signal line CKHM is electrically connected to the control end of the M switch KM;
The 1 st switch K1 to the M th switch KM are all first transistors M1, a first pole of each first transistor M1 is electrically connected with an N data line, N is an integer and is more than or equal to 1 and less than or equal to M, a grid electrode of each first transistor M1 is electrically connected with the N signal line, and a second pole of each first transistor M1 is electrically connected with the driving chip 12;
in the first period T1, the 1 st signal line CKH1 to the M th signal line CKHM simultaneously inputs a first enable signal to the gate of the corresponding first transistor M1, so that the 1 st switch K1 to the M th switch KM are simultaneously turned on in response to the first enable signal;
the 1 st to M-th data lines D1 to DM simultaneously respond to and transmit the first data signal supplied from the driving chip 12, and correspondingly write the first data signal into the data writing module 23.
It will be appreciated that the driving chip 12 provides the data line group 08 with the data signal, the data signal includes the first data signal and the second data signal, and when the 1 st signal line CKH1 to the M signal line CKHM simultaneously provide the 1 st switch K1 to the M switch with the first enable signal, the gate of the first transistor M1 is turned on corresponding to the first enable signal, the first data signal can be simultaneously transmitted to the data writing module 23, and the transmission of the data signal can be precisely controlled.
In some alternative embodiments, referring to fig. 5, 6 and 9, fig. 9 is a timing chart of the pixel driving unit in fig. 6, and the display panel 100 in this embodiment further includes:
The second gate driving circuit 15, the second gate driving circuit 15 includes a plurality of second shift registers Scan2, and the row repeating group 07 is in one-to-one correspondence with and electrically connected to the second shift registers Scan 2;
the second scanning line 20, the second scanning line 20 is set up corresponding to pixel row 05, one end of the second scanning line 20 is connected with the second shift register Scan2 electrically, and the second scanning line 20 is connected with all sub-pixels 02 of the pixel row 05 electrically;
the pixel driving unit 03 includes:
the data writing module 23, the data writing module 23 includes a second transistor M2, the gate of the second transistor M2 is electrically connected to the second scan line 20, the first pole of the second transistor M2 is electrically connected to the nth data line, N is an integer and 1N is not less than M, and the second pole of the second transistor M2 is electrically connected to the first pole N1 of the driving transistor 04;
the line scanning time includes a second time period T2, a third time period T3, and a fourth time period T4;
in the second period T2, the data writing module 23 is turned on in response to the second enable signal of the second scan line 20, writes the first data signal into the first pole N1 of the driving transistor 04 and the second pole N2 of the driving transistor 04, and resets the first pole N1 of the driving transistor 04 and the second pole N2 of the driving transistor 04;
In the third period T3, the 1 st to M-th signal lines CKH1 to CKHM sequentially input a third enable signal to the gate of the corresponding first transistor M1, so that the 1 st to M-th switches K1 to KM are sequentially turned on in response to the third enable signal;
the 1 st data line D1 to the M-th data line DM sequentially respond to and transmit the second data signal provided by the driving chip 12, and correspondingly write the second data signal into the data writing module 23;
in the fourth period T4, the data writing module 23 is turned on in response to the fourth enable signal of the second scan line 20, writes the second data signal to the corresponding driving transistor 04, and sequentially emits light for the 1 st to M th pixel rows L1 to LM.
It is understood that only the data writing module 23 is illustrated in fig. 6 as including a second transistor M2, the gate of the second transistor M2 is electrically connected to the second scan line 20, the first electrode of the second transistor M2 is electrically connected to the nth data line, N is an integer and 1+.n+.m, and the second electrode of the second transistor M2 is electrically connected to the first electrode N1 of the driving transistor 04; the light-emitting control module 24 includes a third transistor M3, a gate of the third transistor M3 is electrically connected to the light-emitting signal input terminal 13, a first pole of the third transistor M3 is electrically connected to a second pole N2 of the driving transistor 04, and a second pole of the third transistor M3 is electrically connected to an anode of the light-emitting element 21; the first initialization module 22 includes a fourth transistor M4, a gate of the fourth transistor M4 is electrically connected to the first scan line 19, a first pole of the fourth transistor M4 is electrically connected to the first reference voltage signal terminal Vref1, and a second pole of the fourth transistor M4 is electrically connected to the gate of the driving transistor 04. The first power supply voltage signal end PVDD is used for providing a first power supply voltage; a second power voltage signal terminal PVEE for providing a second power voltage, a light emitting signal input terminal 13 for providing a light emitting signal, and a display panel 100 further comprising light emitting signal lines, only the row repetition group 07 is illustrated in fig. 5 as comprising two pixel rows 05, so the light emitting signal lines comprise a first light emitting signal line E1 and a second light emitting signal line E2, the first light emitting signal line E1 is electrically connected to all sub-pixels 02 of the 1 st pixel row L1, in particular, the light emitting signal input terminal 13 of the pixel driving unit 03 of the sub-pixel 02 is electrically connected, and the first light emitting signal line E1 transmits the first light emitting signal EMIT1; the second light emitting signal line E2 is electrically connected to all the sub-pixels 02 of the 2 nd pixel row L2, specifically, the light emitting signal input terminal 13 of the pixel driving unit 03 of the sub-pixel 02, and the second light emitting signal line E2 transmits the second light emitting signal EMIT2. Referring to fig. 9, in the first row period H, the first emission signal EMIT1 is at a low level, the low level is at an active level, the second emission signal EMIT2 is at a high level, and in the first row period H, the 1 st pixel row L1 is lit. In the second row period H, the first emission signal EMIT1 is at a high level, the second emission signal EMIT2 is at a low level, and in the second row period H, the 2 nd pixel row L2 is lit. Specifically, taking the first row period H as an example, in the second period T2, the second transistor M2 receives the second enable signal transmitted by the second scan line 20, and is turned on, and transmits the first data signal transmitted to the first pole N1 of the second transistor M2 to the first pole N1 of the driving transistor 04 and the second pole N2 of the driving transistor 04, so as to reset the first pole N1 of the driving transistor 04 and the second pole N2 of the driving transistor 04; in the third period T3, since the first shift register Scan1 and the second shift register Scan2 Scan M pixel rows 05 at the same time, it is necessary to sequentially transmit the second data signals to the 1 st data line D1 to the M data line DM for data writing, so that the square wave signals have regularity, specifically, the 1 st signal line CKH1 to the M signal line CKHM sequentially provide the third enable signal, and the first transistor M1 in the 1 st switch K1 to the M switch KM sequentially receives the third enable signal and is sequentially turned on; in the fourth period T4, the second transistor M2 receives the fourth enable signal transmitted from the second scan line 20 and is turned on, the second data signal transmitted to the first electrode of the second transistor M2 is transmitted and written to the gate of the driving transistor 04, the light-emitting signal input terminal 13 of the pixel driving unit 03 of the sub-pixel 02 in the 1 st pixel row L1 receives the first light-emitting signal EMIT1, and in the fourth period T4, the first power voltage signal terminal PVDD is turned on to the second power voltage signal terminal PVEE, and the current flows through the light-emitting element 21 to light the light-emitting element 21.
In some alternative embodiments, with continued reference to fig. 5, 6 and 9, the display panel 100 in this embodiment includes:
the first gate driving circuit 14, the first gate driving circuit 14 includes a plurality of first shift registers Scan1, and the row repeating group 07 is in one-to-one correspondence with and electrically connected to the first shift registers Scan 1;
the first scanning line 19 is arranged corresponding to the pixel row 05, one end of the first scanning line 19 is electrically connected with the first shift register Scan1, and the first scanning line 19 is electrically connected with all the sub-pixels 02 of the pixel row 05;
the pixel driving circuit further includes:
a light emitting element 21;
the first initialization module 22 includes a fourth transistor M4, a gate of the fourth transistor M4 is electrically connected to the first scan line 19, a first pole of the fourth transistor M4 is electrically connected to the first reference voltage signal terminal Vref1, and a second pole of the fourth transistor M4 is electrically connected to the gate of the driving transistor 04;
the second initialization module 26 includes a sixth transistor M6, a gate of the sixth transistor M6 is electrically connected to the first scan line 19, a first pole of the sixth transistor M6 is electrically connected to the second reference voltage signal terminal Vref2, and a second pole of the sixth transistor M6 is electrically connected to the anode of the light emitting element 21;
in the third period T3, further including:
The first initialization module 22 is turned on in response to the fifth enable signal of the first scan line 19, and transmits the first reference voltage Vref1 signal to the gate of the driving transistor 04; the second initialization module 26 is turned on in response to the sixth enable signal of the first scan line 19, and transmits a second reference voltage signal to the anode of the light emitting element 21.
It can be appreciated that, during the third period T3, the first initialization module 22 is turned on in response to the fifth enable signal transmitted by the first scan line 19, and transmits the first reference voltage signal to the gate of the driving transistor 04; the second initialization module 26 is turned on in response to the sixth enable signal transmitted by the first scan line 19, and transmits the second reference voltage signal to the anode of the light emitting element 21, and since the first pole N1 of the driving transistor 04 and the second pole N2 of the driving transistor 04 have been reset in the second period T2, and then the gate of the driving transistor 04 is reset in the third period T3, the threshold voltage of the driving transistor 04 is ensured to be completely compensated, so that the problems of hysteresis effect and residual image caused by the driving transistor 04 are avoided, and the display quality is improved.
In some alternative embodiments, referring to fig. 5, 6 and 10, fig. 10 is another timing diagram of the pixel driving unit in fig. 6, and the data line group 08 is suspended during the second period T2 and the fourth period T4.
It can be understood that the data line group 08 is suspended in the second time period T2 and the fourth time period T4, so that crosstalk of the data signals is avoided, and the display effect is better.
Based on the same inventive concept, the present application further provides a display device, and fig. 11 is a schematic diagram of a display device provided in an embodiment of the present application, where the display device 200 includes the display panel 100 provided in any of the foregoing embodiments of the present application. When the display device 200 in the present application includes the display panel 100 provided in any of the above embodiments, it is beneficial to avoid the hysteresis effect of the driving transistor 04 of the pixel driving unit 03. It should be noted that, in the embodiments of the display panel 100 provided in the embodiments of the present application, reference may be made to the embodiments of the display panel 100 described above, and the repetition is omitted. The display device 200 provided in the present application may be: any product or component with realistic functions such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like.
According to the embodiment, the display panel provided by the invention has at least the following beneficial effects:
and the control module is respectively and electrically connected with the 1 st data line to the M data line and is used for controlling the 1 st data line to the M data line to transmit a first data signal before row scanning, and the first data signal is used for resetting the first pole of the driving transistor and the second pole of the driving transistor. The offset of the threshold voltage may be due to the formation of the gate bias of the driving transistor or due to the formation of the forward current in the driving transistor, and the first data signal is provided before the row scanning, so as to reset the first pole of the driving transistor and the second pole of the driving transistor at the beginning of the row scanning, thereby being beneficial to avoiding the problems of hysteresis effect and residual image of the driving transistor and improving the display quality.
While certain specific embodiments of the invention have been described in detail by way of example, it will be appreciated by those skilled in the art that the above examples are for illustration only and are not intended to limit the scope of the invention. It will be appreciated by those skilled in the art that modifications may be made to the above embodiments without departing from the scope and spirit of the invention. The scope of the invention is defined by the appended claims.
Claims (14)
1. A display panel, comprising:
the array arrangement comprises sub-pixels, wherein the sub-pixels comprise pixel driving units, and the pixel driving units comprise driving transistors; the sub-pixels are arranged along a first direction to form pixel rows, the sub-pixels are arranged along a second direction to form pixel columns, and the first direction and the second direction are intersected; the pixel rows comprise row repeating groups which are arranged along the second direction, the row repeating groups comprise 1 st pixel row to M th pixel row which are sequentially arranged along the second direction, M is a positive integer, and M is more than or equal to 2;
the data line group is arranged corresponding to the sub-pixel columns and comprises 1 st to Mth data lines sequentially arranged along the first direction, wherein the 1 st data line is electrically connected … with the sub-pixels of the 1 st pixel row, the M+1st pixel row and the 2M+1st pixel row …, and the Mth data line is electrically connected with the sub-pixels of the Mth pixel row, the 2 nd pixel row and the 3 rd pixel row …;
The control module is respectively and electrically connected with the 1 st data line to the M data line and is used for controlling the 1 st data line to the M data line to transmit a first data signal before line scanning, and the first data signal is used for resetting a first pole of the driving transistor and a second pole of the driving transistor.
2. The display panel of claim 1, wherein the control module comprises:
the switch group comprises a 1 st switch to an M th switch, the output end of the 1 st switch is electrically connected with the 1 st data line …, and the output end of the M th switch is electrically connected with the M th data line;
the signal line group comprises 1 st signal line to M signal line, the 1 st signal line is electrically connected … with the control end of the 1 st switch, and the M signal line is electrically connected with the control end of the M switch.
3. The display panel of claim 2, further comprising: a driving chip; the 1 st switch to the M switch are all first transistors, a first pole of each first transistor is electrically connected with an N data line, N is an integer and is more than or equal to 1 and less than or equal to M, a grid electrode of each first transistor is electrically connected with the N signal line, and a second pole of each first transistor is electrically connected with the driving chip.
4. The display panel of claim 1, further comprising:
the first grid driving circuit comprises a plurality of first shift registers, the second grid driving circuit comprises a plurality of second shift registers, and the row repeated groups are respectively in one-to-one correspondence with and electrically connected with the first shift registers and the second shift registers.
5. The display panel of claim 4, further comprising:
arranging a scanning line group along the second direction, wherein the scanning line group is arranged corresponding to the pixel row, the scanning line group comprises a first scanning line and a second scanning line which are sequentially arranged along the second direction, one end of the first scanning line is electrically connected with the first shift register, and the first scanning line is electrically connected with all the sub-pixels of the pixel row; one end of the second scanning line is electrically connected with the second shift register, and the second scanning line is electrically connected with all the sub-pixels of the pixel row.
6. The display panel of claim 5, wherein the pixel driving unit further comprises:
the first power supply voltage signal end is used for providing a first power supply voltage;
The second power supply voltage signal end is used for providing a second power supply voltage which is smaller than the first power supply voltage;
the driving transistor and the light-emitting element are connected in series with the first power supply voltage signal end and the second power supply voltage signal end;
a first initializing module, configured to initialize a gate of the driving transistor;
a data writing module for writing the first data signal and the second data signal into the driving transistor, respectively;
and the light-emitting control module is used for controlling the light-emitting element to emit light.
7. The display panel according to claim 6, wherein the data writing module includes a second transistor, a gate of the second transistor is electrically connected to the second scan line, a first electrode of the second transistor is electrically connected to an nth data line, N is an integer and 1+.n+.m, and a second electrode of the second transistor is electrically connected to the first electrode of the driving transistor;
the light-emitting control module comprises a third transistor, wherein the grid electrode of the third transistor is electrically connected with the light-emitting signal input end, the first electrode of the third transistor is electrically connected with the second electrode of the driving transistor, and the second electrode of the third transistor is electrically connected with the anode of the light-emitting element;
The first initialization module comprises a fourth transistor, wherein the grid electrode of the fourth transistor is electrically connected with the first scanning line, the first pole of the fourth transistor is electrically connected with the first reference voltage signal end, and the second pole of the fourth transistor is electrically connected with the grid electrode of the driving transistor.
8. The display panel of claim 6, wherein the pixel driving unit further comprises:
the threshold compensation module comprises a fifth transistor, wherein the grid electrode of the fifth transistor is electrically connected with the second scanning line, the first pole of the fifth transistor is electrically connected with the second pole of the driving transistor, and the second pole of the fifth transistor is electrically connected with the grid electrode of the driving transistor;
the second initialization module comprises a sixth transistor, wherein the grid electrode of the sixth transistor is electrically connected with the first scanning line, the first electrode of the sixth transistor is electrically connected with the second reference voltage signal end, and the second electrode of the sixth transistor is electrically connected with the anode of the light-emitting element.
9. A driving method of a display panel, the display panel comprising:
the array arrangement comprises sub-pixels, wherein the sub-pixels comprise pixel driving units, and the pixel driving units comprise driving transistors; the sub-pixels are arranged along a first direction to form pixel rows, the sub-pixels are arranged along a second direction to form pixel columns, and the first direction and the second direction are intersected; the pixel rows comprise row repeating groups which are arranged along the second direction, the row repeating groups comprise 1 st pixel row to M th pixel row which are sequentially arranged along the second direction, M is a positive integer, and M is more than or equal to 2;
The data line group is arranged corresponding to the sub-pixel columns and comprises 1 st to Mth data lines sequentially arranged along the first direction, wherein the 1 st data line is electrically connected … with the sub-pixels of the 1 st pixel row, the M+1st pixel row and the 2M+1st pixel row …, and the Mth data line is electrically connected with the sub-pixels of the Mth pixel row, the 2 nd pixel row and the 3 rd pixel row …;
the control module is respectively and electrically connected with the 1 st data line to the M data line;
the time for driving one row of the pixel rows comprises row scanning time and a first time period before the row scanning time, and in the first time period, the control module controls the 1 st data line to the M data line to transmit a first data signal, wherein the first data signal is used for resetting a first pole of the driving transistor and a second pole of the driving transistor.
10. The driving method of a display panel according to claim 9, wherein the display panel further comprises:
a driving chip;
the switch group comprises a 1 st switch to an M th switch, the output end of the 1 st switch is electrically connected with the 1 st data line …, and the output end of the M th switch is electrically connected with the M th data line;
The signal line group comprises 1 st signal lines to M signal lines, the 1 st signal lines are electrically connected … with the control end of the 1 st switch, and the M signal lines are electrically connected with the control end of the M switch;
the 1 st switch to the M switch are all first transistors, a first pole of each first transistor is electrically connected with an N data line, N is an integer and is more than or equal to 1 and less than or equal to M, a grid electrode of each first transistor is electrically connected with the N signal line, and a second pole of each first transistor is electrically connected with the driving chip;
the pixel driving unit comprises a data writing module;
in the first period, the method further comprises the steps that the 1 st signal line to the M th signal line simultaneously input a first enabling signal to the grid electrode of the corresponding first transistor, and the 1 st switch to the M th switch are simultaneously started in response to the first enabling signal;
and the 1 st data line to the M data line simultaneously respond to the first data signal provided by the driving chip and transmit the first data signal, and correspondingly write the first data signal into the data writing module.
11. The driving method of a display panel according to claim 10, wherein the display panel further comprises:
The second grid driving circuit comprises a plurality of second shift registers, and the row repeated groups are in one-to-one correspondence with the second shift registers and are electrically connected;
the second scanning line is arranged corresponding to the pixel row, one end of the second scanning line is electrically connected with the second shift register, and the second scanning line is electrically connected with all the sub-pixels of the pixel row;
the data writing module comprises a second transistor, the grid electrode of the second transistor is electrically connected with the second scanning line, the first electrode of the second transistor is electrically connected with the N data line, N is an integer and is more than or equal to 1 and less than or equal to M, and the second electrode of the second transistor is electrically connected with the first electrode of the driving transistor;
the line scanning time comprises a second time period, a third time period and a fourth time period;
in the second period, the data writing module is turned on in response to a second enable signal of the second scanning line, writes the first data signal into a first pole of the driving transistor and a second pole of the driving transistor, and resets the first pole of the driving transistor and the second pole of the driving transistor;
In the third period, the 1 st signal line to the M th signal line sequentially input a third enable signal to the corresponding gate of the first transistor, so that the 1 st switch to the M th switch are sequentially turned on in response to the third enable signal;
the 1 st data line to the M data line sequentially respond to a second data signal provided by the driving chip and transmit the second data signal, and the second data signal is correspondingly written into the data writing module;
in the fourth period, the data writing module is turned on in response to a fourth enable signal of the second scan line, writes the second data signal into the corresponding driving transistor, and sequentially emits light from the 1 st pixel row to the M th pixel row.
12. The driving method of a display panel according to claim 11, wherein the display panel comprises:
the first grid driving circuit comprises a plurality of first shift registers, and the row repeated groups are in one-to-one correspondence with the first shift registers and are electrically connected;
the first scanning line is arranged corresponding to the pixel row, one end of the first scanning line is electrically connected with the first shift register, and the first scanning line is electrically connected with all the sub-pixels of the pixel row;
The pixel driving unit further includes:
a light emitting element;
the first initialization module comprises a fourth transistor, wherein the grid electrode of the fourth transistor is electrically connected with the first scanning line, the first pole of the fourth transistor is electrically connected with the first reference voltage signal end, and the second pole of the fourth transistor is electrically connected with the grid electrode of the driving transistor;
the second initialization module comprises a sixth transistor, wherein the grid electrode of the sixth transistor is electrically connected with the first scanning line, the first electrode of the sixth transistor is electrically connected with the second reference voltage signal end, and the second electrode of the sixth transistor is electrically connected with the anode of the light-emitting element;
in the third period of time, further comprising:
the first initialization module is conducted in response to a fifth enabling signal of the first scanning line and transmits a first reference voltage signal to the grid electrode of the driving transistor; the second initialization module is turned on in response to a sixth enable signal of the first scan line, and transmits a second reference voltage signal to an anode of the light emitting element.
13. The driving method of a display panel according to claim 11, wherein the data line group is suspended during the second period and the fourth period.
14. A display device comprising a display panel according to any one of the preceding claims 1-8.
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