CN114038429A - Display panel, driving method and display device - Google Patents

Display panel, driving method and display device Download PDF

Info

Publication number
CN114038429A
CN114038429A CN202111406863.5A CN202111406863A CN114038429A CN 114038429 A CN114038429 A CN 114038429A CN 202111406863 A CN202111406863 A CN 202111406863A CN 114038429 A CN114038429 A CN 114038429A
Authority
CN
China
Prior art keywords
circuit
signal line
sub
electrically connected
transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN202111406863.5A
Other languages
Chinese (zh)
Other versions
CN114038429B (en
Inventor
王刚
张锴
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by BOE Technology Group Co Ltd, Chengdu BOE Optoelectronics Technology Co Ltd filed Critical BOE Technology Group Co Ltd
Priority to CN202111406863.5A priority Critical patent/CN114038429B/en
Publication of CN114038429A publication Critical patent/CN114038429A/en
Application granted granted Critical
Publication of CN114038429B publication Critical patent/CN114038429B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0247—Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0257—Reduction of after-image effects

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Control Of El Displays (AREA)

Abstract

The invention provides a display panel, a driving method and a display device, which are applied to the field of display and aim to solve the problems of short-term afterimage and flicker of a display picture of the display panel or the display device. The display panel comprises a refreshing phase and at least one holding phase in one scanning period. The display panel includes: the device comprises a plurality of sub-pixels arranged in an array, a plurality of data lines and a plurality of conversion modules, wherein each data line is electrically connected with one column of sub-pixels; each conversion module is electrically connected with one data line. Each sub-pixel includes a pixel circuit and a light emitting device electrically connected; the conversion module is configured to transmit a data signal to the data line during a refresh phase and a constant voltage signal to the data line during a hold phase.

Description

Display panel, driving method and display device
Technical Field
The invention relates to the technical field of display, in particular to a display panel, a driving method and a display device.
Background
The application of Active-matrix organic light-Emitting diodes (AMOLEDs) in the display field is becoming more and more extensive, and the quality requirement of the screen of the AMOLED display device is becoming higher and higher. Due to some inherent quality defects, the AMOLED display device has the problems of short-term afterimage and flicker of the picture caused by pixel response delay.
Particularly, in a display device driven at a low frequency, the above-mentioned problem and drawback are more obvious, and therefore, a method capable of improving the pixel response delay and improving the display quality is required.
Disclosure of Invention
In order to overcome the defects in the prior art, the invention provides a display panel, a driving method and a display device, so as to improve the short-term afterimage and flicker phenomena of the display device.
In order to achieve the purpose, the invention adopts the following technical scheme:
one aspect provides a display panel including a refresh phase and at least one hold phase within one scan cycle of the display panel. The display panel includes: the device comprises a plurality of sub-pixels arranged in an array, a plurality of data lines and a plurality of conversion modules. Each data line is electrically connected with one column of sub-pixels; each conversion module is electrically connected with one data line. Each sub-pixel includes a pixel circuit and a light emitting device electrically connected; the conversion module is configured to transmit a data signal to the data line during a refresh phase and a constant voltage signal to the data line during a hold phase.
The display panel provided by the invention is provided with the conversion module, a constant voltage signal can be transmitted to the data line in a holding stage, and then the constant voltage signal is transmitted to the pixel circuit of the sub-pixel, electrons or holes in the transistor generate a bias state under the action of the data signal or other stress, and the constant voltage signal can carry out bias stress on the transistor of the pixel circuit, so that the electrons or holes in some transistors of different pixel circuits form a uniform bias state, and thus, the brightness difference caused by different bias states among different sub-pixels is eliminated, and the problems of afterimage and flicker of the display panel are further improved.
In some embodiments, the display panel further comprises: a plurality of source driving signal lines configured to transmit data signals and constant voltage signal lines; the constant voltage signal line is configured to transmit a constant voltage signal; the conversion module is electrically connected with a source driving signal line and a constant voltage signal line.
In some embodiments, the conversion module includes a first switch and a second switch, the first switch being electrically connected between the source driving signal line and the data line; the second switch is electrically connected between the constant voltage signal line and the data line.
In some embodiments, the first switch is configured to turn on the source driving signal line and the data line under control of the first switching signal;
the second switch is configured to turn on the constant voltage signal line and the data line under control of a second switching signal.
In some embodiments, the first switch and the second switch are thin film transistors.
In some embodiments, the display panel further comprises a first switch control bus and a second switch control bus. Wherein the first switch control bus is electrically connected with the first switch, the first switch control bus being configured to provide a first switching signal; a second switch control bus is electrically connected with the second switch, the second switch control bus configured to provide a second switch signal.
In some embodiments, the display panel includes a display area and a peripheral area disposed at least on one side of the display area; the plurality of conversion modules, the plurality of source driving signal lines, the constant voltage signal line, the first switch control bus and the second switch control bus are located in the peripheral area.
In some embodiments, the peripheral region includes a bending region and a first non-bending region, wherein the first non-bending region is located on a side of the bending region away from the display region, the first non-bending region can be bent to a non-light-emitting side of the display panel through the bending region, and the plurality of conversion modules are located in the first non-bending region.
In some embodiments, a pixel circuit includes: a reset sub-circuit, a write compensation sub-circuit, a light emission control sub-circuit, and a drive sub-circuit.
The reset sub-circuit is electrically connected with the first reset signal line, the initialization signal line and the driving sub-circuit, and the reset sub-circuit is configured to input the initialization signal transmitted by the initialization signal line to the driving sub-circuit under the control of the first reset signal transmitted by the first reset signal line.
The reset sub-circuit is also electrically connected with the second reset signal line and the light emitting device, and the reset sub-circuit is configured to input the initialization signal to the light emitting device under the control of a second reset signal transmitted by the second reset signal line.
The write compensation sub-circuit is electrically connected to the first scanning signal line, the second scanning signal line, the data line, and the driving sub-circuit, and the write compensation sub-circuit is configured to write a signal transmitted by the data line into the driving sub-circuit and perform threshold voltage compensation on the driving sub-circuit under control of a first scanning signal transmitted by the first scanning signal line and a second scanning signal transmitted by the second scanning signal line.
The drive sub-circuit is configured to provide a drive current for the light emitting device under control of the emission control sub-circuit and the write compensation sub-circuit.
The light emitting control sub-circuit is electrically connected with the enable signal line, the first voltage wiring, the driving sub-circuit and the light emitting device, and the light emitting control sub-circuit is configured to conduct a current path between the first voltage wiring and the light emitting device and transmit a driving current provided by the driving sub-circuit to the light emitting device under the control of an enable signal transmitted by the enable signal line.
In some embodiments, the driving sub-circuit comprises: a first transistor and a storage capacitor, the write compensation sub-circuit comprising: a second transistor and a third transistor, the light emission control sub-circuit including: a fourth transistor and a fifth transistor; the reset sub-circuit includes: a sixth transistor and a seventh transistor.
The control electrode of the first transistor is electrically connected with the first node, the first electrode of the first transistor is electrically connected with the second node, and the second electrode of the first transistor is electrically connected with the third node. The storage capacitor is electrically connected between the second node and the first voltage trace. The control electrode of the second transistor is electrically connected with the first scanning signal line, the first electrode of the second transistor is electrically connected with the data line, and the second electrode of the second transistor is electrically connected with the first node. A control electrode of the third transistor is electrically connected with the second scanning signal line, a first electrode of the third transistor is electrically connected with the second node, and a second electrode of the third transistor is electrically connected with the third node. The control electrode of the fourth transistor is electrically connected with the enabling signal line, the first electrode of the fourth transistor is electrically connected with the first voltage wire, and the second electrode of the fourth transistor is electrically connected with the first node. A control electrode of the fifth transistor is electrically connected with the enabling signal line, a first electrode of the fifth transistor is electrically connected with the third node, a second electrode of the fifth transistor is electrically connected with the fourth node, and the fourth node is electrically connected with the light-emitting device. A control electrode of the sixth transistor is electrically connected to the first reset signal line, a first electrode of the sixth transistor is electrically connected to the initialization signal line, and a second electrode of the sixth transistor is electrically connected to the first node. A control electrode of the seventh transistor is electrically connected to the second reset signal line, a first electrode of the seventh transistor is electrically connected to the initialization signal line, and a second electrode of the seventh transistor is electrically connected to the fourth node.
In another aspect, there is provided a display device including the display panel according to any one of the above aspects, and a control chip electrically connected to the display panel, wherein the control chip is electrically connected to the constant voltage signal line, the first switch control bus, and the second switch control bus, and the control chip is configured to supply an electric signal to the constant voltage signal line, the first switch control bus, and the second switch control bus.
The display panel improves the inherent problems of afterimage and flicker under the action of the constant voltage signal, and the display device adopting the display panel also has corresponding beneficial effects.
In still another aspect, a driving method of a display panel including a refresh phase and a hold phase in one scan cycle includes: in a refreshing stage, the conversion module transmits a data signal to the data line; in the holding phase, the conversion module transmits a constant voltage signal to the data line.
The driving method of the display panel has the same beneficial effects as the display panel, and is not described herein.
In some embodiments, a driving method of a display panel includes: the first switch conducts a current path between the source driving signal line and the data line during a refresh period, and the second switch conducts a current path between the constant voltage signal line and the data line during a sustain period.
In some embodiments, a driving method of a display panel includes: the holding phase includes a first phase and a second phase. In the hold phase, the first switch opens a path between the source driving signal line and the data line. In the first stage, the second switch connects the constant voltage signal line and the data line, and for each pixel circuit, the light-emitting control sub-circuit disconnects the current path between the first voltage wiring and the light-emitting device under the control of the enable signal line. The reset sub-circuit disconnects a current path between the initialization signal line and the drive sub-circuit under control of the first reset signal line. The reset sub-circuit transmits the initialization signal to the light emitting device under the control of the second reset signal line. The write compensation sub-circuit writes a constant voltage signal to a connection point of the drive sub-circuit and the light emission control sub-circuit under the control of the first scanning signal line and the second scanning signal line. The light emitting device does not emit light.
In the second stage, the second switch disconnects the path between the constant voltage signal line and the data line. The write compensation sub-circuit disconnects a current path between the data line and the driven sub-circuit under the control of the first scanning signal line and the second scanning signal line, and the light-emitting control sub-circuit conducts the current path between the first voltage trace and the light-emitting device under the control of the enable signal line. The driving signal generated by the driving circuit is transmitted to the light-emitting device; the light emitting device emits light.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a plan view of a display panel provided in some embodiments;
FIG. 2 is a schematic diagram of a sub-pixel and its circuit connections according to some embodiments;
FIG. 3 is a plan view of a display panel according to some embodiments of the invention;
FIG. 4 is a block diagram of a conversion module and sub-pixels provided in some embodiments of the invention;
FIG. 5 is an enlarged view of the circuit connections of the transition module of FIG. 4;
FIG. 6 is another block diagram of a conversion module and sub-pixels provided in accordance with some embodiments of the present invention;
FIG. 7 is a block diagram of a pixel circuit provided by some embodiments of the invention;
FIG. 8 is another block diagram of a pixel circuit provided by some embodiments of the invention;
fig. 9 is a plan view of a display device provided in some embodiments of the present invention;
FIG. 10 is a block diagram of an electrical connection between a conversion module and a driver chip according to some embodiments of the invention;
FIG. 11 is a block diagram of another conversion module electrically connected to a driver chip according to some embodiments of the invention;
FIG. 12 is a timing diagram of a driving method according to some embodiments of the present invention;
FIG. 13 is another timing diagram of a driving method according to some embodiments of the invention;
14 a-14 e are diagrams illustrating operation of pixel circuits provided by some embodiments of the invention during a scan cycle;
FIG. 15 is another timing signal diagram of a driving method according to some embodiments of the invention;
FIG. 16 is a timing diagram of data signals/constant voltage signals provided by some embodiments of the present invention.
Detailed Description
The technical solutions in some embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments provided by the present invention belong to the protection scope of the present invention.
Unless the context requires otherwise, throughout the description and the claims, the term "comprise" and its other forms, such as the third person's singular form "comprising" and the present participle form "comprising" are to be interpreted in an open, inclusive sense, i.e. as "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "example", "specific example" or "some examples" and the like are intended to indicate that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present invention. The schematic representations of the terms are not necessarily referring to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be included in any suitable manner in any one or more embodiments or examples.
In the following, the terms "first", "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the embodiments of the present invention, "a plurality" means two or more unless otherwise specified.
In describing some embodiments, expressions of "coupled" and "connected," along with their derivatives, may be used. For example, the term "connected" may be used in describing some embodiments to indicate that two or more elements are in direct physical or electrical contact with each other. As another example, some embodiments may be described using the term "coupled" to indicate that two or more elements are in direct physical or electrical contact. However, the terms "coupled" or "communicatively coupled" may also mean that two or more elements are not in direct contact with each other, but yet still co-operate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents herein.
"at least one of A, B and C" has the same meaning as "A, B or at least one of C," each including the following combination of A, B and C: a alone, B alone, C alone, a and B in combination, a and C in combination, B and C in combination, and A, B and C in combination.
"A and/or B" includes the following three combinations: a alone, B alone, and a combination of A and B.
The use of "adapted to" or "configured to" herein is meant to be an open and inclusive language that does not exclude devices adapted to or configured to perform additional tasks or steps.
Additionally, the use of "based on" means open and inclusive, as a process, step, calculation, or other action that is "based on" one or more stated conditions or values may in practice be based on additional conditions or values beyond those stated.
Example embodiments are described herein with reference to cross-sectional and/or plan views as idealized example figures. In the drawings, the thickness of layers and regions are exaggerated for clarity. Variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, the exemplary embodiments should not be construed as limited to the shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the exemplary embodiments.
Some embodiments of the invention provide a display panel 100, and the display panel 100 may be a self-luminous display panel such as an OLED (Organic Light-Emitting Diode) display panel, a Micro Organic Light-Emitting Diode (Micro OLED) display panel, a Quantum Dot Organic Light-Emitting Diode (QLED) display panel, a Mini LED (Mini Light-Emitting Diode, Mini LED) display panel, or a Micro LED (Micro Light-Emitting Diode, Micro LED). The following description will be given taking the display panel as an AMOLED display panel.
As shown in fig. 1: the display panel 100 includes a display area 10a and a peripheral area 10b disposed at least on one side of the display area 10a, and illustratively, the peripheral area 10b is disposed on one side of the display area 10a, or the peripheral area 10b is disposed around one circumference of the display area 10 a.
The display panel 100 includes a plurality of data lines L, a plurality of gate lines, and a plurality of initialization signal lines Vint disposed in the display region 10 a. The plurality of gate lines include a plurality of scan signal lines G, a plurality of reset signal lines Rst, and a plurality of enable signal lines Em.
The display region 10a is further provided with a plurality of sub-pixels P arranged in an array, each data line L is electrically connected to one column of the sub-pixels P, and the data lines L are configured to transmit display signals. The display signals include data signals for controlling the gray scales of the sub-pixels P, and the plurality of sub-pixels P arranged in an array form a display image on the display panel 100 with different gray scales under the control of the data signals. Illustratively, each of the scan signal lines G is electrically connected to a row of the subpixels P, and the scan signal lines G are configured to transmit a scan signal. Each reset signal line Rst is electrically connected to a row of the sub-pixels P, and the reset signal line Rst is configured to transmit a reset signal. Each enable signal line Em is electrically connected to a row of the sub-pixels P, and the enable signal line Em is configured to transmit an enable signal. Each initialization signal line Vint is electrically connected to a row of the subpixels P, and the initialization signal line Vint is configured to transmit an initialization signal.
The display panel 100 further includes a plurality of first voltage traces ELVdd and a plurality of second voltage traces ELVss, as shown in fig. 2: the sub-pixel P comprises a pixel circuit 1 and a light emitting device 2 electrically connected, and the pixel circuit 1 and the light emitting device 2 connected in series are electrically connected between the first voltage trace ELVdd and the second voltage trace ELVss. The signal lines are all electrically connected to the pixel circuits 1 in the sub-pixels P, each pixel circuit 1 includes a driving transistor, the driving transistor receives the data signal transmitted by the data line L, the driving transistor generates a driving current under the control of the data signal, the magnitude of the driving current affects the light emitting brightness of the light emitting device 2, all the light emitting devices 2 form different light emitting brightness under the control of different data signals, that is, all the sub-pixels P generate different gray scales, so that all the sub-pixels P generate pictures on the display panel 100.
In the display panel 100, during the display process, the plurality of sub-pixels P are scanned line by line, and each pixel circuit 1 receives a set of data signals provided by the data lines L electrically connected thereto, so as to display a picture under the control of the data signals. The operation period between the pixel circuit 1 receiving a set of data signals and a new set of data signals is one scanning period S of the pixel circuit 1. The display panel 100 displays one image or a plurality of images at different image refresh rates according to driving conditions. The image refresh rate is the frequency of data signals written into each sub-pixel P, and can represent the number of times of refreshing the display frames in one second, and the period of refreshing two adjacent display frames is called a scanning period S of the display panel. In some embodiments, as shown in fig. 12, the scanning period S is divided into a plurality of phases, one scanning period S of the display panel 100 includes an initial one of the refresh phases E1 and at least one of the hold phases E2 following the refresh phase E1, and the data signal is written into the corresponding pixel circuit 1 in the refresh phase E1.
In some embodiments, the tfts of the pixel circuit 1 exhibit hysteresis when stressed differently or biased, particularly because electrons or holes inside the tfts are under a bias state when stressed, and when the stress is removed, the electrons or holes cannot return to their original state quickly. For example: in the related art, during one scan period S, in the refresh period E1, a data signal is written into the pixel circuit 1, and the voltage between the gate and the source or between the gate and the drain of the driving transistor causes electrons or holes inside the driving transistor to be in a biased state, and during the hold period E2 after the refresh period E1, the data signal is no longer written into the pixel circuit 1, so that the driving transistor is always in the biased state until a new data signal is input again during the refresh period E1 of the next scan period S. Since the driving transistor is biased for a long time, when a new data signal is written into the driving transistor, the characteristics of the driving transistor have changed, so that the driving transistor cannot be quickly restored, thereby causing the hysteresis of the driving transistor. Such a hysteresis phenomenon causes the image of the display panel 100 to have afterimages and flickers. Especially in the display panel 100 driven at a low frequency, the problems of image sticking and flickering caused by such a hysteresis phenomenon are more serious.
Based on this, some embodiments of the invention provide a display panel 100, a driving method thereof, and a display device 1000. The display panel 100 is further provided with a plurality of conversion modules 3, independent constant voltage signals are provided for the pixel circuits 1 through the conversion modules 3, the thin film transistors of the pixel circuits 1 are biased, problems of image sticking, flicker and the like caused by the hysteresis of the thin film transistors are solved, and particularly in the low-frequency driving display device 1000, the improvement effect is more obvious.
As shown in fig. 3, some embodiments provide a display panel 100 further comprising: a plurality of conversion modules 3, each data line L being electrically connected to a column of sub-pixels P; each conversion module 3 is electrically connected to one data line L. The conversion module 3 is configured to transmit a data signal to the data line L during the refresh phase E1 and transmit a constant voltage signal to the data line L during the hold phase E2.
In the holding period E2, the constant voltage signal is transmitted from the converting module 3 to the pixel circuit 1, the driving transistor of the pixel circuit 1 is subjected to a new bias voltage, and the driving transistor is uniformly biased by the constant voltage signal, i.e. the electrons or holes in all the transistors subjected to the constant voltage signal are uniformly biased. Such uniform bias condition is advantageous to eliminate the display brightness difference of the sub-pixel P caused by the stress deviation caused by displaying different pictures. Especially, when the gray scales displayed by the sub-pixel P before and after are different greatly, for example: the gray scale of the sub-pixel P is from black to white, and the electrons or holes are all in a uniform bias state, so that the characteristics of the transistors are consistent when data is written, and the phenomena of slow response time of the first frame and short-term afterimage of the display panel 100 caused by the hysteresis of the pixel circuit 1 are improved.
In the display panel 100, only the conversion module 3 is arranged and is controlled to output corresponding signals to the data lines L at different stages, so that the data lines L transmit data signals or constant voltage signals to the pixel circuit 1, the output signals of the conversion module 3 share one data line L, bias stress on the thin film transistor of the pixel circuit 1 is realized, the structure of the pixel circuit 1 and the arrangement and connection of a plurality of data lines L are not required to be changed, the complexity of the pixel circuit 1 is not increased, and on the basis of the structure of the existing display panel 100, additional processes and costs are not generated for the preparation of signal lines such as the pixel circuit 1 and the data lines L.
As shown in fig. 4 and 5: in some embodiments, the display panel 100 further includes a plurality of source driving signal lines 4 and constant voltage signal lines 5, the plurality of source driving signal lines 4 being configured to transmit data signals, the constant voltage signal lines 5 being configured to transmit constant voltage signals. Each conversion module 3 is electrically connected to one source driving signal line 4 and a constant voltage signal line 5.
In some examples, the voltage of the constant voltage signal is greater than a voltage difference between a maximum voltage and a minimum voltage of the data signal. Illustratively, the voltage of the constant voltage signal is 2-10V, for example: the voltage of the constant voltage signal is 2V, 5V, or 10V.
The source driving signal line 4 and the constant voltage signal line 5 supply different signals to the pixel circuit 1, respectively, to isolate the two signals from interfering with each other.
In some embodiments, each conversion module 3 comprises a first switch 31 and a second switch 32. The first switch 31 and the second switch 32 are thin film transistors, for example: the first switch 31 is electrically connected between the source drive signal line 4 and the data line L; the second switch 32 is electrically connected between the constant voltage signal line 5 and the data line L. By controlling the opening or closing of the first switch 31 and the second switch 32, a corresponding signal output can be realized.
In some embodiments, as shown in fig. 5: the display panel 100 further includes a first switch control bus 6 and a second switch control bus 7, the first switch control bus 6 is electrically connected to the first switch 31, the first switch control bus 6 is configured to provide a first switch signal, and under the control of the first switch signal, the first switch 31 turns on the source driving signal line 4 and the data line L, so that the source driving signal line 4 transmits the data signal to the data line L and further to the pixel circuit 1. The second switch control bus 7 is electrically connected to the second switch 32, and the second switch control bus 7 is configured to provide a second switch signal, under the control of which the second switch 32 turns on the constant voltage signal line 5 and the data line L, so that the source driving signal line 4 transmits the constant voltage signal to the data line L and further to the pixel circuit 1.
The first switch 31 and the second switch 32 are both thin film transistors, and illustratively, the first switch 31 and the second switch 32 are both P-type transistors, or the first switch 31 is a P-type transistor and the second switch 32 is an N-type transistor. For example: the first switch 31 and the second switch 32 are both P-type transistors, a gate of the first switch 31 is electrically connected to the first switch control bus 6, a first pole of the first switch 31 is electrically connected to one source driving signal line 4, a second pole of the first switch 31 is electrically connected to one data line L, and the first switch 31 is turned on when a first switch signal transmitted by the first switch control bus 6 is at a low level. The gate of the second switch 32 is electrically connected to the second switch control bus 7, the source of the second switch 32 is electrically connected to the constant voltage signal line 5, the drain of the second switch 32 is electrically connected to one data line L, and the second switch 32 is turned on when the second switch signal transmitted from the second switch control bus 7 is at a low level. In the circuit structure of the conversion module 3, the data signal is transmitted to the pixel circuit 1 through the first switch 31, the constant voltage signal is transmitted to the pixel circuit 1 through the second switch 32, and the on and off of the first switch 31 and the second switch 32 are controlled, so that the situation that the data signal and the constant voltage signal enter the pixel circuit 1 at the same time can be avoided, and the interference phenomenon generated between the signals can be avoided as much as possible.
In some embodiments, as shown in fig. 4 and 6: the plurality of conversion modules 3, the plurality of source driving signal lines 4, the constant voltage signal line 5, the first switch control bus 6, and the second switch control bus 7 are located in the peripheral region 10 b.
As shown in fig. 4: the newly added conversion module 3, the plurality of source driving signal lines 4, the constant voltage signal line 5, the first switch control bus 6 and the second switch control bus 7 are disposed in the peripheral region 10b, away from the display region 10a, and the overall transmittance of the display region 10a is not affected, so that the normal operation of the optical identification device located in the display region 10a is not affected, for example: the underscreen fingerprint recognition mounted on the display region 10a is not affected and is more advantageous for the display panel 100 to achieve high pixel density (Pixels Per inc, PPI).
In some examples, the substrate material of the display panel 100 includes glass, and the display panel 100 includes a display area 10a and a peripheral area 10b surrounding the display area 10 a. The plurality of conversion modules 3, the plurality of source driving signal lines 4, the constant voltage signal line 5, the first switch control bus 6, and the second switch control bus 7 are disposed in the peripheral region 10 b. For example: the plurality of conversion modules 3, the plurality of source driving signal lines 4, the constant voltage signal line 5, the first switch control bus 6, and the second switch control bus 7 are disposed in the peripheral region 10b on the same side of the display region 10 a. The peripheral region 10b on the other side of the display panel 100 does not need to add new modules or routing, and the bezel does not need to increase in size, which is beneficial to realizing a narrow bezel.
In other examples, as shown in fig. 6: the peripheral region 10b includes a bending region b1 and a first non-bending region b2, the first non-bending region b2 is located on a side of the bending region b1 away from the display region 10a, the first non-bending region b2 can be bent to a non-light-emitting side of the display panel 100 through a bending region b1, and the plurality of conversion modules 3 are located in the first non-bending region b 2. In some examples, the substrate material of the display panel 100 includes: the first non-bending region b2 can be bent to the non-light-emitting side of the display panel 100 through the bending region b1, and the plurality of conversion modules 3, the plurality of source driving signal lines 4, the constant voltage signal line 5, the first switch control bus 6, and the second switch control bus 7 are located in the first non-bending region b 2. The conversion module 3 is disposed in the first non-bending region b2, and along with the bending of the bending region b1, the conversion module 3 is located on the non-light-emitting side of the display panel 100, so that the frame width of the display panel 100 on the side where the bending region b1 is disposed is not affected, and thus the whole display panel 100 can achieve the purpose of narrow frame.
In some embodiments, the scan signal lines G further include a first scan signal line G1 and a second scan signal line G2, the first scan signal line G1 configured to transmit a first scan signal, the second scan signal line G2 configured to transmit a second scan signal; the reset signal line Rst includes a first reset signal line Rst1 and a second reset signal line Rst2, the first reset signal line Rst1 is configured to transmit a first reset signal, and the second reset signal line Rst2 is configured to transmit a second reset signal.
The following exemplarily provides a structure of the pixel circuit 1, as shown in fig. 7: the pixel circuit 1 includes: a reset sub-circuit 11, a write compensation sub-circuit 12, a light emission control sub-circuit 13, and a drive sub-circuit 14.
The reset sub-circuit 11 is electrically connected to the first reset signal line Rst1, the initialization signal line Vint, and the driving sub-circuit 14, and the reset sub-circuit 11 is configured to input the initialization signal transmitted by the initialization signal line Vint to the driving sub-circuit 14 under the control of the first reset signal transmitted by the first reset signal line Rst 1.
The reset sub-circuit 11 is also electrically connected to the second reset signal line Rst2 and the light emitting device 2, and the reset sub-circuit 11 is configured to input an initialization signal to the light emitting device 2 under the control of a second reset signal transmitted by the second reset signal line Rst 2.
The write compensation sub-circuit 12 is electrically connected to the first scanning signal line G1, the second scanning signal line G2, the data line L, and the driving sub-circuit 14, and the write compensation sub-circuit 12 is configured to write a signal transmitted through the data line L into the driving sub-circuit 14 and perform threshold voltage compensation on the driving sub-circuit 14 under the control of a first scanning signal transmitted through the first scanning signal line G1 and a second scanning signal transmitted through the second scanning signal line G2.
The drive sub-circuit 14 is configured to supply a drive current to the light emitting device 2 under the control of the light emission control sub-circuit 13 and the write compensation sub-circuit 12.
The light emission control sub-circuit 13 is electrically connected to the enable signal line Em, the first voltage trace ELVdd, the driving circuit 14, and the light emitting device 2, and the light emission control sub-circuit 13 is configured to conduct a current path between the first voltage trace ELVdd and the light emitting device 2 and transmit a driving current provided by the driving sub-circuit 14 to the light emitting device 2 under the control of the enable signal line Em.
The circuit structure of the conversion module 3 is suitable for the common pixel circuit 1, and can perform bias stress on the node where the driving sub-circuit 14 is connected with the data line L, thereby improving the problems of slow response and image sticking of the first frame of the display panel 100. The circuit configuration of the pixel circuit 1 described above.
There is also provided in some embodiments a circuit configuration of the pixel circuit 1, as shown in fig. 8: the drive sub-circuit 14 includes: a first transistor T1 and a storage capacitor Cst, wherein the first transistor T1 is a driving transistor of the pixel circuit 1, and the compensation sub-circuit includes: the second transistor T2 and the third transistor T3, the light emission control sub-circuit 13 includes: a fourth transistor T4 and a fifth transistor T5, the reset sub-circuit 11 includes: a sixth transistor T6 and a seventh transistor T7.
A control electrode of the first transistor T1 is electrically connected to the first node N1, a first electrode of the first transistor T1 is electrically connected to the second node N2, and a second electrode of the first transistor T1 is electrically connected to the third node N3.
The storage capacitor Cst is electrically connected between the second node N2 and the first voltage trace ELVdd.
A control electrode of the second transistor T2 is electrically connected to the first scan signal line G1, a first electrode of the second transistor T2 is electrically connected to the data line L, and a second electrode of the second transistor T2 is electrically connected to the first node N1.
A control electrode of the third transistor T3 is electrically connected to the second scan signal line G2, a first electrode of the third transistor T3 is electrically connected to the second node N2, and a second electrode of the third transistor T3 is electrically connected to the third node N3.
A control electrode of the fourth transistor T4 is electrically connected to the enable signal line Em, a first electrode of the fourth transistor T4 is electrically connected to the first voltage trace ELVdd, and a second electrode of the fourth transistor T4 is electrically connected to the first node N1.
A control electrode of the fifth transistor T5 is electrically connected to the enable signal line Em, a first electrode of the fifth transistor T5 is electrically connected to the third node N3, a second electrode of the fifth transistor T5 is electrically connected to the fourth node N4, and the fourth node N4 is electrically connected to the light emitting device 2.
A control electrode of the sixth transistor T6 is electrically connected to the first reset signal line Rst1, a first electrode of the sixth transistor T6 is electrically connected to the initialization signal line Vint, and a second electrode of the sixth transistor T6 is electrically connected to the first node N1.
A control electrode of the seventh transistor T7 is electrically connected to the second reset signal line Rst2, a first electrode of the seventh transistor T7 is electrically connected to the initialization signal line Vint, and a second electrode of the seventh transistor T7 is electrically connected to the fourth node N4.
In some examples, the first transistor T1 is a P-type transistor, the second transistor T2 is a P-type transistor, the third transistor T3 is an N-type transistor, the fourth transistor T4 and the fifth transistor T5 are both P-type transistors, the sixth transistor T6 is an N-type transistor, and the seventh transistor T7 is a P-type transistor.
In some embodiments, in the case that the first switch 31 and the second switch 31 are thin film transistors, the first switch 31 and the second switch 32 may be located in the same film layer as the transistors in the pixel circuit 1 and formed by the same process, so as to simplify the manufacturing process of the display panel 100.
As shown in fig. 9, 10 and 11: an embodiment of the present invention further provides a display device 1000, where the display device 1000 includes the display panel 100 and a control chip 200 electrically connected to the display panel 100, the control chip 200 is electrically connected to the constant voltage signal line 5, the first switch control bus 6, and the second switch control bus 7, and the control chip 200 is configured to provide a constant voltage signal to the constant voltage signal line 5, provide a first switch signal to the first switch control bus 6, and provide a second switch signal to the second switch control bus 7.
The display device 1000 has the same effects as those of the display panel 100, namely: the pixel circuit 1 of the sub-pixel P is biased and stressed, and a balanced, stable and single bias state of the pixel circuit 1 is provided for data signal writing when the next frame of picture is refreshed, so that the problems of picture ghost, flicker and slow response time of the first frame are solved.
The display device 1000 also has the advantage of a narrow frame and a high transmittance of the entire layout of the pixel circuit 1 in the display region 10 a.
In addition, the layout design of the pixel circuit 1 of the display device 1000 is simple, the processing scheme is mature and reliable, and the advantages of high yield and low cost of the display device 1000 can be ensured.
In some examples, as shown in fig. 10: the display device 1000 further includes a source driving chip electrically connected to the plurality of source driving signal lines 4, the source driving chip being configured to supply the data signals to the source driving signal lines 4.
In other examples, as shown in fig. 11: the control chip 200 integrates a source driving module 201 and a control module 202. Wherein the source driving module 201 is configured to provide the data signal by the source driving signal line 4; the control module 202 is configured to provide a constant voltage signal on a constant voltage signal line 5, a first switching signal on a first switch control bus 6, and a second switching signal on a second switch control bus 7.
The embodiment of the present invention further provides a driving method of the display panel 100, as shown in fig. 12: the display process of the display panel 100 includes a plurality of scan cycles S, each scan cycle S including a refresh phase E1 and at least one hold phase E2. During the display process of each sub-pixel P of the display panel 100, the pixel circuit 1 of the sub-pixel P includes a refresh phase E1 and at least one hold phase E2 following the refresh phase E1 within one scan period S. The refresh phase E1 of the pixel circuit 1 is contained within the refresh phase E1 of the display panel 100, and the hold phase E2 of the pixel circuit 1 is contained within the hold phase E2 of the display panel 100.
The driving method of the display panel 100 includes: during the refresh phase E1, the conversion module 3 transmits a data signal to the data line L. In the holding period E2, the conversion module 3 transmits a constant voltage signal to the data line L.
In conjunction with the timing signal diagrams shown in fig. 12 and 13, and the conversion module 3 shown in fig. 5 and the pixel circuit 1 shown in fig. 8, the driving method of the display panel 100 includes: during the refresh period E1, the second switch signal is at high level, and the second switch 32 is controlled by the second switch signal to disconnect the current paths of the constant voltage signal line 5 and the data line L; the first switch signal is at a low level, and the first switch 31 turns on the current path between the source driving signal line 4 and the data line L under the control of the first switch signal, so that the first switch 31 transmits the data signal provided by the source driving signal line 4 to the data line L.
The refresh phase E1 for each pixel circuit 1 includes an initialization phase E11, a data signal writing phase E12, and a light emission phase E13.
In the initialization phase E11, the reset sub-circuit 11 writes the initialization signal transmitted by the initialization signal line Vint into the drive sub-circuit 14 under the control of the first reset signal line Rst 1; the reset sub-circuit 11 disconnects the current path of the initialization signal line Vint and the light emitting device 2 under the control of the second reset signal line Rst 2. The light emission control sub-circuit 13 disconnects the current path between the first voltage trace ELVdd and the light emitting device 2 under the control of the enable signal line Em. The write compensation sub-circuit 12 breaks a current path between the data line L and the drive sub-circuit 14 under the control of the first scanning signal line G1 and the second scanning signal line G2.
In the data signal write phase E12, the reset sub-circuit 11 disconnects the initialization signal line Vint and the current path of the drive sub-circuit 14 under the control of the first reset signal line Rst 1; the reset sub-circuit 11 disconnects the current path of the initialization signal line Vint and the light emitting device 2 under the control of the second reset signal line Rst 2. The write compensation sub-circuit 12 is turned on under the control of the first scanning signal line G1 and the second scanning signal line G2, turns on a current path between the data line L and the drive sub-circuit 14, writes a data signal into the drive sub-circuit 14, and performs threshold voltage compensation on the drive sub-circuit 14.
In the light-emitting period E13, the write compensation sub-circuit 12 disconnects the current path between the data line L and the driving sub-circuit 14 under the control of the first scanning signal line G1 and the second scanning signal line G2. The light emitting control sub-circuit 13 is turned on under the control of the enable signal line Em, and turns on the current path between the first voltage trace ELVdd and the light emitting device 2, so as to transmit the driving current provided by the driving sub-circuit 14 to the light emitting device 2, and the light emitting device 2 emits light.
It should be noted that: in some examples, in the data signal writing phase E12, the reset sub-circuit 11 turns on a current path between the initialization signal line Vint and the light emitting device 2 under the control of the second reset signal, and the initialization signal supplied from the initialization signal line Vint is transmitted to the light emitting device 2.
In the holding period E2, the first switch 31 disconnects the source driving signal line 4 and the data line L. The conversion module 3 transmits a constant voltage signal to the data line L. As shown in fig. 13: the holding phase E2 includes: a first holding phase E21 and a second holding phase E22.
In the first phase E21, the second switch 32 turns on the constant voltage signal line 5 and the data line L, and the data line L transmits the constant voltage signal to the pixel circuit 1. The light emission control sub-circuit 13 disconnects the current path between the first voltage trace ELVdd and the light emitting device 2 under the control of the enable signal line Em. The reset sub-circuit 11 disconnects the current path between the initialization signal line Vint and the drive sub-circuit 14 under the control of the first reset signal line Rst 1. The reset sub-circuit 11 is turned on under the control of the second reset signal line Rst2, transmitting an initialization signal to the light emitting device 2. The write compensation sub-circuit 12 is turned on under the control of the first scanning signal line G1 and the second scanning signal line G2, and writes a constant voltage signal to the connection point of the drive sub-circuit 14 and the light emission control sub-circuit 13; the light emitting device 2 does not emit light.
In the second stage E22, the second switch 32 disconnects the constant voltage signal line 5 from the data line L. The write compensation sub-circuit 12 disconnects the current path between the data line L and the drive sub-circuit 14 under the control of the first scanning signal line G1 and the second scanning signal line G2. The light emission control sub-circuit 13 turns on a current path between the first voltage trace ELVdd and the light emitting device 2 under the control of the enable signal line Em, transmits the driving current supplied from the driving sub-circuit to the light emitting device 2, and the light emitting device 2 emits light.
In some examples, in combination with the pixel circuit 1 shown in fig. 9 and the timing signal diagram shown in fig. 12, a driving method of the display panel is exemplarily described, taking the refresh rate of the display panel 100 as 1Hz as an example. The picture of the display panel 100 is refreshed once in one second. As shown in fig. 12, the pixel circuit 1 includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7, and the operation process of the pixel circuit 1 is as follows: the 1 second Frame period Frame is divided into 60 Frame periods, one scanning period S is provided within 1 second, and the 60 Frame periods Frame includes the first 1 refresh period E1 and 59 hold periods E2 following the refresh period E1.
The refresh phase E1 includes: an initialization phase E11, a data signal writing phase E12, and a light emission phase E13. Throughout the refresh period E1, the first switch 31 turns on the current path between the source driving signal line 4 and the data line L under the control of the first switching signal, and the data signal is transmitted to the pixel circuit 1 through the data line L.
As shown in fig. 14 a: in the initialization stage E11, the sixth transistor T6 is turned on under the control of the first reset signal transmitted through the first reset signal line Rst1, and the first node N1 inputs the initialization signal transmitted through the initialization signal line Vint to the first node N1. The seventh transistor T7 is turned off under the control of the second reset signal transmitted from the second reset signal line Rst2, and interrupts a current path between the initialization signal line Vint and the light emitting device 2. The fourth transistor T4 and the fifth transistor T5 are turned off under the control of the enable signal transmitted from the enable signal line Em, interrupting the current path between the first voltage trace ELVdd and the light emitting device 2. The second transistor T2 is turned off under the control of the first scan signal transmitted from the first scan signal line G1, interrupting the current path between the data line L and the second node N2. The third transistor T3 is turned off under the control of the second scan signal transmitted through the second scan signal line G2, interrupting the current path between the first node N1 and the third node N3.
As shown in fig. 14 b: in the data signal writing period E12, the sixth transistor T6 is turned off under the control of the first reset signal transmitted through the first reset signal line Rst 1. The seventh transistor T7 is turned on under the control of the second reset signal transmitted from the second reset signal line Rst2, turns on a current path between the initialization signal line Vint and the light emitting device 2, and transmits the initialization signal to the light emitting device 2. The second transistor T2 is turned on by the control of the first scan signal transmitted through the first scan signal line G1, the third transistor T3 is turned on by the control of the second scan signal transmitted through the second scan signal line G2, the data signal transmitted through the data line L is transmitted to the first node N1, the third transistor T3 electrically connects the control electrode and the second electrode of the first transistor T1, the threshold voltage of the first transistor T1 is written into the first node N1, the first transistor T1 is turned off when the voltage of the first node N1 is the sum of the voltage of the data signal and the threshold voltage of the first transistor, and the storage capacitor Cst stores and maintains the voltage of the first node N1.
As shown in fig. 14 c: in the light emitting period E13, the seventh transistor T7 is turned off under the control of the second reset signal transmitted through the second reset signal line Rst2, the second transistor T2 is turned off under the control of the first scan signal transmitted through the first scan signal line G1, and the third transistor T3 is turned off under the control of the second scan signal transmitted through the second scan signal line G2. The fourth transistor T4 and the fifth transistor T5 are turned on under the control of an enable signal transmitted from the enable signal line Em, a current path between the first voltage trace ELVdd and the light emitting device 2 is turned on, the first transistor T1 is turned on under the control of the first voltage trace ELVdd and the voltage of the first node N1, a driving current is generated, and the driving current is transmitted to the light emitting device, and the light emitting device 2 emits light.
The holding phase E2 includes: the first switch 31 disconnects the current path between the source driving signal line 4 and the data line L under the control of the first switch control signal during the first phase and the second phase, which is the entire holding phase E2.
As shown in fig. 14 d: in the first phase E21, the second switch 32 is controlled by the second switching signal to turn on the current path between the constant voltage signal line 5 and the data line L, and the data line L transmits the constant voltage signal. The fourth transistor T4 and the fifth transistor T5 are turned off under the control of the enable signal transmitted from the enable signal line Em, interrupting the current path between the first voltage trace ELVdd and the light emitting device 2. The second transistor T2 is turned on under the control of the first scan signal transmitted from the first scan signal line G1, turns on a current path between the data line L and the second node N2, and transmits a constant voltage signal to the second node N2. The first node N1 voltage maintains the sum of the data signal voltage and the threshold voltage of the first transistor T1, and the second node N2 voltage is the voltage of the constant voltage signal. The seventh transistor T7 is turned on under the control of the second reset signal line Rst2, and the current path between the initialization signal line Vint and the light emitting device 2 is turned on, transmitting the initialization signal to the light emitting device.
As shown in fig. 14 e: in the second stage E22, the second switch 32 is turned off under the control of the second switching signal, and the current path between the constant voltage signal line 5 and the data line L is disconnected. The fourth transistor T4 and the fifth transistor T5 are turned on under the control of an enable signal transmitted from the enable signal line Em. Meanwhile, the second transistor T2 is turned off by the first scan signal transmitted through the first scan signal line G1, a current path between the data line L and the second node N2 is cut off, and the voltage of the first node N1 maintains the sum of the data signal voltage and the threshold voltage of the first transistor T1. The first transistor T1 is turned on under the control of the first voltage trace ELVdd and the voltage of the first node N1 to generate a driving current, and the turned-on fourth transistor T4 and fifth transistor T5 transmit the driving current to the light emitting device 2, and the light emitting device 2 emits light. The seventh transistor T7 is turned off under the control of the second reset signal transmitted through the second reset signal line Rst 2.
In some examples, taking the refresh rate of the display panel 100 as 2Hz and the highest compatible 60Hz as an example, the picture of the display panel 100 is refreshed twice within one second, and the Frame is divided into 60 Frame periods within one second. As shown in fig. 15: within 1 second, the operation of the pixel circuit 1 shown in fig. 8 is as follows: 1 second is divided into 60 Frame periods Frame, two scanning periods S are provided within 1 second, the first scanning period S1 is located within the first Frame period to the thirtieth Frame period, the first Frame period to the thirtieth Frame period include an initial one refresh period E1 and a twenty-nine hold period E2 located after the refresh period E1; the second scan period S2 is located within thirty-first to sixty frame periods including the initial one refresh period E1 and twenty-nine sustain periods E2 located after the refresh period E1. In each scanning period S, the driving process of the display panel 100 is as described above, and is not described herein again. In addition, the pixel circuit 1 may also have 3 scan periods S, 30 scan periods S, 60 scan periods S, or 120 scan periods S within 1 second depending on the highest compatible refresh frequency.
In some embodiments, the voltage of the constant voltage signal for different hold phases E2 may be different. For example, the voltage of the constant voltage signal of at least one holding period E2, which is located after the refresh period E1, is greater than the voltage of the constant voltage signal of the other holding periods E2. The voltage of the constant voltage signal of at least one holding period E2, which is located before the refresh period E1, is less than the voltage of the constant voltage signal of the other holding periods E2. And the voltage of the constant voltage signal of several hold phases E2 between the adjacent two refresh phases E1 is in a decreasing state. Illustratively, as shown in fig. 16: with one scan period S within 1 second. In one scan period S, the voltage of the constant voltage signal of the first hold period E2 after the refresh period E1 is greater than the voltages of the other constant voltage signals in the scan period S. In one scan period S, the voltage of the constant voltage signal at the last holding period E2 is smaller than the voltages of the other constant voltage signals in the scan period S. For example: the voltage of the constant voltage signal of the first holding period E2 after the refresh period E1 may be 6V, 8V, or 10V in one scan period S; the voltage of the constant voltage signal at the last holding period E2 may be 2V, 4V, or 5V; the voltage of the constant voltage signal of the plurality of holding periods E2 between the first holding period E2 and the last holding period E2 may be 4V, 6V, or 8V. Through setting up like this, can further promote the display effect as required dynamic adjustment required voltage, and save the consumption.
During the refresh period E1, the characteristic variation of the first transistor T1 caused by the writing of the data signal into the driving sub-circuit 14, especially when the gray scale of two adjacent frames of the sub-pixel P is different greatly, the characteristic variation of the first transistor T1 is larger. In the first stage, the constant voltage signal is supplied to the first electrode of the first transistor T1 at a logic high voltage to counteract the differential characteristic variation generated by the transistors during the refresh stage E1, so as to ensure the transistors are biased uniformly, i.e. the transistors of the sub-pixel P have better uniformity, thereby improving the problem of poor display caused by the hysteresis phenomenon, such as: slow response time of the first frame and short-term ghost.
In addition, in some embodiments, during the holding phase E2 (e.g., the first phase E21), the level of the second scan signal transmitted by the second scan signal line G2 may be set to the on level of the third transistor T3, the third transistor T3 is turned on under the control of the second scan signal transmitted by the second scan signal line G2, and the second transistor T2 is also turned on, so that the current path between the data line L and the second and first nodes N2 and N1 is turned on, and the constant voltage signal is transmitted to the second and first nodes N2 and N1. The constant voltage signal can compensate the voltage loss of the first node N1 caused by the leakage current when the light emitting device 2 emits light, so that the voltage of the first node N1 can be maintained, that is, the voltage of the first node N1 is compensated in a manner of directly compensating the data signal (at this time, the constant voltage signal serves as the data signal), and the voltage value of the constant voltage signal is approximately equal to the voltage loss value of the first node N1, so as to achieve better brightness uniformity of the sub-pixel P and improve the low-frequency flicker phenomenon.
The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims (14)

1. A display panel is characterized in that a one-time scanning period of the display panel comprises a refreshing stage and at least one holding stage; the display panel includes:
a plurality of sub-pixels arranged in an array, each sub-pixel including a pixel circuit and a light emitting device electrically connected;
a plurality of data lines, each of which is electrically connected to a column of sub-pixels;
a plurality of conversion modules, each conversion module electrically connected to one data line, the conversion modules configured to transmit a data signal to the data line during the refresh phase and to transmit a constant voltage signal to the data line during the hold phase.
2. The display panel according to claim 1, characterized in that the display panel further comprises:
a plurality of source driving signal lines configured to transmit data signals;
a constant voltage signal line configured to transmit a constant voltage signal;
the conversion module is electrically connected with a source driving signal line and the constant voltage signal line.
3. The display panel according to claim 2, wherein the conversion module comprises a first switch and a second switch, the first switch being electrically connected between the source driving signal line and the data line; the second switch is electrically connected between the constant voltage signal line and the data line.
4. The display panel according to claim 3,
the first switch is configured to turn on the source driving signal line and the data line under control of a first switching signal;
the second switch is configured to turn on the constant voltage signal line and the data line under control of a second switching signal.
5. The display panel according to claim 4, wherein the first switch and the second switch are thin film transistors.
6. The display panel of claim 4, further comprising a first switch control bus and a second switch control bus, the first switch control bus being electrically connected to the first switch, the first switch control bus being configured to provide the first switch signal; the second switch control bus is electrically connected with the second switch, the second switch control bus configured to provide the second switch signal.
7. The display panel according to claim 6, wherein the display panel comprises a display region and a peripheral region disposed at least on one side of the display region;
the plurality of conversion modules, the plurality of source driving signal lines, the constant voltage signal line, the first switch control bus, and the second switch control bus are located in the peripheral region.
8. The display panel according to claim 7, wherein the peripheral region comprises a bending region and a first non-bending region, the first non-bending region is located on a side of the bending region away from the display region, the first non-bending region can be bent to a non-light-emitting side of the display panel through the bending region, and the plurality of conversion modules are located in the first non-bending region.
9. The display panel according to any one of claims 1 to 8, wherein the pixel circuit comprises: a reset sub-circuit, a write compensation sub-circuit, a light emission control sub-circuit, and a drive sub-circuit;
the reset sub-circuit is electrically connected with a first reset signal line, an initialization signal line and the driving sub-circuit, and the reset sub-circuit is configured to input an initialization signal transmitted by the initialization signal line to the driving sub-circuit under the control of a first reset signal transmitted by the first reset signal line;
the reset sub-circuit is also electrically connected with a second reset signal line and the light-emitting device, and the reset sub-circuit is configured to input the initialization signal to the light-emitting device under the control of a second reset signal transmitted by the second reset signal line;
the writing compensation sub-circuit is electrically connected with a first scanning signal line, a second scanning signal line, the data line and the driving sub-circuit, and is configured to write a data signal transmitted by the data line into the driving sub-circuit and perform threshold voltage compensation on the driving sub-circuit under the control of a first scanning signal transmitted by the first scanning signal line and a second scanning signal transmitted by the second scanning signal line;
the drive sub-circuit is configured to provide a drive current for the light emitting device under control of the emission control sub-circuit and the write compensation sub-circuit;
the light emitting control sub-circuit is electrically connected with an enable signal line, a first voltage wire, the driving sub-circuit and the light emitting device, and the light emitting control sub-circuit is configured to conduct a current path between the first voltage wire and the light emitting device and transmit a driving current provided by the driving sub-circuit to the light emitting device under the control of an enable signal transmitted by the enable signal line.
10. The display panel according to claim 9,
the driving sub-circuit includes: a first transistor and a storage capacitor, the write compensation subcircuit comprising: a second transistor and a third transistor, the light emission control sub-circuit including: a fourth transistor and a fifth transistor; the reset sub-circuit includes: a sixth transistor and a seventh transistor;
a control electrode of the first transistor is electrically connected with a first node, a first electrode of the first transistor is electrically connected with a second node, and a second electrode of the first transistor is electrically connected with a third node;
the storage capacitor is electrically connected between the second node and the first voltage trace;
a control electrode of the second transistor is electrically connected with the first scanning signal line, a first electrode of the second transistor is electrically connected with the data line, and a second electrode of the second transistor is electrically connected with the first node;
a control electrode of the third transistor is electrically connected to the second scanning signal line, a first electrode of the third transistor is electrically connected to the second node, and a second electrode of the third transistor is electrically connected to the third node;
a control electrode of the fourth transistor is electrically connected with the enable signal line, a first electrode of the fourth transistor is electrically connected with the first voltage trace, and a second electrode of the fourth transistor is electrically connected with the first node;
a control electrode of the fifth transistor is electrically connected with the enable signal line, a first electrode of the fifth transistor is electrically connected with the third node, a second electrode of the fifth transistor is electrically connected with a fourth node, and the fourth node is electrically connected with the light emitting device;
a control electrode of the sixth transistor is electrically connected with the first reset signal line, a first electrode of the sixth transistor is electrically connected with the initialization signal line, and a second electrode of the sixth transistor is electrically connected with the first node;
a control electrode of the seventh transistor is electrically connected to the second reset signal line, a first electrode of the seventh transistor is electrically connected to the initialization signal line, and a second electrode of the seventh transistor is electrically connected to the fourth node.
11. A display device, comprising:
the display panel of any one of the preceding claims 1 to 10;
and the control chip is electrically connected with the constant voltage signal line, the first switch control bus and the second switch control bus and is configured to provide electric signals for the constant voltage signal line, the first switch control bus and the second switch control bus.
12. A driving method of a display panel, wherein the display panel includes a refresh phase and at least one hold phase in one scan cycle, the display panel comprising:
a plurality of sub-pixels arranged in an array, each sub-pixel including a pixel circuit and a light emitting device electrically connected;
a plurality of data lines, each of which is electrically connected to a column of sub-pixels;
a plurality of conversion modules, each conversion module electrically connected to one data line;
the driving method of the display panel includes:
in the refreshing stage, the conversion module transmits a data signal to the data line;
in the holding phase, the conversion module transmits a constant voltage signal to the data line.
13. The method for driving a display panel according to claim 12, wherein the display panel further comprises:
a plurality of source driving signal lines configured to transmit data signals;
a constant voltage signal line configured to transmit a constant voltage electrical signal;
the conversion module is electrically connected with a source driving signal line and the constant voltage signal line, and comprises:
a first switch and a second switch, the first switch being electrically connected between the source driving signal line and the data line; the second switch is electrically connected between the constant voltage signal line and the data line;
the driving method of the display panel includes: the first switch turns on the source driving signal line and the data line in the refresh phase, and the second switch turns on the constant voltage signal line and the data line in the hold phase.
14. The method for driving a display panel according to claim 12 or 13,
the pixel circuit includes: a reset sub-circuit, a write compensation sub-circuit, a light emission control sub-circuit, and a drive sub-circuit;
the reset sub-circuit is electrically connected with a first reset signal line, an initialization signal line and the driving sub-circuit, and the reset sub-circuit is configured to input an initialization signal transmitted by the initialization signal line to the driving sub-circuit under the control of a first reset signal transmitted by the first reset signal line;
the reset sub-circuit is electrically connected with a second reset signal line, the initialization signal line and the light emitting device, and the reset sub-circuit is configured to input the initialization signal to the light emitting device under the control of a second reset signal transmitted by the second reset signal line;
the writing compensation sub-circuit is electrically connected with a first scanning signal line, a second scanning signal line, the data line and the driving sub-circuit, and is configured to write a signal transmitted by the data line into the driving sub-circuit and perform threshold voltage compensation on the driving sub-circuit under the control of a first scanning signal transmitted by the first scanning signal line and a second scanning signal transmitted by the second scanning signal line;
the drive sub-circuit is configured to provide a drive current for the light emitting device under control of the emission control sub-circuit and the write compensation sub-circuit;
the light-emitting control sub-circuit is electrically connected with an enable signal line, a first voltage wire, the driving circuit and the light-emitting device, and is configured to conduct a current path between the first voltage wire and the light-emitting device and transmit a driving current provided by the driving sub-circuit to the light-emitting device under the control of an enable signal transmitted by the enable signal line;
the driving method of the display panel includes: the holding phase comprises a first phase and a second phase;
in the hold phase, the first switch opens a path between the source driving signal line and the data line;
in the first stage, the second switch turns on the constant voltage signal line and the data line; for each pixel circuit, the light-emitting control sub-circuit disconnects a current path between the first voltage trace and the light-emitting device under the control of the enable signal line; the reset sub-circuit is controlled by the first reset signal line to disconnect a current path between the initialization signal line and the driving sub-circuit; the reset sub-circuit transmits the initialization signal to the light emitting device under the control of the second reset signal line; the writing compensation sub-circuit writes the constant voltage signal to a connection point of the driving sub-circuit and the light emission control sub-circuit under control of the first scanning signal line and the second scanning signal line; the light emitting device does not emit light;
in the second stage, the second switch disconnects the path between the constant voltage signal line and the data line; for each pixel circuit, the write compensation sub-circuit disconnects a current path between the data line and the driving sub-circuit under the control of the first scanning signal line and the second scanning signal line, and the light emission control sub-circuit conducts the current path between the first voltage trace and the light emitting device under the control of the enable signal line; the driving signal generated by the driving circuit is transmitted to the light-emitting device; the light emitting device emits light.
CN202111406863.5A 2021-11-24 2021-11-24 Display panel, driving method and display device Active CN114038429B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202111406863.5A CN114038429B (en) 2021-11-24 2021-11-24 Display panel, driving method and display device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202111406863.5A CN114038429B (en) 2021-11-24 2021-11-24 Display panel, driving method and display device

Publications (2)

Publication Number Publication Date
CN114038429A true CN114038429A (en) 2022-02-11
CN114038429B CN114038429B (en) 2023-06-13

Family

ID=80145440

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202111406863.5A Active CN114038429B (en) 2021-11-24 2021-11-24 Display panel, driving method and display device

Country Status (1)

Country Link
CN (1) CN114038429B (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114495836A (en) * 2022-02-23 2022-05-13 武汉天马微电子有限公司 Pixel circuit, driving method thereof, display panel and electronic equipment
CN114863875A (en) * 2022-05-25 2022-08-05 武汉天马微电子有限公司 Display panel, driving method thereof and display device
CN115064118A (en) * 2022-06-23 2022-09-16 合肥维信诺科技有限公司 Display panel driving method, driving device and display device
WO2023045315A1 (en) * 2021-09-26 2023-03-30 合肥维信诺科技有限公司 Driving method and driving apparatus for display panel, and display apparatus
WO2023216175A1 (en) * 2022-05-12 2023-11-16 京东方科技集团股份有限公司 Display substrate and driving method therefor, and display apparatus
WO2024007818A1 (en) * 2022-07-04 2024-01-11 华为技术有限公司 Display driving circuit, integrated circuit, oled screen, device and method

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102646389A (en) * 2011-09-09 2012-08-22 京东方科技集团股份有限公司 Organic light emitting diode (OLED) panel and OLED panel driving method
CN109148548A (en) * 2018-09-28 2019-01-04 昆山国显光电有限公司 Array substrate and display panel
CN111710299A (en) * 2020-06-30 2020-09-25 厦门天马微电子有限公司 Display panel, driving method thereof and display device
CN112102785A (en) * 2020-10-15 2020-12-18 厦门天马微电子有限公司 Pixel circuit, display panel, driving method of display panel and display device
CN112509519A (en) * 2020-10-20 2021-03-16 厦门天马微电子有限公司 Display panel driving method and display device
CN112634832A (en) * 2020-12-31 2021-04-09 上海天马有机发光显示技术有限公司 Display panel, driving method and display device
CN113012643A (en) * 2021-03-01 2021-06-22 上海天马微电子有限公司 Display panel, driving method thereof and display device

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102646389A (en) * 2011-09-09 2012-08-22 京东方科技集团股份有限公司 Organic light emitting diode (OLED) panel and OLED panel driving method
CN109148548A (en) * 2018-09-28 2019-01-04 昆山国显光电有限公司 Array substrate and display panel
CN111710299A (en) * 2020-06-30 2020-09-25 厦门天马微电子有限公司 Display panel, driving method thereof and display device
CN112102785A (en) * 2020-10-15 2020-12-18 厦门天马微电子有限公司 Pixel circuit, display panel, driving method of display panel and display device
US20210104196A1 (en) * 2020-10-15 2021-04-08 Xiamen Tianma Micro-Electronics Co., Ltd. Display panel and driving method thereof, and display device
CN112509519A (en) * 2020-10-20 2021-03-16 厦门天马微电子有限公司 Display panel driving method and display device
CN112634832A (en) * 2020-12-31 2021-04-09 上海天马有机发光显示技术有限公司 Display panel, driving method and display device
CN113012643A (en) * 2021-03-01 2021-06-22 上海天马微电子有限公司 Display panel, driving method thereof and display device

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023045315A1 (en) * 2021-09-26 2023-03-30 合肥维信诺科技有限公司 Driving method and driving apparatus for display panel, and display apparatus
CN114495836A (en) * 2022-02-23 2022-05-13 武汉天马微电子有限公司 Pixel circuit, driving method thereof, display panel and electronic equipment
WO2023216175A1 (en) * 2022-05-12 2023-11-16 京东方科技集团股份有限公司 Display substrate and driving method therefor, and display apparatus
CN114863875A (en) * 2022-05-25 2022-08-05 武汉天马微电子有限公司 Display panel, driving method thereof and display device
CN114863875B (en) * 2022-05-25 2023-05-05 武汉天马微电子有限公司 Display panel, driving method thereof and display device
CN115064118A (en) * 2022-06-23 2022-09-16 合肥维信诺科技有限公司 Display panel driving method, driving device and display device
CN115064118B (en) * 2022-06-23 2023-06-02 合肥维信诺科技有限公司 Driving method and driving device of display panel and display device
WO2024007818A1 (en) * 2022-07-04 2024-01-11 华为技术有限公司 Display driving circuit, integrated circuit, oled screen, device and method

Also Published As

Publication number Publication date
CN114038429B (en) 2023-06-13

Similar Documents

Publication Publication Date Title
CN114038429B (en) Display panel, driving method and display device
KR102482335B1 (en) Display apparatus, method of driving display panel using the same
US20240119897A1 (en) Pixel Circuit and Driving Method Therefor and Display Panel
JP5611312B2 (en) Organic light emitting diode display device and driving method thereof
CN113053281B (en) Pixel driving circuit and electroluminescent display device including the same
CN108630151B (en) Pixel circuit, driving method thereof, array substrate and display device
WO2019062579A1 (en) Pixel circuit and driving method thereof, and display device
US20240062721A1 (en) Pixel Circuit and Driving Method Thereof, and Display Panel
KR20190142791A (en) Display apparatus
CN112289269A (en) Pixel circuit, control method thereof and display panel
KR20220155537A (en) Pixel and display device having the same
GB2620507A (en) Pixel circuit and driving method therefor and display panel
CN112365843B (en) Pixel driving circuit and driving method thereof, display panel and device
US20230154405A1 (en) Display device, driving circuit and display driving method
US20230143178A1 (en) Display device and data driving circuit
US20230335053A1 (en) Display panel and display device
US11626079B2 (en) Display device and method for driving the same
JP2024514718A (en) Pixel circuit, backlight module and display panel
KR20230060774A (en) Electroluminescent display device and driving method for the same
KR20140056697A (en) Organic light emitting diode display and method of driving the same
KR20180078932A (en) Method for driving organic light emitting diode display device
US20100214274A1 (en) Active-matrix display panel and device, and method for driving same
US11929025B2 (en) Display device comprising pixel driving circuit
US11996046B2 (en) Display panel and operation method thereof
US11929026B2 (en) Display device comprising pixel driving circuit

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant