CN114863875A

CN114863875A - Display panel, driving method thereof and display device

Info

Publication number: CN114863875A
Application number: CN202210577713.9A
Authority: CN
Inventors: 李玥; 张蒙蒙; 周星耀; 黄高军; 张鹏
Original assignee: Wuhan Tianma Microelectronics Co Ltd
Current assignee: Wuhan Tianma Microelectronics Co Ltd
Priority date: 2022-05-25
Filing date: 2022-05-25
Publication date: 2022-08-05
Anticipated expiration: 2042-05-25
Also published as: CN114863875B

Abstract

The invention discloses a display panel, a driving method thereof and a display device, wherein the display panel comprises: the display device comprises sub-pixels arranged in an array, a data line group and a control module, wherein the control module is respectively electrically connected with a 1 st data line to an Mth data line and is used for controlling the 1 st data line to the Mth data line to transmit a first data signal before line scanning, and the first data signal is used for resetting a first pole of a driving transistor and a second pole of the driving transistor. The first data signal is transmitted to the sub-pixels before the line scanning so as to reset the first pole of the driving transistor and the second pole of the driving transistor at the beginning of the line scanning, thereby being beneficial to avoiding the problems of hysteresis effect and residual shadow of the driving transistor and improving the display quality.

Description

Display panel, driving method thereof and display device

Technical Field

The invention relates to the technical field of display, in particular to a display panel, a driving method thereof and a display device.

Background

In the Display technology, an Organic Light-Emitting diode (Organic Light-Emitting Display OLED) Display panel has the advantages of self-luminescence, high luminous efficiency, short response time, low power consumption, wide viewing angle, rich colors, high brightness, wide temperature range of use, flexible Display and the like, and is considered as a Display panel with the most potential development in the industry.

The sub-pixels of the organic light emitting diode display panel are provided with a pixel driving circuit, the pixel driving circuit is provided with a driving transistor for driving the organic light emitting diode to emit light, the continuous working time of the organic light emitting diode display panel is prolonged or other factors can cause the threshold voltage of the driving transistor to shift, and when the threshold voltage of the driving transistor shifts, the display effect of the organic light emitting diode display panel is reduced, so that when the organic light emitting diode display panel is used, the threshold voltage of the driving transistor needs to be reset, and the display quality of the organic light emitting diode display panel is prevented from being reduced.

Therefore, a display panel, a driving method thereof and a display device capable of resetting a threshold voltage are needed.

Disclosure of Invention

In view of this, the present invention provides a display panel, a driving method thereof and a display device, so as to reset a threshold voltage and avoid a problem of hysteresis of a driving transistor.

In one aspect, the present invention provides a display panel, comprising:

the array-arranged sub-pixels comprise pixel driving units, and the pixel driving units comprise driving transistors; the sub-pixels are arranged along a first direction to form pixel rows, the sub-pixels are arranged along a second direction to form pixel columns, and the first direction is crossed with the second direction; the pixel rows comprise row repeating groups arranged along the second direction, the row repeating groups comprise 1 st pixel row to M th pixel row which are sequentially arranged along the second direction, M is a positive integer and is more than or equal to 2;

a data line group, disposed corresponding to the sub-pixel column, including a 1 st data line to an mth data line sequentially arranged along the first direction, where the 1 st data line is electrically connected … with the sub-pixels of the 1 st pixel row, and the mth data line is electrically connected with the sub-pixels of the mth pixel row;

and the control module is electrically connected with the 1 st data line and the Mth data line respectively and used for controlling the 1 st data line and the Mth data line to transmit a first data signal before line scanning, wherein the first data signal is used for resetting the first pole of the driving transistor and the second pole of the driving transistor.

In another aspect, the present invention also provides a driving method of a display panel, the display panel including:

the control module is electrically connected with the 1 st data line to the Mth data line respectively;

the time for driving one row of the pixel rows comprises a row scanning time and a first time period before the row scanning time, and in the first time period, the control module controls the 1 st data line to the Mth data line to transmit a first data signal, wherein the first data signal is used for resetting the first pole of the driving transistor and the second pole of the driving transistor.

In another aspect, the present invention further provides a display device including the display panel.

Compared with the prior art, the display panel provided by the invention at least realizes the following beneficial effects:

and the control module is electrically connected with the 1 st data line to the Mth data line respectively and is used for controlling the 1 st data line to the Mth data line to transmit a first data signal before line scanning, and the first data signal is used for resetting the first pole of the driving transistor and the second pole of the driving transistor. The threshold voltage shift may be formed by a gate bias of the driving transistor or a forward current in the driving transistor, and the first data signal is provided before the row scan to reset the first electrode of the driving transistor and the second electrode of the driving transistor, so that the first electrode of the driving transistor and the second electrode of the driving transistor are reset before the row scan starts, which is helpful to avoid the problem of residual image caused by hysteresis effect of the driving transistor and improve the display quality.

Of course, it is not necessary for any product in which the present invention is practiced to achieve all of the above-described technical effects simultaneously.

Other features of the present invention and advantages thereof will become apparent from the following detailed description of exemplary embodiments thereof, which proceeds with reference to the accompanying drawings.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description, serve to explain the principles of the invention.

FIG. 1 is a schematic diagram of a display panel in the prior art;

FIG. 2 is a schematic structural diagram of a display panel according to the present invention;

FIG. 3 is a schematic diagram of a pixel driving unit according to the present invention;

FIG. 4 is a schematic structural diagram of another display panel according to the present invention;

FIG. 5 is a schematic structural diagram of another display panel provided in the present invention;

FIG. 6 is a schematic diagram of another pixel driving unit structure provided by the present invention;

FIG. 7 is a schematic diagram of a pixel driving unit according to another embodiment of the present invention;

FIG. 8 is a timing diagram of the pixel driving unit of FIG. 3;

FIG. 9 is a timing diagram of the pixel driving unit of FIG. 6;

FIG. 10 is another timing diagram of the pixel driving unit of FIG. 6;

fig. 11 is a schematic structural diagram of a display device according to the present invention.

Detailed Description

Various exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be noted that: the relative arrangement of the components and steps, the numerical expressions and numerical values set forth in these embodiments do not limit the scope of the present invention unless specifically stated otherwise.

The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the invention, its application, or uses.

Techniques, methods, and apparatus known to one of ordinary skill in the relevant art may not be discussed in detail but are intended to be part of the specification where appropriate.

In all examples shown and discussed herein, any particular value should be construed as merely illustrative, and not limiting. Thus, other examples of the exemplary embodiments may have different values.

It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, further discussion thereof is not required in subsequent figures.

Referring to fig. 1, fig. 1 is a schematic structural diagram of a display panel in the prior art, a plurality of scan lines (G1 '… GI') extending along a first direction X and arranged along a second direction Y are included in the display panel 000, a plurality of data lines (D1 '… DJ') extending along the second direction Y and arranged along the first direction X are included in the display panel 000, and the scan lines (G1 '… GI') and the data lines (D1 '… DJ') intersect to define a pixel unit 01. When the display panel 000 is driven, the pixel units 01 are driven row by row, specifically, the scanning signal is supplied to the scanning line G1 'of the first row first, the data line (D1' … DJ ') charges the pixel units 01 of the first row, then the scanning signal is supplied to the scanning line G2' of the second row, the data line (D1 '… DJ') charges the pixel units 01 of the second row, and so on. As the display panel 000 is developed toward high resolution, the number of pixel units 01 increases, resulting in a shorter time to scan a row of pixel units 01, and a reduction in threshold voltage compensation time when driving the pixel units 01, resulting in insufficient threshold compensation and a reduction in display quality.

In view of the above, the present invention provides a display panel, a driving method thereof and a display device, which are used to reset a threshold voltage and avoid the problem of hysteresis of a driving transistor.

Referring to fig. 2 and 3, fig. 2 is a schematic structural diagram of a display panel provided in the present invention, fig. 3 is a schematic structural diagram of a pixel driving unit provided in the present invention, and the display panel 100 includes:

a subpixel 02 arranged in an array, the subpixel 02 including a pixel driving unit 03, the pixel driving unit 03 including a driving transistor 04; the sub-pixels 02 are arranged along a first direction X to form a pixel row 05, the sub-pixels 02 are arranged along a second direction Y to form a pixel column 06, and the first direction X intersects the second direction Y; the pixel row 05 comprises a row repeating group 07 arranged along the second direction Y, the row repeating group 07 comprises a 1 st pixel row L1 to an Mth pixel row LM which are sequentially arranged along the second direction Y, M is a positive integer and is more than or equal to 2;

the data line group 08 is arranged corresponding to the subpixel 02 column and comprises a 1 st data line D1 to an Mth data line DM which are sequentially arranged along the first direction X, and the 1 st data line D1 is electrically connected … with the subpixels 02 of the 1 st pixel row L1, and the Mth data line DM is electrically connected with the subpixels 02 of the Mth pixel row LM;

the control module 09 is electrically connected to the 1 st data line D1 to the mth data line DM, respectively, and is configured to control the 1 st data line D1 to the mth data line DM to transmit a first data signal before the row scan, where the first data signal is used to reset the first electrode N1 of the driving transistor 04 and the second electrode N2 of the driving transistor 04.

It should be noted that, in fig. 2, only the row repeating group 07 includes three pixel rows 05, the data line group 08 includes 3 data lines, and the control module 09 is located at the lower edge of the sub-pixels 02 arranged in an array, specifically, the number of the sub-pixels 02, the arrangement manner of the sub-pixels 02 in the array, the number of the row repeating group 07, the number of the data line group 08, the number of the pixel rows 05 in the row repeating group 07, the number of the data lines in the data line group 08, and the position of the control module 09 may be adjusted according to actual requirements, and are not limited thereto.

Referring to fig. 2, the control module 09 is electrically connected to the 1 st data line D1 to the mth data line DM, that is, the control module 09 can control the 1 st data line D1 to the mth data line DM to simultaneously transmit data signals, and also can control the 1 st data line D1 to the mth data line DM to time-divisionally transmit data signals, since the pixel row 05 in the row repeating group 07 and the data line in the data line group 08 are correspondingly disposed and connected, the data signals can be transmitted to the sub-pixels 02 in the row repeating group 07 simultaneously, or the data signals can be transmitted to the sub-pixels 02 in the row repeating group 07 in time-divisionally, where the data signals include the first data signals.

Specifically, the line period H is the time required for scanning one line of pixel rows 05, and the calculation method of the line period H is calculated according to the following method:

h ═ 1 s/refresh frequency)/(number of pixel row lines + front and back porches);

where H is a line period, s is a time unit, and s is a second, in this embodiment, the line period H includes a line scanning time, and the line scanning time is a time for providing a signal to the gate driving circuit. The first case of the shift of the threshold voltage is due to the gate bias of the driving transistor 04, the second case is due to the forward current in the driving transistor 04, the control module 09 controls the 1 st data line D1 to the M th data line DM to transmit the first data signal before the line scanning time, the first data signal is transmitted to the first pole N1 (source) of the driving transistor 04 before the line scanning, when the line scanning starts, the first data signal can immediately reset the first pole N1 of the driving transistor 04 and the second pole N2 of the driving transistor 04, the first pole N1 of the driving transistor 04 and the second pole N2 of the driving transistor 04 are the source and drain of the driving transistor, that is, the threshold voltage is compensated for the second case, the problems of hysteresis effect, image sticking and the like of the driving transistor 04 can be improved, and noise in displaying the image can be avoided, and the display effect is improved.

Compared with the prior art, the display panel 100 provided by the invention has the following beneficial effects:

the control module 09 is electrically connected to the 1 st data line D1 to the mth data line DM, respectively, and is configured to control the 1 st data line D1 to the mth data line DM to transmit a first data signal before the row scan, where the first data signal is used to reset the first electrode N1 of the driving transistor 04 and the second electrode N2 of the driving transistor 04. The shift of the threshold voltage may be caused by the gate bias of the driving transistor 04, or may be caused by the forward current in the driving transistor 04, and the first data signal is provided before the row scan to reset the first electrode N1 of the driving transistor 04 and the second electrode N2 of the driving transistor 04, so as to reset the first electrode N1 of the driving transistor 04 and the second electrode N2 of the driving transistor 04 at the beginning of the row scan, which is helpful to avoid the problem of hysteresis effect and image sticking of the driving transistor 04, and improve the display quality.

In some optional embodiments, referring to fig. 4, fig. 4 is a schematic structural diagram of another display panel provided in the present invention, and the control module 09 includes:

the switch group 10 comprises a 1 st switch K1 to an Mth switch KM, wherein the output end of the 1 st switch K1 is electrically connected with a 1 st data line D1, and the output end of … the Mth switch KM is electrically connected with an Mth data line DM;

the signal line group 11 includes a 1 st signal line CKH1 through an M th signal line CKHM, and the 1 st signal line CKH1 is electrically connected … to the control terminal of the 1 st switch K1, and the M th signal line CKHM is electrically connected to the control terminal of the M th switch KM.

It should be noted that, in fig. 3, only the row repeating group 07 includes two pixel rows 05, the data line group 08 includes two data lines, and the switch group 10 includes two switches, but of course, the number of pixel rows 05 in the row repeating group 07, the number of data lines in the data line group 08, and the number of switches in the switch group 10 may be adjusted as long as the number of pixel rows 05 in the row repeating group 07, the number of data lines in the data line group 08, and the number of switches in the switch group 10 are correspondingly set.

It is understood that, taking M >2 as an example, when the control data line group 08 simultaneously transmits data signals to the sub-pixels 02, the 1 st switch K1 to the mth switch KM are simultaneously turned on, and the 1 st data line D1 to the mth data line DM simultaneously transmit data signals to the sub-pixels 02; when the data line group 08 is controlled to transmit data signals to the sub-pixels 02 in the row repeating unit in a time-sharing manner, the 1 st switch K1 is firstly turned on, the 1 st data line D1 transmits data signals to the 1 st pixel row L1, then the 2 nd switch is turned on, the 2 nd data line transmits data signals to the second pixel row 05, and so on. The signal line group 11 controls the switches in the switch group 10 to be turned on simultaneously or in a time-sharing manner, and further controls the data line group 08 to transmit the data signals to the sub-pixels 02 in the row repeating unit simultaneously, or controls the data line group 08 to transmit the data signals to the sub-pixels 02 in the row repeating unit in a time-sharing manner.

In some optional embodiments, with continued reference to fig. 4, the display panel 100 provided in this embodiment further includes: a driver chip 12; the 1 st switch K1 to the mth switch KM are all a first transistor M1, a first pole of the first transistor M1 is electrically connected to the nth data line, N is an integer and is not less than 1 and not more than M, a gate of the first transistor M1 is electrically connected to the nth signal line, and a second pole of the first transistor M1 is electrically connected to the driving chip 12.

It should be noted that fig. 4 only illustrates that the driving chip 12 is located at the lower edge position of the sub-pixels 02 arranged in an array, and fig. 4 also illustrates that in one switch group 10, the second pole of the first transistor M1 is electrically connected to the driving chip 12 after being connected in parallel, but is not limited thereto. In accordance with the characteristics of the transistors, the transistors may be divided into N-type transistors and P-type transistors, the active level of the N-type transistors is high level, the active level of the P-type transistors is low level, fig. 4 only shows that the first transistor M1 is a P-type transistor, the first electrode of the first transistor M1 is a drain electrode, and the second electrode of the first transistor M1 is a source electrode, but the present invention is not limited thereto.

It will be appreciated that the driver chip 12 is arranged to provide a data signal to the driver transistor 04 during the row period H. When the gate of the first transistor M1 of the nth switch receives the enable signal transmitted by the nth signal line, the first transistor M1 of the nth switch is turned on, the nth data line receives the data signal provided by the driving chip 12, and the nth data line transmits the data signal to the corresponding subpixel 02, so as to implement precise control of data signal transmission.

In some optional embodiments, referring to fig. 5, fig. 5 is a schematic structural diagram of another display panel provided in the present invention, and the display panel 100 provided in this embodiment further includes:

the gate driving circuit 14 includes a plurality of first shift registers Scan1, the gate driving circuit 15 includes a plurality of second shift registers Scan2, and the row repeating group 07 is in one-to-one correspondence with and electrically connected to the first shift registers Scan1 and the second shift registers Scan2, respectively.

It should be understood that only one row repeating group 07 is illustrated in fig. 5 as including two pixel rows 05, and the first gate driving circuit 14 and the second gate driving circuit 15 are located at the same side of the sub-pixels 02 arranged in an array, of course, one row repeating group 07 may also include a plurality of pixel rows 05, and the first gate driving circuit 14 and the second gate driving circuit 15 are respectively located at two sides of the sub-pixels 02 arranged in an array, which is not limited thereto.

Specifically, one row repeating group 07 is respectively in one-to-one correspondence with and electrically connected to the first shift register Scan1 and the second shift register Scan2, that is, one row repeating group 07 is electrically connected to one first shift register Scan1, and one row repeating group 07 is electrically connected to one second shift register Scan 2. In the display process, the first shift register Scan1 and the second shift register Scan2 provide different scanning driving signals, and the first shift register Scan1 and the second shift register Scan2 provide the scanning driving signals, and can transmit the scanning driving signals to the M pixel rows 05 at the same time, on this basis, the data line group 08 provides the data signals in a time-sharing manner, so as to realize line-by-line lighting of the M pixel rows 05, and the number of the first shift register Scan1 and the second shift register Scan2 required for driving the sub-pixels 02 is reduced by one-to-one correspondence and electrical connection of the row repeating group 07 with the first shift register Scan1 and the second shift register Scan2, so that the wiring and connection of the edges of the sub-pixels 02 arranged in an array are simplified, and a frame is reduced.

In some optional embodiments, with continued reference to fig. 5, the display panel 100 provided in this embodiment further includes:

arranging a scanning line group 18 along the second direction Y, wherein the scanning line group 18 is arranged corresponding to the pixel row 05, the scanning line group 18 comprises a first scanning line 19 and a second scanning line 20 which are sequentially arranged along the second direction Y, one end of the first scanning line 19 is electrically connected with the first shift register Scan1, and the first scanning line 19 is electrically connected with all the sub-pixels 02 of the pixel row 05; one end of the second Scan line 20 is electrically connected to the second shift register Scan2, and the second Scan line 20 is electrically connected to all the sub-pixels 02 of the pixel row 05.

It is understood that only one wiring manner of the Scan line group 18 is provided in fig. 5, but not limited thereto, since the first and second shift registers Scan1 and Scan2 provide different Scan driving signals, and the sub-pixel 02 is electrically connected to the first shift register Scan1 through the first Scan line 19 and the second shift register Scan2 through the second Scan line 20, the arrangement is reasonable, and the crosstalk between the Scan driving signal provided by the first shift register 16 and the Scan driving signal provided by the second shift register Scan2 is avoided.

In some alternative embodiments, with continued reference to fig. 2 and 3, the pixel driving unit 03 further comprises:

a first power supply voltage signal terminal PVDD for providing a first power supply voltage;

a second power supply voltage signal terminal PVEE for providing a second power supply voltage, wherein the second power supply voltage is less than the first power supply voltage;

a driving transistor 04 and a light emitting element 21 connected in series to a first power supply voltage signal terminal PVDD and a second power supply voltage signal terminal PVEE;

a first initialization module 22, configured to initialize the gate of the driving transistor 04;

a data writing module 23, configured to write a first data signal and a second data signal into the driving transistor 04, respectively;

and a light emitting control module 24 for controlling the light emitting element 21 to emit light.

It should be noted that fig. 3 only illustrates a structural schematic diagram of the pixel driving unit 03, and in some other embodiments of the present application, the structural schematic diagram of the pixel driving circuit 03 may also be embodied as another example, which is not specifically limited in the present application.

It is to be understood that the driving transistor 04 shown in fig. 3 is a P-type transistor, but is not limited thereto, and the stage of driving the pixel driving unit 03 includes a data writing stage and a stage of maintaining the light emitting element 21 to emit light, and preparation work is performed on the pixel driving unit 03 in the data writing stage, such as initialization and data writing on the gate of the driving transistor 04 in the pixel driving unit 03. Before the data writing stage, the signal line group 11 provides a first data signal for resetting the first pole N1 of the driving transistor 04 and the second pole N2 of the driving transistor 04 in the pixel driving circuit, and initializes the gate of the driving transistor 04 in the pixel driving circuit in the data writing stage, so that the problems of hysteresis effect, residual image and the like of the driving transistor 04 can be further improved by compensating the threshold voltage twice, noise is prevented from occurring when a picture is displayed, and the display effect is improved.

In some alternative embodiments, referring to fig. 5 and fig. 6, fig. 6 is a schematic structural diagram of another pixel driving unit provided by the present invention, the data writing module 23 includes a second transistor M2, a gate of the second transistor M2 is electrically connected to the second scan line 20, a first pole of the second transistor M2 is electrically connected to an nth data line, N is an integer and is greater than or equal to 1 and less than or equal to N and less than or equal to M, and a second pole of the second transistor M2 is electrically connected to a first pole N1 of the driving transistor 04;

the light emission control module 24 includes a third transistor M3, a gate of the third transistor M3 is electrically connected to the light emission signal input terminal 13, a first pole of the third transistor M3 is electrically connected to the second pole N2 of the driving transistor 04, and a second pole of the third transistor M3 is electrically connected to the anode of the light emitting element 21;

the first initialization block 22 includes a fourth transistor M4, a gate of the fourth transistor M4 is electrically connected to the first scan line 19, a first pole of the fourth transistor M4 is electrically connected to the first reference voltage signal terminal Vref1, and a second pole of the fourth transistor M4 is electrically connected to the gate of the driving transistor 04.

It should be noted that, in fig. 6, only the second transistor M2, the third transistor M3 and the fourth transistor M4 are illustrated as P-type transistors, and the data writing module 23, the light-emitting control module 24 and the first initialization module 22 include only one transistor, but the invention is not limited thereto, and the light-emitting control module 24 may further include a seventh transistor M7, a first pole of the seventh transistor M7 is electrically connected to the first power supply voltage signal terminal PVDD, a second pole of the seventh transistor M7 is electrically connected to the first pole N1 of the driving transistor 04, and a gate of the seventh transistor M7 is electrically connected to the light-emitting signal input terminal 13, and of course, the invention may further include a storage capacitor 16, one plate of the storage capacitor 16 is electrically connected to the first power supply voltage signal terminal PVDD, and the other plate is electrically connected to the gate of the driving transistor 04, which the embodiment is not limited thereto. In fig. 6, only the first pole of the second transistor M2 is shown as the source, and the second pole of the second transistor M2 is shown as the drain; a first electrode of the third transistor M3 is a source electrode, and a second electrode of the third transistor M3 is a drain electrode; a source electrode of the fourth transistor M4, a drain electrode of the fourth transistor M4; the first pole of the seventh transistor M7 is the source, and the second pole of the seventh transistor M7 is the drain.

It can be understood that, before the row scanning, the signal line group 11 controls the data line group 08 to simultaneously transmit the first data signal, the nth data line outputs the first data signal to the first pole of the second transistor M2, when the row scanning is started, the second Scan line 20 transmits the enable signal provided by the second shift register Scan2, the gate of the second transistor M2 receives the second enable signal to turn on, the first data signal is input to the first pole N1 of the driving transistor 04, the first pole N1 of the driving transistor 04 and the second pole N2 of the driving transistor 04 are reset, that is, the row scanning starts, the threshold voltage of the driving transistor 04 is reset immediately, the threshold voltage of the driving transistor 04 is compensated more fully, the hysteresis effect is avoided, the image sticking is caused, and the display effect is improved.

In some alternative embodiments, referring to fig. 5 and fig. 7, fig. 7 is a schematic structural diagram of another pixel driving unit provided by the present invention, and the pixel driving unit 03 further includes:

the threshold compensation module 25 comprises a fifth transistor M5, a gate of the fifth transistor M5 is electrically connected to the second scan line 20, a first pole of the fifth transistor M5 is electrically connected to the second pole N2 of the driving transistor 04, and a second pole of the fifth transistor M5 is electrically connected to the gate of the driving transistor 04;

the second initialization module 26 includes a sixth transistor M6, a gate of the sixth transistor M6 is electrically connected to the first scan line 19, a first pole of the sixth transistor M6 is electrically connected to the input terminal of the second reference voltage signal Vref2, and a second pole of the sixth transistor M6 is electrically connected to the anode of the light emitting device 21.

It is understood that the first electrode of the fifth transistor M5 is a source electrode, and the second electrode of the fifth transistor M5 is a drain electrode; the first pole of the sixth transistor M6 is the drain, and the second pole of the sixth transistor M6 is the source, the threshold compensation module 25 in this embodiment can raise the potential of the gate of the driving transistor 04, so as to better maintain the potential of the gate of the driving transistor 04, especially when the pixel driving unit 03 includes the storage capacitor 16, the drain of the storage capacitor 16 may cause the potential of the gate of the driving transistor 04 to drop, the threshold compensation module 25 is configured to improve the potential drop of the gate of the driving transistor 04, which may cause the display panel 100 to flicker, and the second initialization module 26 may reset the anode of the light emitting element 21.

In some alternative embodiments, referring to fig. 2, fig. 3 and fig. 8, fig. 8 is a timing diagram of the pixel driving unit in fig. 3, and the display panel 100 in this embodiment includes:

the control module 09 is electrically connected with the 1 st data line D1 to the mth data line DM respectively;

the time for driving a row of pixel lines 05 includes a row scanning time and a first time period T1 before the row scanning time, and in the first time period T1, the control module 09 controls the 1 st data line D1 to the M-th data line DM to transmit a first data signal, which is used for resetting the first pole N1 of the driving transistor 04 and the second pole N2 of the driving transistor 04.

It can be understood that, the structure of the display panel 100 in this embodiment has been described in detail above, and is not described herein too much, the time for driving a row of pixel rows 05 is a row period H, the row scanning time is the time for providing a signal to the gate driving circuit, before the signal is provided by the gate driving circuit, the control module 09 controls the 1 st data line D1 to the M th data line DM to transmit the first data signal, so that when the row scanning time is turned on, that is, when the signal is transmitted by the scanning line, the first data signal is transmitted to the driving transistor 04 immediately, and the first pole N1 of the driving transistor 04 and the second pole N2 of the driving transistor 04 are reset, so as to implement the threshold voltage compensation of the driving transistor 04, and avoid the occurrence of the hysteresis effect and the influence on the display effect.

In some alternative embodiments, with continued reference to fig. 3, 5, and 8, the display panel 100 further comprises:

a driver chip 12;

a signal line group 11, including a 1 st signal line CKH1 through an M th signal line CKHM, wherein the 1 st signal line CKH1 is electrically connected … with the control terminal of the 1 st switch K1, and the M th signal line CKHM is electrically connected with the control terminal of the M th switch KM;

the 1 st switch K1 to the Mth switch KM are all a first transistor M1, the first pole of the first transistor M1 is electrically connected with the Nth data line, N is an integer and is more than or equal to 1 and less than or equal to M, the grid electrode of the first transistor M1 is electrically connected with the Nth signal line, and the second pole of the first transistor M1 is electrically connected with the driving chip 12;

during the first time period T1, the 1 st signal line CKH1 to the M th signal line CKHM input a first enable signal to the gate of the corresponding first transistor M1 at the same time, so that the 1 st switch K1 to the M th switch KM are turned on at the same time in response to the first enable signal;

the 1 st data line D1 to the mth data line DM simultaneously respond to and transmit the first data signal provided by the driving chip 12, and write the first data signal into the data writing module 23 correspondingly.

It is understood that, when the driving chip 12 provides the data signals to the data line group 08, the data signals include a first data signal and a second data signal, and when the 1 st signal line CKH1 to the M th signal line CKHM simultaneously provide the first enable signal to the 1 st switch K1 to the M th switch, the gate of the first transistor M1 is turned on corresponding to the first enable signal, the first data signal can be simultaneously transmitted to the data writing module 23, and the transmission of the data signal can be precisely controlled.

In some alternative embodiments, referring to fig. 5, fig. 6 and fig. 9, fig. 9 is a timing diagram of the pixel driving unit in fig. 6, and the display panel 100 in this embodiment further includes:

the second gate driving circuit 15, the second gate driving circuit 15 includes a plurality of second shift registers Scan2, and the row repeating group 07 is in one-to-one correspondence with and electrically connected to the second shift registers Scan 2;

a second Scan line 20, where the second Scan line 20 is disposed corresponding to the pixel row 05, one end of the second Scan line 20 is electrically connected to the second shift register Scan2, and the second Scan line 20 is electrically connected to all the sub-pixels 02 of the pixel row 05;

the pixel driving unit 03 includes:

the data writing module 23 comprises a second transistor M2, a gate of the second transistor M2 is electrically connected to the second scan line 20, a first pole of the second transistor M2 is electrically connected to the nth data line, N is an integer and is not less than 1 and not more than M, and a second pole of the second transistor M2 is electrically connected to the first pole N1 of the driving transistor 04;

the line scan time includes a second period T2, a third period T3, and a fourth period T4;

in the second time period T2, the data writing module 23 is turned on in response to the second enable signal of the second scan line 20, writes the first data signal into the first pole N1 of the driving transistor 04 and the second pole N2 of the driving transistor 04, and resets the first pole N1 of the driving transistor 04 and the second pole N2 of the driving transistor 04;

during a third time period T3, the 1 st signal line CKH1 to the M th signal line CKHM sequentially input a third enable signal to the gate of the corresponding first transistor M1, so that the 1 st switch K1 to the M th switch KM are sequentially turned on in response to the third enable signal;

the 1 st data line D1 to the mth data line DM sequentially respond to and transmit the second data signal provided by the driving chip 12, and write the second data signal into the data writing module 23 correspondingly;

in the fourth time period T4, the data writing module 23 is turned on in response to the fourth enable signal of the second scan line 20, writes the second data signal into the corresponding driving transistor 04, and sequentially emits light in the 1 st pixel row L1 to the M th pixel row LM.

It is understood that, in fig. 6, only the data writing module 23 is illustrated to include the second transistor M2, the gate of the second transistor M2 is electrically connected to the second scan line 20, the first pole of the second transistor M2 is electrically connected to the nth data line, N is an integer and is greater than or equal to 1 and less than or equal to N and less than or equal to M, and the second pole of the second transistor M2 is electrically connected to the first pole N1 of the driving transistor 04; the light emission control module 24 includes a third transistor M3, a gate of the third transistor M3 is electrically connected to the light emission signal input terminal 13, a first pole of the third transistor M3 is electrically connected to the second pole N2 of the driving transistor 04, and a second pole of the third transistor M3 is electrically connected to the anode of the light emitting element 21; the first initialization block 22 includes a fourth transistor M4, a gate of the fourth transistor M4 is electrically connected to the first scan line 19, a first pole of the fourth transistor M4 is electrically connected to the first reference voltage signal terminal Vref1, and a second pole of the fourth transistor M4 is electrically connected to the gate of the driving transistor 04. A first power supply voltage signal terminal PVDD for providing a first power supply voltage; a second power supply voltage signal terminal PVEE for supplying a second power supply voltage, the light emission signal input terminal 13 for supplying a light emission signal, the display panel 100 further includes a light emission signal line, only the row repeating group 07 is illustrated in fig. 5 as including two pixel rows 05, so that the light emission signal line includes a first light emission signal line E1 and a second light emission signal line E2, the first light emission signal line E1 is electrically connected to all the sub-pixels 02 of the 1 st pixel row L1, specifically, to the light emission signal input terminal 13 of the pixel driving unit 03 of the sub-pixel 02, and the first light emission signal line E1 transmits a first light emission signal EMIT 1; the second light-emitting signal line E2 is electrically connected to all the sub-pixels 02 of the 2 nd pixel row L2, specifically, to the light-emitting signal input terminal 13 of the pixel driving unit 03 of the sub-pixel 02, and the second light-emitting signal line E2 transmits the second light-emitting signal EMIT 2. Referring to fig. 9, the first light emitting signal EMIT1 is at a low level, the low level is at an active level, and the second light emitting signal EMIT2 is at a high level in the first row period H, and the 1 st pixel row L1 is lit up in the first row period H. In the second line period H, the first light emitting signal EMIT1 is at a high level, the second light emitting signal EMIT2 is at a low level, and the 2 nd pixel line L2 is lit up in the second line period H. Specifically, taking the first row period H as an example, in the second time period T2, the second transistor M2 receives the second enable signal transmitted by the second scan line 20 to turn on, transmits the first data signal that has been transmitted to the first pole of the second transistor M2 to the first pole N1 of the driving transistor 04 and the second pole N2 of the driving transistor 04, and resets the first pole N1 of the driving transistor 04 and the second pole N2 of the driving transistor 04; in a third time period T3, since the first shift register Scan1 and the second shift register Scan2 Scan M pixel rows 05 at the same time, it is necessary to sequentially transmit a second data signal to the 1 st data line D1 to the M th data line DM for data writing, so that the square wave signals have regularity, specifically, the 1 st signal line CKH1 to the M th signal line CKHM sequentially provide a third enable signal, and the first transistor M1 in the 1 st switch K1 to the M th switch KM sequentially receives the third enable signal and is sequentially turned on; during the fourth time period T4, the second transistor M2 receives the fourth enable signal transmitted by the second scan line 20 to turn on, transmits the second data signal transmitted to the first electrode of the second transistor M2 to write into the gate of the driving transistor 04, the light-emitting signal input terminal 13 in the pixel driving unit 03 of the sub-pixel 02 in the 1 st pixel row L1 receives the first light-emitting signal EMIT1, and during the fourth time period T4, the first power voltage signal terminal PVDD is turned on to the second power voltage signal terminal PVEE, so that the current flows through the light-emitting element 21 to light the light-emitting element 21.

In some alternative embodiments, with continuing reference to fig. 5, 6, and 9, the display panel 100 of the present embodiment includes:

the first gate driving circuit 14, the first gate driving circuit 14 includes a plurality of first shift registers Scan1, the row repeating group 07 is in one-to-one correspondence with and electrically connected to the first shift registers Scan 1;

the first scanning line 19 is arranged corresponding to the pixel row 05, one end of the first scanning line 19 is electrically connected with the first shift register Scan1, and the first scanning line 19 is electrically connected with all the sub-pixels 02 of the pixel row 05;

the pixel driving circuit further includes:

a light emitting element 21;

the first initialization module 22 includes a fourth transistor M4, a gate of the fourth transistor M4 is electrically connected to the first scan line 19, a first pole of the fourth transistor M4 is electrically connected to the first reference voltage signal terminal Vref1, and a second pole of the fourth transistor M4 is electrically connected to the gate of the driving transistor 04;

the second initialization module 26 includes a sixth transistor M6, a gate of the sixth transistor M6 is electrically connected to the first scan line 19, a first pole of the sixth transistor M6 is electrically connected to the second reference voltage signal terminal Vref2, and a second pole of the sixth transistor M6 is electrically connected to the anode of the light emitting element 21;

in the third time period T3, the method further includes:

the first initialization module 22 turns on in response to the fifth enable signal of the first scan line 19, and transmits the first reference voltage Vref1 signal to the gate of the driving transistor 04; the second initialization module 26 is turned on in response to the sixth enable signal of the first scan line 19, and transmits the second reference voltage signal to the anode of the light emitting element 21.

It is understood that, during the third time period T3, the first initialization module 22 is turned on in response to the fifth enable signal transmitted by the first scan line 19, and transmits the first reference voltage signal to the gate of the driving transistor 04; the second initialization module 26 is turned on in response to the sixth enable signal transmitted by the first scan line 19, transmits the second reference voltage signal to the anode of the light emitting element 21, and since the first pole N1 of the driving transistor 04 and the second pole N2 of the driving transistor 04 have been reset in the second time period T2, and the gate of the driving transistor 04 is reset in the third time period T3, it is ensured that the threshold voltage of the driving transistor 04 is completely compensated, the problem of hysteresis effect and image retention of the driving transistor 04 is avoided, and the display quality is improved.

In some alternative embodiments, referring to fig. 5, 6 and 10, fig. 10 is another timing diagram of the pixel driving unit of fig. 6, in which the data line group 08 is floated during the second period T2 and the fourth period T4.

It can be understood that the data line group 08 floats in the second time period T2 and the fourth time period T4, so as to avoid crosstalk of data signals, and achieve better display effect.

Based on the same inventive concept, the present application further provides a display device, and fig. 11 is a schematic diagram of a display device provided in an embodiment of the present application, where the display device 200 includes the display panel 100 provided in any of the above embodiments of the present application. When the display device 200 in the present application includes the display panel 100 provided in any of the above embodiments, it is beneficial to avoid the hysteresis effect of the driving transistor 04 of the pixel driving unit 03. It should be noted that, for the embodiments of the display panel 100 provided in the embodiments of the present application, reference may be made to the above-mentioned embodiments of the display panel 100, and repeated descriptions are omitted. The display device 200 provided by the present application may be: any product or component with practical functions such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like.

According to the embodiment, the display panel provided by the invention at least has the following beneficial effects:

Although some specific embodiments of the present invention have been described in detail by way of examples, it should be understood by those skilled in the art that the above examples are for illustrative purposes only and are not intended to limit the scope of the present invention. It will be appreciated by those skilled in the art that modifications may be made to the above embodiments without departing from the scope and spirit of the invention. The scope of the invention is defined by the appended claims.

Claims

1. A display panel, comprising:

2. The display panel of claim 1, wherein the control module comprises:

a switch group including 1 st to Mth switches, an output terminal of the 1 st switch being electrically connected … with the 1 st data line and an output terminal of the Mth switch being electrically connected with the Mth data line;

and the signal line group comprises a 1 st signal line to an Mth signal line, wherein the 1 st signal line is electrically connected … with the control end of the 1 st switch, and the Mth signal line is electrically connected with the control end of the Mth switch.

3. The display panel according to claim 2, further comprising: a driving chip; the 1 st switch to the Mth switch are all first transistors, a first pole of each first transistor is electrically connected with an Nth data line, N is an integer and is more than or equal to 1 and less than or equal to M, a grid electrode of each first transistor is electrically connected with an Nth signal line, and a second pole of each first transistor is electrically connected with the driving chip.

4. The display panel according to claim 1, further comprising:

the grid driving circuit comprises a first grid driving circuit and a second grid driving circuit, the first grid driving circuit comprises a plurality of first shift registers, the second grid driving circuit comprises a plurality of second shift registers, and the row repeating groups are in one-to-one correspondence with the first shift registers and the second shift registers and are electrically connected with the first shift registers and the second shift registers.

5. The display panel according to claim 4, further comprising:

arranging a scanning line group along the second direction, wherein the scanning line group is arranged corresponding to the pixel rows and comprises a first scanning line and a second scanning line which are sequentially arranged along the second direction, one end of the first scanning line is electrically connected with the first shift register, and the first scanning line is electrically connected with all the sub-pixels of the pixel rows; one end of the second scanning line is electrically connected with the second shift register, and the second scanning line is electrically connected with all the sub-pixels of the pixel row.

6. The display panel according to claim 5, wherein the pixel driving unit further comprises:

a first power supply voltage signal terminal for providing a first power supply voltage;

a second power supply voltage signal terminal for providing a second power supply voltage, the second power supply voltage being less than the first power supply voltage;

the driving transistor and the light emitting element are connected in series between the first power supply voltage signal end and the second power supply voltage signal end;

the first initialization module is used for initializing the grid electrode of the driving transistor;

the data writing module is used for respectively writing the first data signal and the second data signal into the driving transistor;

and the light emitting control module is used for controlling the light emitting element to emit light.

7. The display panel according to claim 6, wherein the data writing module comprises a second transistor, a gate of the second transistor is electrically connected to the second scan line, a first pole of the second transistor is electrically connected to an Nth data line, N is an integer and is greater than or equal to 1 and less than or equal to N and less than or equal to M, and a second pole of the second transistor is electrically connected to the first pole of the driving transistor;

the light-emitting control module comprises a third transistor, wherein the grid electrode of the third transistor is electrically connected with a light-emitting signal input end, the first pole of the third transistor is electrically connected with the second pole of the driving transistor, and the second pole of the third transistor is electrically connected with the anode of the light-emitting element;

the first initialization module comprises a fourth transistor, a grid electrode of the fourth transistor is electrically connected with the first scanning line, a first electrode of the fourth transistor is electrically connected with a first reference voltage signal end, and a second electrode of the fourth transistor is electrically connected with a grid electrode of the driving transistor.

8. The display panel according to claim 6, wherein the pixel driving unit further comprises:

a threshold compensation module including a fifth transistor, a gate of the fifth transistor being electrically connected to the second scan line, a first pole of the fifth transistor being electrically connected to the second pole of the driving transistor, and a second pole of the fifth transistor being electrically connected to the gate of the driving transistor;

and the second initialization module comprises a sixth transistor, the grid electrode of the sixth transistor is electrically connected with the first scanning line, the first electrode of the sixth transistor is electrically connected with the second reference voltage signal end, and the second electrode of the sixth transistor is electrically connected with the anode of the light-emitting element.

9. A driving method of a display panel, the display panel comprising:

10. The method for driving a display panel according to claim 9, wherein the display panel further comprises:

a driving chip;

the signal line group comprises a 1 st signal line to an Mth signal line, wherein the 1 st signal line is electrically connected … with the control end of the 1 st switch, and the Mth signal line is electrically connected with the control end of the Mth switch;

the 1 st switch to the Mth switch are all first transistors, a first pole of each first transistor is electrically connected with an Nth data line, N is an integer and is more than or equal to 1 and less than or equal to M, a grid electrode of each first transistor is electrically connected with an Nth signal line, and a second pole of each first transistor is electrically connected with the driving chip;

in the first time period, the method further includes that the 1 st signal line to the Mth signal line simultaneously input a first enable signal to the corresponding gates of the first transistors, so that the 1 st switch to the Mth switch are turned on simultaneously in response to the first enable signal;

and the 1 st data line to the Mth data line respond to and transmit the first data signal provided by the driving chip at the same time, and correspondingly write the first data signal into the data writing module.

11. The method for driving a display panel according to claim 10, wherein the display panel further comprises:

the second grid driving circuit comprises a plurality of second shift registers, and the row repeating groups correspond to the second shift registers one by one and are electrically connected with the second shift registers;

the second scanning line is arranged corresponding to the pixel row, one end of the second scanning line is electrically connected with the second shift register, and the second scanning line is electrically connected with all the sub-pixels of the pixel row;

the pixel driving unit includes:

the data writing module comprises a second transistor, the grid electrode of the second transistor is electrically connected with the second scanning line, the first pole of the second transistor is electrically connected with the Nth data line, N is an integer and is not less than 1 and not more than M, and the second pole of the second transistor is electrically connected with the first pole of the driving transistor;

the line scan time includes a second time period, a third time period, and a fourth time period;

in the second time period, the data writing module is turned on in response to a second enable signal of the second scan line, writes the first data signal into the first pole of the driving transistor and the second pole of the driving transistor, and resets the first pole of the driving transistor and the second pole of the driving transistor;

in the third time period, the 1 st signal line to the mth signal line sequentially input a third enable signal to the gate of the corresponding first transistor, so that the 1 st switch to the mth switch are sequentially turned on in response to the third enable signal;

the 1 st data line to the Mth data line sequentially respond to and transmit a second data signal provided by the driving chip, and correspondingly write the second data signal into the data writing module;

in the fourth time period, the data writing module is turned on in response to a fourth enable signal of the second scan line, writes the second data signal into the corresponding driving transistor, and sequentially emits light from the 1 st pixel row to the M th pixel row.

12. The method for driving a display panel according to claim 11, wherein the display panel comprises:

the first grid driving circuit comprises a plurality of first shift registers, and the row repeating groups correspond to the first shift registers one by one and are electrically connected with the first shift registers;

the first scanning line is arranged corresponding to the pixel row, one end of the first scanning line is electrically connected with the first shift register, and the first scanning line is electrically connected with all the sub-pixels of the pixel row;

the pixel driving circuit further includes:

a light emitting element;

the first initialization module comprises a fourth transistor, wherein the grid electrode of the fourth transistor is electrically connected with the first scanning line, the first electrode of the fourth transistor is electrically connected with the first reference voltage signal end, and the second electrode of the fourth transistor is electrically connected with the grid electrode of the driving transistor;

a second initialization module including a sixth transistor, a gate of the sixth transistor being electrically connected to the first scan line, a first electrode of the sixth transistor being electrically connected to a second reference voltage signal terminal, and a second electrode of the sixth transistor being electrically connected to an anode of the light emitting element;

during the third time period, further comprising:

the first initialization module is turned on in response to a fifth enable signal of the first scan line, and transmits a first reference voltage signal to the gate of the driving transistor; the second initialization module is turned on in response to a sixth enable signal of the first scan line, and transmits a second reference voltage signal to an anode of the light emitting element.

13. The method for driving a display panel according to claim 11, wherein the data line group floats during the second period and the fourth period.

14. A display device comprising the display panel according to any one of claims 1 to 8.