TWI662535B - Pixel driving circuit and display apparatus thereof - Google Patents

Abstract

The invention relates to a pixel driving circuit for driving a pixel group composed of two adjacently arranged pixel units. The pixel driving circuit includes a driving module, a first switching module and a second switching module. The driving module includes a control terminal, a first connection terminal, a second connection terminal, and a driving transistor. The voltage on the side of the control terminal can store voltage, and the drive module is used to adjust and control the size of the electrical signal through the driving transistor according to the voltage stored on the side of the control terminal. The first switch module provides the driving current generated by the driving module to the first pixel unit according to the first control signal. The second switch module provides the driving current generated by the driving module to the second pixel unit according to the second control signal. The invention also provides a display device having a pixel driving circuit.

Description

Pixel driving circuit and display device with pixel driving circuit

The invention relates to a pixel driving circuit and a display device having the pixel driving circuit.

With the continuous development of electronic technology, most display devices such as mobile phones, portable computers, personal digital assistants (PDAs), tablet computers, and media players use display panels as input and output devices to make products more human-friendly. Dialogue mode. Organic light emitting diode (OLED) or micro light emitting diode (μ LED) as a light emitting device, because of its self-luminous, fast response, wide viewing angle and can be manufactured in Features such as flexible substrates are increasingly used in the field of high-performance displays. Display devices using OLEDs generally have a display area and a non-display area. Pixel units with matrix settings are set in the display area. Each pixel unit corresponds to a pixel driving circuit. A display driving circuit for driving the pixel driving circuit is provided in the non-display area. The pixel driving circuit includes a selection transistor, a driving transistor, a storage capacitor, and a light emitting element. When the size of the display becomes larger, as the number of pixel units increases, the size of the display driving circuit for driving the pixel driving circuit also increases correspondingly, thereby causing the area of the non-display area to be too large. As the design requirements for narrow bezels increase, the area of non-display areas shrinks. Therefore, the circuit structure of the display device needs to be simplified.

In view of this, it is necessary to provide a pixel driving circuit which is favorable for narrow frame design.

It is also necessary to provide a display device which is advantageous for narrow frame design.

A pixel driving circuit is used for driving a pixel group composed of two adjacently arranged pixel units. The pixel group includes a first pixel unit and a second pixel unit. The first pixel unit includes a first light emitting element, and the second pixel unit includes a second light emitting element. Each pixel driving circuit can drive a first pixel unit and a second pixel unit of the same pixel group. The pixel driving circuit includes a driving module, and the driving module is located in one of the pixel units of the same pixel group. Including the control terminal, the first connection terminal, the second connection terminal and the driving transistor, the side where the control terminal is located can store a voltage, and the driving module is used to adjust and control the voltage passing through the driving transistor according to the voltage stored on the side of the control terminal. The size of the electrical signal; the first switch module and the first light-emitting module are located in the first pixel unit of the same pixel group, and the driving current generated by the driving module is provided to the first light emitting device according to the loaded first control signal. Component; a second switch module, which is located in a second pixel unit of the same pixel group, and the second switch module provides the driving current generated by the driving module to the same pixel group according to the loaded second control signal A second light-emitting element; a common compensation module electrically connected to the control terminal for writing and storing a control terminal voltage for compensating the driving transistor according to a scan signal A data voltage; reset module, the reset module and the driving module electrically connected to the driving transistor in accordance with the received reset signal resetting state.

A display device with a pixel driving circuit is defined with a display area and a non-display area provided around the display area. The display area includes a plurality of pixel units. A light emitting element is provided in each pixel unit. Two adjacent pixel units form a pixel group. Each pixel group corresponds to a pixel driving circuit. Each pixel driving circuit can drive a first pixel unit and a second pixel unit of the same pixel group. The pixel driving circuit includes a driving module, and the driving module is located in one of the pixel units of the same pixel group. , Including the control terminal, the first connection terminal, the second connection terminal and the driving transistor, the side where the control terminal is located can store the voltage, drive The moving module is used to adjust and control the size of the electric signal through the driving transistor according to the voltage stored on the side of the control terminal. The first switch module and the first light-emitting module are located in the first pixel unit of the same pixel group. , According to the loaded first control signal, the driving current generated by the driving module is provided to the first light-emitting element; the second switching module is located in the second pixel unit of the same pixel group, and the second switching module is based on The loaded second control signal provides the driving current generated by the driving module to the second light-emitting element of the same pixel group; a common compensation module, the common compensation module is electrically connected to the control terminal, and is used for The data voltage used to compensate the control terminal voltage of the driving transistor is written and stored according to the scanning signal; a reset module is electrically connected to the driving module and is used to The reset signal resets the working state of the driving transistor.

Compared with the conventional technology, the pixel driving circuit and display device with the above structure are adopted. Two adjacent pixel units are driven by the same pixel driving circuit, which reduces the area of the pixel driving circuit and extends the life of the light-emitting element. , Which is more conducive to manufacturing higher resolution display devices. At the same time, the number of corresponding scanning lines and data lines is reduced, thereby reducing the size of the display driving circuit in the corresponding non-display area, which is more conducive to the narrow frame design of the display device.

1‧‧‧ display device

11‧‧‧display area

13‧‧‧ Non-display area

S1-Sn‧‧‧scan line

D1-Dm‧‧‧Data cable

EM1-EM2n‧‧‧Control line

10‧‧‧ Pixel Unit

10a‧‧‧first pixel unit

10b‧‧‧Second Pixel Unit

100‧‧‧ Pixel Group

20‧‧‧Gate driver

30‧‧‧Source Driver

40‧‧‧Control drive

300a, 300b‧‧‧pixel driving circuit

M1‧‧‧Reset transistor

M2‧‧‧First transistor

M3‧‧‧Second transistor

M4‧‧‧scanning transistor

M5‧‧‧Compensation transistor

M6‧‧‧Third transistor

M7‧‧‧Fourth transistor

Td‧‧‧Drive Transistor

271‧‧‧Control terminal

272‧‧‧first connection

273‧‧‧Second connection terminal

C1‧‧‧storage capacitor

EL (n-1) ‧‧‧first light emitting element

ELn‧‧‧Second light emitting element

N1‧‧‧First Node

N2‧‧‧Second Node

N3‧‧‧ third node

Ta‧‧‧The first sub-drive stage

Tb‧‧‧Second Sub-Drive Stage

T1, T1’‧‧‧‧ Reset stage

T2, T2’‧‧‧‧ write compensation stage

T3, T3’‧‧‧‧light-emitting stage

FIG. 1 is a module schematic diagram of a display device according to a preferred embodiment of the present invention.

FIG. 2 is a schematic diagram of a module of a display device according to a second embodiment of the present invention.

FIG. 3 is a module schematic diagram of a display device according to a third embodiment of the present invention.

FIG. 4 is a circuit diagram of a pixel driving circuit according to the first embodiment shown in FIG. 1. FIG.

FIG. 5 is a driving timing diagram of the pixel driving circuit shown in FIG. 4.

FIG. 6 is a circuit diagram of the pixel driving circuit shown in FIG. 4 operating in a reset stage, and the cut-off of the transistor is indicated by “X” in FIG. 6.

FIG. 7 is a circuit diagram of the pixel driving circuit shown in FIG. 4 operating in the compensation stage, and the cut-off of the transistor is indicated by “X” in FIG. 7.

FIG. 8 is a circuit diagram of the pixel driving circuit shown in FIG. 4 operating in the first light-emitting stage, and the cut-off of the transistor is indicated by “X” in FIG. 8.

FIG. 9 is a circuit diagram of the pixel driving circuit shown in FIG. 4 operating in the second light-emitting stage, and “X” in FIG. 9 indicates the cut-off of the transistor.

FIG. 10 is a circuit diagram of a pixel driving circuit according to the second embodiment in FIG. 1.

FIG. 11 is a circuit diagram of the pixel driving circuit shown in FIG. 10 operating in a reset stage, and the cut-off of the transistor is indicated by “X” in FIG. 11.

FIG. 12 is a circuit diagram of the pixel driving circuit shown in FIG. 10 operating in the compensation phase, and the cut-off of the transistor is indicated by “X” in FIG. 12.

FIG. 13 is a circuit diagram of the pixel driving circuit shown in FIG. 10 operating in a first light emitting stage, and the cut-off of the transistor is indicated by “X” in FIG. 13.

FIG. 14 is a circuit diagram of the pixel driving circuit shown in FIG. 10 operating in the second light-emitting stage, and the cut-off of the transistor is indicated by “X” in FIG. 14.

The invention provides a display device. The display device defines a display area and a non-display area provided around the display area. The display area includes a plurality of pixel units. A light emitting element is provided in each pixel unit. Two adjacent pixel units form a pixel group. Each pixel group corresponds to a pixel driving circuit.

In one embodiment, the pixel driving circuit includes: The driving module is located in one pixel unit of the same pixel group, and includes a control terminal, a first connection terminal, a second connection terminal, and a driving transistor. The side of the control terminal can store voltage, and the driving module is used for It adjusts and controls the size of the electric signal through the driving transistor according to the voltage stored on the side of the control terminal. The first switch module and the first light-on module are located in the first pixel unit of the same pixel group. The input first control signal provides the driving current generated by the driving module to the first light emitting element; the second switch module is located in the second pixel unit of the same pixel group, and the second switch module is based on the loaded The second control signal provides a driving current generated by the driving module to the second light emitting element of the same pixel group.

In one embodiment, each pixel driving circuit drives the first pixel unit and the second pixel unit of the same pixel group in a time-sharing manner.

In one embodiment, the pixel driving circuit further includes: a common compensation module, which is electrically connected to the control terminal, and is used for writing and storing data for compensating the voltage of the control terminal of the driving transistor according to the scanning signal. Voltage; reset module, the reset module is electrically connected to the drive module, and is used to reset the working state of the drive transistor according to the received reset signal.

In one embodiment, the reset module resets the control terminal to the reference voltage according to the reset signal. The common compensation module provides a data voltage for compensating the control terminal voltage of the driving transistor to the first connection terminal according to the scan signal.

In one embodiment, the common compensation module includes a scanning transistor, a compensation transistor, and a storage capacitor. The gate of the scanning transistor receives the scanning signal, the source of the scanning transistor is electrically connected to the data line, and the drain of the scanning transistor is electrically connected to the control terminal. One end of the storage capacitor receives the power supply voltage, and the other end is electrically connected to the control end. The gate of the compensation transistor receives the scanning signal and compensates The source of the transistor is electrically connected to the second connection terminal, and the drain of the compensation transistor is electrically connected to the first connection terminal.

In one embodiment, the reset module resets the second connection terminal to the reference voltage according to the reset signal. The common compensation module provides a data voltage for compensating the control terminal voltage of the driving transistor to the control terminal according to the scanning signal.

In one embodiment, a scanning transistor, a compensation transistor, and a storage capacitor are used. The gate of the scanning transistor receives the scanning signal, the source of the scanning transistor is electrically connected to the data line, and the drain of the scanning transistor is electrically connected to the control terminal through a storage capacitor, and is electrically connected to the first switch module and the second The switch module is electrically connected. The gate of the compensation transistor receives the scanning signal, the source of the compensation transistor is electrically connected to the second connection terminal, and the drain of the compensation transistor is electrically connected to the control terminal.

In one embodiment, the first switch module is electrically connected to the common compensation module and the control terminal at the same time. The second switch module is electrically connected to the common compensation module and the control terminal at the same time. The first switch module provides a reference voltage to the storage capacitor according to the first control signal and is electrically connected to the second connection terminal and the first light emitting element. The second switch module provides a reference voltage to the storage capacitor according to the second control signal and is electrically connected to the second connection terminal and the first light emitting element.

In one embodiment, the first switch module is electrically connected to the first connection terminal and the second connection terminal simultaneously. The second switch module is electrically connected to the first connection terminal and the second connection terminal at the same time. The first switch module provides a power voltage to the first connection terminal according to the first control signal and electrically connects the second connection terminal and the first light-emitting element. The second switch module provides a power supply voltage to the first connection terminal according to the second control signal and electrically connects the second connection terminal and the first light-emitting element.

In one embodiment, the display device includes a first sub-driving stage and a second sub-driving stage. In the first sub-driving stage, the first light emission in the plurality of pixel groups is sequentially driven; in the second sub-driving stage, the second light-emitting elements in the plurality of pixel groups are sequentially driven.

In one embodiment, the gate driver is disposed in the display area.

In one embodiment, the gate driver is disposed in the non-display area.

In one embodiment, the display device includes two gate drivers. One of the gate drivers is used to provide a scanning signal to the pixel driving circuit, and the other gate driver is used to provide a first control signal and a second control signal to the pixel driving circuit.

The following describes specific embodiments of the touch panel of the present invention with reference to the drawings.

Please refer to FIG. 1 together, which is a schematic diagram of a module of a display device 1 according to an embodiment of the present invention. The display device 1 defines a display area 11 and a non-display area 13 provided around the display area 11. The display area 11 includes a plurality of pixel units 10. A light emitting element is disposed in each pixel unit 10. The light emitting element is used to generate light required for display. The light emitting element may be an organic light emitting diode (Organic Emitting Diode) or a micro light emitting diode (micro LED). The display device 1 includes light-emitting diodes capable of generating blue light, green light, and red light, respectively. Diodes of different colors are respectively disposed in different pixel units 10. Alternatively, the display device 1 may include only a light-emitting diode that generates white light, and further include a color filter layer. Furthermore, the light of the first primary color generated by the light emitting diode of the display device 1 can be converted by the action of the quantum dot film to obtain light of other primary colors. But it is not limited to this. The plurality of pixel units 10 are divided into a plurality of pixel groups 100. Each pixel group 100 includes a first pixel unit 10a and a second pixel unit 10b that are disposed adjacently along the first direction Y.

The display device 11 further includes a plurality of mutually parallel scanning lines S1-Sn, a plurality of mutually parallel data lines D1-Dm, and a plurality of mutually parallel control lines EM1-EM (2n). Among them, n is an integer greater than or equal to 2, and m is an integer greater than or equal to 1. The plurality of scanning lines S1-Sn extend in a second direction X perpendicular to the first direction Y, and are used to provide a scanning signal for the pixel unit 10. The plurality of data lines D1-Dm extend along the first direction Y and are used to provide data signals for the pixel unit 10. The scanning lines and the data lines are arranged to cross each other to form a grid, and a pixel unit 10 is correspondingly arranged in the hollowed out place of the grid. The pixel units 10 are arranged in a matrix. First pixel unit 10a and second pixel unit 10b of the same pixel group In a parallel arrangement, the first pixel unit 10a in a pixel group is provided with at least a transistor controlled by a scanning signal loaded on a scanning line and used to provide a light-emitting element for the first pixel unit 10a. The second pixel unit 10b is provided with at least a part of a pixel driving circuit of a pixel driving circuit for driving a transistor for the electric signal used for light emission. Another part of the drive circuit. In other words, the same pixel driving circuit can drive both the light emitting condition of the light emitting element of the first pixel unit 10a and the light emitting condition of the light emitting element of the second pixel unit 10b. The lighting condition includes whether to emit light and emit light. strength.

A gate driver 20, a source driver 30, and a control driver 40 are provided in the non-display area 13. Each pixel group 100 is electrically connected to the gate driver 20 through a scanning line Sn, and is electrically connected to the source driver 30 through a data line Dm, and through two control lines EM (2n-1)- EM (2n) and control driver 40. A frame of image display time is divided into a first sub-driving stage Ta and a second sub-driving stage Tb (as shown in FIG. 5). In the first sub-driving stage Ta, the first pixel unit in the plurality of pixel groups 100 10a is sequentially scanned; in the second sub-driving stage Tb, the second pixel units 10b in the plurality of pixel groups 100 are sequentially scanned. In this embodiment, the gate driver 20, the source driver 30, and the control driver 40 can be implemented by tape-automated bonding (TAB) or by a chip-on-glass (COG). The method is connected to a pad (not shown) on the display panel, and can also be directly set on the display panel by a gate-in-panel (GIP) method. In other embodiments, the gate driver 20, the source driver 30, and the control driver 40 may also be directly integrated on the display panel as part of the display panel. In other embodiments, the non-display area 13 further includes a timing controller. The timing controller is used to provide a plurality of synchronous control signals to the gate driver 20, the source driver 30 and the control driver 40 to drive the gate driver 20, the source driver 30 and the control driver 40. The plurality of synchronization control signals may include a horizontal synchronization signal (horizontal synchronization, Hsync), A vertical synchronization signal (vertical synchronization, Vsync), a clock signal (clock, CLK), and a data enable signal (EN).

In the present embodiment, the gate driver 20 is provided on the non-display area 13 on the side of the display area 11. Alternatively, as shown in FIG. 2, the display device 1 may further include two gate drivers 20. The two gate drivers 20 are respectively disposed on opposite sides of the non-display area 13. Among them, the gate driver 20 located on the right side frame of the non-display area 13 is used to drive and control the scanning lines S1-Sn, and the left side frame located on the non-display area 13 is used to drive the control lines EM1-EM (2n). That is, the control signals loaded on the control lines EM1-EM (2n) may also be provided by the gate driver 20.

It can be understood that, as shown in FIG. 3, compared with the conventional technique, the number of scan lines S1-Sn in this embodiment shown in FIG. 2 is halved, so that there are fewer leads of the gate driver 20, and thus the gate The driver 20 can be disposed in the display area 11, and the display device 1 can further realize a narrow frame design.

Please refer to FIG. 4 together, which is a pixel driving circuit 300a suitable for an embodiment of the pixel group 100. FIG. 4 uses only one pixel group 100 as an example for description, and the remaining pixel groups 100 have the same picture respectively.素 driven circuit 300a. Each pixel group 100 corresponds to a pixel driving circuit 300a. The pixel driving circuit 300a is electrically connected to two adjacent scanning lines S (n-1) -Sn, a data line Dm, and two adjacent control lines EM (2n-1) -EM (2n).

The pixel driving circuit 300a receives the signal on the previous scanning line S (n-1) as the reset signal, the signal on the corresponding scanning line Sn as the scanning signal, the data signal on the corresponding data line Dm, and the control line EM The signal on (2n-1) is used as the first control signal, and the signal on the control line EM (2n) is received as the second control signal. The scanning signals of two adjacent scanning lines S (n-1) -Sn are sequentially shifted by elements. The pixel driving circuit 300a drives the first pixel unit 10a and the second pixel unit 10b in the pixel group 100 in a time-division manner. The pixel driving circuit 300a in the first sub-driving phase Ta and the second sub-driving phase Tb sequentially operates in the reset phase T1 \ T1 ', the write compensation phase T2 \ T2', and the light-emitting phase. T3 \ T3 ’. In the light-emitting phase T3 of the first sub-driving phase Ta, the pixel driving circuit 300a drives the first light-emitting element EL (n-1) of the first pixel unit 10a to emit light; in the light-emitting phase T3 'of the second sub-driving phase Tb, The pixel driving circuit 300a drives the second light emitting element ELn of the second pixel unit 10b to emit light. In the present embodiment, the pixel driving circuit 300a is a current-type driving circuit.

The pixel driving circuit 300a includes a reset module 21, a first switch module 23, a second switch module 25, a drive module 27, a common compensation module 29, a first light emitting element EL (n-1), and a second Light emitting element ELn. The first light-emitting element EL (n-1) corresponds to the first pixel unit 10a, and the second light-emitting element ELn corresponds to the second pixel unit 10b. The circuit composed of the reset module 21, the first switch module 23, the driving module 27, and the common compensation module 29 is used to drive the first pixel unit 10a. The circuit composed of the reset module 21, the second switch module 25, the driving module 27, the common compensation module 29, and the second light-emitting element ELn is used to drive the second pixel unit 10b. That is, the first pixel unit 10a and the second pixel unit 10b share the reset module 21, the drive module 27, and the common compensation module 29. Wherein, in this embodiment, from the perspective of the circuit layout, the reset module 21, the first switch module 23, the drive module 27, and the common compensation module 29 are provided corresponding to the first pixel unit 10a, and the second switch module Group 25 is set corresponding to the second pixel unit 10b. Alternatively, one or more of the reset module 21, the driving module 27, and the common compensation module 29 may be correspondingly disposed in the second pixel unit 10b, but not limited thereto.

The driving module 27 includes a control terminal 271, a first connection terminal 272, a second connection terminal 273, and a driving transistor Td. The driving module 27 is used to adjust and control the driving transistor according to the voltage stored on the side of the control terminal 271. The current of Td controls the brightness and gray scale of the pixel unit 10. A storage capacitor C1 is connected between the control terminal 271 and the power voltage Vdd, and is used to store the voltage. A connection point between the control terminal 271 and one end of the storage capacitor C1 defines a first node N1. The source of the driving transistor Td is connected to the first connection terminal 272 of the driving module 27. The connection point defines the second node N2. The drain of the driving transistor Td is connected to the second connection terminal 273 of the driving module 27. The gate connection control End 271. The control terminal 271 of the drive module 27 and the output terminal of the reset module 21 are connected to the first node N1, the drive The first connection terminal 272 of the module 27 is connected to the first switch module 23 and the second switch module 25 to the second node N2, the second connection terminal 273 of the drive module 27 is connected to the first switch module 23 and the second The switching module 25 is connected to the node N3, and the common compensation module 29 is connected between the power supply voltage Vdd and the third node N3. The driving transistor Td has a threshold voltage Vth. In this embodiment, the driving transistor Td is a P-type thin film transistor.

The reset module 21 receives a signal on the scan line S (n-1) as a reset signal to reset the driving module 27. After the driving module 27 is reset, the voltage of the first node N1 is reset to the reference voltage Vref. The output of the reset module 21 is connected to the first node N1, so that the reset signal is transmitted to the control terminal 271 of the drive module 27. The reset module 21 includes a reset transistor M1. The gate of the reset transistor M1 is electrically connected to the scan line S (n-1). The drain of the reset transistor M1 receives the reference voltage Vref (as a reset signal), and resets the source and driver of the transistor M1. The module 27 is electrically connected. In this embodiment, the reset transistor M1 is a P-type thin film transistor.

The first switch module 23 is used to control whether the power supply voltage Vdd is provided to the first connection terminal 272 of the driving module 27 according to the first control signal, and to control whether the current generated from the driving module 27 is provided to the first light emitting element EL ( n-1). The first switching module 23 includes a first transistor M2 and a second transistor M3. The first transistor M2 is connected between the power voltage Vdd and the first connection terminal 272 of the driving module 27. Specifically, the gate of the first transistor M2 receives the first control signal, the source of the first transistor M2 receives the power supply voltage Vdd, and the drain of the first transistor M2 is connected to the first connection terminal of the driving module 27. 272 electrically connected. The gate of the second transistor M3 receives the first control signal, the source of the second transistor M3 is electrically connected to the second connection terminal 273 of the driving module 27, and the drain of the second transistor M3 is connected to the first light-emitting element. EL (n-1) is electrically connected. In this embodiment, the first transistor M2 and the second transistor M3 are both P-type thin film transistors. In this embodiment, the power supply voltage Vdd is greater than the reference voltage Vref.

The second switching module 25 is used to control whether the power supply voltage Vdd is provided to the first connection terminal 272 of the driving module 27 according to the second control signal, and to control whether the current generated from the driving module 27 is provided to the second light-emitting element ELn. The second switching module 25 includes a third transistor M6 and a fourth transistor M7. The third transistor M6 and the first transistor M2 are connected in parallel between the power supply voltage Vdd and the first connection terminal 272 of the driving module 27. Specifically, the gate of the third transistor M6 is connected to receive the second control signal, the source of the third transistor M6 is electrically connected to the power supply voltage Vdd, and the drain of the third transistor M6 is connected to the first of the driving module 27. The connection terminal 272 is electrically connected. The fourth transistor M7 is connected between the second connection terminal 273 of the driving module 27 and the second light-emitting element ELn. Specifically, the gate of the fourth transistor M7 receives the second control signal, the source of the fourth transistor M7 is electrically connected to the second connection terminal 273 of the driving module 27, and the drain of the fourth transistor M7 is connected to the first transistor M7. The two light emitting elements ELn are electrically connected. In this embodiment, the third transistor M6 and the fourth transistor M7 are both P-type thin film transistors.

The common compensation module 29 is used to write and store the compensation data voltage loaded on the data line Dm for compensating the gate voltage of the driving transistor Td in the first driving stage and / or the second driving stage to drive the driving. Module 27 performs compensation. The common compensation module 29 includes a scanning transistor M4, a compensation transistor M5, and a storage capacitor C1. The gate of the scanning transistor M4 is electrically connected to the scanning line Sn, the drain of the scanning transistor M4 is electrically connected to the source of the driving transistor Td, and the source of the scanning transistor M4 is electrically connected to the data line Dm. The gate of the compensation transistor M5 is electrically connected to the scanning line Sn, and the source of the compensation transistor M5 is connected to the second connection terminal 273 of the driving module 27, and is further electrically connected to the source of the driving transistor Td. The drain of the compensation transistor M5 is connected to the control terminal 271 of the driving module 27 and is further electrically connected to the gate of the driving transistor Td. The first terminal of the storage capacitor C1 is electrically connected to the voltage source Vdd, and the second terminal is electrically connected to the gate of the driving transistor Td. In this embodiment, the scanning transistor M4 and the compensation transistor M5 are both P-type thin film transistors. In this embodiment, the reference voltage Vref is smaller than the data voltage Vdata and the threshold voltage Vth.

The anode of the first light-emitting element EL (n-1) is electrically connected to the source of the driving transistor Td via the second transistor M3, and the cathode is grounded. The anode of the second light-emitting element ELn is electrically connected to the source of the driving transistor Td via the fourth transistor M7, and the cathode is grounded.

Please refer to FIG. 5 and FIG. 6 together, which are driving timing diagrams of the pixel driving circuit 300 a and a schematic circuit diagram of the pixel driving circuit 300 a in the reset phase T1 of the first sub-driving phase Ta.

In the reset stage T1 of the first sub-drive stage Ta, the signal on the scanning line S (n-1) is valid, the signal on the scanning line Sn is invalid (if it is a low level), and the control line EM (2n-1)- The signal on EM (2n) is invalid (if high level), only the reset transistor M1 is turned on, and the reset module 21 outputs the reference voltage Vref, so that the gate voltage of the driving transistor Td is reset to the reference The voltage Vref can ensure that the voltage on the data line Dm can be normally written to the gate of the driving transistor Td.

Please refer to FIG. 5 and FIG. 7 together, which are driving timing diagrams of the pixel driving circuit 300a and schematic circuit diagrams of the pixel driving circuit 300a in the write compensation phase T2 of the first sub-driving phase Ta. In the write compensation phase T2 of the first sub-drive stage Ta, the signal on the scanning line S (n-1) is invalid, the signal on the scanning line Sn is valid, and the signal on the control line EM (2n-1) -EM (2n) The signal is invalid, the scanning transistor M4 is turned on according to the signal on the scanning line Sn, and the data voltage Vdata on the data line Dm is provided to the source of the driving transistor Td. At the same time, the compensation transistor M5 is turned on according to the signal on the scanning line Sn, and the gate of the transistor Td is electrically connected to the drain, and the transistor Td is driven in a diode connection mode, so that the data voltage Vdata on the data line Dm The gate of the driving transistor Td is transmitted to compensate the threshold voltage Vth of the driving transistor Td. At this time, the voltage of the first node N1 is Vdata-Vth, and the voltage of the second node N2 is Vdata. The voltage on the first terminal of the storage capacitor C1 is always equal to the power supply voltage Vdd, and the voltage on the second terminal is equal to the voltage of the first node N1. Therefore, the storage voltage of the storage capacitor C1 is the difference between the power supply voltage Vdd and the voltage of the first node N1, that is, the storage voltage is Vdd + Vth-Vdata. Therefore, the threshold voltage Vth and the data voltage Vdata are stored. Therefore, the storage capacitor C1 realizes the compensation of the threshold voltage Vth and the storage of the data voltage Vdata.

Please refer to FIG. 5 and FIG. 8 together, which are driving timing diagrams of the pixel driving circuit 300 a and a schematic circuit diagram of the pixel driving circuit 300 a in the light-emitting phase T 3 of the first sub-driving phase Ta. In the light-emitting phase T3 of the first sub-driving phase Ta, the signal on the scanning line S (n-1) is invalid, the signal on the scanning line Sn is invalid, the signal on the control line EM (2n-1) is valid, and the control line EM ( The signal on 2n) is invalid. The first transistor M2 and the second transistor M3 are turned on by the signal on the control line EM (2n-1), and the voltage at the first node N1 remains unchanged across the storage capacitor C1. Under the effect of Vdata-Vth, the voltage at the second node N2 is the same as the power supply voltage Vdd, the driving transistor Td is turned on, and a driving current Ioled is generated to drive the first light-emitting element EL (n-1) to emit light. At this time, the driving current Ioled can be calculated by the following method.

Ioled = k × (Vgs-Vth) ² = k × [Vdd- (Vdata-Vth) -Vth] ² = k × (Vdd-Vdata) ²

Among them, k is a current amplification factor of the driving transistor Td, which is related to a proportionality constant determined by the mobility of the driving transistor Td and a ratio of a channel width and a channel length. It can be seen that the driving current Ioled is independent of the threshold voltage of the driving transistor Td, and is only related to the data voltage Vdata.

The reset phase T1 'and the write compensation phase T2' in the second sub-drive phase Tb work in the same manner as the reset phase T1 and the write compensation phase T2 in the first sub-drive phase Ta. Therefore, I will not repeat them here.

Please refer to FIG. 5 and FIG. 9 together, which are driving timing diagrams of the pixel driving circuit 300a and schematic circuit diagrams of the pixel driving circuit 300a in the light-emitting phase T3 'of the second sub-driving phase Tb. In the light-emitting phase T3 'of the second sub-driving phase Ta, the signal on the scanning line S (n-1) is invalid, the signal on the scanning line Sn is invalid, the signal on the control line EM (2n) is valid, and the control line EM (2n) The signal on -1) is invalid. The third transistor M6 and the fourth transistor M7 are guided by the signal on the control line EM (2n). ON, the voltage of the first node N1 remains Vdata-Vth unchanged under the action of the storage capacitor C1, the voltage of the second node N2 is the same as the power supply voltage Vdd, the driving transistor Td is turned on, and a driving current Ioled is generated to drive the second light The element EL (n) emits light.

In summary, using the pixel driving circuit of the above structure, two adjacent pixel units are driven by the same pixel driving circuit, which reduces the area of the pixel driving circuit and extends the life of the light-emitting element, which is more conducive to Manufacture higher-resolution display devices. At the same time, the number of corresponding scanning lines and data lines is reduced, thereby reducing the size of the display driving circuit in the corresponding non-display area, which is more conducive to the narrow frame design of the display device.

Please refer to FIG. 10, which is a pixel driving circuit 300 b suitable for another embodiment of the pixel group 100. FIG. 10 uses only one pixel group 100 as an example for description, and the remaining pixel groups 100 each have the same pixel driving circuit 300b. Each pixel group 100 corresponds to a pixel driving circuit 300a. The pixel driving circuit 300a is electrically connected to two adjacent scanning lines S (n-1) -Sn, a data line Dm, and two adjacent control lines EM (2n-1) -EM (2n).

The pixel driving circuit 300b receives the signal on the previous scanning line S (n-1) as the reset signal, the signal on the corresponding scanning line Sn as the scanning signal, the data signal on the corresponding data line Dm, and the control line EM The signal on (2n-1) is used as the first control signal, and the signal on the control line EM (2n) is received as the second control signal. The scanning signals of two adjacent scanning lines S (n-1) -Sn are sequentially shifted by elements. The pixel driving circuit 300b drives the first pixel unit 10a and the second pixel unit 10b in the pixel group 100 in a time-sharing manner. The pixel driving circuit 300a in the first sub-driving phase Ta and the second sub-driving phase Tb are sequentially operated in the reset phase T1 \ T1 ', the write compensation phase T2 \ T2', and the light-emitting phase T3 \ T3 '. In the light-emitting phase T3 of the first sub-driving phase Ta, the pixel driving circuit 300b drives the first light-emitting element EL (n-1) of the first pixel unit 10a to emit light; in the light-emitting phase T3 'of the second sub-driving phase Tb, The pixel driving circuit 300b drives the second light emitting element ELn of the second pixel unit 10b to emit light. In the present embodiment, the pixel driving circuit 300b is a current-type driving circuit.

The pixel driving circuit 300b includes a reset module 21, a first switching module 23, a second switching module 25, a driving module 27, a common compensation module 29, a first light emitting element EL (n-1), and a second Light emitting element ELn. The first light-emitting element EL (n-1) corresponds to the first pixel unit 10a, and the second light-emitting element ELn corresponds to the second pixel unit 10b. The circuit composed of the reset module 21, the first switch module 23, the driving module 27, and the common compensation module 29 is used to drive the first pixel unit 10a. The circuit composed of the reset module 21, the second switch module 25, the driving module 27, the common compensation module 29, and the second light-emitting element ELn is used to drive the second pixel unit 10b. That is, the first pixel unit 10a and the second pixel unit 10b share the reset module 21, the drive module 27, and the common compensation module 29. Wherein, in this embodiment, from the perspective of the circuit layout, the reset module 21, the first switch module 23, the drive module 27, and the common compensation module 29 are provided corresponding to the first pixel unit 10a, and the second switch module Group 25 is set corresponding to the second pixel unit 10b. Alternatively, one or more of the reset module 21, the driving module 27, and the common compensation module 29 may be correspondingly disposed in the second pixel unit 10b, but not limited thereto.

The driving module 27 includes a control terminal 271, a first connection terminal 272, a second connection terminal 273, and a driving transistor Td. The driving module 27 is used to adjust and control the driving transistor according to the voltage stored on the side of the control terminal 271. The current of Td controls the brightness and gray scale of the pixel unit 10. A storage capacitor C1 is connected between the control terminal 271 and the common compensation module 29 for storing a voltage. The connection point between the control terminal 271 and one end of the storage capacitor C1 defines a first node N1, and the connection point between the shared compensation module 29 and the other end of the storage capacitor C1 is defined as a second node N2. The source of the driving transistor Td is connected to the first connection terminal 272 of the driving module 27, the drain of the driving transistor Td is connected to the second connection terminal 273 of the driving module 27, and the gate is connected to the control terminal 271. The control terminal 271 and the storage capacitor C1 of the drive module 27 are connected to the first node N1, the first connection terminal 272 of the drive module 27 is connected to the power supply voltage Vdd, and the second connection terminal 273 of the drive module 27 is connected to the first switch module. The group 23 and the second switch module 25 are connected to the node N3. The output terminal of the common compensation module 29 is connected to the storage capacitor C1 through the second node N2, and is connected to the first switch module 23 and the second switch module 25 through the third node N3. drive The transistor Td has a threshold voltage Vth. In this embodiment, the driving transistor Td is a P-type thin film transistor.

The reset module 21 receives a signal on the scanning line S (n-1) as a reset signal to reset the second connection terminal 273 of the driving module 27. After the reset module 27 is reset, the voltage of the third node N3 is reset to the reference voltage Vref. The output of the reset module 21 is connected to the first node N1, so that the reset signal is transmitted to the control terminal 271 of the drive module 27. The reset module 21 includes a reset transistor M1. The gate of the reset transistor M1 is electrically connected to the scan line S (n-1). The drain of the reset transistor M1 receives the reference voltage Vref (as a reset signal), and resets the source and the driver of the transistor M1. The module 27 is electrically connected. In this embodiment, the reset transistor M1 is a P-type thin film transistor.

The first switch module 23 is used to control whether the reference voltage Vref is provided to the common compensation module 29 and to control whether the current generated by the driving module 27 is provided to the first light-emitting element EL (n-1) according to the first control signal. The first switching module 23 includes a first transistor M2 and a second transistor M3. The first transistor M2 is connected between the reference voltage Vref and the second node N2 of the common compensation module 29. Specifically, the gate of the first transistor M2 receives a first control signal, the source of the first transistor M2 receives a reference voltage Vref, the drain of the first transistor M2 and a second node of the common compensation module 29 N2 is electrically connected. The second transistor M3 is connected between the third node N3 of the common compensation module 29 and the first light emitting element EL (n-1). Specifically, the gate of the second transistor M3 receives the first control signal, the source of the second transistor M3 is electrically connected to the third node N3, and is further electrically connected to the second connection terminal 273 of the driving module 27. The drain of the second transistor M3 is electrically connected to the first light-emitting element EL (n-1). In this embodiment, the first transistor M2 and the second transistor M3 are both P-type thin film transistors.

The second switching module 25 is used to control whether to provide the reference voltage Vref to the common compensation module 29 and to control whether the current generated by the driving module 27 is provided to the second light-emitting element ELn according to the second control signal. The second switching module 25 includes a third transistor M6 and a fourth transistor M7. The third transistor M6 is connected between the reference voltage Vref and the second node N2 of the common compensation module 29. specifically, The gate of the third transistor M6 is connected to receive the first control signal. The source of the third transistor M6 is electrically connected to the reference voltage Vref. The drain of the third transistor M6 is connected to the second node N2 of the compensation module 29. Electrical connection. The fourth transistor M7 is connected between the third node N3 of the common compensation module 29 and the second light-emitting element ELn. Specifically, the gate of the fourth transistor M7 receives the second control signal, and the source of the fourth transistor M7 is electrically connected to the third node N3 of the common compensation module 29 and further connected to the second connection of the driving module 27. The terminal 273 is electrically connected, and the drain of the fourth transistor M7 is electrically connected to the second light-emitting element ELn. In this embodiment, the third transistor M6 and the fourth transistor M7 are both P-type thin film transistors.

The common compensation module 29 is configured to compensate the driving module 27 by writing the data voltage on the storage data line Dm in the first driving stage and / or the second driving stage. The common compensation module 29 includes a scanning transistor M4, a compensation transistor M5, a storage capacitor C1, and a second node N2. The first terminal of the storage capacitor C1 is electrically connected to the gate of the scanning transistor M4 through the second node N2, and the second terminal of the storage capacitor C1 is electrically connected to the gate of the driving transistor Td through the first node N1. connection. The gate of the scanning transistor M4 is electrically connected to the scanning line Sn, the drain of the scanning transistor M4 is electrically connected to the storage capacitor C1 through the second node N2, and the source of the scanning transistor M4 is electrically connected to the data line Dm. . The gate of the compensation transistor M5 is electrically connected to the scanning line Sn, and the source of the compensation transistor M5 is connected to the second connection terminal 273 of the driving transistor Td, and is further electrically connected to the source of the driving transistor Td to compensate. The drain of the transistor M5 is electrically connected to the gate of the driving transistor Td. In this embodiment, the scanning transistor M4 and the compensation transistor M5 are both P-type thin film transistors.

Please refer to FIG. 5 and FIG. 11 together, which are driving timing diagrams of the pixel driving circuit 300 b and schematic circuit diagrams of the pixel driving circuit 300 b in the reset stage T1 of the first sub-driving stage Ta. In the reset stage T1 of the first sub-drive stage Ta, the signal on the scanning line S (n-1) is valid, the signal on the scanning line Sn is invalid (if it is a low level), and the control line EM (2n-1)- The signal on EM (2n) is invalid (such as high level), only the reset transistor M1 is turned on, and the voltage of the second node N2 is reset to the reference voltage. Press Vref to prevent the anodes of the first light-emitting element EL (n-1) and the second light-emitting element ELn from being affected by the data signal in the previous frame time.

Please refer to FIG. 5 and FIG. 12 together, which are driving timing diagrams of the pixel driving circuit 300b and schematic circuit diagrams of the pixel driving circuit 300b in the write compensation phase T2 of the first sub-driving phase Ta. In the write compensation phase T2 of the first sub-drive stage Ta, the signal on the scanning line S (n-1) is invalid, the signal on the scanning line Sn is valid, and the signal on the control line EM (2n-1) -EM (2n) is invalid. The signal is invalid, the scanning transistor M4 is turned on according to the signal on the scanning line Sn, and the data voltage Vdata on the data line Dm is provided to the second node N2. At the same time, the compensation transistor M5 is turned on according to the signal on the scan line Sn, the gate of the driving transistor Td is electrically connected to the drain, and the driving transistor Td is connected in a diode. At this time, the voltage of the first node N1 is the power supply voltage Vdd-Vth. The voltage on the first terminal connected to the storage capacitor C1 and the scanning transistor M4 is equal to the voltage on the second node N2, that is, Vdata, and the voltage on the second terminal is equal to the voltage on the first node N1. Therefore, the storage voltage on the storage capacitor C1 is the difference between the first node N1 and the second node N2, that is, the storage voltage is Vdd-Vth-Vdata. Therefore, the storage capacitor C1 realizes the compensation of the threshold voltage Vth and the storage of the data voltage Vdata.

Please refer to FIG. 5 and FIG. 13 together, which are driving timing diagrams of the pixel driving circuit 300 b and a schematic circuit diagram of the pixel driving circuit 300 b in the light-emitting phase T 3 of the first sub-driving phase Ta.

In the light-emitting phase T3 of the first sub-driving phase Ta, the signal on the scanning line S (n-1) is invalid, the signal on the scanning line Sn is invalid, the signal on the control line EM (2n-1) is valid, and the control line EM ( The signal on 2n) is invalid, the first transistor M2 and the second transistor M3 are turned on by the signal on the control line EM (2n-1), and the voltage at the second node N2 jumps to Vref; it remains in the storage capacitor C1 With the constant voltage difference across the two ends, the voltage at the first node N1 becomes Vref + Vdd-Vth-Vdata; the driving transistor Td is turned on, and a driving current Ioled is generated to drive the first light-emitting element EL (n-1) to emit light. At this time, the driving current Ioled can be calculated by the following method.

Ioled = k × (Vgs-Vth) ² = k × [Vdd- (Vref + Vdd-Vth-Vdata) -Vth] ² = k × (Vdata-Vref) ²

Among them, k is a current amplification factor of the driving transistor Td, which is related to a proportionality constant determined by the mobility of the driving transistor Td and a ratio of a channel width and a channel length.

It can be seen that the driving current Ioled is independent of the threshold voltage of the driving transistor Td, and is only related to the data voltage Vdata.

The reset phase T1 'and the write compensation phase T2' in the second sub-drive phase Tb work in the same manner as the reset phase T1 and the write compensation phase T2 in the first sub-drive phase Ta. Therefore, I will not repeat them here.

Please refer to FIG. 5 and FIG. 14 together, which are driving timing diagrams of the pixel driving circuit 300b and a schematic circuit diagram of the pixel driving circuit 300b in the light-emitting stage T3 'of the second sub-driving stage Tb. In the light-emitting phase T3 'of the second sub-driving phase Ta, the signal on the scanning line S (n-1) is invalid, the signal on the scanning line Sn is invalid, the signal on the control line EM (2n) is valid, and the control line EM (2n) The signal on -1) is invalid, the third transistor M6 and the fourth transistor M7 are turned on by the signal on the control line EM (2n), and the voltage of the second node N2 jumps to Vref; the role of the storage capacitor C1 Next, the voltage of the first node N1 becomes Vref + Vdd-Vth-Vdata; the driving transistor Td is turned on, and a driving current Ioled is generated to drive the second light-emitting element ELn to emit light.

In summary, using the pixel driving circuit of the above structure, two adjacent pixel units are driven by the same pixel driving circuit, which reduces the area of the pixel driving circuit and extends the life of the light-emitting element, which is more conducive to Manufacture higher-resolution display devices. At the same time, the number of corresponding scanning lines and data lines is reduced, thereby reducing the size of the display driving circuit in the corresponding non-display area, which is more conducive to the narrow frame design of the display device. Further, compared with the pixel driving circuit of the first embodiment, the data voltage in the pixel driving circuit is written into the driving transistor by the source of the driving transistor. Gate, the data voltage in the pixel driving circuit of the second embodiment is directly written to the gate of the driving transistor, which simplifies the writing operation.

Claims (13)

A pixel driving circuit is used for driving a pixel group composed of two adjacently arranged pixel units, the pixel group includes a first pixel unit and a second pixel unit; the first pixel unit includes A first light-emitting element, and the second pixel unit includes a second light-emitting element, which is improved in that each pixel driving circuit can drive the first pixel unit and the second pixel unit of the same pixel group The pixel driving circuit includes a driving module. The driving module is located in one of the pixel units of the same pixel group, and includes a control terminal, a first connection terminal, a second connection terminal, and a driver. The transistor is capable of storing a voltage on the side of the control terminal, and the driving module is configured to adjust and control the size of the electric signal passing through the driving transistor according to the voltage stored on the side of the control terminal; the first switching mode Group, the first light-emitting module is located in the first pixel unit of the same pixel group, and provides a driving current generated by the driving module to the first pixel unit according to a loaded first control signal. A light-emitting element; second on A module, which is located in the second pixel unit of the same pixel group, and the second switch module provides a driving current generated by the driving module to the second pixel unit according to a loaded second control signal The second light emitting element of the same pixel group; a common compensation module, the common compensation module is electrically connected to the control terminal, and is used to write and store a compensation signal for compensating the driving transistor according to a scanning signal; Data voltage of the control terminal voltage; a reset module, the reset module is electrically connected to the drive module, and is configured to reset the working state of the drive transistor according to the received reset signal. The pixel driving circuit according to claim 1, wherein each pixel driving circuit drives the first pixel unit and the second pixel unit of the same pixel group in a time-sharing manner. The pixel driving circuit according to claim 1, wherein the reset module resets the control terminal to a reference voltage according to the reset signal; and the shared compensation module sets the control terminal according to the scan signal. A data voltage for compensating a control terminal voltage of the driving transistor is provided to the first connection terminal. The pixel driving circuit according to claim 3, wherein the common compensation module includes a scanning transistor, a compensation transistor, and a storage capacitor; a gate of the scanning transistor receives the scanning signal, and the scanning electrode The source of the crystal is electrically connected to the data line, the drain of the scanning transistor is electrically connected to the control terminal; one end of the storage capacitor receives a power supply voltage, and the other end is electrically connected to the control terminal; The gate of the compensation transistor receives the scanning signal, the source of the compensation transistor is electrically connected to the second connection terminal, and the drain of the compensation transistor is electrically connected to the first connection terminal. connection. The pixel driving circuit according to claim 1, wherein the reset module resets the second connection terminal to a reference voltage according to the reset signal; and the shared compensation module resets the second connection terminal according to the scan signal. The data voltage for compensating the control terminal voltage of the driving transistor is provided to the control terminal. The pixel driving circuit according to claim 5, wherein the common compensation module includes a scanning transistor, a compensation transistor, and a storage capacitor; a gate of the scanning transistor receives the scanning signal, and the scanning electrode The source of the crystal is electrically connected to the data line, and the drain of the scanning transistor is electrically connected to the control terminal through the storage capacitor, and is electrically connected to the first switch module and the second switch module. A gate of the compensation transistor receives the scan signal, a source of the compensation transistor is electrically connected to the second connection terminal, and a drain of the compensation transistor is connected to the control The terminal is electrically connected. The pixel driving circuit according to claim 6, wherein the first switch module is electrically connected to the common compensation module and the control terminal at the same time; the second switch module is simultaneously connected to the common The compensation module is electrically connected to the control terminal; the first switch module provides a reference voltage to the storage capacitor according to the first control signal and electrically connects the second connection terminal to the first terminal. A light-emitting element; the second switch module provides the reference voltage to the storage capacitor according to the second control signal and electrically connects the second connection terminal and the first light-emitting element. The pixel driving circuit according to claim 1, wherein the first switch module is electrically connected to the first connection terminal and the second connection terminal at the same time; the second switch module is simultaneously connected to the The first connection terminal is electrically connected to the second connection terminal; the first switch module provides a power voltage to the first connection terminal according to the first control signal and is electrically connected to the second connection terminal. And the first light emitting element; the second switch module supplies the power supply voltage to the first connection terminal according to the second control signal and electrically connects the second connection terminal to the first connection terminal Light emitting element. A display device with a pixel driving circuit, which defines a display area and a non-display area provided around the display area; the display area includes a plurality of pixel units; each of the pixel units has a light-emitting element; two The pixel units disposed adjacently constitute a pixel group; each pixel group corresponds to a pixel driving circuit; each pixel driving circuit can drive a first pixel of the same pixel group A unit and a second pixel unit, the display device includes at least one gate driver; the improvement is that the pixel driving circuit adopts the pixel driving circuit according to any one of claims 1 to 8. The display device according to claim 9, wherein the display device includes a first sub-driving phase and a second sub-driving phase; in the first sub-driving phase, the first in the plurality of pixel groups Light emission is sequentially driven; in the second sub-driving stage, the second light emitting elements in the plurality of pixel groups are sequentially driven. The display device according to claim 9, wherein the gate driver is disposed in the display area. The display device according to claim 9, wherein the gate driver is disposed in the non-display area. The display device according to claim 12, wherein the display device includes two gate drivers; one of the gate drivers is used to provide a scanning signal to the pixel driving circuit, and the other is used for the gate driver. And providing the first control signal and the second control signal to the pixel driving circuit.