TWI753778B - Display device - Google Patents

Abstract

A display device includes a substrate, gate lines, driving circuit, and assisting gate lines. The substrate has a display area. The gate lines are configured in the display area, and are in parallel with a first edge of the display area, and include a first gate line which is farthest to the first edge. The driving circuit is configured near the first edge. The assisting gate lines are substantially vertically connected to the gate lines, and are in parallel with a second edge of the display area. The assisting gate lines include a first assisting gate line and at least one assisting gate line. The first assisting gate line in configured to connect the first gate line to the driving circuit. The at least one assisting gate line is configured between the second edge and the first assisting gate line.

Description

display device

The present case relates to a display device, especially a display device with a narrow frame.

With the advancement of display device technology, users have increased the pursuit of the thickness of the frame of the display device or the panel. In the current narrow-frame display devices, the layout of V-shaped switching lines is often used. Although this method can reduce the width of the left and right sides of the frame, the resistance and capacitance load (RC loading) caused by the switching lines increases, making it difficult to be widely used. It is suitable for panels of large size, high resolution, and high refresh rate.

In order to solve the above problems, the present disclosure provides a display device including a substrate, a plurality of gate lines, a driving circuit and a plurality of auxiliary gate lines. The substrate has a display area. The plurality of gate lines are disposed in the display area and are respectively parallel to the first boundary of the display area, and the plurality of gate lines include a first gate line farthest from the first boundary. The driving circuit is disposed adjacent to the first boundary of the display area. A plurality of auxiliary gate lines are arranged in the display area, and the plurality of auxiliary gate lines are substantially vertically connected to the plurality of gate lines and are respectively parallel to a second boundary of the display area. The plurality of auxiliary gate lines include a first auxiliary gate line and at least one auxiliary gate line. The first auxiliary gate line is used for connecting the first gate line to the driving circuit. At least one auxiliary gate line is disposed between the second boundary and the first auxiliary gate line.

Another aspect of the present disclosure provides a display device including a substrate, a plurality of data lines, a first driving circuit and a plurality of auxiliary data lines. The substrate has a display area, the display area includes a first block and a second block, the first block is adjacent to a first side of the display area, the second block is adjacent to a second side of the display area, and the first block is adjacent to a first side of the display area. The one side and the second side are located on opposite sides of the display area. The plurality of data lines are respectively disposed in the first block and the second block. In the first block, the plurality of data lines include a first data line farthest from the first side. The first driving circuit is disposed adjacent to the first side of the display area. A plurality of auxiliary data lines are respectively disposed in the first block and the second block, the plurality of auxiliary data lines are substantially vertically connected to the plurality of data lines, and are respectively parallel to a top side of the display area. In the first block, the plurality of auxiliary data lines include a first auxiliary data line and at least one auxiliary data line. The first auxiliary data line is used for connecting the first data line to the first driving circuit. At least one auxiliary data line is disposed between the top edge and the first auxiliary data line.

All terms used herein have their ordinary meanings. The above-mentioned words are defined in commonly used dictionaries, and the usage examples of any of the words discussed herein included in the content of this specification are only examples, and should not limit the scope and meaning of the present disclosure. Likewise, the present disclosure is not limited to the various embodiments shown in this specification.

It will be understood that the terms first, second, and third, etc., are used herein to describe various elements, components, regions, layers and/or blocks. However, these elements, components, regions, layers and/or blocks should not be limited by these terms. These terms are only used to identify a single element, component, region, layer and/or block. Thus, a first element, component, region, layer and/or block hereinafter could also be termed a second element, component, region, layer and/or block without departing from the meaning of the present disclosure. As used herein, "and/or" includes any and all combinations of one or more of the associated items.

As used herein, "coupled" or "connected" may refer to two or more elements in direct physical or electrical contact with each other, or in indirect physical or electrical contact with each other, or two or more elements Elements interact or act on each other.

Indexes 1 to n in the component numbers and signal numbers used in the description and drawings of this application are only for the convenience of referring to individual components and signals, and are not intended to limit the number of the aforementioned components and signals to a specific number. In the description and drawings of this application, if a component number or signal number is used without specifying the index of the component number or signal number, it means that the component number or signal number refers to an unspecified component group or signal group to which it belongs. of any component or signal. For example, the object referred to by the element number GL1 is the gate line GL1, and the object referred to by the element number GL is any unspecified gate line among the gate lines GL1 to GLn.

Please refer to FIG. 1 . FIG. 1 is a schematic diagram of a display device 100 according to an embodiment of the disclosure. As shown in FIG. 1 , the display device 100 includes a substrate 110 , a gate driving circuit 120 and a data driving circuit 130 .

The substrate 110 includes a display area 111, and the display area 111 has a top edge E1 and a first side edge SE1 perpendicular to the top edge E1. The gate driving circuit 120 and the data driving circuit 130 are disposed on the same side of the display area 111 and adjacent to the top side E1 of the display area 111 .

In a common configuration of a general display device, the gate driver circuit and the data driver circuit are usually arranged on different sides of the display area. For example, the data driver circuit can be arranged on the upper and lower sides of the display area to transmit data through vertically extending data lines. To control the pixels in the display area in the display area, the gate driving circuit can be arranged on the left and right sides of the display area and use the horizontally extending gate lines to transfer to the display area to control the pixels in the display area. Under the above configuration, the display area At least one side of the upper and lower sides and at least one side of the left and right sides of the display device need to retain a certain width to accommodate the gate driving circuit, the data driving circuit and the related line connection points. The above configuration will make it difficult to reduce the width of the frame on each side of the display device. Under the current development trend of display panels of mobile devices pursuing narrow bezels and high screen-to-body ratios, the above configuration will prevent the bezels from being reduced and the screen-to-body ratio to be further increased.

As shown in the embodiment of FIG. 1 , the gate driving circuit 120 and the data driving circuit 130 of the display device 100 are arranged on the same side of the display area 111 (eg, the top side E1 ), so that the left and right sides of the display area 111 are There is no need to reserve extra space for the gate driving circuit, so that the frame width of the display device 100 can be reduced. The detailed configuration method will be described in detail in the following paragraphs.

In some embodiments, the display area 111 includes a plurality of data lines DL and a plurality of gate lines GL1 - GL3 , and the data lines DL and the plurality of gate lines GL1 - GL3 are respectively connected to the display area 111 arranged in a matrix manner Multiple display pixels (not shown). The data driving circuit 130 is used for generating a data voltage to the data line DL, and providing the data voltage to each display pixel in the display area 111 through the data line DL. The gate driving circuit 120 is used for generating a gate voltage to the gate lines GL1 ˜ GL3 , and controlling the pixel switch of each display pixel through the gate voltage on the gate lines GL1 ˜ GL3 .

As shown in FIG. 1 , the data line DL and the first side SE1 of the display area 111 are completely parallel or substantially parallel. The gate lines GL1 - GL3 are completely or substantially parallel to the top edge E1 of the display area 111 .

In some embodiments, in order to match the gate driving circuit 120 and the data driving circuit 130 on the same side of the display area 111 , the display area 111 includes auxiliary gate lines AG11 ˜ AG13 , AG21 ˜ AG23 , which are respectively connected to the gate lines One of the GL1 ˜GL3 is used for turning the gate lines GL1 ˜GL3 to be connected to the gate driving circuit 120 . The auxiliary gate lines AG11 ˜ AG13 , AG21 ˜ AG23 and the first side SE1 of the display area 111 are completely parallel or substantially parallel.

In other words, in the embodiment of FIG. 1, the auxiliary gate lines AG11-AG13 and AG21-AG23 extending in the vertical direction are connected between the gate driving circuit 120 and the gate lines GL1-GL3 extending in the horizontal direction. The auxiliary gate lines AG11 ˜ AG13 , AG21 ˜ AG23 are used to transmit the gate signals generated by the gate driving circuit 120 disposed above the display area 111 to different gate lines GL1 ˜ GL3 along the vertical direction. In this way, the display device 100 can realize that the gate driving circuit 120 and the data driving circuit 130 are disposed on the same side of the display area 111 , while maintaining the normal functions of gate driving and data driving.

In some embodiments, the auxiliary gate lines AG11 ˜ AG13 and the auxiliary gate lines AG21 ˜ AG23 are arranged in a mirror-symmetric manner. For easy understanding, please refer to the first auxiliary gate line group 1401 located in the left half of the display area 111 shown in FIG. 1 . The first auxiliary gate line group 1401 includes auxiliary gate lines AG11 ˜ AG13 . The auxiliary gate line AG11 is connected to the gate line GL1 farthest from the top edge E1, and the auxiliary gate line AG12 connected to the gate line GL2 is included between the auxiliary gate line AG11 and the first side SE1. In other words, the auxiliary gate line AG11 is not the one of the auxiliary gate lines AG closest to the boundary of the display area 111 , and at least one auxiliary gate line AG is included between the auxiliary gate line AG11 and the first side SE1 .

Similarly, please refer to the second auxiliary gate line group 1402 located on the right half of the display area 111 shown in FIG. 1 , the second auxiliary gate line group 1402 includes auxiliary gate lines AG21 - AG23 . The auxiliary gate line AG21 is connected to the gate line GL1 farthest from the top edge E1, and between the auxiliary gate line AG21 and the other side (SE2, not shown in the figure) corresponding to the first side SE1 includes a The auxiliary gate line AG22 of the gate line GL2 is connected. In other words, the auxiliary gate line AG21 is not the one of the auxiliary gate lines AG closest to the boundary of the display area 111 , and at least one auxiliary gate line AG is included between it and the other side SE2 .

In some examples, when the longest auxiliary gate line (for example, the auxiliary gate line AG11 in FIG. 1 ) is connected to the gate line farthest from the gate driving circuit (for example, the gate line GL1 in FIG. ) is arranged at the outermost side of the display area (for example, the side closest to the first side SE1 in the first figure), the gate driving circuit 120 from above will reach the bottom of the display area 111 through the above line and be located in the center The distance between the pixels is relatively long, so the RC loading on the path will be relatively high.

Compared with the arrangement in which the auxiliary gate line AG11 connected to the gate line GL1 farthest from the gate driving circuit 120 is arranged at the outermost side of the display area 111 (adjacent to the first side SE1 ), by the above embodiment , which can effectively reduce the resistance-capacitance load of the auxiliary gate line AG11 and the gate fall time.

Please refer to Figure 2. FIG. 2 is a partial schematic diagram of the display device shown in FIG. 1 according to an embodiment of the disclosure. In order to make the drawings more concise and easy to understand, compared with FIG. 1 , the display device 100A in FIG. 2 omits the data driving circuit and the data lines, and further describes the gate driving circuit.

As shown in FIG. 2 , the display device 100A includes a substrate 110 and a gate driving circuit 120 . The substrate 110 includes a display area 111 . The display area 111 has a top edge E1 and a first side edge SE1. The gate driving circuit 120 is disposed adjacent to one side of the top edge E1.

In some embodiments, the display area 111 includes gate lines GL1 ˜ GL5 connected to the gate driving circuit 120 , and the gate lines GL1 ˜ GL5 are completely or substantially parallel to the top edge E1 of the display area 111 . The display area 111 includes a first auxiliary gate line group 1401 and a second auxiliary gate line group 1402 .

In some embodiments, the first auxiliary gate line group 1401 includes auxiliary gate lines AG11 ˜ AG15 . The auxiliary gate line AG11 is connected to the gate line GL1 farthest from the top edge E1, and the auxiliary gate line AG12 is offset by a distance X from the auxiliary gate line AG11 to the first side SE1, and is connected to the gate line GL1 farthest from the top edge E1. gate line GL2. The auxiliary gate line AG13 is offset by a distance X from the auxiliary gate line AG11 to the opposite side of the first side SE1, and is connected to the gate line GL3. By analogy, each auxiliary gate line AG is connected to one of the gate lines GL in a staggered manner of "left, right, left, right", so that the gate line GL can be turned to be connected to the adjacent top edge E1 the gate drive circuit 120.

In some embodiments, the second auxiliary gate line group 1402 includes auxiliary gate lines AG21 ˜ AG25 . The auxiliary gate line AG21 is connected to the gate line GL1 farthest from the top edge E1, and the auxiliary gate line AG22 is offset by a distance X from the auxiliary gate line AG21 to the opposite side of the first side SE1, and is connected to the top edge E1 The next most distant gate line GL2. The auxiliary gate line AG23 is offset by a distance X from the auxiliary gate line AG21 to the first side SE1, and is connected to the gate line GL3. By analogy, the auxiliary gate lines AG are connected to one of the gate lines GL in a staggered manner of “right, left, right, left”, so that the gate line GL can be turned to be connected to the gate line GL adjacent to the top edge E1. Gate drive circuit 120 .

It can be known from the above embodiments that the gate lines GL1 - GL5 are provided by one of the auxiliary gate lines AG in the first auxiliary gate line group 1401 and one of the auxiliary gate lines in the second auxiliary gate line group 1402 . The line AG is connected to the gate driving circuit 120 . In addition, the first auxiliary gate line group 1401 and the second auxiliary gate line group 1402 are mirror-symmetrical.

In some embodiments, when one gate line GL connects two auxiliary gate lines AG, the distance D1 between the auxiliary gate line AG11 and the first side SE1 is a quarter of the length L1 of the display area 111 , that is, D1=L1/4.

Please refer to Figure 3. FIG. 3 is a partial schematic diagram of the display device shown in FIG. 1 according to another embodiment of the disclosure. The difference between FIG. 3 and FIG. 2 is that the arrangement of the auxiliary gate lines AG in the first auxiliary gate line group 1401 and the second auxiliary gate line group 1402 is different. Although the first auxiliary gate line group 1401 and the second auxiliary gate line group 1402 in the display device 100B are mirror-symmetrical, the auxiliary gate lines AG in the first auxiliary gate line group 1401 are represented by "Right, Left, The auxiliary gate lines AG in the second auxiliary gate line group 1402 are arranged in a staggered manner of "left, right, left, right". In other words, unlike the first auxiliary gate line group 1401 in the display device 100A, the auxiliary gate lines inward from the first side SE1 are AG14, AG12, AG11, AG13 and AG15 in sequence, the display device 100B In the first auxiliary gate line group 1401, the auxiliary gate lines inward from the first side SE1 are AG15, AG13, AG11, AG12 and AG14 in sequence. The second auxiliary gate line group 1402 in the display device 100B is also changed correspondingly, and is not repeated here for the sake of simplicity.

Compared with the arrangement in which the auxiliary gate line AG11 connected to the gate line GL1 farthest from the gate driving circuit 120 is arranged at the outermost side of the display area 111 (adjacent to the first side SE1 ), by the above embodiment , which can effectively reduce the resistance-capacitance load of the auxiliary gate line AG11, and reduce the gate fall time by 15 to 25 percent.

Please refer to Figure 4. FIG. 4 is a partial schematic diagram of the display device shown in FIG. 1 according to another embodiment of the disclosure. The difference between FIG. 4 and FIG. 2 is that the symmetry and partial arrangement of the auxiliary gate lines AG in the first auxiliary gate line group 1401 and the second auxiliary gate line group 1402 are different. As shown in FIG. 4 , the first auxiliary gate line group 1401 of the display device 100C is the same as the first auxiliary gate line group 1401 of the display device 100A in FIG. 2 . The second auxiliary gate line group 1402 of the display device 100C is different from the second auxiliary gate line group 1402 of the display device 100A in FIG. 2, and is different from the auxiliary gate lines AG11~ in the first auxiliary gate line group 1401 The AG15 has the same arrangement. In other words, when the auxiliary gate lines AG11 to AG15 of the first auxiliary gate line group 1401 in the display device 100C are arranged in a staggered manner of “left, right, left, right”, the second auxiliary gate line group 1402 The auxiliary gate lines AG21 to AG25 are also arranged in a staggered manner of “left, right, left, right”, so that the first auxiliary gate line group 1401 and the second auxiliary gate line group 1402 in the display device 100C form a translation symmetry.

Similarly, when the auxiliary gate lines AG11 to AG15 of the first auxiliary gate line group 1401 are arranged in a staggered manner of "right, left, right, left" (not shown in the figure), the second auxiliary gate line group The auxiliary gate lines AG21 to AG25 of 1402 are then arranged in a staggered manner of "right, left, right, left" to form translational symmetry.

Compared with arranging the first auxiliary gate line group 1401 and the second auxiliary gate line group 1402 in a mirror-symmetrical manner, with the above-mentioned translational symmetry arrangement, in practice, the mask exposure can be performed in a splicing manner. It is more advantageous in terms of cost and efficiency of the process to be carried out without using different masks.

It should be noted that, in order to simplify the description, the above-mentioned embodiments and the accompanying drawings only take some components as an example to illustrate the connection relationship, and both are described by taking two auxiliary gate lines AG connected to one gate line GL as an example. The embodiment can be applied to any number of combinations of gate lines GL and data lines DL, and any number of auxiliary gate lines AG can be connected to the gate lines GL, and the present disclosure is not limited thereto. When each gate line GL is driven by n auxiliary gate lines AG (that is, n auxiliary gate lines AG are connected to the same gate line GL), it is connected to the gate line GL1 farthest from the top edge E1 Among the n auxiliary gate lines AG, the distance between the one closest to the first side SE1 and the first side SE1 is 1/2n times the length L1 of the display area, and the distance between the auxiliary gate lines AG is The pitch is 1/n times the length L1.

In the above embodiment, the gate driving circuit 120 is disposed above the display area 111 , and the data driving circuit 130 is also disposed above the display area 111 unilaterally. However, it should be understood that the present disclosure is not limited to the above-mentioned arrangement. In practical applications, the data driving circuit can be arranged at any position such as the bottom, the side, and the left and right sides of the display area.

Please refer to Figure 5. FIG. 5 is a schematic diagram of a display device 500 according to another embodiment of the disclosure. As shown in FIG. 5 , the display device 500 includes a substrate 510 , a gate driving circuit 520 , a data driving circuit 5301 and a data driving circuit 5302 .

The substrate 510 includes a display area 511, and the display area 511 has a top edge E1, a bottom edge E2, a first side edge SE1 and a second side edge SE2. The top edge E1 and the bottom edge E2 are substantially parallel and correspond to each other, and the first side edge SE1 and the second side edge SE2 are substantially perpendicular to the top edge E1 and are opposite to each other. The gate driving circuit 520 and the data driving circuit 5301 are disposed on the same side of the display area 111 and adjacent to the first side SE1 of the display area 111 . The data driving circuit 5302 is disposed adjacent to the second side SE2 of the display area 111 .

In some embodiments, the display area 111 includes a plurality of gate lines GL connected to the gate driving circuit 520 , and the gate lines GL and the top edge E1 of the display area 111 are completely parallel or substantially parallel.

In some embodiments, the display area 111 includes a first block B1 and a second block B2. The first block B1 includes data lines DL11 - DL13 and auxiliary data lines AD11 - AD13 for turning the data lines DL11 - DL13 to be connected to the data driving circuit 5301 . The second block B2 includes data lines DL21 - DL23 and auxiliary data lines AD21 - AD23 for turning the data lines DL21 - DL23 to be connected to the data driving circuit 5301 . The data lines DL11 ˜ DL13 , DL21 ˜ DL23 and the top edge E1 of the display area 111 are completely parallel or substantially parallel. The auxiliary data lines AD11 ˜ AD13 , AD21 ˜ AD23 and the top edge E1 of the display area 111 are completely vertical or substantially vertical.

In some embodiments, the auxiliary data lines AD11 ˜ AD13 and the auxiliary data lines AD21 ˜ AD23 are arranged in a mirror-symmetrical manner. For easy understanding, please refer to the first block B1 located in the left half of the display area 511 shown in FIG. 5 . The auxiliary data line AD11 is connected to the data line DL11 farthest from the first side SE1 in the first block B1, and the auxiliary data line AD12 is connected to the data line DL12 that is the second farthest from the first side SE1. By analogy, each auxiliary data line AD is connected to one of the data lines DL in a staggered manner of "up, down, up, and down". In other words, there is at least one auxiliary data line AD on both sides of the auxiliary data line AD11.

Similarly, please refer to the second block B2 located on the right half of the display area 511 shown in FIG. 5 . The auxiliary data line AD21 is connected to the data line DL21 farthest from the first side SE2 in the second block B2, and the auxiliary data line AD22 is connected to the data line DL22 farthest from the first side SE1. By analogy, each auxiliary data line AD is connected to one of the data lines DL in a staggered manner of "up, down, up, and down". In other words, at least one auxiliary data line AD is provided on both sides of the auxiliary data line AD11 and the auxiliary data line AD12.

In some embodiments, the distance D2 between the auxiliary data line AD11 and the auxiliary data line AD21 and the top edge E1 and the distance D3 between the auxiliary data line AD11 and the bottom edge E2 are equal.

In some embodiments, the auxiliary data lines AD11-AD13 and the auxiliary data lines AD21-AD23 can be centered on the auxiliary data line AD11 and the auxiliary data line AD21 respectively, so that the remaining auxiliary data lines AD are in the order of "down, up, down, up" ” are arranged in sequence in a staggered manner. To simplify the description, they will not be repeated here.

By the above-mentioned setting method in relation to FIG. 5, the data fall time can be reduced by about 15%, and it is especially suitable for a long-strip display panel.

In the above embodiment, the data driving circuit 5301 and the data driving circuit 5302 are arranged on both sides of the display area 511 , and the gate driving circuit 520 is arranged on one side of the display area 111 . However, it should be understood that the present disclosure is not limited to the above-mentioned arrangement. In practical applications, the gate driving circuit can be arranged at any position above, below, or on both sides of the display area.

To sum up, the display device provided by the present disclosure can achieve the narrow frame effect and reduce the load of resistance and capacitance by changing the line and placing the line connecting the farthest distance from the driving circuit to the inner side of the display area. .

Although this case has been disclosed above in terms of implementation, it does not limit this case. Anyone who is familiar with this technique can make various changes and modifications without departing from the spirit and scope of this case. Therefore, the scope of protection in this case should be regarded as attached hereto. The scope of the patent application shall prevail.

In order to make the above and other objects, features, advantages and embodiments of the present disclosure more clearly understood, the descriptions of the appended symbols are as follows: 100, 100A~100C, 500: Display device 110,510: Substrate 111,511: Display area 120,520: Gate drive circuit 130, 5301, 5302: Data drive circuit DL, DL11~DL13, DL21~DL23: data line AD11~AD13, AD21~AD23: Auxiliary data line GL, GL1~GL5: gate line AG11~AG15, AG21~AG25: Auxiliary gate line 1401: The first auxiliary gate line group 1402: The second auxiliary gate line group E1: top edge E2: Bottom edge SE1: First side SE2: Second side D1~D3: Distance L1: length

In order to make the above and other objects, features, advantages and embodiments of the present disclosure more clearly understood, the accompanying drawings are described as follows: FIG. 1 is a schematic diagram of a display device according to an embodiment of the disclosure. FIG. 2 is a partial schematic diagram of the display device shown in FIG. 1 according to an embodiment of the disclosure. FIG. 3 is a partial schematic diagram of the display device shown in FIG. 1 according to another embodiment of the disclosure. FIG. 4 is a partial schematic diagram of the display device shown in FIG. 1 according to another embodiment of the disclosure. FIG. 5 is a schematic diagram of a display device according to another embodiment of the disclosure.

Domestic storage information (please note in the order of storage institution, date and number) none Foreign deposit information (please note in the order of deposit country, institution, date and number) none

100A: Display device

110: Substrate

111: Display area

120: Gate drive circuit

GL1~GL5: gate line

AG11~AG15, AG21~AG25: Auxiliary gate line

E1: top edge

SE1: First side

1401: The first auxiliary gate line group

1402: The second auxiliary gate line group

D1: Distance

L1: length

Claims (10)

A display device, comprising: A substrate has a display area, the display area includes a first area and a second area, the first area is adjacent to a first side of the display area, and the second area is adjacent to a side of the display area a second side, the first side and the second side are located on opposite sides of the display area; a plurality of data lines, respectively disposed in the first block and the second block, in the first block, the plurality of data lines include a first data line farthest from the first side; a first driving circuit disposed adjacent to the first side of the display area; and A plurality of auxiliary data lines are respectively disposed in the first block and the second block, the auxiliary data lines are substantially vertically connected to the plurality of data lines, and are respectively parallel to a top side of the display area , the plurality of auxiliary data lines in the first block include: a first auxiliary data line for connecting the first data line to the first driving circuit; and At least one auxiliary data line is disposed between the top edge and the first auxiliary data line. The display device of claim 1, wherein the first block and the second block are mirror-symmetrical. The display device of claim 1, wherein the plurality of auxiliary data lines in the first block further comprise: a plurality of second auxiliary data lines disposed on one side of the first auxiliary data lines; and A plurality of third auxiliary data lines are arranged on the other side of the first auxiliary data lines. The display device of claim 3, wherein the first auxiliary data line, the plurality of second auxiliary data lines, and the plurality of third auxiliary data lines are respectively connected to the first block in a staggered manner the plurality of data lines. The display device of claim 1, wherein a first distance between the first auxiliary data line and the top edge is equal to a second distance between the first auxiliary data line and a bottom edge, wherein the top edge is opposite to the bottom edge. The display device of claim 1, wherein the plurality of data lines include a second data line farthest from the second side, and the plurality of auxiliary data lines in the second block further include: a fourth auxiliary data line connected to the second data line; a plurality of fifth auxiliary data lines arranged on one side of the fourth auxiliary data line; and A plurality of sixth auxiliary data lines are arranged on the other side of the fourth auxiliary data lines. The display device of claim 6, wherein the fourth auxiliary data line, the plurality of fifth auxiliary data lines and the plurality of sixth auxiliary data lines are respectively connected to the second block in a staggered manner the plurality of data lines. The display device of claim 6, wherein the display device further comprises a second driving circuit, the second driving circuit is disposed adjacent to the second side of the display area, wherein the fourth auxiliary data line is the second driving circuit The data line is connected to the second driving circuit. The display device of claim 6, wherein a third distance between the fourth auxiliary data line and the top edge is equal to a fourth distance between the fourth auxiliary data line and a bottom edge, wherein the top edge is opposite to the bottom edge. The display device of claim 6, wherein the auxiliary data lines in the first block and the auxiliary data lines in the second block are mirror-symmetrical.

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