TWI487990B - Active device array substrate and display panel thereof - Google Patents

Description

Display panel and active device array substrate thereof

The present invention relates to a display panel and an active device array substrate thereof, and more particularly to an active device array substrate having a narrow frame side and a display panel.

Generally, the display panel is composed of an active device array substrate, an opposite substrate, and a display medium. When the active device array is fabricated, a peripheral circuit that cooperates with the die-glass bonding process or the die-film bonding process is usually fabricated simultaneously in the non-display area (peripheral region) of the active device array substrate.

FIG. 1 is a top plan view of a conventional active device array substrate. Referring to FIG. 1 , the active device array substrate 10 includes a substrate 11 , a plurality of scanning lines 12 , a plurality of data lines 13 , a plurality of pixel units 14 , a gate driving wafer 15 , and a source driving wafer 16 . The substrate 11 has a display area A and a non-display area B surrounding the display area A. The scanning lines 12 are arranged on the substrate 11 in parallel with each other in a direction from left to right. The data lines 13 are arranged parallel to each other on the substrate 11 in parallel with each other, and are interleaved perpendicularly to the data lines 13 to form a plurality of pixel units 14 located in the display area A.

The substrate 11 has a first side 11a and a second side 11b which are adjacent to each other. The gate driving chip 15 is located in the non-display area B of the first side 11a of the substrate 11 and is electrically connected to the scan lines 12. The source driving chip 16 is located in the non-display area B of the second side 11b of the substrate 11 and is electrically connected to the data lines 13. In particular, the scan line 12 passes through the display area A. The non-display area B on the left and right sides performs wire routing of the peripheral lines to electrically connect the gates to drive the wafer 15. The data line 13 passes through the non-display area B on the upper and lower sides of the display area A to perform wire routing of the peripheral lines to electrically connect the source driving wafer 16.

However, as many applications of display panels are gradually moving toward light, thin, short, and small trends, such as mobile phones, digital cameras and other electronic products, plus gate drive wafers and source drive wafers for the two sides of the substrate. Most of the space in the non-display area causes the active device array substrate to create a problem that it is difficult to achieve a narrow bezel.

Therefore, how to provide a solution to solve the problem that the active device array substrate is difficult to realize a narrow bezel to improve the portability of the electronic product is a problem that needs to be solved urgently.

The invention provides an active device array substrate with narrow frame edges, which can improve space utilization.

The invention provides an active device array substrate. The active device array substrate comprises a plurality of pixel units, a plurality of scan lines and a plurality of data lines. The pixel units are arranged in an X×Y pixel array, and both X and Y are positive integers, and X>Y>1. The scan lines are coupled to the pixel units. The data lines conform to an arrangement and are coupled to the pixel units in the pixel array. The arrangement manner is consistent with the i-th+1 pixel unit of the i-th data line coupled to the j-th column, i=1~X, i≧j, wherein when i≦Y, j=1~i, Conversely, when i>Y, j=1~Y, i and j are positive integers.

Furthermore, in an embodiment of the invention, the mth of the data lines The data line is further coupled to the Xth row of X+Y-n-m+1 pixel units, where m=1~(X-Y), n=(Y-m+1)~Y, and m and n are positive integers.

The invention further provides an active device array substrate, the active device array substrate comprising a substrate, a pixel array, a plurality of scan lines and a plurality of data lines. The pixel array is arranged on the substrate by a plurality of pixel units, including the first side and the second side and the opposite third side and the fourth side, wherein the first side and the second side are both located on the third side and the first side Between the four sides. The scan lines are arranged in parallel and spaced apart within the pixel array. The data lines are disposed in the pixel array, and the scan lines pass through the first side of the pixel array. Each of the data lines alternately extends toward the second side and the fourth side of the pixel array in the pixel array such that a stepped shape is formed in the pixel array in a staggered arrangement with the scan lines.

In an embodiment of the invention, the pixel array includes a plurality of pixel columns and pixel rows arranged in parallel. The pixel units of each pixel row and the pixel units of each pixel column are linear and spaced apart from each other. The scan lines are parallel to the pixel rows, and each scan line is coupled to all of the pixel cells in one of the pixel rows.

In an embodiment of the invention, each data line is coupled to at least one pixel unit of a different pixel column.

In one embodiment of the present invention, all of the pixel units to which the data lines are coupled are not arranged in the same pixel row of the pixel array, and are not arranged in the same pixel column of the pixel array.

In an embodiment of the invention, each data line includes a plurality of first segments and a plurality of second segments. These first segments are parallel to the scan lines. The second segments are perpendicular to the scan lines, and each of the second segments is connected between any two adjacent first segments and is located in a different pixel row.

In an embodiment of the invention, the pixel arrays are arranged according to an X×Y array mode, wherein X and Y are positive integers, and X>Y>1.

In one embodiment of the present invention, the number of the scan lines is the same as the number of the data lines, which are all X.

In an embodiment of the invention, when each scan line activates all of the pixel units in one of the pixel rows, only the number of Y data lines respectively provide the pixel unit data to all of the pixel units in the corresponding pixel row.

In one embodiment of the invention, a total number of (X-Y) data lines pass through the fourth side of the pixel array and extend from outside the pixel array to the second side of the pixel array.

In an embodiment of the invention, the number of (XY) data lines passes through the second side of the pixel array, and alternately extends in the pixel array toward the first side and the third side, such that the pixels Another step in the array is formed in a staggered configuration with the scan lines.

In an embodiment of the invention, the active device array substrate further includes at least one source driving wafer and at least one gate driving wafer. The source drive wafer is located on one side of the substrate. The gate drive wafer and the source drive wafer share the same side of the substrate.

The invention further proposes an active device array substrate. The active device array substrate includes a plurality of pixel units, a plurality of scan lines, and a plurality of data lines. The pixel units are arranged in an array of pixels. Each of the scan lines is coupled to the pixel units of the same row. The data lines are stepped and diagonally coupled to the pixel units. All the pixel units to which the data lines are connected are not arranged in the same row of the pixel array, and all the pixel units to which the data lines are coupled are not arranged in the same column of the pixel array.

In an embodiment of the invention, the pixel arrays are arranged according to an array of X×Y, where X>Y>1, and X and Y are positive integers.

In one embodiment of the invention, a total of (X-Y) data lines extend from one side of the pixel array and extend to the other side of the pixel array, wherein the two sides are adjacent to each other.

The present invention further provides a display panel having the above-described active device array substrate, which can reduce manufacturing cost and increase product portability.

Such a display panel includes the above-described active device array substrate, a counter substrate, and a display medium. The display medium is disposed between the opposite substrate and the active device array substrate.

In summary, since the active device array substrate of the present invention has a unique circuit design, the present invention can reduce the frame width and thereby improve space utilization. Furthermore, since the display panel of the present invention has the active element array substrate described above, the present invention can reduce manufacturing costs and increase product portability.

The present invention will be apparent from the following description and the detailed description of the embodiments of the present invention, which may be modified and modified by the teachings of the present invention without departing from the invention. The spirit and scope.

The active device array substrate of the present invention comprises a pixel array arranged by a plurality of pixel units, a plurality of scan lines and a plurality of data lines. The scan line is coupled to the pixel unit of the same row. The data lines are substantially all diagonally coupled to all of the pixel units in a stepped arrangement. As such, due to the active components of the present invention The stepped circuit layout design on the array substrate reduces the space on the active device array substrate to occupy the space of the edge region of the active device array substrate, helps reduce the width of the active device array substrate side, or improves the side of the active device array substrate. Space utilization.

2 is a top view of the active device array substrate of the present invention. Referring to FIG. 2, an active device array substrate 400 includes a substrate 410, one or more source driving chips 420, one or more gate driving wafers 430, a pixel array 440, and a plurality of scanning lines 500 (scan line And a plurality of data lines 600 (source line or data line). The substrate 410 includes a display area A and a non-display area B adjacent to the display area A. The pixel array 440 is disposed on the substrate 410. The area of the pixel array 440 is defined as the display area A described above, and the non-display area B is the frame area after the substrate 410 is deducted from the display area A.

The pixel array 440 is arranged by a plurality of pixel units 450 (or sub-pixels), such as red pixel units, blue pixel units, and green pixel units. The pixel array 440 includes a first side 441 and a second side 442 and an opposite third side 443 and a fourth side 444. The first side 441 and the second side 442 are both located between the third side 443 and the fourth side 444. .

The source driving wafer 420 is located in the frame side region on the side of the substrate 410. The gate driving wafer 430 and the source driving wafer 420 are in the rim region on the same side of the substrate 410. In this way, the active device array substrate 400 of the present invention is more helpful in achieving narrow frame edge characteristics, thereby improving space utilization. Further, the source driving wafer 420 and the gate driving wafer 430 may also be integrated into a single individual, however, the present invention is not limited to the above variations.

The number of scan lines 500 is less than or equal to the number of data lines 600, and the scan lines 500 are disposed in the pixel array 440 in parallel and spaced apart from each other. Specifically, the scan line 500 is connected to the gate driving wafer 430 and passes through the first side 441 and the second side 442 of the pixel array 440, that is, the frame edge region of the scan line 500 from the substrate 410 side (ie, the non-display area). B) extends through pixel array 440 to another rim region of substrate 410 (ie, non-display region B).

The data lines 600 are disposed in the pixel array 440 at intervals, and all of the pixel units 450 are obliquely coupled in a direction toward the lower right in the figure in a substantially stepped manner. Specifically, the data line 600 passes through the first side 441 of the pixel array 440 and enters the pixel array 440, and alternately faces the second side 442 of the pixel array 440 and the fourth toward the pixel array 440 in the pixel array 440. The direction of the side 444 extends such that the data line 600 forms a first stepped path (e.g., the direction of the data line 600c of FIG. 4c) that is interleaved with the scan line 500 within the pixel array 440.

In more detail, the pixel array 440 includes a plurality of pixel columns 451 and pixel rows 452 arranged in parallel. The pixel row 452, as shown in Fig. 2, is parallel to each other in the upward and downward directions in the figure. The pixel column 451, as shown in Fig. 3, is parallel to each other in the direction of the left and right in the figure. The direction of the pixel column 451 is orthogonal to the direction of the pixel row 452. The pixel unit 450 in each pixel row 452 and the pixel unit 450 in each pixel column 451 are linear and spaced apart from each other. The scan line 500 is parallel to the pixel row 452, and each scan line 500 is coupled to all of the pixel cells 450 in each pixel row 452.

In addition, all the pixel units 450 to which the data lines 600 are coupled are not arranged in the same pixel row 452 of the pixel array 440, and are not arranged in the same pixel column 451 of the pixel array 440. In more detail, each data line 600 A plurality of first segments 610 and a plurality of second segments 620 are included. Each of the second segments 620 is directly connected between any two adjacent first segments 610 and is located in a different pixel row 452, and is coupled to at least one pixel unit 450 in a different pixel row 452. The first segment 610 extends toward the upper and lower directions of the drawing, and is not limited to be parallel to the scanning lines 500 or not parallel to each other. The second segment 620 extends in the left and right directions, and is not limited to being perpendicular to the scanning line 500 or perpendicular to each other. However, the present invention is not limited thereto, and each data line may also be coupled to two or more pixel units in different pixel columns, and/or two or more pixel units in different pixel rows.

In addition, as can be seen from FIG. 2, a portion of the data lines 600 extend from the fourth side 444 to the pixel array 440 and then extend to the second side 442 of the pixel array 440, respectively, and from the second side 442 of the pixel array 440. After extending into the pixel array 440, the pixel array 440 is alternately extended in the direction of the first side 441 and the third side 443, so that a second stepped route interposed with the scan line 500 is formed in the pixel array 440 ( For example, the direction of the data line 600f in Figure 5d). In this way, the remaining pixel units 450 that are not located in the first stepped path can also be coupled to the data line 600 by the second stepped route, so that no additional number of data lines need to be configured, thereby helping to reduce manufacturing. Cost and implementation of narrow rim features of the active device array substrate.

FIG. 3 is a top view of a pixel array according to an embodiment of the invention. Referring to FIG. 3, the coupling relationship between the first stepped path of the data line 600 and the pixel unit 450 is further described mathematically.

The pixel array 440 is an X×Y array, wherein both X and Y are Is a positive integer, X>Y>1. Therefore, the pixel unit 450 in each pixel column 451 is 1~X, and the number thereof is X, which is also consistent with the number of the scan line 500 and the data line 600. The number of pixel units 450 in each pixel row 452 is 1~Y, and the number is Y.

The data line 600 is coupled to the majority of the pixel units 450 in accordance with the first arrangement to form the first stepped path described above. The first arrangement is in accordance with the i-th+1 pixel unit 450 of the i-th data line 600 coupled to the j-th column, i=1~X, i≧j, wherein when i≦Y, j =1~i, otherwise, when i>Y, j=1~Y, i and j are positive integers.

For example, the 4a to 4d diagrams are schematic diagrams of the lower right direction of a certain data line in the 9x5 pixel array 440.

As shown in FIG. 4a, when X=9, Y=5 is taken as an example, and when the i-th data line 600 is in order from right to left, and the j-th column of the pixel array 440 is in order from top to bottom. The following provides a number of explanations for the change of the data line in the 9x5 pixel array 440 according to the first arrangement described above and the coupling relationship with the pixel unit (hereinafter, the pixel unit coupled by the dot square): as in 4a As shown in the figure, when i=1, it corresponds to i≦5, j=1~1, so the first data line 600a is coupled to the (1-1+1=1)th pixel unit 450a of the first column of the pixel array 440. (As shown in the dot box); as shown in Fig. 4b, when i=3, it conforms to i≦5, j=1~3, so the third data line 600b is coupled to the first column of the pixel array 440 (3) -1+1=3) pixel unit 450b (as indicated by a dot box), (3-2+1=2) pixel unit 450c of the second column (as indicated by a dot box), and the third column (3-3+1=1) pixel units 450d (as indicated by dot boxes); As shown in FIG. 4c, when i=7, i>5, j=1~5 is met, so the seventh data line 600c is coupled to the (7-1+1=7)th column of the first column of the pixel array 440. Pixel unit 450e (as indicated by the dot box), (7-2+1=6) pixel unit 450f of the second column (as indicated by the dot box), and the third column (7-3+1=5) a pixel unit 450g (as shown by a dot box), a fourth (7-4+1=4) pixel unit 450h of the fourth column (as indicated by a dot box), and a fifth column (7-5+1) = 3) pixel units 450i (as indicated by the dot matrix).

As shown in FIG. 4d, when i=9, i=5, j=1~5, so the ninth data line 600d is coupled to the first column of the pixel array 440 (9-1+1=9). Pixel unit 450j (as indicated by the dot box), (9-2+1=8) pixel unit 450k of the second column (as indicated by the dot box), and the third column (9-3+1=) 7) pixel unit 450l (as shown by the dot box), the (9-4+1=6) pixel unit 450m of the fourth column (as indicated by the dot box), and the fifth column (9-5+) 1 = 5) pixel units 450n (as indicated by the dot matrix).

In addition, referring to FIG. 3, the number of the data lines 600 in the second stepped path and the coupling relationship between the data lines 600 and the pixel unit 450 in the second stepped path are also mathematically described below.

In this embodiment, a total number of (X-Y) data lines 600 extend from the pixel array 440 beyond the fourth side 444 of the pixel array 440 and extend from the outside of the pixel array 440 to the second side 442 of the pixel array 440, respectively. The number of (XY) data lines 600 pass through the second side 442 of the pixel array 440 and alternately extend in the direction of the first side 441 and the third side 443 in the pixel array 440, so that the pixel array 440 is formed. The second stepped route described above is alternately arranged with the scanning line 500.

The data line 600 described above extends from the second side 442 of the pixel array 440 After the pixel array 440, the data lines 600 are coupled to the remaining portion of the pixel unit 450 in accordance with the second arrangement to form the second stepped path described above. The second arrangement is in accordance with the mth data line 600 in the data line 600, and is further coupled to the nth column, X+Yn-m+1 pixel units 450, where m=1~(XY), n= (Y-m+1)~Y, m and n are both positive integers.

For the same example, the 5th to 5th diagrams are schematic diagrams of the upper left direction of a certain data line 600 in the 9x5 pixel array 440.

In the same example, as in Figure 5a, when X=9, Y=5, and when the mth data line 600 is in order from right to left, and the nth column of the pixel array 440 is in order from top to bottom , then m = 1 ~ (9-5 = 4), the following provides a number of explanation data lines according to the second arrangement of the above-mentioned changes in the 9x5 pixel array and the coupling relationship with the pixel unit (hereinafter by the dot box) Represents the pixel unit being coupled): As shown in FIG. 5a, when m=1, n=(5-1+1=5)~5, the first data line 600a is further coupled to the fifth column of the pixel array 440 (9+5-5- 1+1=9) pixel units 450o (as shown in the dot box); as shown in Figure 5b, when m=2, n=(5-2+1=4)~5, the second data line 600e is further coupled to the fifth column of the pixel array 440 (9+5-5-2+1=8) pixel units 450p (as shown in the dot box) and the fourth column (9+5-4-2+1) =9) pixel unit 450q (as shown in the dot box); as shown in Fig. 5c, when m=3, n=(5-3+1=3)~5, the third data line 600b is more coupled. Connected to the fifth column of the pixel array 440 (9+5-3-2+1=7) pixel units 450r (as shown in the dot box), and the fourth column (9+5-4-3+1=8) a pixel unit 450s (shown as a dot box) and a third column (9+5-3-3+1=9) pixel units 450t (as shown by the dot matrix); As shown in FIG. 5d, when m=4, n=(5-4+1=2)~5, the fourth data line 600f is further coupled to the fifth column of the pixel array 440 (9+5-5- 4+1=6) pixel units 450u (as indicated by dot boxes), 4th column (9+5-4-4+1=7) pixel units 450v (as indicated by dot boxes), column 3 The (9+5-3-4+1=8) pixel unit 450w (shown as a dot box) and the second column (9+5-2-4+1=9) pixel unit 450x (such as a dot) As shown in the box).

FIG. 6 is a top plan view of a pixel array 440 according to another embodiment of the present invention. Referring to Fig. 6, the order of the first to ninth pixel rows 452 in Fig. 6 is changed from left to right. Although the first stepped direction of the data line 600 in FIG. 6 is obliquely coupled to most of the pixel units 450 in the lower left direction of the figure, the second stepped direction of the data line 600 is oblique to the upper right direction in the figure. The remaining pixel unit 450 is coupled to the ground. However, the downward direction of the data line 600 in FIG. 6 is also applicable to the rule of the first arrangement, and the direction of the data line 600 toward the upper right also applies to the second arrangement. rule.

7a to 7b are schematic diagrams showing the operation of one of the scan lines and the corresponding five data lines in the 9x5 pixel array, wherein the activated pixel unit is represented by a dot square.

In operation, as shown in FIG. 7a, when the active device array substrate 400 is driven, first, a pixel unit turn-on voltage is sequentially input to the scan lines, and then, when the scan lines are sequentially input to the pixel unit turn-on voltage, sequentially Input pixel unit data for the data lines interleaved with these scan lines.

For example, as shown in FIG. 7a, when the pixel cell turn-on voltage is input to the first scan line 501 to all the pixel cells 450A-E of the first row of the pixel array 440, from the right to the left, 1~5 data lines 601 to 605 input pixel unit data for the first to fifth pixel units 450A to E of the first row of the pixel array 440 from the top to the bottom. That is, the first data line 601 inputs the pixel unit data, the second data line 602, and the pixel array 440 to the first pixel unit 450A (shown as a dot box) in the top-to-bottom order in the first row of the pixel array 440. In the first row, the second pixel unit 450B (shown as a dot box) in the top-to-bottom order inputs the pixel unit data, and the third data line 603 is the third in the first row from the top to the bottom of the pixel array 440. The pixel unit 450C (shown as a dot box) inputs the pixel unit data, and the fourth data line 604 inputs the fourth pixel unit 450D (shown as a dot box) in the top-to-bottom order of the pixel array 440 in the first row. The pixel unit data, and the fifth data line 605, input pixel unit data to the fifth pixel unit 450E (shown as a dot box) in the top-to-bottom order in the first row of the pixel array 440.

Referring to FIG. 7b, when the second scanning line 502 inputs a pixel unit turn-on voltage to all the pixel units 450F~J of the second row of pixel rows, the second to sixth data lines 602-606 respectively The second row of the pixel array 440 inputs the pixel unit data from the first to fifth pixel units 450F to J in the top-to-bottom order. That is, the second data line 602 inputs the pixel unit data, the third data line 603, and the pixel array 440 to the first pixel unit 450F (shown as a dot box) in the top-to-bottom order in the second row of the pixel array 440. In the second row, the second pixel unit 450G (shown as a dot box) in the top-to-bottom order inputs the pixel unit data, the fourth data line 604, and the third row from the top to the bottom in the second row of the pixel array 440. The pixel unit 450H (shown as a dot box) inputs the pixel unit data, the fifth data line 605, and the fourth pixel unit 450I in the second row from the top row of the pixel array 440 (such as a dot box) The input of one pixel unit data, and the sixth data line 606 input pixel unit data to the fifth pixel unit 450J (shown as a dot box) in the top-to-bottom order of the second row of the pixel array 440.

Therefore, it can be seen that, in the above-mentioned pixel array 440 is an X×Y array, when X (for example, 9) scan lines respectively activate all the pixel units in the corresponding pixel row, only the number is Y ( For example, 5) data lines respectively provide pixel unit data to all pixel units of the corresponding pixel row, and do not need to use all data lines.

FIG. 8 is a schematic diagram of a display panel 100 according to an embodiment of the present invention. Referring to FIG. 8, the active device array substrate 400 described above is more applicable to a display panel 100. The display panel 100 includes a counter substrate 200, a display medium 300, and the above-described active device array substrate 400. The counter substrate 200 is disposed above the active device array substrate 400. The display medium 300 is disposed between the opposite substrate 200 and the active device array substrate 400. The display panel 100 is, for example, a liquid crystal display panel, an electrophoretic display panel, or other display panel. The counter substrate 200 is, for example, a color filter substrate, and the display medium 300 is, for example, a liquid crystal layer or other material. In the present embodiment, the display panel 100 is, for example, a display panel of landscape viewing, however, the present invention is not limited thereto.

In summary, since the active device array substrate of the present invention has a unique circuit design, the present invention can reduce the frame width and thereby improve space utilization. Furthermore, since the display panel of the present invention has the active element array substrate described above, the present invention can reduce manufacturing costs and increase product portability.

The present invention is not limited to the present invention. It is to be understood that the scope of the present invention is defined by the scope of the appended claims.

100‧‧‧ display panel

200‧‧‧ opposite substrate

300‧‧‧Display media

400‧‧‧Active component array substrate

410‧‧‧Substrate

420‧‧‧Source Drive Chip

430‧‧ ‧ gate drive chip

440‧‧‧pixel array

441‧‧‧ first side

442‧‧‧ second side

443‧‧‧ third side

444‧‧‧ fourth side

450, 450a~450x‧‧‧ pixel units

451‧‧‧pixel columns

452‧‧‧ pixel row

500, 501~502‧‧‧ scan lines

600, 600a~600f, 600A~600J, 601~606‧‧‧ data line

610‧‧‧ first paragraph

620‧‧‧ second paragraph

A‧‧‧ display area

B‧‧‧Non-display area

The above and other objects, features, advantages and embodiments of the present invention will become more apparent and understood.

2 is a top view of the active device array substrate of the present invention.

FIG. 3 is a top view of a pixel array according to an embodiment of the invention.

4a to 4d are schematic diagrams of the right lower direction of a data line in a 9x5 pixel array.

Figures 5a to 5d are schematic diagrams of the upper left direction of a data line in a 9x5 pixel array.

FIG. 6 is a top view of a pixel array according to another embodiment of the present invention.

Figures 7a through 7b are schematic diagrams of a single scan line and its corresponding five data lines in a 9x5 pixel array.

Figure 8 is a schematic view of a display panel in accordance with an embodiment of the present invention.

400‧‧‧Active component array substrate

410‧‧‧Substrate

420‧‧‧Source Drive Chip

430‧‧ ‧ gate drive chip

440‧‧‧pixel array

441‧‧‧ first side

442‧‧‧ second side

443‧‧‧ third side

444‧‧‧ fourth side

450‧‧‧pixel unit

451‧‧‧pixel columns

452‧‧‧ pixel row

500‧‧‧ scan line

600‧‧‧Information line

610‧‧‧ first paragraph

620‧‧‧ second paragraph

A‧‧‧ display area

B‧‧‧Non-display area

Claims (16)

An active device array substrate comprising: a plurality of pixel units arranged in an X×Y pixel array, X and Y are positive integers, X>Y>1, wherein the pixel array comprises a plurality of pixel columns arranged in parallel a pixel row, the pixel units of each of the pixel rows and the pixel cells of each of the pixel columns are linear and spaced apart from each other; a plurality of scan lines coupled to the pixel cells, the scan lines Parallel to the plurality of pixel rows, each of the scan lines being coupled to all of the pixel cells in one of the pixel rows; and a plurality of data lines coupled to the pixel cells in the pixel array, wherein the ith row The data line is coupled to the i-th+1 pixel unit of the jth column, i≧j, i=1~X, when i≦Y, j=1~i, when i>Y, j=1~ Y, i and j are both positive integers. The active device array substrate according to claim 1, wherein the mth data line is further coupled to the nth column of X+Yn-m+1 pixel units, where m=1~(XY), n=(Y- m+1)~Y, m and n are positive integers. An active device array substrate includes: a substrate; an array of pixels arranged on the substrate by a plurality of pixel units, including opposite first and second sides and opposite third and fourth sides, The first side and the second side are both located between the third side and the fourth side, and the pixel array comprises a plurality of pixel columns and pixel rows arranged in parallel, each The pixel units of the pixel rows and the pixel units of each of the pixel columns are linear and spaced apart from each other; a plurality of scan lines are disposed in the pixel array in parallel and at intervals, and the scan lines are Parallelizing the pixel rows and each of the scan lines is coupled to all of the pixel cells in one of the pixel rows; and a plurality of data lines disposed in the pixel array, and the scan lines are all passed through the pixel array The first side, each of the data lines alternately extending toward the second side and the fourth side of the pixel array in the pixel array, such that a pixel line is interlaced with the scan lines The configuration is stepped. The active device array substrate of claim 3, wherein each of the data lines is coupled to at least one pixel unit of a different pixel column. The active device array substrate of claim 4, wherein all the pixel units to which each of the data lines are coupled are not arranged in the same pixel row of the pixel array, and are not arranged in the same pixel column of the pixel array. . The active device array substrate of claim 3, wherein each of the data lines comprises: a plurality of first segments parallel to the scan lines; and a plurality of second segments perpendicular to the scan lines, each of the plurality of scan lines The second segment is connected between any of the first segments adjacent to each other and is located in a different pixel row. The active device array substrate according to claim 3, wherein the pixel The arrays are arranged according to an X×Y array, X and Y are positive integers, and X>Y>1. The active device array substrate according to claim 7, wherein the number of the scan lines is the same as the number of the data lines, which are all X. The active device array substrate of claim 7, wherein when each of the scan lines activates all of the pixel units in the one of the pixel rows, only the number of the plurality of data lines respectively provide the pixel unit data to Corresponding to all pixel units of the pixel rows. The active device array substrate of claim 7, wherein a total number of (X-Y) data lines pass through the fourth side of the pixel array and extend from the outside of the pixel array to the second side of the pixel array. The active device array substrate of claim 10, wherein the (XY) number of data lines pass through the second side of the pixel array, and alternately face the first side and the first in the pixel array The direction of the three sides extends such that another step shape in which the scanning lines are alternately arranged is formed in the pixel array. The active device array substrate of claim 3 further comprising: at least one source driving wafer on one side of the substrate; and at least one gate driving wafer co-located with the source driving chip on the same side of the substrate. An active device array substrate comprising: a plurality of pixel units arranged in a pixel array, the pixel array comprising a plurality of pixel columns and pixel rows arranged in parallel, the pixel units of each of the pixel rows and each of the pixels The plurality of pixel units are linear and spaced apart from each other; a plurality of scan lines are parallel to the pixel lines, and each of the scan lines is coupled to all of the pixel units of the same row; and a plurality of data Each of the data lines is stepped and obliquely coupled to the pixel units, and all of the pixel units to which each of the data lines are coupled are not arranged in the same row of the pixel array, and each of the pixels All of the pixel units to which the data lines are coupled are also not arranged in the same column of the pixel array. The active device array substrate according to claim 13, wherein the pixel array is arranged according to an array of X×Y, X>Y>1, and X and Y are positive integers. The active device array substrate of claim 14, wherein the plurality of (XY) of the data lines protrude from one side of the pixel array and extend to the other side of the pixel array, wherein the side is The other side is adjacent. A display panel comprising: an active device array substrate according to any one of claims 1 to 15; a pair of substrates disposed above the active device array substrate; A display medium is disposed between the opposite substrate and the active device array substrate.