KR102207621B1 - Liquid crystal display device - Google Patents

Abstract

The present invention includes a gate wiring and a data wiring crossing each other on a first substrate to define a pixel region; A gate electrode connected to the gate line, a semiconductor layer disposed on the gate electrode, a source electrode connected to the data line on the semiconductor layer, and a drain spaced apart from the source electrode and disposed on one side of the gate line A thin film transistor including an electrode; A pixel electrode located in the pixel region and connected to the drain electrode; A common wiring extending along an extension direction of the gate wiring, positioned on one side of the gate wiring, and overlapping the drain electrode; A common electrode connected to the common wiring and facing the pixel electrode; A liquid crystal display device including a black matrix including a first portion covering the gate wiring, the thin film transistor, and the common wiring on a second substrate is provided.

Description

Liquid crystal display device

The present invention relates to a display device, and more particularly, to a liquid crystal display device capable of improving the aperture ratio and light transmittance by reducing the width of a black matrix in a liquid crystal display device having a common wiring.

As the information society develops, the demand for display devices for displaying images is increasing in various forms, and in recent years, liquid crystal display devices (LCD), plasma display panels (PDP), organic Various flat display devices such as OLED (organic light emitting diodes) are being used.

Among these flat panel display devices, liquid crystal display devices are widely used because they have advantages of miniaturization, weight reduction, thinness, and low power driving.

A liquid crystal display device displays an image by driving a liquid crystal by generating an electric field between a pixel electrode and a common electrode.

Recently, a horizontal electric field type liquid crystal display device in which a pixel electrode and a common electrode are formed together on an array substrate to drive a liquid crystal with a horizontal electric field is widely used. As such a transverse electric field type liquid crystal display device, for example, an in-plane switching (IPS) mode liquid crystal display device in which electrode patterns of pixel electrodes and common electrodes are alternately arranged, or layers having different pixel electrodes and common electrodes A fringe-field switchig (FFS) mode liquid crystal display device is used, which is disposed on and configured one of them as an electrode pattern.

1 is a schematic cross-sectional view of a conventional transverse electric field type liquid crystal display device.

Referring to FIG. 1, a liquid crystal display device includes an array substrate below, a color filter substrate above, and a liquid crystal layer 10 between the two substrates.

In the array substrate, a gate wiring 22 and a data wiring (not shown) crossing each other to define the pixel region P are formed on the inner surface of the first substrate 11. In the pixel region P, a thin film transistor T including a gate electrode 24 and a source electrode and drain electrodes 54 and 56, and a pixel electrode 72 connected to the drain electrode 56 of the thin film transistor T. ) Is formed. The common electrode 82 is formed on the pixel electrode 72, and the common electrode 82 has a plurality of bar-shaped electrode patterns 83 corresponding to the pixel region P.

In addition, a common wiring 26 is formed on the array substrate, spaced apart from the gate wiring 22 and extending in parallel, and connected to the common electrode 82.

On the other hand, the gate insulating layer 30 is formed on the gate wiring 22, the first and second protective layers 60 and 62 are formed on the source and drain electrodes 54 and 56, and the third protective layer is formed on the pixel electrode 72. A protective film 80 is formed.

In the color filter substrate facing the array substrate, the color filter 94 corresponding to the pixel region P on the inner surface of the second substrate 91, the gate wiring 22 of the array substrate, the data wiring and the thin film transistor T ) And a black matrix 92 corresponding to a non-display device such as a common wiring 26 is formed.

In such a conventional liquid crystal display device, the common wiring 26 and the thin film transistor T are disposed near both sides with the gate wiring 22 interposed therebetween.

Accordingly, the black matrix 92 positioned on the gate wiring 22 is formed to cover not only the gate wiring 22 but also the thin film transistors and common wirings T and 26 positioned on both sides of the gate wiring 22 Should be.

Accordingly, the width (wbp) of the black matrix 92 increases, and thus the aperture ratio and light transmittance are lowered.

An object of the present invention is to provide a method of improving the aperture ratio and transmittance by reducing the width of the black matrix located above the gate wiring.

In order to achieve the above-described problems, the present invention provides a gate wiring and a data wiring crossing each other on a first substrate to define a pixel region; A gate electrode connected to the gate line, a semiconductor layer disposed on the gate electrode, a source electrode connected to the data line on the semiconductor layer, and a drain spaced apart from the source electrode and disposed on one side of the gate line A thin film transistor including an electrode; A pixel electrode located in the pixel region and connected to the drain electrode; A common wiring extending along an extension direction of the gate wiring, positioned on one side of the gate wiring, and overlapping the drain electrode; A common electrode connected to the common wiring and facing the pixel electrode; A liquid crystal display device including a black matrix including a first portion covering the gate wiring, the thin film transistor, and the common wiring on a second substrate is provided.

Here, the common wiring may overlap a connection portion of the drain electrode connected to the pixel electrode.

It may include a gate insulating layer positioned on the common wiring, the gate wiring, and the gate electrode, and positioned under the source electrode and the drain electrode.

At least one of the common electrode and the pixel electrode may have a plurality of bar-shaped electrode patterns.

An insulating layer disposed between the common electrode and the pixel electrode may be included.

The black matrix may include a second portion covering the data line.

In the present invention, the thin film transistor and the common wiring are positioned together near one side of the gate wiring.

Accordingly, the black matrix on the gate wiring can have a significantly narrower width compared to the prior art, since it only needs to be extended in one direction of the gate wiring. Accordingly, the aperture ratio and light transmittance can be improved.

1 is a schematic cross-sectional view of a conventional transverse electric field type liquid crystal display device.
2 is a plan view schematically illustrating a liquid crystal display according to an exemplary embodiment of the present invention.
3 is a plan view showing a portion around the gate wiring of FIG. 2;
4 is a cross-sectional view taken along line IV-IV of FIG. 3.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 2 is a plan view schematically illustrating a liquid crystal display device according to an exemplary embodiment of the present invention, and FIG. 3 is a plan view illustrating a portion around the gate wiring of FIG. 2.

2 and 3, the liquid crystal display device 100 according to the embodiment of the present invention is an array substrate and a counter substrate facing the array substrate, for example, a color filter substrate and a liquid crystal filled between the array substrate and the color filter substrate. Includes layers.

In the array substrate, a plurality of gate wirings and data wirings 122 and 152 are formed on the inner surface of the first substrate to cross each other to define a plurality of pixel regions P. The plurality of pixel areas P are arranged in a matrix form within the display area.

The gate wiring 122 is a first direction and extends along, for example, a row direction, and the data wiring 152 is a second direction, and extends along, for example, a column direction.

In the embodiment of the present invention, a pixel arrangement structure of the Z inversion method is taken as an example. In this regard, each of the data lines 152 may be configured to be alternately connected to pixel regions P located on both sides. That is, one side of the data line 156 is connected to the pixel area P connected to the (2n-1)-th gate line 122 (that is, the pixel area P located on the (2n-1)-th row line). The other side of the data line 156 may be configured to be connected to the pixel area P connected to the 2n-th gate line 122 (ie, the pixel area P located on the 2n-th row line).

In such a connection structure, when dot inversion is implemented, each data line 152 receives data voltages of the same polarity during each frame. That is, the data driving circuit outputs a data voltage of the same polarity to the data line 156 during each frame. Accordingly, the voltage output fluctuation width of the data driving circuit, that is, the swing width is reduced, so that power consumption can be reduced.

Meanwhile, a pixel arrangement structure different from the pixel arrangement structure of the Z inversion driving method may be applied.

In the pixel region P, a thin film transistor T connected to the corresponding gate and data lines 122 and 152 is formed.

The thin film transistor T includes a gate electrode 124, a semiconductor layer 142, and source and drain electrodes 154 and 156.

The gate electrode 124 is connected to the gate wiring 122 and may be formed in the same process as the gate wiring 122. The gate electrode 124 may be configured to protrude from the gate wiring 122, for example, and may be configured to protrude in the direction of the pixel region P.

The semiconductor layer 142 is positioned on the gate electrode 124 with a gate insulating layer therebetween, and may be made of amorphous silicon, but is not limited thereto.

The source and drain electrodes 154 and 156 are positioned to be spaced apart from each other on the semiconductor layer 124. The source electrode 154 is connected to the data line 152, and the source and drain electrodes 154 and 156 may be formed in the same process as the data line 152.

The source electrode 154 may be formed to have a “U” shape, and in this case, the channel of the semiconductor layer 124 is also configured to have a “U” shape, but is not limited thereto.

In the foregoing description, the thin film transistor T having a bottom gate structure has been described as an example, but the present invention is not limited thereto. For example, a thin film transistor having a co-planar structure may be used.

In the pixel region P, a substantially plate-shaped pixel electrode 172 connected to the drain electrode 156 of the thin film transistor T is formed. At least one insulating layer may be formed between the drain electrode 156 and the pixel electrode 172. The pixel electrode 172 is configured to contact the pixel electrode 172 through the drain contact hole 161 exposing the drain electrode 156.

A common electrode 182 is formed on the pixel electrode 172 substantially over the entire display area. The common electrode 182 may be configured to have a plurality of bar-shaped electrode patterns 183 extending along the second direction corresponding to the pixel region P. In addition, an opening 184 may be formed between the plurality of electrode patterns 183.

As described above, an electric field is generated between the common electrode 182 and the pixel electrode 172 formed on the same substrate, and the liquid crystal layer can be driven by the electric field.

In the above description, a structure in which the plate-shaped pixel electrode 172 and the common electrode 182 having a plurality of electrode patterns 183 are disposed thereon has been described as an example, but is not limited thereto.

For example, a structure in which a plate-shaped common electrode 182 and a pixel electrode 172 having a plurality of bar-shaped electrode patterns are disposed thereon may be used.

As another example, a common electrode 182 having a plurality of electrode patterns and a pixel electrode 172 having a plurality of electrode patterns are positioned on the same layer or on different layers with an insulating film therebetween, and the electrode pattern of the common electrode 182 And the electrode patterns of the pixel electrodes 172 are alternately arranged in the pixel region P may be used.

Meanwhile, the common electrode 182, that is, the electrode pattern 183 of the common electrode 182 is inclined at a certain angle with respect to the gate wiring 122, and may be formed to have a shape in which the central portion of the pixel region P is bent. . For example, as shown, it may be configured to have a first bending portion in the center and second and third bending portions on both sides of the first bending portion.

In such a case, the data line 152 may also be formed to have the same shape as the common electrode 182, inclined to the gate line 122 at a predetermined angle and bent.

Meanwhile, a common wiring 126 connected to the common electrode 182 is formed on the array substrate. The common wiring 126 is spaced apart from the gate wiring 122 and is formed to extend along a first direction, which is an extension direction of the gate wiring 122.

The common wiring 126 is one side of the gate wiring 122 in the width direction and is located near one side of the gate wiring 122 on which the thin film transistor T is formed. That is, the common wiring 126 and the thin film transistor T are positioned together near one side of the gate wiring 122. Here, for convenience of explanation, one side of the gate wiring 122 where the common wiring and the thin film transistors 182 and T are located is referred to as a first side, and the other side of the gate wiring 122 opposite to this is referred to as a second side. do.

In particular, the common wiring 126 is spaced apart from the gate electrode 124 and is configured to overlap the drain electrode 156. More preferably, the common wiring 126 is configured to overlap the drain connection portion 157 that is a portion of the drain electrode 156 in contact with the pixel electrode 172.

As described above, in the embodiment of the present invention, the common wiring 126 is disposed together on the first side of the gate wiring 122 on which the thin film transistor T is formed, and is configured to overlap the drain electrode 156.

A black matrix 192 and a color filter are formed on the color filter substrate facing the array substrate configured as described above.

The black matrix 192 is formed in a lattice shape along the periphery of the pixel area P to cover non-display elements of the array substrate, and has an opening 193 through which light passes.

The color filter may be formed to cover the opening of the black matrix 192 and partially overlap the black matrix 192. The color filter may include, for example, red, green, and blue color filter patterns, such as red, green, and blue color filter patterns. May be positioned to correspond to each of the red, green, and blue pixel regions P.

Here, the black matrix 192 includes a first portion 192a extending in a first direction corresponding to the gate wiring 122 and a second portion 192b extending in a second direction corresponding to the data wiring 152 It can be composed of. That is, the first part 192a is located on opposite sides of the opening 193, and the second part 192b is located on the other opposite sides of the opening 193.

At this time, the first portion 192a covers not only the gate wiring 122 but also the thin film transistor T and the common wiring 126. The width wb of the first portion 192a is smaller than that of the black matrix (92 in FIG. 1) corresponding to the conventional gate wiring (22 in FIG. 1) (wbp in FIG. 1).

That is, referring again to FIG. 1, in the related art, since the thin film transistor T and the common wiring 26 are positioned on both sides of the gate wiring 22, that is, the first and second sides, the black matrix 92 is Since the thin film transistor T and the common wiring 26 must be expanded in both directions of the gate wiring 22 so as to cover both the thin film transistor T and the common wiring 26, it has a wide width.

On the other hand, according to the embodiment of the present invention, since the thin film transistor T and the common wiring 126 are located together on one side of the gate wiring 122, that is, near the first side, the corresponding black matrix 192, that is, The first part 192a may have a relatively narrow width wb as long as it expands in the direction of the first side of the gate wiring 122.

That is, according to the embodiment of the present invention, the upper portion of the gate wiring is substantially as wide as the outside of the common wiring (ie, the side farther from the gate wiring among both sides of the common wiring) Since it is possible to reduce the width of the black matrix, it is possible to reduce the width wb of the black matrix 192 to a superior degree compared to the prior art.

Accordingly, as a result, the area of the opening 193 of the black matrix 192 that emits light of the pixel region P can be increased, so that the aperture ratio and the light transmittance can be improved.

For example, in the case of a 14-inch (inch) Z inversion model, the conventional structure has an aperture ratio of about 55.6%, but according to the present embodiment, a high aperture ratio of about 67.1% can be achieved. And, compared with the prior art, the light transmittance has an effect of approximately 7.1% increase.

Hereinafter, a cross-sectional structure of a liquid crystal display device according to an embodiment of the present invention will be described with reference to FIG. 4. 4 is a cross-sectional view taken along line IV-IV of FIG. 3.

4, a gate wiring 122, a gate electrode 124, and a common wiring 126 are formed on the inner surface of the first substrate 111 on the array substrate.

Here, the common wiring 126 extends in a first direction, which is an extension direction of the gate wiring 122, and the gate electrode 124 is located on the first side of the gate wiring 122 where the drain electrode 156 is located. It will be located apart from and. The common wiring 126 may include a common connection part 127 in contact with the common electrode 182.

A gate insulating layer 130 is formed substantially along the entire surface of the first substrate 101 on the gate wiring 122, the gate electrode 124, and the common wiring 126. The gate insulating layer 130 is an inorganic insulating material, and may be formed of, for example, silicon oxide (SiO ₂ ) or silicon nitride (SiNx).

A semiconductor layer 142 is formed on the gate insulating layer 130 to correspond to the gate electrode 124. The semiconductor layer 142 may be made of amorphous silicon, but is not limited thereto.

Source electrodes and drain electrodes 154 and 156 spaced apart from each other are formed on the semiconductor layer 142. The source electrode 154 is connected to a data line (152 in FIG. 2) formed on the gate insulating layer 130. The source electrode 154 may be formed in a "U" shape, and accordingly, the channel of the semiconductor layer 142 may also have a "U" shape, but is not limited thereto.

The gate electrode 124, the semiconductor layer 142, and the source and drain electrodes 154 and 156 constitute a thin film transistor T.

The drain electrode 156 is configured to overlap the lower common wiring 126. For example, the drain connection part 157, which is a portion of the drain electrode 156 in contact with the pixel electrode 172, may be configured to overlap the common wiring 126.

As described above, by placing the common wiring 126 under the drain electrode 156, the common wiring and the drain electrode 156 can be effectively overlapped. That is, if the common wiring 126 is positioned above the drain electrode 156, the common wiring 126 should be designed to bypass the connection portion between the pixel electrode 172 and the drain electrode 156. In this case, It becomes difficult to overlap with the drain electrode 156. For this reason, it is preferable to form the common wiring 126 under the drain electrode 156.

The first and second protective layers 160 and 162, which are insulating layers, may be formed on the data line and the source and drain electrodes 154 and 156 substantially on the entire surface of the first substrate 101. A drain contact hole 161 exposing the drain connection part 157 is formed in the first and second passivation layers 160 and 162.

Here, the first passivation layer 160 may be formed of an inorganic insulating material such as silicon oxide (SiO ₂ ) or silicon nitride (SiNx). In addition, the second protective layer 162 on the first protective layer 160 may be formed of an organic insulating material such as photoacrylic or benzocyclobutene (BCB).

In the above description, the case where the two protective layers 160 and 162 are formed has been exemplified, but as another example, one protective layer may be formed.

A pixel electrode 172 is formed on the second passivation layer 162 to correspond to the pixel region P. The pixel electrode 172 comes into contact with the drain electrode 126 below, that is, the drain connection part 127 through the drain contact hole 161. The pixel electrode 172 may be formed in a plate shape in the pixel region P. The pixel electrode 162 may be formed of a transparent conductive material such as ITO or IZO.

A third passivation layer 180 is formed on the pixel electrode 172. The third passivation layer 180 may be formed of an inorganic insulating material or an organic insulating material. The third passivation layer 180 and the second and first passivation layers 162 and 160 below the third passivation layer 180 are formed with a common wiring 126, that is, a common contact hole 181 exposing the common connection portion 127.

A common electrode 182 is formed on the third passivation layer 180 substantially over the entire display area. The common electrode 182 comes into contact with the lower common wiring 126, that is, the common connection part 127 through the common contact hole 181.

The common electrode 182 may include a plurality of electrode patterns 183 extending in the second direction in the pixel region P when facing the lower pixel electrode 162. In addition, an opening 184 may be formed between the plurality of electrode patterns 183. The pixel electrode 162 may be formed of a transparent conductive material such as ITO or IZO.

Meanwhile, although not specifically shown, an alignment layer formed along the entire substrate may be formed on the common electrode 182.

Meanwhile, in the above description, a structure in which the plate-shaped pixel electrode 172 and the common electrode 182 having a plurality of electrode patterns 183 are disposed thereon has been described as an example, but the present invention is not limited thereto.

For example, a structure in which a plate-shaped common electrode 182 and a pixel electrode 172 having a plurality of electrode patterns are disposed thereon may be used.

As another example, a common electrode 182 having a plurality of electrode patterns and a pixel electrode 172 having a plurality of electrode patterns are positioned on the same layer or on different layers with an insulating film therebetween, and the electrode pattern of the common electrode 182 A structure in which electrode patterns of the and pixel electrodes are alternately arranged in the pixel region P may be used.

A black matrix 192 and a color filter 194 are formed on the inner surface of the second substrate 191 on the color filter substrate facing the array substrate configured as described above.

The black matrix 192 is a non-display element of the array substrate. The black matrix 192 covers the periphery of the pixel area P to cover the data line (152 in FIG. 2), the gate line 122, the common line 126, and the thin film transistor T. Accordingly, it is formed in a grid shape, and has an opening 193 through which light passes.

The black matrix 192 includes a first portion 192a extending in a first direction corresponding to the gate wiring 122 and a second portion extending in a second direction corresponding to the data wiring 152 (192b in FIG. 2 ). ) Can be included.

At this time, the first portion 192a of the upper portion of the gate wiring 122 includes not only the gate wiring 122 but also the thin film transistors and common wirings (T, 126) co-located in the vicinity of the first side of the gate wiring 122. It is configured to cover up.

Accordingly, the first portion 192a positioned on the gate wiring 122 may have a width wb that is significantly smaller than the width of the black matrix (wbp in FIG. 1) corresponding to the conventional gate wiring.

Accordingly, the area of the opening 193 of the black matrix 192 through which light is emitted from the pixel region P can be increased, and thus the aperture ratio and light transmittance can be improved.

The color filter 194 may be formed to cover the opening of the black matrix 192 and partially overlap the black matrix 192. The color filter 194 may include, for example, red, green, and blue color filter patterns, such as red, green, and blue The color filter pattern may be positioned to correspond to each of the red, green, and blue pixel regions P.

Meanwhile, although not specifically shown, a planarization layer may be formed on the color filter 194 substantially on the entire surface of the second substrate 191. In addition, on the planarization layer, an alignment layer for liquid crystal alignment may be formed on the entire substrate.

A liquid crystal layer 200 is filled between the array substrate and the color filter substrate as described above.

As described above, according to the embodiment of the present invention, the thin film transistor and the common wiring are positioned together near one side of the gate wiring.

Accordingly, the black matrix on the gate wiring can have a significantly narrower width compared to the prior art, since it only needs to be extended in one direction of the gate wiring. Accordingly, the aperture ratio and light transmittance can be improved.

The above-described embodiment of the present invention is an example of the present invention, and can be freely modified within the scope of the spirit of the present invention. Accordingly, the present invention includes modifications of the present invention within the scope of the appended claims and equivalents thereto.

100: liquid crystal display 111: first substrate
122: gate wiring 124: gate electrode
126: common wiring 127: common connection
130: gate insulating film 142: semiconductor layer
152: data wiring 154: source electrode
156: drain electrode 157: drain connection portion
160: first protective layer 161: drain contact hole
162: second protective layer 172: pixel electrode
180: third protective layer 181: common contact hole
182: common electrode 191: second substrate
192: black matrix 193: opening
194: color filter 195: planarization layer

Claims (7)

A gate wiring in a first direction and a data wiring in a second direction crossing each other on the first substrate to define a pixel region;
A gate electrode connected to the gate line, a semiconductor layer disposed on the gate electrode, a source electrode connected to the data line on the semiconductor layer, and a drain spaced apart from the source electrode and disposed on one side of the gate line A thin film transistor including an electrode;
A pixel electrode located in the pixel region and connected to the drain electrode;
A common wiring extending along an extension direction of the gate wiring, positioned on one side of the gate wiring, and overlapping the drain electrode;
A common electrode connected to the common wiring and facing the pixel electrode;
A black matrix including a first portion covering the gate wiring, the thin film transistor, and the common wiring on a second substrate
Including,
The common wiring includes a common connection part in contact with the common electrode,
A liquid crystal display device in which a width of the black matrix corresponding to the common connection portion along the second direction is narrower than a width of a black matrix corresponding to the thin film transistor.
The method of claim 1,
The common wiring overlaps a connection portion of the drain electrode connected to the pixel electrode.
Liquid crystal display.
The method of claim 1,
A gate insulating film positioned on the common wiring, the gate wiring, and the gate electrode, and below the source electrode and drain electrode
Liquid crystal display device comprising a.
The method of claim 1,
At least one of the common electrode and the pixel electrode has a plurality of bar-shaped electrode patterns.
Liquid crystal display.
The method of claim 1,
An insulating film positioned between the common electrode and the pixel electrode
Liquid crystal display device comprising a.
The method of claim 1,
The black matrix includes a second portion covering the data wiring.
Liquid crystal display. The method of claim 1,
The common connection portion is a liquid crystal display device protruding toward the gate wiring from one side of the common wiring.

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