CN102938244B - Display panel and active component array substrate thereof - Google Patents
Display panel and active component array substrate thereof Download PDFInfo
- Publication number
- CN102938244B CN102938244B CN201210441748.6A CN201210441748A CN102938244B CN 102938244 B CN102938244 B CN 102938244B CN 201210441748 A CN201210441748 A CN 201210441748A CN 102938244 B CN102938244 B CN 102938244B
- Authority
- CN
- China
- Prior art keywords
- pel array
- pixel
- active component
- data line
- base board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Landscapes
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
- Liquid Crystal (AREA)
Abstract
The invention discloses a display panel and an active component array substrate thereof. The active component array substrate comprises a plurality pixel units, a plurality of scanning lines and a plurality of data lines. The pixel units are distributed into an X*Y pixel array, wherein X and Y are both positive integers, and X>Y>1. The scanning lines are connected with the pixel units in coupling mode. The data lines accord with a linear arrangement mode and connected with the pixel units in coupling mode in the pixel array. The arrangement mode accords with the mode that the ith data line is connected with the (i-j+1)th pixel unit in the jth line in coupling mode, wherein i=1-X, i>=j, when i<=Y, j=1-i, otherwise, when i>Y, j=1-Y, and i and j are both positive integers.
Description
Technical field
The present invention is relevant for a kind of display panel and active component array base board thereof, and particularly relevant for a kind of active component array base board and display panel with narrow edge.
Background technology
Generally speaking, display panel is consisted of active component array base board, subtend substrate and display medium.When making active cell array, conventionally can make the perimeter circuit matching with crystal grain-glass bond processing procedure or crystal grain-film connection process in the non-display area (neighboring area) of active component array base board simultaneously.
Fig. 1 be known a kind of active component array base board on look schematic diagram.Please refer to Fig. 1, active component array base board 10 comprises substrate 11, multi-strip scanning line 12, many data lines 13, a plurality of pixel cell 14, grid drive chip 15 and source driving chips 16.Substrate 11 has viewing area A and around the non-display area B of viewing area A.Sweep trace 12 is all towards the trend of left-to-right and be disposed in parallel to each other on substrate 11.Data line 13 all upward under trend and be disposed in parallel to each other on substrate 11, and staggered perpendicular to each other with these data lines 13, to form a plurality of pixel cells 14 that are positioned at viewing area A.
Substrate 11 has each other adjacent 11aYu second side, first side 11b.Grid drive chip 15 is arranged in the non-display area B of the first side 11a of substrate 11, and is electrically connected with these sweep traces 12.Source driving chip 16 is arranged in the non-display area B of the second side 11b of substrate 11, and is electrically connected with these data lines 13.Especially, the non-display area B of the sweep trace 12 A left and right sides, transmission display district carries out the cabling layout (wire routing) of perimeter circuit, to be electrically connected grid drive chip 15.The non-display area B of the data line 13 upper and lower both sides of A, transmission display district carries out the cabling layout (wirerouting) of perimeter circuit, to be electrically connected source driving chip 16.
Yet, because many application of display panel are gradually towards light, thin, short, little trend, as: the electronic products such as mobile phone, digital camera, add that grid drive chip and source driving chip respectively occupy most of space of the non-display area of substrate dual side-edge, cause this active component array base board to produce a problem that is difficult for realizing narrow frame.
Therefore, how to provide a solution to solve active component array base board, to be difficult for realizing the problem of narrow frame, to improve the portability of electronic product, real is a current problem urgently to be resolved hurrily.
Summary of the invention
The invention provides a kind of active component array base board, it has narrow edge, can improve space availability ratio.
The present invention proposes a kind of active component array base board, and this active component array base board comprises a plurality of pixel cells, multi-strip scanning line and many data lines.These pixel cells are arranged in the pel array of an X * Y, and X and Y are positive integer, X>Y>1.These sweep traces couple these pixel cells.These data lines meet an arrangement mode, and in pel array, couple these pixel cells.Described arrangement mode meets i-j+1 the pixel cell that i bar data line couples j row, i=1～X, and i≤j, wherein when i≤Y, j=1～i, anti-, when i>Y, j=1～Y, i and j are positive integer.
In addition, in one embodiment of this invention, the m bar data line in these data lines also couples n and is listed as X+Y-n-m+1 pixel cell, m=1～(X-Y) wherein, and n=(Y-m+1)～Y, m and n are positive integer.
The present invention proposes again a kind of active component array base board, and this active component array base board comprises a substrate, a pel array, multi-strip scanning line and many data lines.Pel array be by a plurality of pixel cell line up on substrate, comprise the first relative side and the second side and relative the 3rd side and the 4th side, the first side and the second side are all between the 3rd side and the 4th side.Parallel and the compartment of terrain of sweep trace is disposed in pel array.Data line is disposed in pel array, all passes through the first side of pel array with these sweep traces.Each data line alternately extends towards the second side of pel array and the direction of the 4th side in pel array so that in pel array, form one with interconnected stepped of these sweep traces.
In one embodiment of this invention, described pel array comprises a plurality of configured in parallel pixel column and pixel column.These pixel cells of each pixel column and these pixel cells of each pixel column are all linearity and each interval is arranged.Parallel these pixel columns of these sweep traces, and each sweep trace couples wherein all pixel cells in a pixel column.
In one embodiment of this invention, each data line couples at least one pixel cell in different pixels row.
In one embodiment of this invention, all pixel cells that each data line couples are not all arranged in the same pixel column of pel array, are not also arranged in the same pixel column of pel array.
In one embodiment of this invention, each data line comprises a plurality of first paragraphs and a plurality of second segment.Parallel these sweep traces of these first paragraphs.Vertical these sweep traces of these second segments, each second segment is connected between wantonly two adjacent first paragraphs, and lays respectively in different pixel columns.
In one embodiment of this invention, pel array is arranged according to one X * Y array way, and wherein X, Y are positive integer, X>Y>1.
The quantity of these sweep traces and the quantity of data line are consistent in one embodiment of this invention, are all X.
In one embodiment of this invention, when each sweep trace starts wherein in a pixel column all pixel cells, only having quantity is that the data line of Y provides respectively pixel cell data to all pixel cells in corresponding pixel column.
In one embodiment of this invention, total quantity be that (X-Y) individual data line passes through the 4th side of pel array, and the second side to pel array from pel array extension respectively.
In one embodiment of this invention, these quantity are that (X-Y) individual data line is by the second side of pel array, and alternately towards the direction of the first side and the 3rd side, extend, so that in pel array, form interconnected stepped of another and these sweep trace in pel array.
In one embodiment of this invention, active component array base board also comprises at least one source driving chip and at least one grid drive chip.Source driving chip is positioned at a side of substrate.The homonymy of the common position of grid drive chip and source driving chip substrate.
The present invention proposes again a kind of active component array base board.This active component array base board comprises a plurality of pixel cells, multi-strip scanning line and many data lines.Pixel cell is arranged in a pel array.Each scanning linear all couples these pixel cells of same a line.These data lines are stepped and oblique these pixel cells that couples all.All pixel cells that each data line couples are not all arranged in same a line of pel array, and all pixel cells of coupling of each data line are not also arranged in the same row of pel array.
In one embodiment of this invention, pel array is arranged according to the array way of one X * Y, X>Y>1 wherein, and X, Y are positive integer.
In one embodiment of this invention, total quantity is stretched out from a side of pel array for (X-Y) individual data line, extends to respectively the opposite side of pel array, and wherein this two side is adjacent each other.
The present invention provides again a kind of display panel, and it has above-mentioned active component array base board, can reduce manufacturing cost, increase product portability.
This kind of display panel comprises above-mentioned active component array base board, subtend substrate and display medium.Display medium is disposed between subtend substrate and active component array base board.
In sum, because active component array base board of the present invention has unique line design, so the present invention can reduce edge width, and then improves space availability ratio.In addition, because display panel of the present invention has above-mentioned active component array base board, so the present invention can reduce manufacturing cost and increase product portability.
Accompanying drawing explanation
For above and other object of the present invention, feature, advantage and embodiment can be become apparent, being described in detail as follows of appended accompanying drawing:
Fig. 1 be known a kind of active component array base board on look schematic diagram;
Fig. 2 be active component array base board of the present invention on look schematic diagram;
Fig. 3 be one embodiment of the invention pel array on look schematic diagram;
Fig. 4 a ~ Fig. 4 d is that schematic diagram is moved towards in the bottom right in 9x5 pel array for certain data line;
Fig. 5 a ~ Fig. 5 d is that schematic diagram is moved towards in the upper left in 9x5 pel array for certain data line;
Fig. 6 be another embodiment of the present invention pel array on look schematic diagram;
Fig. 7 a～Fig. 7 b is the schematic diagram of single scanning line five data lines corresponding to it in 9x5 pel array;
Fig. 8 is the schematic diagram of the display panel of one embodiment of the invention.
[main element symbol description]
100: display panel
200: subtend substrate
300: display medium
400: active component array base board
410: substrate
420: source driving chip
430: grid drive chip
440: pel array
441: the first sides
442: the second sides
443: the three sides
444: the four sides
450,450a ~ 450x: pixel cell
451: pixel column
452: pixel column
500,501 ~ 502: sweep trace
600,600a ~ 600f, 600A ~ 600J, 601～606: data line
610: first paragraph
620: second segment
A: viewing area
B: non-display area
Embodiment
Below will clearly demonstrate spirit of the present invention with accompanying drawing and detailed description, if person skilled in the art is after understanding embodiments of the invention, when can be by the technology of teachings of the present invention, change and modification, it does not depart from spirit of the present invention and scope.
Active component array base board of the present invention comprises a pel array being arranged in by a plurality of pixel cells, multi-strip scanning line and many data lines.Scanning linear couples the pixel cell of same a line.Data line roughly all obliquely couples all pixel cells in arranged in step shape mode.So, due to the stepped configuration design on active component array base board of the present invention, make the circuit on active component array base board reduce the space that takies active component array base board edge region, help and reduce active component array base board side width, or improve the space availability ratio of using active component array base board side.
Fig. 2 be active component array base board of the present invention on look schematic diagram.Please refer to Fig. 2, a kind of active component array base board 400 comprises a substrate 410, one or more source driving chip 420, one or more grid drive chip 430, a pel array 440, multi-strip scanning line 500(scan line) and many data line 600(source line or data line).Substrate 410 comprise a viewing area A and with the non-display area B of viewing area A adjacency.Pel array 440 is disposed on substrate 410, and the region of pel array 440 is defined as above-mentioned viewing area A, and non-display area B is the edge region after substrate 410 deduction viewing area A.
Pel array 440 is by a plurality of pixel cell 450(or claims sub-pixel unit, sub pixels) institute lines up, and these pixel cells 450 are for example red pixel unit, blue pixel unit and green pixel unit.Pel array 440 comprises the first relative side 441 and the second side 442 and relative the 3rd side 443 and the 4th side 444, the first sides 441 and the second side 442 all between the 3rd side 443 and the 4th side 444.
Source driving chip 420 is positioned at the edge region of substrate 410 1 sides.In the edge region of grid drive chip 430 and 420 common substrates of source driving chip, 410 homonymies.So, more help active component array base board 400 of the present invention and realize narrow edge characteristic, and then improve space availability ratio.In addition, source driving chip 420 also can be integrated into single individuality with grid drive chip 430, yet the present invention is not limited only to above-mentioned variation.
The quantity of sweep trace 500 is less than or equal to the quantity of data line 600, and sweep trace 500 is parallel to each other and compartment of terrain is disposed in pel array 440.Specifically, sweep trace 500 connects grid drive chip 430, and by the first side 441 and second side 442 of pel array 440, this means, sweep trace 500 extends to substrate 410 another edge regions (being non-display area B) from the edge region (being non-display area B) of substrate 410 1 sides through pel array 440.
Data line 600 compartment of terrains are disposed in pel array 440, are all with rough stepped trend towards the direction of bottom right in figure and obliquely couple most of pixel cell 450.Specifically, data line 600 is by the first side 441 of pel array 440, and enter after pel array 440, in pel array 440, alternately towards the direction of the second side 442 of pel array 440 and towards the direction of the 4th side 444 of pel array 440, extend, make data line 600 in the interior formation of pel array 440 and interconnected the first stepped route (as the trend of the data line 600c of Fig. 4 c) of sweep trace 500.
More specifically, described pel array 440 comprises a plurality of configured in parallel pixel column 451 and pixel column 452.Pixel column 452 as shown in Figure 2, is towards upper and lower trend in figure and be parallel to each other.Pixel column 451 as shown in Figure 3, is towards the trend of figure middle left and right and be parallel to each other.The trend of pixel column 451 and pixel column 452 move towards phase quadrature.Pixel cell 450 in each pixel column 452 and the pixel cell 450 in each pixel column 451 are all linearity and each interval is arranged.Sweep trace 500 parallel pixels are capable 452, and each sweep trace 500 couples pixel cells 450 all in each pixel column 452.
In addition, all pixel cells 450 that each data line 600 couples are not all arranged in the same pixel column 452 of pel array 440, are not also arranged in the same pixel column 451 of pel array 440.More specifically, each data line 600 comprises a plurality of first paragraphs 610 and a plurality of second segment 620.Each second segment 620 is directly connected between wantonly two adjacent first paragraphs 610, and lays respectively in different pixel column 452, and in different pixel column 452, couples at least one pixel cell 450.First paragraph 610 extends towards upper and lower moving towards in figure, does not limit with sweep trace 500 and is parallel to each other or is not parallel to each other.The moving towards of second segment 620 figure middle left and rights extended, do not limit mutually vertical or mutually not vertical with sweep trace 500,
Yet, the invention is not restricted to this, each data line also can couple two above pixel cells in different pixels row, and/or two above pixel cells in different pixels row.
In addition, as shown in Figure 2, the data line 600 of partial amt just extends to respectively the second side 442 of pel array 440 after the 4th side 444 is stretched out pel array 440, and from the second side 442 of pel array 440, stretch into after pel array 440 respectively, be convenient to alternately towards the direction of the first side 441 and the direction of the 3rd side 443, extend in pel array 440, so that the interconnected second-order scalariform route (as the trend of the data line 600f of Fig. 5 d) of the interior formation of pel array 440 and sweep trace 500.So, the rest of pixels unit 450 that is not positioned at the first stepped route also can couple with data line 600 mutually by second-order scalariform route, therefore do not need to configure in addition the data line of greater number, and then help the realization of the narrow edge feature that reduces manufacturing cost and active component array base board.
Fig. 3 be one embodiment of the invention pel array on look schematic diagram.Consult Fig. 3, further with mathematical way, describe the first stepped route of above-mentioned data line 600 and the relation that couples of pixel cell 450.
Above-mentioned pel array 440 is one X * Y array, and wherein X and Y are positive integer, X>Y>1.Therefore pixel cell 450 is 1～X in each pixel column 451, its quantity is X, also consistent with the quantity of data line 600 with sweep trace 500 respectively.In each pixel column 452, the quantity of pixel cell 450 is 1～Y, and its quantity is Y.
Data line 600 meets first order mode and couples described most of pixel cell 450, to form the first above-mentioned stepped route.Described first order mode is to meet i-j+1 the pixel cell 450 that i bar data line 600 couples j row, i=1～X, and i≤j, wherein when i≤Y, j=1～i, anti-, when i>Y, j=1～Y, i and j are positive integer.
For instance, Fig. 4 a ~ Fig. 4 d is that schematic diagram is moved towards in the bottom right in 9x5 pel array 440 for certain data line.
As shown in Fig. 4 a, work as X=9, Y=5 is example, and when i bar data line 600 is the orders on limit from right to left, and when the j of pel array 440 row are order from top to bottom, below provide several routine decryption lines according to above-mentioned first order mode moving towards in 9x5 pel array 440 change and with the relation that couples (representing by site square the pixel cell being coupled below) of pixel cell:
As shown in Fig. 4 a, work as i=1, meet i≤5, j=1～1, therefore the 1st data line 600a couples (1-1+1=1) individual pixel cell 450a (as shown in the square of site) that pel array 440 the 1st is listed as;
As shown in Figure 4 b, work as i=3, meet i≤5, j=1～3, (3-1+1=3) individual pixel cell 450b (as shown in the square of site) that therefore the 3rd data line 600b couples pel array 440 the 1st row is, (3-3+1=1) individual pixel cell 450d (as shown in the square of site) of (3-2+1=2) individual pixel cell 450c (as shown in the square of site) of the 2nd row and the 3rd row;
As shown in Fig. 4 c, work as i=7, meet i>5, j=1～5, therefore the 7th data line 600c couple pel array 440 the 1st row (7-1+1=7) individual pixel cell 450e (as shown in the square of site), (7-3+1=5) individual pixel cell 450g (as shown in the square of site) of (7-2+1=6) individual pixel cell 450f (as shown in the square of site) of the 2nd row, the 3rd row, (7-5+1=3) individual pixel cell 450i (as shown in the square of site) of (7-4+1=4) individual pixel cell 450h (as shown in the square of site) of the 4th row and the 5th row.
As shown in Fig. 4 d, work as i=9, while meeting i>5, j=1～5, therefore the 9th data line 600d couple pel array 440 the 1st row (9-1+1=9) individual pixel cell 450j (as shown in the square of site), (9-3+1=7) individual pixel cell 450l (as shown in the square of site) of (9-2+1=8) individual pixel cell 450k (as shown in the square of site) of the 2nd row, the 3rd row, (9-5+1=5) individual pixel cell 450n (as shown in the square of site) of (9-4+1=6) individual pixel cell 450m (as shown in the square of site) of the 4th row and the 5th row.
In addition, consult again Fig. 3, below also with mathematical way, describe above-mentioned data line 600 in the quantity of second-order scalariform route, and above-mentioned data line 600 in second-order scalariform route with the relation that couples of pixel cell 450.
In this embodiment, the 4th side 444 that total quantity is stretched out pel array 440 for (X-Y) individual data line 600 in pel array 440, and the second side 442 from pel array 440 extensions to pel array 440 respectively.These quantity are that (X-Y) individual data line 600 is by the second side 442 of pel array 440, and in pel array 440, alternately the direction towards the first side 441 and the 3rd side 443 is extended, so that the interconnected above-mentioned second-order scalariform route of the interior formation of pel array 440 and sweep trace 500.
Above-mentioned data line 600 stretches into after pel array 440 from the second side 442 of pel array 440, and these data lines 600 meet second order mode and couple the pixel cell 450 of remainder, to form above-mentioned second-order scalariform route.Described second order mode is to meet m bar data line 600 in data line 600 also to couple n and be listed as X+Y-n-m+1 pixel cell 450, m=1～(X-Y) wherein, and n=(Y-m+1)～Y, m and n are positive integer.
Lift same example, Fig. 5 a ~ Fig. 5 d is for to move towards schematic diagram for certain data line 600 upper left in 9x5 pel array 440.
In the same example, as Fig. 5 a, work as X=9, Y=5, and when m bar data line 600 is the orders on limit from right to left, and when the n of pel array 440 row are order from top to bottom, m=1～(9-5=4), below provide several routine decryption lines according to above-mentioned second order mode moving towards in 9x5 pel array change and with the relation that couples (representing by site square the pixel cell being coupled below) of pixel cell:
As shown in Figure 5 a, work as m=1, n=(5-1+1=5)～5, the 1st data line 600a also couples pel array 440 the 5th and is listed as (9+5-5-1+1=9) individual pixel cell 450o (as shown in the square of site);
As shown in Figure 5 b, work as m=2, n=(5-2+1=4)～5, the 2nd data line 600e also couples pel array 440 the 5th and is listed as (9+5-5-2+1=8) individual pixel cell 450p (as shown in the square of site) and the 4th and is listed as (9+5-4-2+1=9) individual pixel cell 450q (as shown in the square of site);
As shown in Figure 5 c, work as m=3, n=(5-3+1=3)～5, the 3rd data line 600b also couples pel array 440 the 5th and is listed as (9+5-3-2+1=7) individual pixel cell 450r (as shown in the square of site), the 4th and is listed as (9+5-4-3+1=8) individual pixel cell 450s (as shown in the square of site) and the 3rd and is listed as (9+5-3-3+1=9) individual pixel cell 450t (as shown in the square of site);
As shown in Fig. 5 d, work as m=4, n=(5-4+1=2)～5, the 4th data line 600f also couples pel array 440 the 5th and is listed as (9+5-5-4+1=6) individual pixel cell 450u (as shown in the square of site), the 4th and is listed as (9+5-4-4+1=7) individual pixel cell 450v (as shown in the square of site), the 3rd and is listed as (9+5-3-4+1=8) individual pixel cell 450w (as shown in the square of site) and the 2nd and is listed as (9+5-2-4+1=9) individual pixel cell 450x (as shown in the square of site).
Fig. 6 be another embodiment of the present invention pel array 440 on look schematic diagram.Refer to Fig. 6, in Fig. 6, the first order to the 9th pixel column 452 changes the order on limit from left to right into.Although being the directions towards lower-left in figure, the first stepped trend of the data line 600 in Fig. 6 obliquely couples most of pixel cell 450, the second-order scalariform trend of data line 600 is that the direction towards upper right in figure obliquely couples rest of pixels unit 450, but, data line 600 in Fig. 6 is also applicable to the rule of above-mentioned first order mode towards the trend of lower-left, and data line 600 is towards the also rule of applicable above-mentioned second order mode of the trend of upper right.
Fig. 7 a ~ Fig. 7 b is the operation chart of one scan line five data lines corresponding to it wherein in 9x5 pel array, wherein by site square, represents the pixel cell being activated.
During operation, as shown in Figure 7a, when driving above-mentioned active component array base board 400, first sequentially sweep trace is inputted to a pixel cell cut-in voltage, then, when sequentially to sweep trace input pixel cell cut-in voltage, sequentially to the staggered data line input pixel cell data of these scanning linears.
For example, as shown in Figure 7a, from right to left in the order on limit, when to the 1st scanning linear 501 input pixel cell cut-in voltages during to all pixel cell 450A ~ E of pel array 440 the 1st row, 1st～5 data lines 601 ~ 605 are respectively to pel array 440 the 1st row 1st～5 pixel cell 450A of order ~ E input from top to bottom pixel cell data., article 1, in 601 pairs of pel arrays 440 of data line the 1st row, from top to bottom the 1st the pixel cell 450A (as shown in the square of site) of order inputs pixel cell data, article 2, in 602 pairs of pel arrays 440 of data line the 1st row, from top to bottom the 2nd the pixel cell 450B (as shown in the square of site) of order inputs pixel cell data, article 3, in 603 pairs of pel arrays 440 of data line the 1st row, from top to bottom the 3rd the pixel cell 450C (as shown in the square of site) of order inputs pixel cell data, article 4, in 604 pairs of pel arrays 440 of data line the 1st row, from top to bottom the 4th the pixel cell 450D (as shown in the square of site) of order inputs pixel cell data, and the pixel cell of the 5th the pixel cell 450E (as shown in the square of site) of order input from top to bottom data in 605 pairs of pel arrays 440 of the 5th data line the 1st row.
Consult as shown in Figure 7b, when the 2nd scanning linear 502 inputted all pixel cell 450F ~ J of pixel cell cut-in voltage to the 2 row pixel columns, 2nd～6 data lines 602 ~ 606 are respectively to pel array 440 the 2nd row 1st～5 pixel cell 450F of order ~ J input from top to bottom pixel cell data., article 2, in 602 pairs of pel arrays 440 of data line the 2nd row, from top to bottom the 1st the pixel cell 450F (as shown in the square of site) of order inputs pixel cell data, article 3, in 603 pairs of pel arrays 440 of data line the 2nd row, from top to bottom the 2nd the pixel cell 450G (as shown in the square of site) of order inputs pixel cell data, article 4, in 604 pairs of pel arrays 440 of data line the 2nd row, from top to bottom the 3rd the pixel cell 450H (as shown in the square of site) of order inputs pixel cell data, article 5, in 605 pairs of pel arrays 440 of data line the 2nd row, from top to bottom the 4th the pixel cell 450I (as shown in the square of site) of order inputs pixel cell data, and the pixel cell of the 5th the pixel cell 450J (as shown in the square of site) of order input from top to bottom data in 606 pairs of pel arrays 440 of the 6th data line the 2nd row.
Therefore, it is known that the rest may be inferred, take above-mentioned pel array 440 as X * Y array, for example, in X bar (9) the corresponding pixel column of each self-starting of sweep trace during all pixel cells, only having quantity is that Y bar (for example 5) data line provides respectively all pixel cells of pixel cell data to corresponding pixel column, does not need to use all data lines.
Fig. 8 is the schematic diagram of the display panel 100 of one embodiment of the invention.Please refer to Fig. 8, above-mentioned active component array base board 400 more can be applicable in a display panel 100.Display panel 100 comprises subtend substrate 200, display medium 300 and above-mentioned active component array base board 400.Subtend substrate 200 is disposed at active component array base board 400 tops.Display medium 300 is disposed between subtend substrate 200 and active component array base board 400.Display panel 100 is for example display panels, electrophoresis type display panel or other display panels.Subtend substrate 200 is for example colored optical filtering substrates, and display medium 300 is for example liquid crystal layer or other material.In the present embodiment, display panel 100 is for example the display panel of a kind of horizontal demonstration (Landscape viewing), yet the present invention is not limited only to this.
In sum, because active component array base board of the present invention has unique line design, so the present invention can reduce edge width, and then improves space availability ratio.In addition, because display panel of the present invention has above-mentioned active component array base board, so the present invention can reduce manufacturing cost and increase product portability.
The present invention discloses in each embodiment as above; not in order to limit the present invention, be anyly familiar with this skill person, without departing from the spirit and scope of the present invention; when being used for a variety of modifications and variations, so the scope that protection scope of the present invention ought define depending on appending claims is as the criterion.
Claims (12)
1. an active component array base board, is characterized in that, comprising:
One substrate;
One pel array, on this substrate, comprises the first relative side and the second side and relative the 3rd side and the 4th side by a plurality of pixel cell line up, and this first side and this second side are all between the 3rd side and the 4th side;
Multi-strip scanning line, parallel and compartment of terrain is disposed in this pel array; And
Many data lines, be disposed in this pel array, all pass through this first side of this pel array with described multi-strip scanning line, described in each, data line alternately extends towards this second side of this pel array and the direction of the 4th side in this pel array so that in this pel array, form one with interconnected stepped of described multi-strip scanning line;
The pixel column that this pel array comprises a plurality of configured in parallel and pixel column, described in each described a plurality of pixel cells of pixel column and described in each described a plurality of pixel cells of pixel column be all linearity and each interval and arrange, a plurality of pixel columns described in described multi-strip scanning line parallel, and described in each, sweep trace couples described a plurality of pixel column all pixel cells in one of them.
2. active component array base board according to claim 1, is characterized in that, described in each, data line couples at least one pixel cell in different pixels row.
3. active component array base board according to claim 2, is characterized in that, all pixel cells that described in each, data line couples are not all arranged in the same pixel column of this pel array, is not also arranged in the same pixel column of this pel array.
4. active component array base board according to claim 1, is characterized in that, described in each, data line comprises:
A plurality of first paragraphs, parallel described multi-strip scanning line; And
A plurality of second segments, vertical described multi-strip scanning line, described in each, second segment is connected between wantonly two adjacent described first paragraphs, and lays respectively in different pixel columns.
5. active component array base board according to claim 1, is characterized in that, this pel array is arranged according to one X * Y array way, and X, Y are positive integer, X > Y > 1.
6. active component array base board according to claim 5, is characterized in that, the quantity of described multi-strip scanning line is consistent with the quantity of data line, is all X.
7. active component array base board according to claim 5, it is characterized in that, when sweep trace described in each starts described a plurality of pixel columns in one of them during all pixel cells, only having quantity is that the described data line of Y provides respectively all pixel cells of pixel cell data to corresponding described a plurality of pixel columns.
8. active component array base board according to claim 5, is characterized in that, total quantity be that (X-Y) individual data line passes through the 4th side of this pel array, and this second side to this pel array from this pel array extension respectively.
9. active component array base board according to claim 8, it is characterized in that, described quantity is that (X-Y) individual data line is by this second side of this pel array, and alternately towards the direction of this first side and the 3rd side, extend, so that in this pel array, form interconnected stepped of another and described multi-strip scanning line in this pel array.
10. active component array base board according to claim 1, is characterized in that, also comprises:
At least one source driving chip, is positioned at a side of this substrate; And
At least one grid drive chip, is co-located at the homonymy of this substrate with this source driving chip.
11. 1 kinds of active component array base boards, is characterized in that, comprise:
A plurality of pixel cells, are arranged in a pel array;
Multi-strip scanning line, described in each, scanning linear all couples described a plurality of pixel cells of same a line; And
Many data lines, described many data lines are all stepped and oblique couples described a plurality of pixel cell, the all described pixel cell that described in each, data line couples is not all arranged in same a line of this pel array, and all described pixel cell that described in each, data line couples is not also arranged in the same row of this pel array;
This pel array is arranged according to the array way of one X * Y, X > Y > 1, and X, Y are positive integer;
Total quantity is stretched out from a side of this pel array for (X-Y) individual described data line, extends to respectively the opposite side of this pel array, and wherein this side is adjacent with this opposite side.
12. 1 kinds of display panels, is characterized in that, comprise:
Active component array base board just like claim 1～11 described in one of them;
One subtend substrate, is disposed at this active component array base board top; And
One display medium, is disposed between this subtend substrate and this active component array base board.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210441748.6A CN102938244B (en) | 2012-11-08 | 2012-11-08 | Display panel and active component array substrate thereof |
| TW101148664A TWI487990B (en) | 2012-11-08 | 2012-12-20 | Active device array substrate and display panel thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210441748.6A CN102938244B (en) | 2012-11-08 | 2012-11-08 | Display panel and active component array substrate thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102938244A CN102938244A (en) | 2013-02-20 |
| CN102938244B true CN102938244B (en) | 2014-11-26 |
Family
ID=47697135
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210441748.6A Expired - Fee Related CN102938244B (en) | 2012-11-08 | 2012-11-08 | Display panel and active component array substrate thereof |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN102938244B (en) |
| TW (1) | TWI487990B (en) |
Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106782373A (en) * | 2016-12-26 | 2017-05-31 | 惠科股份有限公司 | Display device and display panel thereof |
| CN106991952B (en) * | 2017-05-02 | 2020-10-16 | 厦门天马微电子有限公司 | Display panel and display device |
| CN108280317B (en) * | 2018-04-27 | 2024-02-13 | 深圳市爱协生科技股份有限公司 | Display driving integrated circuit structure and manufacturing method thereof |
| WO2019241993A1 (en) * | 2018-06-22 | 2019-12-26 | 惠科股份有限公司 | Display device and display panel thereof |
| CN109166460B (en) * | 2018-09-30 | 2020-09-25 | 武汉天马微电子有限公司 | Display panel and display device |
| CN109461384B (en) * | 2018-12-18 | 2021-03-16 | 武汉华星光电半导体显示技术有限公司 | Manufacturing method of display panel or array assembly for preventing static electricity and display panel |
| TWI690914B (en) * | 2019-05-17 | 2020-04-11 | 友達光電股份有限公司 | Pixel array substrate |
| TWI753778B (en) * | 2020-03-17 | 2022-01-21 | 友達光電股份有限公司 | Display device |
| TWI729735B (en) * | 2020-03-17 | 2021-06-01 | 友達光電股份有限公司 | Display device |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1659614A (en) * | 2002-06-11 | 2005-08-24 | 皇家飞利浦电子股份有限公司 | Non rectangular display device |
| CN101110189A (en) * | 2006-07-20 | 2008-01-23 | 精工爱普生株式会社 | Display device, method of driving display device, and electronic apparatus |
| CN102116953A (en) * | 2010-12-30 | 2011-07-06 | 友达光电股份有限公司 | Liquid crystal display and liquid crystal display panel thereof |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63260375A (en) * | 1987-04-17 | 1988-10-27 | Mitsubishi Electric Corp | Geometrical distortion correcting method for matrix type television receiver |
-
2012
- 2012-11-08 CN CN201210441748.6A patent/CN102938244B/en not_active Expired - Fee Related
- 2012-12-20 TW TW101148664A patent/TWI487990B/en not_active IP Right Cessation
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1659614A (en) * | 2002-06-11 | 2005-08-24 | 皇家飞利浦电子股份有限公司 | Non rectangular display device |
| CN101110189A (en) * | 2006-07-20 | 2008-01-23 | 精工爱普生株式会社 | Display device, method of driving display device, and electronic apparatus |
| CN102116953A (en) * | 2010-12-30 | 2011-07-06 | 友达光电股份有限公司 | Liquid crystal display and liquid crystal display panel thereof |
Non-Patent Citations (1)
| Title |
|---|
| JP昭63-260375A 1988.10.27 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102938244A (en) | 2013-02-20 |
| TW201418854A (en) | 2014-05-16 |
| TWI487990B (en) | 2015-06-11 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102938244B (en) | Display panel and active component array substrate thereof | |
| CN107561806B (en) | Array substrate and display panel | |
| CN110310576B (en) | Display panel and display device | |
| US10783821B2 (en) | Display panel, and method for driving the display panel | |
| CN105161059B (en) | Display drive method, display panel and preparation method thereof, display device | |
| CN102540525B (en) | Liquid crystal display device | |
| CN107886924B (en) | Display panel, display device and driving method | |
| CN103366666B (en) | Display driving framework and signal transmission method thereof, display device and manufacturing method thereof | |
| CN101673015B (en) | Active-element array substrate and display panel | |
| US20110109579A1 (en) | Touch-Sensitive Display Panel | |
| CN110379390B (en) | Display panel, driving method thereof and display device | |
| CN107992229A (en) | Touch-control display panel and touch control display apparatus | |
| CN102508372B (en) | Display panel | |
| CN104409037B (en) | Display panel and display device | |
| CN108091310B (en) | Display panel, display device and driving method | |
| CN109765737B (en) | Array substrate and display device | |
| CN108831365B (en) | Display panel and display device | |
| US10403648B2 (en) | Array substrates with adjacent sub-pixels having opposite polarities | |
| CN102959608A (en) | Active matrix substrate, display device, and method for testing the active matrix substrate or the display device | |
| CN105469764A (en) | Array substrate, liquid crystal display panel and electronic equipment | |
| CN107608560A (en) | Touch display panel and display device | |
| CN111429859A (en) | Gate drive circuit and display device | |
| CN103529614A (en) | Array base plate, display device and driving method thereof | |
| CN100399176C (en) | LCD device | |
| CN108109599A (en) | Display panel, display device and driving method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20141126 Termination date: 20201108 |