CN102938244B - Display panel and active component array substrate thereof - Google Patents

Display panel and active component array substrate thereof Download PDF

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CN102938244B
CN102938244B CN201210441748.6A CN201210441748A CN102938244B CN 102938244 B CN102938244 B CN 102938244B CN 201210441748 A CN201210441748 A CN 201210441748A CN 102938244 B CN102938244 B CN 102938244B
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pixel
array
pel array
active component
data line
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CN102938244A (en
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张宝华
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AU Optronics Suzhou Corp Ltd
AUO Corp
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Abstract

本发明揭露一种显示面板及其主动元件阵列基板,此主动元件阵列基板包含多个像素单元、多条扫描线以及多条数据线。这些像素单元排列成一个X×Y的像素阵列,X与Y均为正整数,X>Y>1。这些扫描线耦接这些像素单元。这些数据线符合一排列方式,并于像素阵列内耦接这些像素单元。所述的排列方式符合第i条数据线耦接第j列的第i-j+1个像素单元,i=1~X,i≧j,其中当i≦Y时,j=1~i,反的,当i>Y时,j=1~Y,i与j均为正整数。

The invention discloses a display panel and an active element array substrate thereof. The active element array substrate includes a plurality of pixel units, a plurality of scanning lines and a plurality of data lines. These pixel units are arranged into an X×Y pixel array, where both X and Y are positive integers, and X>Y>1. The scan lines are coupled to the pixel units. The data lines conform to an arrangement and are coupled to the pixel units in the pixel array. The arrangement is consistent with the i-th data line being coupled to the i-j+1 pixel unit in the j-th column, i=1~X, i≧j, wherein when i≦Y, j=1~i, Conversely, when i>Y, j=1˜Y, and both i and j are positive integers.

Description

显示面板及其主动元件阵列基板Display panel and its active element array substrate

技术领域technical field

本发明有关于一种显示面板及其主动元件阵列基板,且特别是有关于一种具有窄框边的主动元件阵列基板以及显示面板。The present invention relates to a display panel and its active element array substrate, and in particular to an active element array substrate with a narrow frame and a display panel.

背景技术Background technique

一般而言,显示面板是由主动元件阵列基板、对向基板以及显示介质所构成。在制作主动元件阵列时,通常会于主动元件阵列基板的非显示区(周边区域)同时制作与晶粒-玻璃接合制程或晶粒-薄膜接合制程相配合的周边线路。Generally speaking, a display panel is composed of an active element array substrate, an opposite substrate and a display medium. When fabricating an active device array, peripheral circuits matching with a die-glass bonding process or a die-film bonding process are usually fabricated simultaneously in the non-display area (peripheral area) of the active device array substrate.

图1为已知一种主动元件阵列基板的上视示意图。请参照图1,主动元件阵列基板10包括基板11、多条扫描线12、多条数据线13、多个像素单元14、栅极驱动芯片15以及源极驱动芯片16。基板11具有显示区A及围绕显示区A的非显示区B。扫描线12皆朝左至右的走向而相互平行地配置于基板11上。数据线13皆朝上至下的走向而相互平行地配置于基板11上,并与这些数据线13彼此垂直地交错,以形成位于显示区A内的多个像素单元14。FIG. 1 is a schematic top view of a known active device array substrate. Referring to FIG. 1 , the active device array substrate 10 includes a substrate 11 , a plurality of scan lines 12 , a plurality of data lines 13 , a plurality of pixel units 14 , a gate driver chip 15 and a source driver chip 16 . The substrate 11 has a display area A and a non-display area B surrounding the display area A. The scanning lines 12 are arranged parallel to each other on the substrate 11 , running from left to right. The data lines 13 are arranged parallel to each other on the substrate 11 from top to bottom, and vertically intersect with these data lines 13 to form a plurality of pixel units 14 in the display area A. Referring to FIG.

基板11具有互为相邻的第一侧边11a与第二侧边11b。栅极驱动芯片15位于基板11的第一侧边11a的非显示区B中,且与这些扫描线12电性连接。源极驱动芯片16位于基板11的第二侧边11b的非显示区B中,且与这些数据线13电性连接。尤其是,扫描线12透过显示区A左右两侧的非显示区B来进行周边线路的走线布局(wire routing),以电性连接栅极驱动芯片15。数据线13透过显示区A上下两侧的非显示区B来进行周边线路的走线布局(wirerouting),以电性连接源极驱动芯片16。The substrate 11 has a first side 11a and a second side 11b adjacent to each other. The gate driver chip 15 is located in the non-display area B of the first side 11 a of the substrate 11 and is electrically connected to the scan lines 12 . The source driver chip 16 is located in the non-display area B of the second side 11 b of the substrate 11 and is electrically connected to the data lines 13 . In particular, the scan lines 12 pass through the non-display areas B on the left and right sides of the display area A to perform wire routing of peripheral circuits, so as to electrically connect the gate driver chip 15 . The data line 13 passes through the non-display area B on the upper and lower sides of the display area A to perform wire routing of peripheral circuits, so as to electrically connect the source driver chip 16 .

然而,由于显示面板的诸多应用逐渐朝向轻、薄、短、小的趋势,如:移动电话、数字相机等电子产品,加上栅极驱动芯片以及源极驱动芯片各占用于基板二侧边的非显示区的大部分空间,导致此主动元件阵列基板产生一个不易实现窄边框的问题。However, since many applications of display panels are gradually moving towards light, thin, short, and small trends, such as: mobile phones, digital cameras and other electronic products, plus gate driver chips and source driver chips each occupying two sides of the substrate. Most of the space in the non-display area leads to a problem that the active device array substrate is difficult to achieve a narrow frame.

因此,如何提供一种解决方案以解决主动元件阵列基板不易实现窄边框的问题,以提高电子产品的可携带性,实为当前亟待解决的一项课题。Therefore, how to provide a solution to solve the problem that the active device array substrate is difficult to achieve a narrow frame, so as to improve the portability of electronic products, is an urgent problem to be solved at present.

发明内容Contents of the invention

本发明提供一种主动元件阵列基板,其具有窄框边,可提高空间利用率。The invention provides an active element array substrate, which has a narrow frame and can improve space utilization.

本发明提出一种主动元件阵列基板,此主动元件阵列基板包含多个像素单元、多条扫描线以及多条数据线。这些像素单元排列成一个X×Y的像素阵列,X与Y均为正整数,X>Y>1。这些扫描线耦接这些像素单元。这些数据线符合一排列方式,并于像素阵列内耦接这些像素单元。所述的排列方式符合第i条数据线耦接第j列的第i-j+1个像素单元,i=1~X,i≧j,其中当i≦Y时,j=1~i,反的,当i>Y时,j=1~Y,i与j均为正整数。The invention provides an active device array substrate, which includes a plurality of pixel units, a plurality of scanning lines and a plurality of data lines. These pixel units are arranged into an X×Y pixel array, where both X and Y are positive integers, and X>Y>1. The scan lines are coupled to the pixel units. The data lines conform to an arrangement and couple the pixel units in the pixel array. The arrangement conforms to that the i-th data line is coupled to the i-j+1th pixel unit in the j-th column, i=1~X, i≧j, wherein when i≦Y, j=1~i, Conversely, when i>Y, j=1˜Y, and both i and j are positive integers.

此外,在本发明的一实施例中,这些数据线中的第m条数据线还耦接第n列第X+Y-n-m+1个像素单元,其中m=1~(X-Y),n=(Y-m+1)~Y,m与n均为正整数。In addition, in an embodiment of the present invention, the mth data line among these data lines is also coupled to the X+Y-n-m+1th pixel unit in the nth column, where m=1˜(X-Y), n= (Y-m+1)~Y, m and n are both positive integers.

本发明又提出一种主动元件阵列基板,此主动元件阵列基板包括一基板、一像素阵列、多条扫描线以及多条数据线。像素阵列是由多个像素单元所排成于基板上,包含相对的第一侧与第二侧以及相对的第三侧与第四侧,第一侧与第二侧皆位于第三侧与第四侧之间。扫描线平行且间隔地配置于像素阵列内。数据线配置于像素阵列内,与这些扫描线皆通过像素阵列的第一侧。各数据线于像素阵列内交替地朝像素阵列的第二侧以及第四侧的方向延伸,以致于像素阵列内形成一与这些扫描线交错配置的阶梯状。The present invention further provides an active device array substrate, which includes a substrate, a pixel array, a plurality of scanning lines and a plurality of data lines. The pixel array is arranged on the substrate by a plurality of pixel units, including the opposite first side and the second side and the opposite third side and the fourth side, and the first side and the second side are both located on the third side and the third side between the four sides. The scan lines are arranged in the pixel array in parallel and at intervals. The data lines are arranged in the pixel array, and the scanning lines pass through the first side of the pixel array. Each data line extends alternately in the direction of the second side and the fourth side of the pixel array in the pixel array, so that a ladder shape is formed in the pixel array and arranged alternately with the scanning lines.

在本发明的一实施例中,所述像素阵列包含多个平行配置的像素列与像素行。各像素行的这些像素单元以及各像素列的这些像素单元皆为线性且彼此间隔排列。这些扫描线平行这些像素行,且各扫描线耦接其中一像素行中所有的像素单元。In an embodiment of the present invention, the pixel array includes a plurality of pixel columns and pixel rows arranged in parallel. The pixel units of each pixel row and the pixel units of each pixel column are arranged linearly and spaced apart from each other. The scan lines are parallel to the pixel rows, and each scan line is coupled to all pixel units in a pixel row.

在本发明的一实施例中,各数据线耦接不同像素列中至少一像素单元。In an embodiment of the invention, each data line is coupled to at least one pixel unit in a different pixel column.

在本发明的一实施例中,各数据线所耦接的所有像素单元均未排列于像素阵列的同一像素行,亦未排列于像素阵列的同一像素列中。In an embodiment of the present invention, all the pixel units coupled to the data lines are neither arranged in the same pixel row of the pixel array, nor arranged in the same pixel column of the pixel array.

在本发明的一实施例中,各数据线包含多个第一段以及多个第二段。这些第一段平行这些扫描线。这些第二段垂直这些扫描线,各第二段连接于任二相邻的第一段之间,且分别位于不同的像素行内。In an embodiment of the present invention, each data line includes a plurality of first segments and a plurality of second segments. The first segments are parallel to the scan lines. The second segments are perpendicular to the scan lines, each second segment is connected between any two adjacent first segments, and is respectively located in different pixel rows.

在本发明的一实施例中,像素阵列依据一X×Y阵列方式所排列,其中X、Y为正整数,X>Y>1。In an embodiment of the present invention, the pixel array is arranged in an X×Y array, wherein X and Y are positive integers, and X>Y>1.

在本发明的一实施例中这些扫描线的数量与数据线的数量一致,皆为X个。In an embodiment of the present invention, the number of these scan lines is the same as the number of data lines, both being X.

在本发明的一实施例中,当各扫描线启动其中一像素行中所有像素单元时,只有数量为Y个的数据线分别提供像素单元数据至对应的像素行中所有的像素单元。In an embodiment of the present invention, when each scan line activates all pixel units in a pixel row, only Y number of data lines respectively provide pixel unit data to all pixel units in the corresponding pixel row.

在本发明的一实施例中,共有数量为(X-Y)个数据线通过像素阵列的第四侧,且分别自像素阵列外延伸至像素阵列的第二侧。In an embodiment of the present invention, a total of (X-Y) data lines pass through the fourth side of the pixel array, and respectively extend from the outside of the pixel array to the second side of the pixel array.

在本发明的一实施例中,这些数量为(X-Y)个的数据线通过像素阵列的第二侧,且于像素阵列内交替地朝第一侧以及第三侧的方向延伸,以致于像素阵列内形成另一与这些扫描线交错配置的阶梯状。In an embodiment of the present invention, these data lines (X-Y) in number pass through the second side of the pixel array, and alternately extend toward the first side and the third side in the pixel array, so that the pixel array Another ladder shape interlaced with these scan lines is formed inside.

在本发明的一实施例中,主动元件阵列基板还包含至少一源极驱动芯片以及至少一栅极驱动芯片。源极驱动芯片位于基板的一侧。栅极驱动芯片与源极驱动芯片共同位基板的同侧。In an embodiment of the present invention, the active device array substrate further includes at least one source driver chip and at least one gate driver chip. The source driver chip is located on one side of the substrate. The gate driver chip and the source driver chip are located on the same side of the substrate.

本发明又提出一种主动元件阵列基板。此主动元件阵列基板包含多个像素单元、多条扫描线以及多条数据线。像素单元排列成一像素阵列。各扫瞄线均耦接同一行的这些像素单元。这些数据线均呈阶梯状而斜向耦接这些像素单元。各数据线所耦接的所有像素单元均未排列于像素阵列的同一行,且各数据线所耦接的所有像素单元亦未排列于像素阵列的同一列。The invention further provides an active element array substrate. The active device array substrate includes a plurality of pixel units, a plurality of scanning lines and a plurality of data lines. The pixel units are arranged into a pixel array. Each scan line is coupled to the pixel units in the same row. The data lines are ladder-shaped and obliquely coupled to the pixel units. All pixel units coupled to each data line are not arranged in the same row of the pixel array, and all pixel units coupled to each data line are not arranged in the same column of the pixel array.

在本发明的一实施例中,像素阵列依据一X×Y的阵列方式排列,其中X>Y>1,X、Y为正整数。In an embodiment of the present invention, the pixel array is arranged in an X×Y array, wherein X>Y>1, and X and Y are positive integers.

在本发明的一实施例中,共有数量为(X-Y)个的数据线从像素阵列的一侧伸出,分别延伸至像素阵列的另一侧,其中此二侧互为相邻。In an embodiment of the present invention, a total of (X-Y) data lines protrude from one side of the pixel array and respectively extend to the other side of the pixel array, wherein the two sides are adjacent to each other.

本发明又提供一种显示面板,其具有上述的主动元件阵列基板,可降低制造成本、增加产品可携带性。The present invention further provides a display panel, which has the above-mentioned active device array substrate, which can reduce manufacturing cost and increase product portability.

此种显示面板包括上述的主动元件阵列基板、对向基板以及显示介质。显示介质配置于对向基板与主动元件阵列基板之间。Such a display panel includes the above-mentioned active element array substrate, an opposite substrate and a display medium. The display medium is disposed between the opposite substrate and the active element array substrate.

综上所述,由于本发明的主动元件阵列基板具有独特的线路设计,因此本发明可减少框边宽度,进而提高空间利用率。此外,由于本发明的显示面板具有上述的主动元件阵列基板,因此本发明可降低制造成本且增加产品可携带性。To sum up, since the active device array substrate of the present invention has a unique circuit design, the present invention can reduce the width of the frame, thereby improving space utilization. In addition, since the display panel of the present invention has the above-mentioned active device array substrate, the present invention can reduce manufacturing cost and increase product portability.

附图说明Description of drawings

为让本发明的上述和其他目的、特征、优点与实施例能更明显易懂,所附附图的详细说明如下:In order to make the above and other objects, features, advantages and embodiments of the present invention more comprehensible, the detailed description of the accompanying drawings is as follows:

图1为已知一种主动元件阵列基板的上视示意图;FIG. 1 is a schematic top view of a known active element array substrate;

图2为本发明的主动元件阵列基板的上视示意图;2 is a schematic top view of the active element array substrate of the present invention;

图3为本发明一实施例的像素阵列的上视示意图;3 is a schematic top view of a pixel array according to an embodiment of the present invention;

图4a~图4d为针对某个数据线于9x5像素阵列中的右下走向示意图;Figures 4a to 4d are schematic diagrams of the lower right direction of a certain data line in a 9x5 pixel array;

图5a~图5d为针对某个数据线于9x5像素阵列中的左上走向示意图;5a to 5d are schematic diagrams of the upper left direction of a certain data line in a 9x5 pixel array;

图6为本发明另一实施例的像素阵列的上视示意图;FIG. 6 is a schematic top view of a pixel array according to another embodiment of the present invention;

图7a~图7b为单一扫描线与其对应五条数据线于9x5像素阵列中的示意图;7a-7b are schematic diagrams of a single scanning line and its corresponding five data lines in a 9x5 pixel array;

图8为本发明一实施例的显示面板的示意图。FIG. 8 is a schematic diagram of a display panel according to an embodiment of the invention.

【主要元件符号说明】[Description of main component symbols]

100:显示面板100: display panel

200:对向基板200: opposite substrate

300:显示介质300: display media

400:主动元件阵列基板400: active element array substrate

410:基板410: Substrate

420:源极驱动芯片420: Source driver chip

430:栅极驱动芯片430: gate drive chip

440:像素阵列440: pixel array

441:第一侧441: First side

442:第二侧442: second side

443:第三侧443: Third side

444:第四侧444: Fourth Side

450、450a~450x:像素单元450, 450a~450x: pixel unit

451:像素列451: pixel column

452:像素行452: pixel row

500、501~502:扫描线500, 501~502: scanning line

600、600a~600f、600A~600J、601~606:数据线600, 600a~600f, 600A~600J, 601~606: data line

610:第一段610: first paragraph

620:第二段620: Second paragraph

A:显示区A: display area

B:非显示区B: non-display area

具体实施方式Detailed ways

以下将以附图及详细说明清楚说明本发明的精神,如熟悉此技术的人员在了解本发明的实施例后,当可由本发明所教示的技术,加以改变及修饰,其并不脱离本发明的精神与范围。The following will clearly illustrate the spirit of the present invention with the accompanying drawings and detailed descriptions. After those skilled in the art understand the embodiments of the present invention, they can be changed and modified by the techniques taught in the present invention without departing from the present invention. spirit and scope.

本发明的主动元件阵列基板包含一由多个像素单元所排列成的像素阵列、多条扫描线与多条数据线。扫瞄线耦接同一行的像素单元。数据线大致均以阶梯状排列方式而斜向地耦接所有像素单元。如此,由于本发明的主动元件阵列基板上的阶梯状线路布局设计,使得主动元件阵列基板上的线路减少占用主动元件阵列基板框边区域的空间,有助减少主动元件阵列基板侧边宽度,或提高使用主动元件阵列基板侧边的空间利用率。The active device array substrate of the present invention includes a pixel array formed by a plurality of pixel units, a plurality of scanning lines and a plurality of data lines. The scan lines are coupled to the pixel units in the same row. The data lines are generally arranged in a ladder-like manner and are obliquely coupled to all the pixel units. In this way, due to the stepped line layout design on the active element array substrate of the present invention, the lines on the active element array substrate reduce the space occupied by the frame area of the active element array substrate, which helps to reduce the side width of the active element array substrate, or The space utilization ratio of the side of the substrate using the active element array is improved.

图2为本发明的主动元件阵列基板的上视示意图。请参照图2,一种主动元件阵列基板400包括一基板410、一或多个源极驱动芯片420、一或多个栅极驱动芯片430、一像素阵列440、多条扫描线500(scan line)以及多条数据线600(source line或data line)。基板410包括一显示区A以及与显示区A邻接的非显示区B。像素阵列440配置于基板410上,像素阵列440的所在区域被定义为上述的显示区A,而非显示区B为基板410扣除显示区A后的框边区域。FIG. 2 is a schematic top view of the active device array substrate of the present invention. Please refer to FIG. 2 , an active device array substrate 400 includes a substrate 410, one or more source driver chips 420, one or more gate driver chips 430, a pixel array 440, and a plurality of scan lines 500 (scan line ) and multiple data lines 600 (source line or data line). The substrate 410 includes a display area A and a non-display area B adjacent to the display area A. The pixel array 440 is disposed on the substrate 410 , and the area where the pixel array 440 is located is defined as the above-mentioned display area A, while the non-display area B is the border area of the substrate 410 minus the display area A.

像素阵列440是由多个像素单元450(或称子像素单元,sub pixels)所排成,这些像素单元450例如为红色像素单元、蓝色像素单元与绿色像素单元。像素阵列440包含相对的第一侧441与第二侧442以及相对的第三侧443与第四侧444,第一侧441与第二侧442皆位于第三侧443与第四侧444之间。The pixel array 440 is formed by a plurality of pixel units 450 (or called sub-pixel units, sub pixels), and these pixel units 450 are, for example, red pixel units, blue pixel units and green pixel units. The pixel array 440 includes opposite first sides 441 and second sides 442 and opposite third sides 443 and fourth sides 444, the first side 441 and the second side 442 are located between the third side 443 and the fourth side 444 .

源极驱动芯片420位于基板410一侧的框边区域内。栅极驱动芯片430与源极驱动芯片420共同位基板410同侧的框边区域内。如此,更加有助本发明主动元件阵列基板400实现窄框边特性,进而提高空间利用率。此外,源极驱动芯片420与栅极驱动芯片430亦可整合为单一个体,然而,本发明不仅限于上述变化。The source driver chip 420 is located in a frame area on one side of the substrate 410 . The gate driver chip 430 and the source driver chip 420 are located in the frame area on the same side of the substrate 410 . In this way, it is more helpful for the active device array substrate 400 of the present invention to achieve narrow frame characteristics, thereby improving space utilization. In addition, the source driver chip 420 and the gate driver chip 430 can also be integrated into a single body, however, the present invention is not limited to the above changes.

扫描线500的数量小于等于数据线600的数量,且扫描线500相互平行且间隔地配置于像素阵列440内。具体来说,扫描线500连接栅极驱动芯片430,且通过像素阵列440的第一侧441与第二侧442,意即,扫描线500从基板410一侧的框边区域(即非显示区B)经像素阵列440延伸至基板410另一框边区域(即非显示区B)。The number of scan lines 500 is less than or equal to the number of data lines 600 , and the scan lines 500 are arranged parallel to each other and spaced apart in the pixel array 440 . Specifically, the scan line 500 is connected to the gate driver chip 430, and passes through the first side 441 and the second side 442 of the pixel array 440, that is, the scan line 500 starts from the frame area on one side of the substrate 410 (that is, the non-display area) B) extending through the pixel array 440 to another border area of the substrate 410 (ie, the non-display area B).

数据线600间隔地配置于像素阵列440内,均呈以约略呈阶梯状的走向而朝图中右下的方向斜向地耦接大部分像素单元450。具体来说,数据线600通过像素阵列440的第一侧441,并进入像素阵列440后,于像素阵列440内交替地朝像素阵列440的第二侧442的方向以及朝像素阵列440的第四侧444的方向延伸,使得数据线600于像素阵列440内形成与扫描线500交错配置的第一阶梯状路线(如图4c的数据线600c的走向)。The data lines 600 are arranged at intervals in the pixel array 440 , and all of them are inclined to couple most of the pixel units 450 in a roughly step-like direction toward the bottom right in the figure. Specifically, the data line 600 passes through the first side 441 of the pixel array 440, and after entering the pixel array 440, in the pixel array 440 alternately faces toward the second side 442 of the pixel array 440 and toward the fourth side of the pixel array 440. The direction of the side 444 extends, so that the data lines 600 form a first stepped route intersecting with the scan lines 500 in the pixel array 440 (such as the direction of the data lines 600c shown in FIG. 4c ).

更详细而言,所述像素阵列440包含多个平行配置的像素列451与像素行452。像素行452,如图2所示,是朝图中上、下的走向而相互平行。像素列451,如图3所示,是朝图中左、右的走向而相互平行。像素列451的走向与像素行452的走向相正交。各像素行452中的像素单元450以及各像素列451中的像素单元450皆为线性且彼此间隔排列。扫描线500平行像素行452,且各扫描线500耦接每一像素行452中所有的像素单元450。More specifically, the pixel array 440 includes a plurality of pixel columns 451 and pixel rows 452 arranged in parallel. The pixel rows 452, as shown in FIG. 2 , are parallel to each other in the direction of up and down in the figure. The pixel rows 451, as shown in FIG. 3 , are parallel to each other along the left and right directions in the figure. The orientation of the pixel columns 451 is orthogonal to the orientation of the pixel rows 452 . The pixel units 450 in each pixel row 452 and the pixel units 450 in each pixel column 451 are linear and arranged at intervals. The scan lines 500 are parallel to the pixel rows 452 , and each scan line 500 is coupled to all the pixel units 450 in each pixel row 452 .

此外,各数据线600所耦接的所有像素单元450均未排列于像素阵列440的同一像素行452,亦未排列于像素阵列440的同一像素列451中。更详细而言,各数据线600包含多个第一段610以及多个第二段620。各第二段620直接连接于任二相邻的第一段610之间,且分别位于不同的像素行452内,并于不同的像素行452内耦接至少一个像素单元450。第一段610朝图中上、下的走向延伸,不限与扫描线500相互平行或不相互平行。第二段620图中左、右的走向延伸,不限与扫描线500相互垂直或不相互垂直,In addition, all the pixel units 450 coupled to each data line 600 are neither arranged in the same pixel row 452 of the pixel array 440 nor arranged in the same pixel column 451 of the pixel array 440 . In more detail, each data line 600 includes a plurality of first segments 610 and a plurality of second segments 620 . Each second segment 620 is directly connected between any two adjacent first segments 610 , and is respectively located in a different pixel row 452 , and is coupled to at least one pixel unit 450 in a different pixel row 452 . The first segment 610 extends toward the upper and lower directions in the figure, and is not limited to be parallel to or not parallel to the scan line 500 . The left and right directions in the second segment 620 are extended, and are not limited to being perpendicular to the scanning line 500 or not perpendicular to each other,

然而,本发明不限于此,各数据线也可耦接不同像素列中的二个以上的像素单元,及/或不同像素行中的二个以上的像素单元。However, the present invention is not limited thereto, and each data line may also be coupled to more than two pixel units in different pixel columns, and/or more than two pixel units in different pixel rows.

另外,由图2可知,部分数量的数据线600自第四侧444伸出像素阵列440后便分别延伸至像素阵列440的第二侧442,并分别自像素阵列440的第二侧442伸入像素阵列440后,便于像素阵列440内交替地朝第一侧441的方向以及第三侧443的方向延伸,以致于像素阵列440内形成与扫描线500交错配置的第二阶梯状路线(如图5d的数据线600f的走向)。如此,不位于第一阶梯状路线内的其余像素单元450也可通过第二阶梯状路线而与数据线600相耦接,因此不需另外配置更多数量的数据线,进而有助降低制造成本以及主动元件阵列基板的窄框边特征的实现。In addition, it can be seen from FIG. 2 that part of the data lines 600 extend from the fourth side 444 of the pixel array 440 to the second side 442 of the pixel array 440 respectively, and respectively extend into the second side 442 of the pixel array 440. Behind the pixel array 440, it is convenient for the pixel array 440 to alternately extend toward the direction of the first side 441 and the direction of the third side 443, so that a second stepped route interlaced with the scanning lines 500 is formed in the pixel array 440 (as shown in FIG. 5d data line 600f direction). In this way, the rest of the pixel units 450 not located in the first stepped route can also be coupled to the data line 600 through the second stepped route, so there is no need to additionally configure a larger number of data lines, thereby helping to reduce manufacturing costs And the realization of the narrow frame edge feature of the active element array substrate.

图3为本发明一实施例的像素阵列的上视示意图。参阅图3,更进一步地以数学方式描述上述数据线600的第一阶梯状路线与像素单元450的耦接关系。FIG. 3 is a schematic top view of a pixel array according to an embodiment of the present invention. Referring to FIG. 3 , the coupling relationship between the above-mentioned first stepped route of the data line 600 and the pixel unit 450 is further mathematically described.

上述的像素阵列440为一X×Y阵列,其中X与Y均为正整数,X>Y>1。故,各像素列451中像素单元450为1~X,其数量为X个,也分别与扫描线500与数据线600的数量一致。各像素行452中像素单元450的数量为1~Y,其数量为Y个。The aforementioned pixel array 440 is an X×Y array, where X and Y are both positive integers, and X>Y>1. Therefore, the number of pixel units 450 in each pixel column 451 is 1˜X, and the number is X, which is also consistent with the number of the scan lines 500 and the data lines 600 . The number of pixel units 450 in each pixel row 452 is 1˜Y, and the number is Y.

数据线600符合第一排列方式而耦接所述的大部分像素单元450,以形成上述的第一阶梯状路线。所述的第一排列方式是符合第i条数据线600耦接第j列的第i-j+1个像素单元450,i=1~X,i≧j,其中当i≦Y时,j=1~i,反的,当i>Y时,j=1~Y,i与j均为正整数。The data line 600 conforms to the first arrangement and is coupled to most of the pixel units 450 to form the above-mentioned first stepped route. The first arrangement is consistent with the i-th data line 600 being coupled to the i-j+1-th pixel unit 450 of the j-th column, i=1-X, i≧j, wherein when i≦Y, j =1~i, conversely, when i>Y, j=1~Y, both i and j are positive integers.

举例来说,图4a~图4d为针对某个数据线于9x5像素阵列440中的右下走向示意图。For example, FIGS. 4 a to 4 d are schematic diagrams of the bottom right direction of a certain data line in the 9×5 pixel array 440 .

如图4a所示,当X=9,Y=5为例,且当第i条数据线600是从右至左边的顺序,且像素阵列440的第j列是从上至下的顺序时,以下提供几例解释数据线依据上述的第一排列方式于9x5像素阵列440内的走向变化以及与像素单元的耦接关系(以下通过网点方块表示被耦接的像素单元):As shown in FIG. 4a, when X=9, Y=5 as an example, and when the ith data line 600 is in the order from right to left, and the jth column of the pixel array 440 is in the order from top to bottom, The following provides several examples to explain the change of the direction of the data lines in the 9x5 pixel array 440 and the coupling relationship with the pixel units according to the above-mentioned first arrangement mode (the coupled pixel units are represented by dotted squares below):

如图4a所示,当i=1,符合i≦5,j=1~1,因此第1条数据线600a耦接像素阵列440第1列的第(1-1+1=1)个像素单元450a(如网点方块所示);As shown in FIG. 4a, when i=1, i≦5, j=1~1, so the first data line 600a is coupled to the (1-1+1=1)th pixel in the first column of the pixel array 440 Unit 450a (shown as dotted square);

如图4b所示,当i=3,符合i≦5,j=1~3,因此第3条数据线600b耦接像素阵列440第1列的第(3-1+1=3)个像素单元450b(如网点方块所示)、第2列的第(3-2+1=2)个像素单元450c(如网点方块所示)以及第3列的第(3-3+1=1)个像素单元450d(如网点方块所示);As shown in FIG. 4b, when i=3, i≦5, j=1~3, so the third data line 600b is coupled to the (3-1+1=3)th pixel in the first column of the pixel array 440 Unit 450b (shown as a grid dot square), the (3-2+1=2)th pixel unit 450c of the second column (shown as a grid dot square) and the (3-3+1=1)th pixel unit 450c of the third column A pixel unit 450d (shown as a grid dot square);

如图4c所示,当i=7,符合i>5,j=1~5,因此第7条数据线600c耦接像素阵列440第1列的第(7-1+1=7)个像素单元450e(如网点方块所示)、第2列的第(7-2+1=6)个像素单元450f(如网点方块所示)、第3列的第(7-3+1=5)个像素单元450g(如网点方块所示)、第4列的第(7-4+1=4)个像素单元450h(如网点方块所示)以及第5列的第(7-5+1=3)个像素单元450i(如网点方块所示)。As shown in FIG. 4c, when i=7, i>5, j=1~5, so the seventh data line 600c is coupled to the (7-1+1=7)th pixel in the first column of the pixel array 440 Unit 450e (as shown in the dot square), the (7-2+1=6)th pixel unit 450f in the second column (as shown in the dot square), the (7-3+1=5) in the third column pixel unit 450g (as shown in the grid dot square), the (7-4+1=4) pixel unit 450h in the 4th column (as shown in the grid dot square) and the (7-5+1=4)th pixel unit in the 5th column 3) Pixel units 450i (as shown by dotted squares).

如图4d所示,当i=9,符合i>5时,j=1~5,因此第9条数据线600d耦接像素阵列440第1列的第(9-1+1=9)个像素单元450j(如网点方块所示)、第2列的第(9-2+1=8)个像素单元450k(如网点方块所示)、第3列的第(9-3+1=7)个像素单元450l(如网点方块所示)、第4列的第(9-4+1=6)个像素单元450m(如网点方块所示)以及第5列的第(9-5+1=5)个像素单元450n(如网点方块所示)。As shown in FIG. 4d, when i=9 and i>5, j=1~5, so the ninth data line 600d is coupled to the (9-1+1=9)th of the first column of the pixel array 440 Pixel unit 450j (as shown in the grid dot square), the (9-2+1=8)th pixel unit 450k in the second column (as shown in the grid dot square), the (9-3+1=7)th pixel unit in the third column ) pixel unit 450l (as shown in the dot square), the (9-4+1=6) pixel unit 450m of the 4th row (as shown in the dot square) and the (9-5+1) of the 5th row = 5) pixel units 450n (shown as dotted squares).

此外,复参阅图3,以下亦以数学方式描述上述数据线600于第二阶梯状路线的数量,以及上述数据线600于第二阶梯状路线内与像素单元450的耦接关系。In addition, referring to FIG. 3 , the number of the data lines 600 in the second stepped route and the coupling relationship between the data lines 600 and the pixel unit 450 in the second stepped route are also described mathematically.

在此实施例中,共有数量为(X-Y)个数据线600自像素阵列440内伸出像素阵列440的第四侧444,且分别从像素阵列440外延伸至像素阵列440的第二侧442。这些数量为(X-Y)个的数据线600通过像素阵列440的第二侧442,且于像素阵列440内交替地朝第一侧441以及第三侧443的方向延伸,以致于像素阵列440内形成与扫描线500交错配置的上述的第二阶梯状路线。In this embodiment, a total of (X−Y) data lines 600 extend from the pixel array 440 to the fourth side 444 of the pixel array 440 , and respectively extend from the pixel array 440 to the second side 442 of the pixel array 440 . These (X-Y) data lines 600 pass through the second side 442 of the pixel array 440, and alternately extend in the direction of the first side 441 and the third side 443 in the pixel array 440, so that a pixel array 440 forms a The above-mentioned second ladder-shaped route interlaced with the scan lines 500 .

上述的数据线600自像素阵列440的第二侧442伸入像素阵列440后,这些数据线600符合第二排列方式而耦接其余部分的像素单元450,以形成上述的第二阶梯状路线。所述的第二排列方式是符合数据线600中的第m条数据线600还耦接第n列第X+Y-n-m+1个像素单元450,其中m=1~(X-Y),n=(Y-m+1)~Y,m与n均为正整数。After the above-mentioned data lines 600 extend into the pixel array 440 from the second side 442 of the pixel array 440 , these data lines 600 conform to the second arrangement and couple to the rest of the pixel units 450 to form the above-mentioned second stepped route. The second arrangement is consistent with the fact that the mth data line 600 of the data lines 600 is also coupled to the nth column of X+Y-n-m+1 pixel units 450, where m=1~(X-Y), n= (Y-m+1)~Y, m and n are both positive integers.

举同一例来说,图5a~图5d为针对某个数据线600于9x5像素阵列440中的左上走向示意图。For the same example, FIGS. 5a to 5d are schematic diagrams showing the upper left direction of a certain data line 600 in the 9×5 pixel array 440 .

同上例中,如图5a,当X=9,Y=5,且当第m条数据线600是从右至左边的顺序,且像素阵列440的第n列是从上至下的顺序时,则m=1~(9-5=4),以下提供几例解释数据线依据上述的第二排列方式于9x5像素阵列内的走向变化以及与像素单元的耦接关系(以下通过网点方块表示被耦接的像素单元):In the above example, as shown in Figure 5a, when X=9, Y=5, and when the mth data line 600 is in the order from right to left, and the nth column of the pixel array 440 is in the order from top to bottom, Then m=1~(9-5=4), the following provides several examples to explain the change of the direction of the data lines in the 9x5 pixel array according to the above-mentioned second arrangement mode and the coupling relationship with the pixel units (hereinafter represented by dotted squares coupled pixel units):

如图5a所示,当m=1,n=(5-1+1=5)~5,则第1条数据线600a还耦接像素阵列440第5列第(9+5-5-1+1=9)个像素单元450o(如网点方块所示);As shown in FIG. 5a, when m=1, n=(5-1+1=5)~5, the first data line 600a is also coupled to the fifth column (9+5-5-1) of the pixel array 440 +1=9) pixel unit 450o (as shown in the dot box);

如图5b所示,当m=2,n=(5-2+1=4)~5,则第2条数据线600e还耦接像素阵列440第5列第(9+5-5-2+1=8)个像素单元450p(如网点方块所示)以及第4列第(9+5-4-2+1=9)个像素单元450q(如网点方块所示);As shown in Figure 5b, when m=2, n=(5-2+1=4)~5, then the second data line 600e is also coupled to the fifth column of the pixel array 440 (9+5-5-2 +1=8) pixel unit 450p (as shown in the dot square) and the 4th column (9+5-4-2+1=9) pixel unit 450q (as shown in the dot square);

如图5c所示,当m=3,n=(5-3+1=3)~5,则第3条数据线600b还耦接像素阵列440第5列第(9+5-3-2+1=7)个像素单元450r(如网点方块所示)、第4列第(9+5-4-3+1=8)个像素单元450s(如网点方块所示)以及第3列第(9+5-3-3+1=9)个像素单元450t(如网点方块所示);As shown in FIG. 5c, when m=3, n=(5-3+1=3)~5, the third data line 600b is also coupled to the fifth column (9+5-3-2) of the pixel array 440 +1=7) pixel unit 450r (as shown in the grid dot square), the 4th column (9+5-4-3+1=8) pixel unit 450s (as shown in the grid dot square) and the 3rd column (9+5-3-3+1=9) pixel units 450t (as shown in dot squares);

如图5d所示,当m=4,n=(5-4+1=2)~5,则第4条数据线600f还耦接像素阵列440第5列第(9+5-5-4+1=6)个像素单元450u(如网点方块所示)、第4列第(9+5-4-4+1=7)个像素单元450v(如网点方块所示)、第3列第(9+5-3-4+1=8)个像素单元450w(如网点方块所示)以及第2列第(9+5-2-4+1=9)个像素单元450x(如网点方块所示)。As shown in FIG. 5d, when m=4, n=(5-4+1=2)~5, the fourth data line 600f is also coupled to the fifth column (9+5-5-4) of the pixel array 440 +1=6) pixel units 450u (as shown in dotted squares), the 4th column (9+5-4-4+1=7) pixel units 450v (as shown in dotted dots), the 3rd column (9+5-3-4+1=8) pixel units 450w (as shown in dot squares) and the second column (9+5-2-4+1=9) pixel units 450x (as dot squares shown).

图6为本发明另一实施例的像素阵列440的上视示意图。请参阅图6,图6中第一至第九像素行452的顺序改为从左至右边的顺序。虽然图6中的数据线600的第一阶梯状走向是朝图中左下的方向斜向地耦接大部分像素单元450,数据线600的第二阶梯状走向是朝图中右上的方向斜向地耦接其余像素单元450,但是,图6中的数据线600朝左下的走向亦适用于上述第一排列方式的规则,而数据线600朝右上的走向亦适用上述第二排列方式的规则。FIG. 6 is a schematic top view of a pixel array 440 according to another embodiment of the present invention. Please refer to FIG. 6 , the order of the first to ninth pixel rows 452 in FIG. 6 is changed from left to right. Although the first step-like direction of the data line 600 in FIG. 6 is obliquely coupled to most of the pixel units 450 toward the lower left direction in the figure, the second step-like direction of the data line 600 is obliquely toward the upper right direction in the figure. The other pixel units 450 are ground-coupled. However, the direction of the data line 600 toward the lower left in FIG.

图7a~图7b为9x5像素阵列中其中一扫描线与其对应五条数据线的操作示意图,其中通过网点方块表示被启动的像素单元。FIGS. 7 a - 7 b are schematic diagrams illustrating the operation of one scan line and its corresponding five data lines in a 9x5 pixel array, wherein activated pixel units are represented by dotted squares.

操作时,如图7a所示,当驱动上述主动元件阵列基板400时,首先依序对扫描线输入一像素单元开启电压,接着,当依序对扫描线输入像素单元开启电压时,依序对与这些扫瞄线交错的数据线输入像素单元数据。During operation, as shown in FIG. 7a, when driving the above-mentioned active device array substrate 400, a pixel unit turn-on voltage is first sequentially input to the scan lines, and then, when the pixel unit turn-on voltage is sequentially input to the scan lines, the pixel unit turn-on voltage is sequentially input to the scan lines. Data lines interleaved with these scan lines input pixel unit data.

举例而言,如图7a所示,从右至左边的顺序中,当对第1条扫瞄线501输入像素单元开启电压至像素阵列440第1行的所有像素单元450A~E时,第1~5条数据线601~605分别对像素阵列440第1行由上至下顺序的第1~5个像素单元450A~E输入像素单元数据。即,第1条数据线601对像素阵列440第1行中由上至下顺序的第1个像素单元450A(如网点方块所示)输入像素单元数据、第2条数据线602对像素阵列440第1行中由上至下顺序的第2个像素单元450B(如网点方块所示)输入像素单元数据、第3条数据线603对像素阵列440第1行中由上至下顺序的第3个像素单元450C(如网点方块所示)输入像素单元数据、第4条数据线604对像素阵列440第1行中由上至下顺序的第4个像素单元450D(如网点方块所示)输入像素单元数据,以及第5条数据线605对像素阵列440第1行中由上至下顺序的第5个像素单元450E(如网点方块所示)输入像素单元数据。For example, as shown in FIG. 7a, in the order from right to left, when the pixel unit turn-on voltage is input to the first scan line 501 to all the pixel units 450A~E in the first row of the pixel array 440, the first The ~5 data lines 601 ~ 605 respectively input pixel unit data to the first to fifth pixel units 450A~E in the first row of the pixel array 440 from top to bottom. That is, the first data line 601 inputs pixel unit data to the first pixel unit 450A (as shown by the dotted square) in the first row of the pixel array 440 from top to bottom, and the second data line 602 inputs the pixel unit data to the pixel array 440. The second pixel unit 450B in the order from top to bottom in the first row (as shown by the dotted square) inputs the pixel unit data, and the third data line 603 pairs with the third pixel unit 450B in the order from top to bottom in the first row of the pixel array 440 A pixel unit 450C (as shown in the dotted square) inputs the pixel unit data, and the fourth data line 604 inputs the fourth pixel unit 450D (as shown in the dotted square) from top to bottom in the first row of the pixel array 440. The pixel unit data and the fifth data line 605 input the pixel unit data to the fifth pixel unit 450E (as shown by the dotted square) in the first row of the pixel array 440 from top to bottom.

参阅如图7b所示,当第2条扫瞄线502输入一像素单元开启电压至第2行像素行的所有像素单元450F~J时,第2~6条数据线602~606分别对像素阵列440第2行由上至下顺序的第1~5个像素单元450F~J输入像素单元数据。即,第2条数据线602对像素阵列440第2行中由上至下顺序的第1个像素单元450F(如网点方块所示)输入像素单元数据、第3条数据线603对像素阵列440第2行中由上至下顺序的第2个像素单元450G(如网点方块所示)输入像素单元数据、第4条数据线604对像素阵列440第2行中由上至下顺序的第3个像素单元450H(如网点方块所示)输入像素单元数据、第5条数据线605对像素阵列440第2行中由上至下顺序的第4个像素单元450I(如网点方块所示)输入一像素单元数据,以及第6条数据线606对像素阵列440第2行中由上至下顺序的第5个像素单元450J(如网点方块所示)输入像素单元数据。Referring to Fig. 7b, when the second scan line 502 inputs a pixel unit turn-on voltage to all pixel units 450F~J in the second row of pixel rows, the second to sixth data lines 602~606 respectively control the pixel array In line 440, pixel unit data is input to the first to fifth pixel units 450F~J in order from top to bottom. That is, the second data line 602 inputs the pixel unit data to the first pixel unit 450F (as shown by the dotted square) in the second row of the pixel array 440 from top to bottom, and the third data line 603 inputs the pixel unit data to the pixel array 440 The second pixel unit 450G from top to bottom in row 2 inputs pixel unit data, and the fourth data line 604 pairs with the third pixel unit from top to bottom in row 2 of pixel array 440. Each pixel unit 450H (shown as a dotted square) inputs pixel unit data, and the fifth data line 605 inputs the fourth pixel unit 450I (as shown by a dotted square) from top to bottom in the second row of the pixel array 440 One pixel unit data, and the sixth data line 606 inputs the pixel unit data to the fifth pixel unit 450J from top to bottom in the second row of the pixel array 440 (as shown by the dotted square).

故,依此类推可知,以上述的像素阵列440为X×Y阵列而言,当X条(例如9条)扫描线各自启动所对应的像素行中所有像素单元时,只有数量为Y条(例如5条)数据线分别提供像素单元数据至对应的像素行的所有像素单元,不需使用所有数据线。Therefore, it can be deduced by analogy that if the above-mentioned pixel array 440 is an X×Y array, when X (for example, 9) scanning lines each activate all the pixel units in the corresponding pixel row, there are only Y ( For example, 5 data lines respectively provide pixel unit data to all pixel units in the corresponding pixel row, and it is not necessary to use all the data lines.

图8为本发明一实施例的显示面板100的示意图。请参照图8,上述的主动元件阵列基板400更可应用于一显示面板100中。显示面板100包括对向基板200、显示介质300以及上述的主动元件阵列基板400。对向基板200配置于主动元件阵列基板400上方。显示介质300配置于对向基板200与主动元件阵列基板400之间。显示面板100例如是液晶显示面板、电泳式显示面板或其他显示面板。对向基板200例如是彩色滤光基板,而显示介质300则例如为液晶层或是其他的材料。在本实施例中,显示面板100例如是一种横向显示(Landscape viewing)的显示面板,然而,本发明不仅限于此。FIG. 8 is a schematic diagram of a display panel 100 according to an embodiment of the present invention. Please refer to FIG. 8 , the above-mentioned active device array substrate 400 can be further applied to a display panel 100 . The display panel 100 includes an opposite substrate 200 , a display medium 300 and the aforementioned active device array substrate 400 . The opposite substrate 200 is disposed above the active device array substrate 400 . The display medium 300 is disposed between the opposite substrate 200 and the active device array substrate 400 . The display panel 100 is, for example, a liquid crystal display panel, an electrophoretic display panel or other display panels. The opposite substrate 200 is, for example, a color filter substrate, and the display medium 300 is, for example, a liquid crystal layer or other materials. In this embodiment, the display panel 100 is, for example, a landscape viewing display panel, however, the present invention is not limited thereto.

综上所述,由于本发明的主动元件阵列基板具有独特的线路设计,因此本发明可减少框边宽度,进而提高空间利用率。此外,由于本发明的显示面板具有上述的主动元件阵列基板,因此本发明可降低制造成本且增加产品可携带性。To sum up, since the active device array substrate of the present invention has a unique circuit design, the present invention can reduce the width of the frame, thereby improving space utilization. In addition, since the display panel of the present invention has the above-mentioned active device array substrate, the present invention can reduce manufacturing cost and increase product portability.

本发明所揭露如上的各实施例中,并非用以限定本发明,任何熟悉此技艺者,在不脱离本发明的精神和范围内,当可作各种的更动与润饰,因此本发明的保护范围当视所附的权利要求书所界定的范围为准。The above embodiments disclosed in the present invention are not intended to limit the present invention. Any skilled person may make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection should be based on the scope defined by the appended claims.

Claims (12)

1. an active component array base board, is characterized in that, comprising:
One substrate;
One pel array, on this substrate, comprises the first relative side and the second side and relative the 3rd side and the 4th side by a plurality of pixel cell line up, and this first side and this second side are all between the 3rd side and the 4th side;
Multi-strip scanning line, parallel and compartment of terrain is disposed in this pel array; And
Many data lines, be disposed in this pel array, all pass through this first side of this pel array with described multi-strip scanning line, described in each, data line alternately extends towards this second side of this pel array and the direction of the 4th side in this pel array so that in this pel array, form one with interconnected stepped of described multi-strip scanning line;
The pixel column that this pel array comprises a plurality of configured in parallel and pixel column, described in each described a plurality of pixel cells of pixel column and described in each described a plurality of pixel cells of pixel column be all linearity and each interval and arrange, a plurality of pixel columns described in described multi-strip scanning line parallel, and described in each, sweep trace couples described a plurality of pixel column all pixel cells in one of them.
2. active component array base board according to claim 1, is characterized in that, described in each, data line couples at least one pixel cell in different pixels row.
3. active component array base board according to claim 2, is characterized in that, all pixel cells that described in each, data line couples are not all arranged in the same pixel column of this pel array, is not also arranged in the same pixel column of this pel array.
4. active component array base board according to claim 1, is characterized in that, described in each, data line comprises:
A plurality of first paragraphs, parallel described multi-strip scanning line; And
A plurality of second segments, vertical described multi-strip scanning line, described in each, second segment is connected between wantonly two adjacent described first paragraphs, and lays respectively in different pixel columns.
5. active component array base board according to claim 1, is characterized in that, this pel array is arranged according to one X * Y array way, and X, Y are positive integer, X > Y > 1.
6. active component array base board according to claim 5, is characterized in that, the quantity of described multi-strip scanning line is consistent with the quantity of data line, is all X.
7. active component array base board according to claim 5, it is characterized in that, when sweep trace described in each starts described a plurality of pixel columns in one of them during all pixel cells, only having quantity is that the described data line of Y provides respectively all pixel cells of pixel cell data to corresponding described a plurality of pixel columns.
8. active component array base board according to claim 5, is characterized in that, total quantity be that (X-Y) individual data line passes through the 4th side of this pel array, and this second side to this pel array from this pel array extension respectively.
9. active component array base board according to claim 8, it is characterized in that, described quantity is that (X-Y) individual data line is by this second side of this pel array, and alternately towards the direction of this first side and the 3rd side, extend, so that in this pel array, form interconnected stepped of another and described multi-strip scanning line in this pel array.
10. active component array base board according to claim 1, is characterized in that, also comprises:
At least one source driving chip, is positioned at a side of this substrate; And
At least one grid drive chip, is co-located at the homonymy of this substrate with this source driving chip.
11. 1 kinds of active component array base boards, is characterized in that, comprise:
A plurality of pixel cells, are arranged in a pel array;
Multi-strip scanning line, described in each, scanning linear all couples described a plurality of pixel cells of same a line; And
Many data lines, described many data lines are all stepped and oblique couples described a plurality of pixel cell, the all described pixel cell that described in each, data line couples is not all arranged in same a line of this pel array, and all described pixel cell that described in each, data line couples is not also arranged in the same row of this pel array;
This pel array is arranged according to the array way of one X * Y, X > Y > 1, and X, Y are positive integer;
Total quantity is stretched out from a side of this pel array for (X-Y) individual described data line, extends to respectively the opposite side of this pel array, and wherein this side is adjacent with this opposite side.
12. 1 kinds of display panels, is characterized in that, comprise:
Active component array base board just like claim 1~11 described in one of them;
One subtend substrate, is disposed at this active component array base board top; And
One display medium, is disposed between this subtend substrate and this active component array base board.
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