CN102938244B - Display panel and active component array substrate thereof - Google Patents

Abstract

The invention discloses a display panel and an active element array substrate thereof. The active element array substrate includes a plurality of pixel units, a plurality of scanning lines and a plurality of data lines. These pixel units are arranged into an X×Y pixel array, where both X and Y are positive integers, and X>Y>1. The scan lines are coupled to the pixel units. The data lines conform to an arrangement and are coupled to the pixel units in the pixel array. The arrangement is consistent with the i-th data line being coupled to the i-j+1 pixel unit in the j-th column, i=1~X, i≧j, wherein when i≦Y, j=1~i, Conversely, when i>Y, j=1˜Y, and both i and j are positive integers.

Description

Display panel and its active element array substrate

technical field

The present invention relates to a display panel and its active element array substrate, and in particular to an active element array substrate with a narrow frame and a display panel.

Background technique

Generally speaking, a display panel is composed of an active element array substrate, an opposite substrate and a display medium. When fabricating an active device array, peripheral circuits matching with a die-glass bonding process or a die-film bonding process are usually fabricated simultaneously in the non-display area (peripheral area) of the active device array substrate.

FIG. 1 is a schematic top view of a known active device array substrate. Referring to FIG. 1 , the active device array substrate 10 includes a substrate 11 , a plurality of scan lines 12 , a plurality of data lines 13 , a plurality of pixel units 14 , a gate driver chip 15 and a source driver chip 16 . The substrate 11 has a display area A and a non-display area B surrounding the display area A. The scanning lines 12 are arranged parallel to each other on the substrate 11 , running from left to right. The data lines 13 are arranged parallel to each other on the substrate 11 from top to bottom, and vertically intersect with these data lines 13 to form a plurality of pixel units 14 in the display area A. Referring to FIG.

The substrate 11 has a first side 11a and a second side 11b adjacent to each other. The gate driver chip 15 is located in the non-display area B of the first side 11 a of the substrate 11 and is electrically connected to the scan lines 12 . The source driver chip 16 is located in the non-display area B of the second side 11 b of the substrate 11 and is electrically connected to the data lines 13 . In particular, the scan lines 12 pass through the non-display areas B on the left and right sides of the display area A to perform wire routing of peripheral circuits, so as to electrically connect the gate driver chip 15 . The data line 13 passes through the non-display area B on the upper and lower sides of the display area A to perform wire routing of peripheral circuits, so as to electrically connect the source driver chip 16 .

However, since many applications of display panels are gradually moving towards light, thin, short, and small trends, such as: mobile phones, digital cameras and other electronic products, plus gate driver chips and source driver chips each occupying two sides of the substrate. Most of the space in the non-display area leads to a problem that the active device array substrate is difficult to achieve a narrow frame.

Therefore, how to provide a solution to solve the problem that the active device array substrate is difficult to achieve a narrow frame, so as to improve the portability of electronic products, is an urgent problem to be solved at present.

Contents of the invention

The invention provides an active element array substrate, which has a narrow frame and can improve space utilization.

The invention provides an active device array substrate, which includes a plurality of pixel units, a plurality of scanning lines and a plurality of data lines. These pixel units are arranged into an X×Y pixel array, where both X and Y are positive integers, and X>Y>1. The scan lines are coupled to the pixel units. The data lines conform to an arrangement and couple the pixel units in the pixel array. The arrangement conforms to that the i-th data line is coupled to the i-j+1th pixel unit in the j-th column, i=1~X, i≧j, wherein when i≦Y, j=1~i, Conversely, when i>Y, j=1˜Y, and both i and j are positive integers.

In addition, in an embodiment of the present invention, the mth data line among these data lines is also coupled to the X+Y-n-m+1th pixel unit in the nth column, where m=1˜(X-Y), n= (Y-m+1)～Y, m and n are both positive integers.

The present invention further provides an active device array substrate, which includes a substrate, a pixel array, a plurality of scanning lines and a plurality of data lines. The pixel array is arranged on the substrate by a plurality of pixel units, including the opposite first side and the second side and the opposite third side and the fourth side, and the first side and the second side are both located on the third side and the third side between the four sides. The scan lines are arranged in the pixel array in parallel and at intervals. The data lines are arranged in the pixel array, and the scanning lines pass through the first side of the pixel array. Each data line extends alternately in the direction of the second side and the fourth side of the pixel array in the pixel array, so that a ladder shape is formed in the pixel array and arranged alternately with the scanning lines.

In an embodiment of the present invention, the pixel array includes a plurality of pixel columns and pixel rows arranged in parallel. The pixel units of each pixel row and the pixel units of each pixel column are arranged linearly and spaced apart from each other. The scan lines are parallel to the pixel rows, and each scan line is coupled to all pixel units in a pixel row.

In an embodiment of the invention, each data line is coupled to at least one pixel unit in a different pixel column.

In an embodiment of the present invention, all the pixel units coupled to the data lines are neither arranged in the same pixel row of the pixel array, nor arranged in the same pixel column of the pixel array.

In an embodiment of the present invention, each data line includes a plurality of first segments and a plurality of second segments. The first segments are parallel to the scan lines. The second segments are perpendicular to the scan lines, each second segment is connected between any two adjacent first segments, and is respectively located in different pixel rows.

In an embodiment of the present invention, the pixel array is arranged in an X×Y array, wherein X and Y are positive integers, and X>Y>1.

In an embodiment of the present invention, the number of these scan lines is the same as the number of data lines, both being X.

In an embodiment of the present invention, when each scan line activates all pixel units in a pixel row, only Y number of data lines respectively provide pixel unit data to all pixel units in the corresponding pixel row.

In an embodiment of the present invention, a total of (X-Y) data lines pass through the fourth side of the pixel array, and respectively extend from the outside of the pixel array to the second side of the pixel array.

In an embodiment of the present invention, these data lines (X-Y) in number pass through the second side of the pixel array, and alternately extend toward the first side and the third side in the pixel array, so that the pixel array Another ladder shape interlaced with these scan lines is formed inside.

In an embodiment of the present invention, the active device array substrate further includes at least one source driver chip and at least one gate driver chip. The source driver chip is located on one side of the substrate. The gate driver chip and the source driver chip are located on the same side of the substrate.

The invention further provides an active element array substrate. The active device array substrate includes a plurality of pixel units, a plurality of scanning lines and a plurality of data lines. The pixel units are arranged into a pixel array. Each scan line is coupled to the pixel units in the same row. The data lines are ladder-shaped and obliquely coupled to the pixel units. All pixel units coupled to each data line are not arranged in the same row of the pixel array, and all pixel units coupled to each data line are not arranged in the same column of the pixel array.

In an embodiment of the present invention, the pixel array is arranged in an X×Y array, wherein X>Y>1, and X and Y are positive integers.

In an embodiment of the present invention, a total of (X-Y) data lines protrude from one side of the pixel array and respectively extend to the other side of the pixel array, wherein the two sides are adjacent to each other.

The present invention further provides a display panel, which has the above-mentioned active device array substrate, which can reduce manufacturing cost and increase product portability.

Such a display panel includes the above-mentioned active element array substrate, an opposite substrate and a display medium. The display medium is disposed between the opposite substrate and the active element array substrate.

To sum up, since the active device array substrate of the present invention has a unique circuit design, the present invention can reduce the width of the frame, thereby improving space utilization. In addition, since the display panel of the present invention has the above-mentioned active device array substrate, the present invention can reduce manufacturing cost and increase product portability.

Description of drawings

In order to make the above and other objects, features, advantages and embodiments of the present invention more comprehensible, the detailed description of the accompanying drawings is as follows:

FIG. 1 is a schematic top view of a known active element array substrate;

2 is a schematic top view of the active element array substrate of the present invention;

3 is a schematic top view of a pixel array according to an embodiment of the present invention;

Figures 4a to 4d are schematic diagrams of the lower right direction of a certain data line in a 9x5 pixel array;

5a to 5d are schematic diagrams of the upper left direction of a certain data line in a 9x5 pixel array;

FIG. 6 is a schematic top view of a pixel array according to another embodiment of the present invention;

7a-7b are schematic diagrams of a single scanning line and its corresponding five data lines in a 9x5 pixel array;

FIG. 8 is a schematic diagram of a display panel according to an embodiment of the invention.

[Description of main component symbols]

100: display panel

200: opposite substrate

300: display media

400: active element array substrate

410: Substrate

420: Source driver chip

430: gate drive chip

440: pixel array

441: First side

442: second side

443: Third side

444: Fourth Side

450, 450a~450x: pixel unit

451: pixel column

452: pixel row

500, 501~502: scanning line

600, 600a~600f, 600A~600J, 601~606: data line

610: first paragraph

620: Second paragraph

A: display area

B: non-display area

Detailed ways

The following will clearly illustrate the spirit of the present invention with the accompanying drawings and detailed descriptions. After those skilled in the art understand the embodiments of the present invention, they can be changed and modified by the techniques taught in the present invention without departing from the present invention. spirit and scope.

The active device array substrate of the present invention includes a pixel array formed by a plurality of pixel units, a plurality of scanning lines and a plurality of data lines. The scan lines are coupled to the pixel units in the same row. The data lines are generally arranged in a ladder-like manner and are obliquely coupled to all the pixel units. In this way, due to the stepped line layout design on the active element array substrate of the present invention, the lines on the active element array substrate reduce the space occupied by the frame area of the active element array substrate, which helps to reduce the side width of the active element array substrate, or The space utilization ratio of the side of the substrate using the active element array is improved.

FIG. 2 is a schematic top view of the active device array substrate of the present invention. Please refer to FIG. 2 , an active device array substrate 400 includes a substrate 410, one or more source driver chips 420, one or more gate driver chips 430, a pixel array 440, and a plurality of scan lines 500 (scan line ) and multiple data lines 600 (source line or data line). The substrate 410 includes a display area A and a non-display area B adjacent to the display area A. The pixel array 440 is disposed on the substrate 410 , and the area where the pixel array 440 is located is defined as the above-mentioned display area A, while the non-display area B is the border area of the substrate 410 minus the display area A.

The pixel array 440 is formed by a plurality of pixel units 450 (or called sub-pixel units, sub pixels), and these pixel units 450 are, for example, red pixel units, blue pixel units and green pixel units. The pixel array 440 includes opposite first sides 441 and second sides 442 and opposite third sides 443 and fourth sides 444, the first side 441 and the second side 442 are located between the third side 443 and the fourth side 444 .

The source driver chip 420 is located in a frame area on one side of the substrate 410 . The gate driver chip 430 and the source driver chip 420 are located in the frame area on the same side of the substrate 410 . In this way, it is more helpful for the active device array substrate 400 of the present invention to achieve narrow frame characteristics, thereby improving space utilization. In addition, the source driver chip 420 and the gate driver chip 430 can also be integrated into a single body, however, the present invention is not limited to the above changes.

The number of scan lines 500 is less than or equal to the number of data lines 600 , and the scan lines 500 are arranged parallel to each other and spaced apart in the pixel array 440 . Specifically, the scan line 500 is connected to the gate driver chip 430, and passes through the first side 441 and the second side 442 of the pixel array 440, that is, the scan line 500 starts from the frame area on one side of the substrate 410 (that is, the non-display area) B) extending through the pixel array 440 to another border area of the substrate 410 (ie, the non-display area B).

The data lines 600 are arranged at intervals in the pixel array 440 , and all of them are inclined to couple most of the pixel units 450 in a roughly step-like direction toward the bottom right in the figure. Specifically, the data line 600 passes through the first side 441 of the pixel array 440, and after entering the pixel array 440, in the pixel array 440 alternately faces toward the second side 442 of the pixel array 440 and toward the fourth side of the pixel array 440. The direction of the side 444 extends, so that the data lines 600 form a first stepped route intersecting with the scan lines 500 in the pixel array 440 (such as the direction of the data lines 600c shown in FIG. 4c ).

More specifically, the pixel array 440 includes a plurality of pixel columns 451 and pixel rows 452 arranged in parallel. The pixel rows 452, as shown in FIG. 2 , are parallel to each other in the direction of up and down in the figure. The pixel rows 451, as shown in FIG. 3 , are parallel to each other along the left and right directions in the figure. The orientation of the pixel columns 451 is orthogonal to the orientation of the pixel rows 452 . The pixel units 450 in each pixel row 452 and the pixel units 450 in each pixel column 451 are linear and arranged at intervals. The scan lines 500 are parallel to the pixel rows 452 , and each scan line 500 is coupled to all the pixel units 450 in each pixel row 452 .

In addition, all the pixel units 450 coupled to each data line 600 are neither arranged in the same pixel row 452 of the pixel array 440 nor arranged in the same pixel column 451 of the pixel array 440 . In more detail, each data line 600 includes a plurality of first segments 610 and a plurality of second segments 620 . Each second segment 620 is directly connected between any two adjacent first segments 610 , and is respectively located in a different pixel row 452 , and is coupled to at least one pixel unit 450 in a different pixel row 452 . The first segment 610 extends toward the upper and lower directions in the figure, and is not limited to be parallel to or not parallel to the scan line 500 . The left and right directions in the second segment 620 are extended, and are not limited to being perpendicular to the scanning line 500 or not perpendicular to each other,

However, the present invention is not limited thereto, and each data line may also be coupled to more than two pixel units in different pixel columns, and/or more than two pixel units in different pixel rows.

In addition, it can be seen from FIG. 2 that part of the data lines 600 extend from the fourth side 444 of the pixel array 440 to the second side 442 of the pixel array 440 respectively, and respectively extend into the second side 442 of the pixel array 440. Behind the pixel array 440, it is convenient for the pixel array 440 to alternately extend toward the direction of the first side 441 and the direction of the third side 443, so that a second stepped route interlaced with the scanning lines 500 is formed in the pixel array 440 (as shown in FIG. 5d data line 600f direction). In this way, the rest of the pixel units 450 not located in the first stepped route can also be coupled to the data line 600 through the second stepped route, so there is no need to additionally configure a larger number of data lines, thereby helping to reduce manufacturing costs And the realization of the narrow frame edge feature of the active element array substrate.

FIG. 3 is a schematic top view of a pixel array according to an embodiment of the present invention. Referring to FIG. 3 , the coupling relationship between the above-mentioned first stepped route of the data line 600 and the pixel unit 450 is further mathematically described.

The aforementioned pixel array 440 is an X×Y array, where X and Y are both positive integers, and X>Y>1. Therefore, the number of pixel units 450 in each pixel column 451 is 1˜X, and the number is X, which is also consistent with the number of the scan lines 500 and the data lines 600 . The number of pixel units 450 in each pixel row 452 is 1˜Y, and the number is Y.

The data line 600 conforms to the first arrangement and is coupled to most of the pixel units 450 to form the above-mentioned first stepped route. The first arrangement is consistent with the i-th data line 600 being coupled to the i-j+1-th pixel unit 450 of the j-th column, i=1-X, i≧j, wherein when i≦Y, j =1~i, conversely, when i>Y, j=1~Y, both i and j are positive integers.

For example, FIGS. 4 a to 4 d are schematic diagrams of the bottom right direction of a certain data line in the 9×5 pixel array 440 .

As shown in FIG. 4a, when X=9, Y=5 as an example, and when the ith data line 600 is in the order from right to left, and the jth column of the pixel array 440 is in the order from top to bottom, The following provides several examples to explain the change of the direction of the data lines in the 9x5 pixel array 440 and the coupling relationship with the pixel units according to the above-mentioned first arrangement mode (the coupled pixel units are represented by dotted squares below):

As shown in FIG. 4a, when i=1, i≦5, j=1~1, so the first data line 600a is coupled to the (1-1+1=1)th pixel in the first column of the pixel array 440 Unit 450a (shown as dotted square);

As shown in FIG. 4b, when i=3, i≦5, j=1~3, so the third data line 600b is coupled to the (3-1+1=3)th pixel in the first column of the pixel array 440 Unit 450b (shown as a grid dot square), the (3-2+1=2)th pixel unit 450c of the second column (shown as a grid dot square) and the (3-3+1=1)th pixel unit 450c of the third column A pixel unit 450d (shown as a grid dot square);

As shown in FIG. 4c, when i=7, i>5, j=1~5, so the seventh data line 600c is coupled to the (7-1+1=7)th pixel in the first column of the pixel array 440 Unit 450e (as shown in the dot square), the (7-2+1=6)th pixel unit 450f in the second column (as shown in the dot square), the (7-3+1=5) in the third column pixel unit 450g (as shown in the grid dot square), the (7-4+1=4) pixel unit 450h in the 4th column (as shown in the grid dot square) and the (7-5+1=4)th pixel unit in the 5th column 3) Pixel units 450i (as shown by dotted squares).

As shown in FIG. 4d, when i=9 and i>5, j=1~5, so the ninth data line 600d is coupled to the (9-1+1=9)th of the first column of the pixel array 440 Pixel unit 450j (as shown in the grid dot square), the (9-2+1=8)th pixel unit 450k in the second column (as shown in the grid dot square), the (9-3+1=7)th pixel unit in the third column ) pixel unit 450l (as shown in the dot square), the (9-4+1=6) pixel unit 450m of the 4th row (as shown in the dot square) and the (9-5+1) of the 5th row = 5) pixel units 450n (shown as dotted squares).

In addition, referring to FIG. 3 , the number of the data lines 600 in the second stepped route and the coupling relationship between the data lines 600 and the pixel unit 450 in the second stepped route are also described mathematically.

In this embodiment, a total of (X−Y) data lines 600 extend from the pixel array 440 to the fourth side 444 of the pixel array 440 , and respectively extend from the pixel array 440 to the second side 442 of the pixel array 440 . These (X-Y) data lines 600 pass through the second side 442 of the pixel array 440, and alternately extend in the direction of the first side 441 and the third side 443 in the pixel array 440, so that a pixel array 440 forms a The above-mentioned second ladder-shaped route interlaced with the scan lines 500 .

After the above-mentioned data lines 600 extend into the pixel array 440 from the second side 442 of the pixel array 440 , these data lines 600 conform to the second arrangement and couple to the rest of the pixel units 450 to form the above-mentioned second stepped route. The second arrangement is consistent with the fact that the mth data line 600 of the data lines 600 is also coupled to the nth column of X+Y-n-m+1 pixel units 450, where m=1~(X-Y), n= (Y-m+1)～Y, m and n are both positive integers.

For the same example, FIGS. 5a to 5d are schematic diagrams showing the upper left direction of a certain data line 600 in the 9×5 pixel array 440 .

In the above example, as shown in Figure 5a, when X=9, Y=5, and when the mth data line 600 is in the order from right to left, and the nth column of the pixel array 440 is in the order from top to bottom, Then m=1～(9-5=4), the following provides several examples to explain the change of the direction of the data lines in the 9x5 pixel array according to the above-mentioned second arrangement mode and the coupling relationship with the pixel units (hereinafter represented by dotted squares coupled pixel units):

As shown in FIG. 5a, when m=1, n=(5-1+1=5)~5, the first data line 600a is also coupled to the fifth column (9+5-5-1) of the pixel array 440 +1=9) pixel unit 450o (as shown in the dot box);

As shown in Figure 5b, when m=2, n=(5-2+1=4)~5, then the second data line 600e is also coupled to the fifth column of the pixel array 440 (9+5-5-2 +1=8) pixel unit 450p (as shown in the dot square) and the 4th column (9+5-4-2+1=9) pixel unit 450q (as shown in the dot square);

As shown in FIG. 5c, when m=3, n=(5-3+1=3)~5, the third data line 600b is also coupled to the fifth column (9+5-3-2) of the pixel array 440 +1=7) pixel unit 450r (as shown in the grid dot square), the 4th column (9+5-4-3+1=8) pixel unit 450s (as shown in the grid dot square) and the 3rd column (9+5-3-3+1=9) pixel units 450t (as shown in dot squares);

As shown in FIG. 5d, when m=4, n=(5-4+1=2)~5, the fourth data line 600f is also coupled to the fifth column (9+5-5-4) of the pixel array 440 +1=6) pixel units 450u (as shown in dotted squares), the 4th column (9+5-4-4+1=7) pixel units 450v (as shown in dotted dots), the 3rd column (9+5-3-4+1=8) pixel units 450w (as shown in dot squares) and the second column (9+5-2-4+1=9) pixel units 450x (as dot squares shown).

FIG. 6 is a schematic top view of a pixel array 440 according to another embodiment of the present invention. Please refer to FIG. 6 , the order of the first to ninth pixel rows 452 in FIG. 6 is changed from left to right. Although the first step-like direction of the data line 600 in FIG. 6 is obliquely coupled to most of the pixel units 450 toward the lower left direction in the figure, the second step-like direction of the data line 600 is obliquely toward the upper right direction in the figure. The other pixel units 450 are ground-coupled. However, the direction of the data line 600 toward the lower left in FIG.

FIGS. 7 a - 7 b are schematic diagrams illustrating the operation of one scan line and its corresponding five data lines in a 9x5 pixel array, wherein activated pixel units are represented by dotted squares.

During operation, as shown in FIG. 7a, when driving the above-mentioned active device array substrate 400, a pixel unit turn-on voltage is first sequentially input to the scan lines, and then, when the pixel unit turn-on voltage is sequentially input to the scan lines, the pixel unit turn-on voltage is sequentially input to the scan lines. Data lines interleaved with these scan lines input pixel unit data.

For example, as shown in FIG. 7a, in the order from right to left, when the pixel unit turn-on voltage is input to the first scan line 501 to all the pixel units 450A~E in the first row of the pixel array 440, the first The ~5 data lines 601 ~ 605 respectively input pixel unit data to the first to fifth pixel units 450A~E in the first row of the pixel array 440 from top to bottom. That is, the first data line 601 inputs pixel unit data to the first pixel unit 450A (as shown by the dotted square) in the first row of the pixel array 440 from top to bottom, and the second data line 602 inputs the pixel unit data to the pixel array 440. The second pixel unit 450B in the order from top to bottom in the first row (as shown by the dotted square) inputs the pixel unit data, and the third data line 603 pairs with the third pixel unit 450B in the order from top to bottom in the first row of the pixel array 440 A pixel unit 450C (as shown in the dotted square) inputs the pixel unit data, and the fourth data line 604 inputs the fourth pixel unit 450D (as shown in the dotted square) from top to bottom in the first row of the pixel array 440. The pixel unit data and the fifth data line 605 input the pixel unit data to the fifth pixel unit 450E (as shown by the dotted square) in the first row of the pixel array 440 from top to bottom.

Referring to Fig. 7b, when the second scan line 502 inputs a pixel unit turn-on voltage to all pixel units 450F~J in the second row of pixel rows, the second to sixth data lines 602~606 respectively control the pixel array In line 440, pixel unit data is input to the first to fifth pixel units 450F~J in order from top to bottom. That is, the second data line 602 inputs the pixel unit data to the first pixel unit 450F (as shown by the dotted square) in the second row of the pixel array 440 from top to bottom, and the third data line 603 inputs the pixel unit data to the pixel array 440 The second pixel unit 450G from top to bottom in row 2 inputs pixel unit data, and the fourth data line 604 pairs with the third pixel unit from top to bottom in row 2 of pixel array 440. Each pixel unit 450H (shown as a dotted square) inputs pixel unit data, and the fifth data line 605 inputs the fourth pixel unit 450I (as shown by a dotted square) from top to bottom in the second row of the pixel array 440 One pixel unit data, and the sixth data line 606 inputs the pixel unit data to the fifth pixel unit 450J from top to bottom in the second row of the pixel array 440 (as shown by the dotted square).

Therefore, it can be deduced by analogy that if the above-mentioned pixel array 440 is an X×Y array, when X (for example, 9) scanning lines each activate all the pixel units in the corresponding pixel row, there are only Y ( For example, 5 data lines respectively provide pixel unit data to all pixel units in the corresponding pixel row, and it is not necessary to use all the data lines.

FIG. 8 is a schematic diagram of a display panel 100 according to an embodiment of the present invention. Please refer to FIG. 8 , the above-mentioned active device array substrate 400 can be further applied to a display panel 100 . The display panel 100 includes an opposite substrate 200 , a display medium 300 and the aforementioned active device array substrate 400 . The opposite substrate 200 is disposed above the active device array substrate 400 . The display medium 300 is disposed between the opposite substrate 200 and the active device array substrate 400 . The display panel 100 is, for example, a liquid crystal display panel, an electrophoretic display panel or other display panels. The opposite substrate 200 is, for example, a color filter substrate, and the display medium 300 is, for example, a liquid crystal layer or other materials. In this embodiment, the display panel 100 is, for example, a landscape viewing display panel, however, the present invention is not limited thereto.

To sum up, since the active device array substrate of the present invention has a unique circuit design, the present invention can reduce the width of the frame, thereby improving space utilization. In addition, since the display panel of the present invention has the above-mentioned active device array substrate, the present invention can reduce manufacturing cost and increase product portability.

The above embodiments disclosed in the present invention are not intended to limit the present invention. Any skilled person may make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection should be based on the scope defined by the appended claims.

Claims (12)

1. an active component array base board, is characterized in that, comprising:

One substrate;

One pel array, on this substrate, comprises the first relative side and the second side and relative the 3rd side and the 4th side by a plurality of pixel cell line up, and this first side and this second side are all between the 3rd side and the 4th side;

Multi-strip scanning line, parallel and compartment of terrain is disposed in this pel array; And

Many data lines, be disposed in this pel array, all pass through this first side of this pel array with described multi-strip scanning line, described in each, data line alternately extends towards this second side of this pel array and the direction of the 4th side in this pel array so that in this pel array, form one with interconnected stepped of described multi-strip scanning line;

The pixel column that this pel array comprises a plurality of configured in parallel and pixel column, described in each described a plurality of pixel cells of pixel column and described in each described a plurality of pixel cells of pixel column be all linearity and each interval and arrange, a plurality of pixel columns described in described multi-strip scanning line parallel, and described in each, sweep trace couples described a plurality of pixel column all pixel cells in one of them.

2. active component array base board according to claim 1, is characterized in that, described in each, data line couples at least one pixel cell in different pixels row.

3. active component array base board according to claim 2, is characterized in that, all pixel cells that described in each, data line couples are not all arranged in the same pixel column of this pel array, is not also arranged in the same pixel column of this pel array.

4. active component array base board according to claim 1, is characterized in that, described in each, data line comprises:

A plurality of first paragraphs, parallel described multi-strip scanning line; And

A plurality of second segments, vertical described multi-strip scanning line, described in each, second segment is connected between wantonly two adjacent described first paragraphs, and lays respectively in different pixel columns.

5. active component array base board according to claim 1, is characterized in that, this pel array is arranged according to one X * Y array way, and X, Y are positive integer, X > Y > 1.

6. active component array base board according to claim 5, is characterized in that, the quantity of described multi-strip scanning line is consistent with the quantity of data line, is all X.

7. active component array base board according to claim 5, it is characterized in that, when sweep trace described in each starts described a plurality of pixel columns in one of them during all pixel cells, only having quantity is that the described data line of Y provides respectively all pixel cells of pixel cell data to corresponding described a plurality of pixel columns.

8. active component array base board according to claim 5, is characterized in that, total quantity be that (X-Y) individual data line passes through the 4th side of this pel array, and this second side to this pel array from this pel array extension respectively.

9. active component array base board according to claim 8, it is characterized in that, described quantity is that (X-Y) individual data line is by this second side of this pel array, and alternately towards the direction of this first side and the 3rd side, extend, so that in this pel array, form interconnected stepped of another and described multi-strip scanning line in this pel array.

10. active component array base board according to claim 1, is characterized in that, also comprises:

At least one source driving chip, is positioned at a side of this substrate; And

At least one grid drive chip, is co-located at the homonymy of this substrate with this source driving chip.

11. 1 kinds of active component array base boards, is characterized in that, comprise:

A plurality of pixel cells, are arranged in a pel array;

Multi-strip scanning line, described in each, scanning linear all couples described a plurality of pixel cells of same a line; And

Many data lines, described many data lines are all stepped and oblique couples described a plurality of pixel cell, the all described pixel cell that described in each, data line couples is not all arranged in same a line of this pel array, and all described pixel cell that described in each, data line couples is not also arranged in the same row of this pel array;

This pel array is arranged according to the array way of one X * Y, X > Y > 1, and X, Y are positive integer;

Total quantity is stretched out from a side of this pel array for (X-Y) individual described data line, extends to respectively the opposite side of this pel array, and wherein this side is adjacent with this opposite side.

12. 1 kinds of display panels, is characterized in that, comprise:

Active component array base board just like claim 1～11 described in one of them;

One subtend substrate, is disposed at this active component array base board top; And

One display medium, is disposed between this subtend substrate and this active component array base board.