CN114038429B - Display panel, driving method and display device - Google Patents

Display panel, driving method and display device Download PDF

Info

Publication number
CN114038429B
CN114038429B CN202111406863.5A CN202111406863A CN114038429B CN 114038429 B CN114038429 B CN 114038429B CN 202111406863 A CN202111406863 A CN 202111406863A CN 114038429 B CN114038429 B CN 114038429B
Authority
CN
China
Prior art keywords
signal line
circuit
sub
electrically connected
transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN202111406863.5A
Other languages
Chinese (zh)
Other versions
CN114038429A (en
Inventor
王刚
张锴
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by BOE Technology Group Co Ltd, Chengdu BOE Optoelectronics Technology Co Ltd filed Critical BOE Technology Group Co Ltd
Priority to CN202111406863.5A priority Critical patent/CN114038429B/en
Publication of CN114038429A publication Critical patent/CN114038429A/en
Application granted granted Critical
Publication of CN114038429B publication Critical patent/CN114038429B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0247—Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0257—Reduction of after-image effects

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Control Of El Displays (AREA)

Abstract

The invention provides a display panel, a driving method and a display device, which are applied to the field of display and aim to solve the problems of short-term afterimage and flickering of a display picture of the display panel or the display device. The display panel includes a refresh phase and at least one hold phase within one scan period. The display panel includes: the array-arranged sub-pixels, a plurality of data lines and a plurality of conversion modules, wherein each data line is electrically connected with a row of sub-pixels; each conversion module is electrically connected with one data line. Each sub-pixel comprises a pixel circuit and a light emitting device which are electrically connected; the conversion module is configured to transmit a data signal to the data line during a refresh phase and to transmit a constant voltage signal to the data line during a hold phase.

Description

Display panel, driving method and display device
Technical Field
The present invention relates to the field of display technologies, and in particular, to a display panel, a driving method thereof, and a display device.
Background
Active-matrix organic light Emitting diodes (AMOLED) are increasingly used in the display field, and the quality requirements of the screen of the AMOLED display device are increasing. Due to some inherent quality defects, the AMOLED display device has problems of short-term image sticking, flickering and the like caused by pixel reaction delay.
In particular, in a display device driven at a low frequency, the above-described drawbacks are more remarkable, and thus a method capable of improving a pixel response delay and improving display quality is demanded.
Disclosure of Invention
In order to overcome the defects in the prior art, the invention provides a display panel, a driving method and a display device, so as to improve the phenomena of short-term image sticking and flickering of a picture of the display device.
In order to achieve the purpose, the invention adopts the following technical scheme:
in one aspect, a display panel is provided that includes a refresh phase and at least one hold phase within a single scan period of the display panel. The display panel includes: the array comprises a plurality of sub-pixels, a plurality of data lines and a plurality of conversion modules which are arranged in an array. Each data line is electrically connected with a column of sub-pixels; each conversion module is electrically connected with one data line. Each sub-pixel comprises a pixel circuit and a light emitting device which are electrically connected; the conversion module is configured to transmit a data signal to the data line during a refresh phase and to transmit a constant voltage signal to the data line during a hold phase.
The conversion module is arranged in the display panel, and can transmit constant voltage signals to the data lines in a holding stage, so that the constant voltage signals are transmitted to the pixel circuits of the sub-pixels, electrons or holes in the transistors generate bias states under the action of the data signals or other stresses, the constant voltage signals can bias the transistors of the pixel circuits, so that the electrons or holes in some transistors of different pixel circuits form uniform bias states, and the brightness difference caused by different bias states among different sub-pixels is eliminated, and the problems of residual shadows and flickering of the display panel are further improved.
In some embodiments, the display panel further includes: a plurality of source drive signal lines and constant voltage signal lines, the source drive signal lines configured to transmit data signals; the constant voltage signal line is configured to transmit a constant voltage signal; the conversion module is electrically connected with a source driving signal line and a constant voltage signal line.
In some embodiments, the conversion module includes a first switch electrically connected between the source drive signal line and the data line; the second switch is electrically connected between the constant voltage signal line and the data line.
In some embodiments, the first switch is configured to turn on the source driving signal line and the data line under control of the first switch signal;
the second switch is configured to turn on the constant voltage signal line and the data line under control of a second switching signal.
In some embodiments, the first switch and the second switch are thin film transistors.
In some embodiments, the display panel further comprises a first switch control bus and a second switch control bus. Wherein the first switch control bus is electrically connected with the first switch, the first switch control bus being configured to provide a first switch signal; the second switch control bus is electrically connected to the second switch, the second switch control bus configured to provide a second switch signal.
In some embodiments, the display panel includes a display area and a peripheral area disposed at least on one side of the display area; the plurality of conversion modules, the plurality of source driving signal lines, the constant voltage signal line, the first switch control bus and the second switch control bus are positioned in the peripheral area.
In some embodiments, the peripheral area includes a bending area and a first non-bending area, wherein the first non-bending area is located at a side of the bending area away from the display area, the first non-bending area can bend to a non-light emitting side of the display panel through the bending area, and the plurality of conversion modules are located at the first non-bending area.
In some embodiments, the pixel circuit includes: a reset sub-circuit, a write compensation sub-circuit, a light emission control sub-circuit, and a drive sub-circuit.
The reset sub-circuit is electrically connected with the first reset signal line, the initialization signal line and the driving sub-circuit, and is configured to input the initialization signal transmitted by the initialization signal line to the driving sub-circuit under the control of the first reset signal transmitted by the first reset signal line.
The reset sub-circuit is also electrically connected to the second reset signal line and the light emitting device, and is configured to input an initialization signal to the light emitting device under control of a second reset signal transmitted by the second reset signal line.
The write compensation sub-circuit is electrically connected with the first scanning signal line, the second scanning signal line, the data line and the driving sub-circuit, and is configured to write the signal transmitted by the data line into the driving sub-circuit under the control of the first scanning signal transmitted by the first scanning signal line and the second scanning signal transmitted by the second scanning signal line, and perform threshold voltage compensation on the driving sub-circuit.
The drive sub-circuit is configured to provide a drive current for the light emitting device under control of the light emission control sub-circuit and the write compensation sub-circuit.
The light-emitting control sub-circuit is electrically connected with the enabling signal line, the first voltage wiring, the driving sub-circuit and the light-emitting device, and is configured to conduct a current path between the first voltage wiring and the light-emitting device under the control of an enabling signal transmitted by the enabling signal line and transmit a driving current provided by the driving sub-circuit to the light-emitting device.
In some embodiments, the drive sub-circuit includes: a first transistor and a storage capacitor, the write compensation subcircuit comprising: a second transistor and a third transistor, the light emission control sub-circuit includes: a fourth transistor and a fifth transistor; the reset sub-circuit includes: a sixth transistor and a seventh transistor.
The control electrode of the first transistor is electrically connected with the first node, the first electrode of the first transistor is electrically connected with the second node, and the second electrode of the first transistor is electrically connected with the third node. The storage capacitor is electrically connected between the second node and the first voltage trace. The control electrode of the second transistor is electrically connected with the first scanning signal line, the first electrode of the second transistor is electrically connected with the data line, and the second electrode of the second transistor is electrically connected with the first node. The control electrode of the third transistor is electrically connected with the second scanning signal line, the first electrode of the third transistor is electrically connected with the second node, and the second electrode of the third transistor is electrically connected with the third node. The control electrode of the fourth transistor is electrically connected with the enabling signal line, the first electrode of the fourth transistor is electrically connected with the first voltage wiring, and the second electrode of the fourth transistor is electrically connected with the first node. The control electrode of the fifth transistor is electrically connected with the enable signal line, the first electrode of the fifth transistor is electrically connected with the third node, the second electrode of the fifth transistor is electrically connected with the fourth node, and the fourth node is electrically connected with the light emitting device. The control electrode of the sixth transistor is electrically connected to the first reset signal line, the first electrode of the sixth transistor is electrically connected to the initialization signal line, and the second electrode of the sixth transistor is electrically connected to the first node. The control electrode of the seventh transistor is electrically connected to the second reset signal line, the first electrode of the seventh transistor is electrically connected to the initialization signal line, and the second electrode of the seventh transistor is electrically connected to the fourth node.
In another aspect, there is provided a display device including the display panel of any one of the above aspects and a control chip electrically connected to the display panel, wherein the control chip is electrically connected to the constant voltage signal line, the first switch control bus and the second switch control bus, and the control chip is configured to provide electrical signals to the constant voltage signal line, the first switch control bus and the second switch control bus.
Under the action of the constant voltage signal, the display panel improves the inherent problems of residual shadow and flicker, and the display device adopting the display panel has corresponding beneficial effects.
In still another aspect, there is provided a driving method of a display panel including a refresh phase and a hold phase in one scan period, the driving method of the display panel including: in the refreshing stage, the conversion module transmits a data signal to the data line; in the hold phase, the conversion module transmits a constant voltage signal to the data line.
The driving manner of the display panel has the same beneficial effects as the display panel, and is not described herein.
In some embodiments, a driving method of a display panel includes: in the refresh stage, the first switch turns on a current path between the source driving signal line and the data line, and in the hold stage, the second switch turns on a current path between the constant voltage signal line and the data line.
In some embodiments, a driving method of a display panel includes: the hold phase includes a first phase and a second phase. In the hold phase, the first switch disconnects the path between the source drive signal line and the data line. In the first stage, the second switch turns on the constant voltage signal line and the data line, and for each pixel circuit, the light emission control sub-circuit turns off the current path between the first voltage line and the light emitting device under the control of the enable signal line. The reset sub-circuit disconnects a current path between the initialization signal line and the drive sub-circuit under control of the first reset signal line. The reset sub-circuit transmits an initialization signal to the light emitting device under control of the second reset signal line. The write compensation sub-circuit writes a constant voltage signal to a connection point of the driving sub-circuit and the light emission control sub-circuit under control of the first scanning signal line and the second scanning signal line. The light emitting device does not emit light.
In the second stage, the second switch disconnects the path between the constant voltage signal line and the data line. The write compensation sub-circuit disconnects a current path between the data line and the driven sub-circuit under control of the first scanning signal line and the second scanning signal line, and the light emission control sub-circuit turns on a current path between the first voltage line and the light emitting device under control of the enable signal line. The driving signal generated by the driving circuit is transmitted to the light emitting device; the light emitting device emits light.
Drawings
In order to more clearly illustrate the embodiments of the invention or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a plan view of a display panel according to some embodiments;
FIG. 2 is a schematic diagram of a sub-pixel and its circuit connection according to some embodiments;
FIG. 3 is a plan view of a display panel according to some embodiments of the present invention;
FIG. 4 is a block diagram of a conversion module and sub-pixels according to some embodiments of the present invention;
FIG. 5 is an enlarged view of the circuit connection of the conversion module of FIG. 4;
FIG. 6 is another block diagram of a conversion module and sub-pixels provided in some embodiments of the present invention;
FIG. 7 is a block diagram of a pixel circuit according to some embodiments of the present invention;
FIG. 8 is another block diagram of a pixel circuit according to some embodiments of the invention;
FIG. 9 is a plan view of a display device according to some embodiments of the present invention;
FIG. 10 is a block diagram illustrating an electrical connection between a conversion module and a driver chip according to some embodiments of the present invention;
FIG. 11 is a block diagram illustrating another embodiment of an electrical connection between a conversion module and a driver chip;
FIG. 12 is a timing diagram of a driving method according to some embodiments of the present invention;
FIG. 13 is a timing diagram of a driving method according to some embodiments of the present invention;
FIGS. 14 a-14 e are diagrams illustrating operation of a pixel circuit according to some embodiments of the invention during a scan cycle;
FIG. 15 is a timing diagram of a driving method according to some embodiments of the present invention;
FIG. 16 is a timing diagram of data/constant voltage signals according to some embodiments of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made more apparent and fully hereinafter with reference to the accompanying drawings, in which some, but not all embodiments of the invention are shown. All other embodiments obtained by a person skilled in the art based on the embodiments provided by the present invention fall within the scope of protection of the present invention.
Throughout the specification and claims, unless the context requires otherwise, the word "comprise" and its other forms such as the third person referring to the singular form "comprise" and the present word "comprising" are to be construed as open, inclusive meaning, i.e. as "comprising, but not limited to. In the description of the present specification, the terms "one embodiment", "some embodiments", "example embodiment", "example", "specific example", or "some examples" and the like are intended to indicate that a specific feature, structure, material, or characteristic related to the embodiment or example is included in at least one embodiment or example of the present invention. The schematic representations of the terms do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics may be combined in any suitable manner in any one or more embodiments or examples.
The terms "first" and "second" are used below for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the embodiments of the present invention, unless otherwise indicated, the meaning of "a plurality" is two or more.
In describing some embodiments, expressions of "coupled" and "connected" and their derivatives may be used. For example, the term "connected" may be used in describing some embodiments to indicate that two or more elements are in direct physical or electrical contact with each other. As another example, the term "coupled" may be used in describing some embodiments to indicate that two or more elements are in direct physical or electrical contact. However, the term "coupled" or "communicatively coupled (communicatively coupled)" may also mean that two or more elements are not in direct contact with each other, but yet still co-operate or interact with each other. The embodiments disclosed herein are not necessarily limited to the disclosure herein.
At least one of "A, B and C" has the same meaning as at least one of "A, B or C," both include the following combinations of A, B and C: a alone, B alone, C alone, a combination of a and B, a combination of a and C, a combination of B and C, and a combination of A, B and C.
"A and/or B" includes the following three combinations: only a, only B, and combinations of a and B.
The use of "adapted" or "configured to" herein is meant to be an open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.
In addition, the use of "based on" is intended to be open and inclusive in that a process, step, calculation, or other action "based on" one or more of the stated conditions or values may be based on additional conditions or beyond the stated values in practice.
Exemplary embodiments are described herein with reference to cross-sectional and/or plan views as idealized exemplary figures. In the drawings, the thickness of layers and regions are exaggerated for clarity. Thus, variations from the shape of the drawings due to, for example, manufacturing techniques and/or tolerances, are to be expected. Thus, the exemplary embodiments should not be construed as limited to the shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of example embodiments.
Some embodiments of the present invention provide a display panel 100, where the display panel 100 may be, for example, an OLED (Organic Light-Emitting Diode) display panel, a Micro-Organic Light-Emitting Diode (Micro Organic Light-Emitting Diode, micro OLED) display panel, a quantum dot Organic Light-Emitting Diode (Quantum Dot Light Emitting Diodes, QLED) display panel, a Mini Light-Emitting Diode (Mini LED) display panel, or a self-luminous display panel such as a Micro Light-Emitting Diode (Micro LED). The following description will take the display panel as an AMOLED display panel as an example.
As shown in fig. 1: the display panel 100 includes a display area 10a and a peripheral area 10b disposed at least on one side of the display area 10a, and the peripheral area 10b is illustratively disposed on one side of the display area 10a or the peripheral area 10b is disposed around a circumference of the display area 10 a.
The display panel 100 includes a plurality of data lines L, a plurality of gate lines, and a plurality of initialization signal lines Vint disposed in the display area 10 a. Wherein the plurality of gate lines include a plurality of scan signal lines G, a plurality of reset signal lines Rst, and a plurality of enable signal lines Em.
The display area 10a is further provided with a plurality of sub-pixels P arranged in an array, each data line L is electrically connected to a column of the sub-pixels P, and the data lines L are configured to transmit display signals. The display signal includes a data signal for controlling gray levels of the sub-pixels P, and the plurality of sub-pixels P arranged in an array form a display image on the display panel 100 at different gray levels under the control of the data signal. Illustratively, each scan signal line G is electrically connected to a row of subpixels P, the scan signal lines G being configured to transmit scan signals. Each reset signal line Rst is electrically connected to one row of the subpixels P, and the reset signal line Rst is configured to transmit a reset signal. Each of the enable signal lines Em is electrically connected to a row of the sub-pixels P, and the enable signal lines Em are configured to transmit an enable signal. Each of the initialization signal lines Vint is electrically connected to a row of the subpixels P, and the initialization signal lines Vint are configured to transmit an initialization signal.
The display panel 100 further includes a plurality of first voltage traces ELVdd and a plurality of second voltage traces ELVss as shown in fig. 2: the sub-pixel P includes a pixel circuit 1 and a light emitting device 2 electrically connected, and the pixel circuit 1 and the light emitting device 2 connected in series are electrically connected between a first voltage trace ELVdd and a second voltage trace ELVss. The signal lines are electrically connected to the pixel circuits 1 in the sub-pixels P, the pixel circuits 1 include driving transistors, the driving transistors receive the data signals transmitted by the data lines L, the driving transistors generate driving currents under the control of the data signals, the driving currents affect the light emitting brightness of the light emitting devices 2, and all the light emitting devices 2 form different light emitting brightness under the control of different data signals, that is, all the sub-pixels P generate different gray scales, so that all the sub-pixels P generate images on the display panel 100.
In the display process of the display panel 100, a plurality of sub-pixels P are scanned line by line, and each pixel circuit 1 receives a set of data signals provided by the data lines L electrically connected thereto, so that a picture is displayed under the control of the data signals, and when a plurality of sub-pixels P are scanned line by line again, each pixel circuit 1 receives a new set of data signals provided by the data lines L electrically connected thereto, a new picture is displayed, and thus the display picture is refreshed. The running period between the pixel circuit 1 receiving a set of data signals and a new set of data signals is one scanning period S of the pixel circuit 1. The display panel 100 displays one image or a plurality of images at different image refresh rates according to driving conditions. The image refresh rate is the frequency at which the data signal is written into each subpixel P, and can represent the number of display screen refreshes in one second, and the period of two adjacent display screen refreshes is referred to as one scanning period S of the display panel. In some embodiments, as shown in fig. 12, the scan period S is divided into a plurality of phases, and one scan period S of the display panel 100 includes an initial refresh phase E1 and at least one hold phase E2 located after the refresh phase E1, and the data signal is written into the corresponding pixel circuit 1 in the refresh phase E1.
In some embodiments, the thin film transistor of the pixel circuit 1 exhibits hysteresis when subjected to different stresses or biases, specifically because electrons or holes in the thin film transistor are in a biased state when subjected to stresses, and the electrons or holes cannot quickly return to the original state when the stresses are removed. For example: in the related art, in one scan period S, a data signal is written into the pixel circuit 1 in the refresh period E1, the voltage between the gate and the source or between the gate and the drain of the driving transistor causes the electrons or holes inside the driving transistor to be in a biased state, and in the hold period E2 after the refresh period E1, the data signal is not written into the pixel circuit 1 any more, so that the driving transistor is in a biased state until the refresh period E1 of the next scan period S, and a new data signal is input again. Since the drive transistor is biased for a long time, when a new data signal is written to the drive transistor, the characteristics of the drive transistor have changed, resulting in a failure of the drive transistor to recover quickly, and thus a delay of the drive transistor. This hysteresis causes a situation in which the picture of the display panel 100 is ghost and flickering. In particular, in the display panel 100 driven at a low frequency, the problem of picture sticking and flicker caused by such hysteresis is more serious.
Based on this, some embodiments of the present invention provide a display panel 100, a driving method thereof, and a display device 1000. The display panel 100 is further provided with a plurality of conversion modules 3, and the conversion modules 3 provide independent constant voltage signals for the pixel circuits 1 to bias the thin film transistors of the pixel circuits 1, so that the problems of residual shadows, flickering and the like caused by the hysteresis phenomenon of the thin film transistors are solved, and particularly in the display device 1000 driven by low frequency, the improvement effect is more obvious.
As shown in fig. 3, some embodiments provide a display panel 100 further comprising: a plurality of conversion modules 3, each data line L is electrically connected to a column of sub-pixels P; each conversion module 3 is electrically connected to one data line L. The conversion module 3 is configured to transmit a data signal to the data line L in the refresh stage E1 and to transmit a constant voltage signal to the data line L in the holding stage E2.
In the holding stage E2, the constant voltage signal is transmitted from the conversion module 3 to the pixel circuit 1, and the driving transistor of the pixel circuit 1 receives a new bias voltage, and the driving transistor forms a uniform bias under the action of the constant voltage signal, that is, electrons or holes in all the transistors receiving the constant voltage signal are in a uniform bias state. This uniform bias state is advantageous in eliminating display luminance differences of the sub-pixels P due to stress deviations caused by displaying different pictures. In particular, when the gray scale difference between the two displays before and after the sub-pixel P is large, for example: the gray scale of the sub-pixel P is from black to white, and electrons or holes are in a uniform bias state, so that the consistency of the characteristics of transistors during data writing is ensured, and the phenomena of slow response time and short-term afterimage of the first frame of the display panel 100 caused by hysteresis of the pixel circuit 1 are improved.
In the display panel 100, only by setting the conversion module 3 and controlling the conversion module to output corresponding signals to the data lines L at different stages, the data lines L transmit data signals or constant voltage signals to the pixel circuit 1, the conversion module 3 outputs signals sharing one data line L, so that the structure of the pixel circuit 1 and the arrangement and connection of a plurality of data lines L are not required to be changed while the bias stress of the thin film transistor of the pixel circuit 1 is realized, the complexity of the pixel circuit 1 is not increased, and no additional process and cost are generated for the preparation of the signal lines such as the pixel circuit 1 and the data lines L on the basis of the structure of the conventional display panel 100.
As shown in fig. 4 and 5: in some embodiments, the display panel 100 further includes a plurality of source driving signal lines 4 and constant voltage signal lines 5, the plurality of source driving signal lines 4 being configured to transmit data signals, and the constant voltage signal lines 5 being configured to transmit constant voltage signals. Each conversion module 3 is electrically connected to one source drive signal line 4 and one constant voltage signal line 5.
In some examples, the voltage of the constant voltage signal is greater than a voltage difference between a maximum voltage and a minimum voltage of the data signal. Illustratively, the constant voltage signal has a voltage of 2 to 10V, for example: the voltage of the constant voltage signal is 2V, 5V, or 10V.
The source drive signal line 4 and the constant voltage signal line 5 supply different signals to the pixel circuit 1, respectively, to isolate mutual interference between the two signals.
In some embodiments, each conversion module 3 comprises a first switch 31 and a second switch 32. The first switch 31 and the second switch 32 are thin film transistors, for example: the first switch 31 is electrically connected between the source driving signal line 4 and the data line L; the second switch 32 is electrically connected between the constant voltage signal line 5 and the data line L. By controlling the opening or closing of the first switch 31 and the second switch 32, the corresponding signal output can be realized.
In some embodiments, as shown in fig. 5: the display panel 100 further includes a first switch control bus 6 and a second switch control bus 7, the first switch control bus 6 is electrically connected to the first switch 31, the first switch control bus 6 is configured to provide a first switch signal, and under the control of the first switch signal, the first switch 31 turns on the source driving signal line 4 and the data line L, so that the source driving signal line 4 transmits the data signal to the data line L and further to the pixel circuit 1. The second switch control bus 7 is electrically connected to the second switch 32, and the second switch control bus 7 is configured to provide a second switch signal, and under the control of the second switch signal, the second switch 32 turns on the constant voltage signal line 5 and the data line L, so that the source drive signal line 4 transmits the constant voltage signal to the data line L and further to the pixel circuit 1.
The first switch 31 and the second switch 32 are both thin film transistors, and the first switch 31 and the second switch 32 are illustratively P-type transistors, or the first switch 31 is a P-type transistor, and the second switch 32 is an N-type transistor. For example: the first switch 31 and the second switch 32 are P-type transistors, the gate of the first switch 31 is electrically connected to the first switch control bus 6, the first pole of the first switch 31 is electrically connected to one source driving signal line 4, the second pole of the first switch 31 is electrically connected to one data line L, and when the first switch signal transmitted by the first switch control bus 6 is at a low level, the first switch 31 is turned on. The gate of the second switch 32 is electrically connected to the second switch control bus 7, the source of the second switch 32 is electrically connected to the constant voltage signal line 5, the drain of the second switch 32 is electrically connected to the one data line L, and the second switch 32 is turned on when the second switch signal transmitted from the second switch control bus 7 is at a low level. The circuit structure of the conversion module 3 transmits the data signal to the pixel circuit 1 through the first switch 31, and transmits the constant voltage signal to the pixel circuit 1 through the second switch 32, and controls the on and off of the first switch 31 and the second switch 32, so that the condition that the data signal and the constant voltage signal enter the pixel circuit 1 at the same time can be avoided, and the interference phenomenon generated between the signals is avoided as much as possible.
In some embodiments, as shown in fig. 4 and 6: the plurality of conversion modules 3, the plurality of source drive signal lines 4, the constant voltage signal line 5, the first switching control bus 6, and the second switching control bus 7 are located in the peripheral region 10b.
As shown in fig. 4: the conversion module 3, the plurality of source driving signal lines 4, the constant voltage signal line 5, the first switch control bus 6 and the second switch control bus 7 are arranged in the peripheral area 10b, far away from the display area 10a, the overall transmittance of the display area 10a is not affected, so that the normal operation of the optical identification device in the display area 10a is not affected, for example: the under-screen fingerprint recognition mounted on the display area 10a is not affected and is more advantageous for the display panel 100 to realize high pixel density (PPI).
In some examples, the substrate material of the display panel 100 includes glass, and the display panel 100 includes a display region 10a and a peripheral region 10b surrounding the display region 10 a. The plurality of conversion modules 3, the plurality of source drive signal lines 4, the constant voltage signal line 5, the first switching control bus 6, and the second switching control bus 7 are provided in the peripheral region 10b. For example: the plurality of conversion modules 3, the plurality of source driving signal lines 4, the constant voltage signal lines 5, the first switching control bus 6, and the second switching control bus 7 are all disposed in the peripheral region 10b on the same side of the display region 10 a. The peripheral area 10b on the other side of the display panel 100 does not need to add a new module or wiring, and the frame does not need to increase in size, which is beneficial to realizing a narrow frame.
In other examples, as shown in fig. 6: the peripheral area 10b includes a bending area b1 and a first non-bending area b2, the first non-bending area b2 is located at a side of the bending area b1 away from the display area 10a, the first non-bending area b2 can be bent to a non-light emitting side of the display panel 100 through the bending area b1, and the plurality of conversion modules 3 are located at the first non-bending area b2. In some examples, the substrate materials of the display panel 100 include: the first non-bending region b2 can be bent to the non-light emitting side of the display panel 100 through the bending region b1 by using a flexible material such as polyimide or saturated polyester, and the plurality of conversion modules 3, the plurality of source driving signal lines 4, the constant voltage signal lines 5, the first switch control bus 6 and the second switch control bus 7 are located in the first non-bending region b2. The conversion module 3 is disposed in the first non-bending area b2, and along with the bending of the bending area b1, the conversion module 3 is located on the non-light-emitting side of the display panel 100, so that the frame width of the side of the display panel 100, on which the bending area b1 is disposed, is not affected, and thus the whole display panel 100 can achieve the purpose of narrow frame.
In some embodiments, the scan signal line G further includes a first scan signal line G1 and a second scan signal line G2, the first scan signal line G1 configured to transmit a first scan signal, and the second scan signal line G2 configured to transmit a second scan signal; the reset signal line Rst includes a first reset signal line Rst1 configured to transmit a first reset signal and a second reset signal line Rst2 configured to transmit a second reset signal, the first reset signal line Rst1 being configured to transmit a first reset signal.
The following exemplary provides a structure of the pixel circuit 1, as shown in fig. 7: the pixel circuit 1 includes: a reset sub-circuit 11, a write compensation sub-circuit 12, a light emission control sub-circuit 13, and a drive sub-circuit 14.
The reset sub-circuit 11 is electrically connected to the first reset signal line Rst1, the initialization signal line Vint, and the driving sub-circuit 14, and the reset sub-circuit 11 is configured to input the initialization signal transmitted by the initialization signal line Vint to the driving sub-circuit 14 under the control of the first reset signal transmitted by the first reset signal line Rst 1.
The reset sub-circuit 11 is also electrically connected to the second reset signal line Rst2 and the light emitting device 2, the reset sub-circuit 11 being configured to input an initialization signal to the light emitting device 2 under control of a second reset signal transmitted by the second reset signal line Rst 2.
The write compensation sub-circuit 12 is electrically connected to the first scan signal line G1, the second scan signal line G2, the data line L, and the driving sub-circuit 14, and the write compensation sub-circuit 12 is configured to write the signal transmitted by the data line L into the driving sub-circuit 14 and perform threshold voltage compensation on the driving sub-circuit 14 under control of the first scan signal transmitted by the first scan signal line G1 and the second scan signal transmitted by the second scan signal line G2.
The driving sub-circuit 14 is configured to supply a driving current to the light emitting device 2 under the control of the light emission control sub-circuit 13 and the write compensation sub-circuit 12.
The light emission control sub-circuit 13 is electrically connected to the enable signal line Em, the first voltage trace ELVdd, the driving circuit 14, and the light emitting device 2, and the light emission control sub-circuit 13 is configured to conduct a current path between the first voltage trace ELVdd and the light emitting device 2 and transmit a driving current supplied from the driving sub-circuit 14 to the light emitting device 2 under control of the enable signal line Em.
The circuit structure of the conversion module 3 is suitable for the common pixel circuit 1, and can bias the node of the driving sub-circuit 14 connected with the data line L, so as to improve the problems of slow first frame response and ghost of the display panel 100. As in the circuit configuration of the pixel circuit 1 described above.
In some embodiments, a circuit structure of the pixel circuit 1 is also provided, as shown in fig. 8: the drive sub-circuit 14 includes: a first transistor T1 and a storage capacitor Cst, wherein the first transistor T1 is a driving transistor of the pixel circuit 1, and the compensation sub-circuit includes: the second transistor T2 and the third transistor T3, the light emission control sub-circuit 13 includes: the fourth transistor T4 and the fifth transistor T5, the reset sub-circuit 11 includes: a sixth transistor T6 and a seventh transistor T7.
The control electrode of the first transistor T1 is electrically connected to the first node N1, the first electrode of the first transistor T1 is electrically connected to the second node N2, and the second electrode of the first transistor T1 is electrically connected to the third node N3.
The storage capacitor Cst is electrically connected between the second node N2 and the first voltage trace ELVdd.
The control electrode of the second transistor T2 is electrically connected to the first scan signal line G1, the first electrode of the second transistor T2 is electrically connected to the data line L, and the second electrode of the second transistor T2 is electrically connected to the first node N1.
The control electrode of the third transistor T3 is electrically connected to the second scan signal line G2, the first electrode of the third transistor T3 is electrically connected to the second node N2, and the second electrode of the third transistor T3 is electrically connected to the third node N3.
The control electrode of the fourth transistor T4 is electrically connected to the enable signal line Em, the first electrode of the fourth transistor T4 is electrically connected to the first voltage trace ELVdd, and the second electrode of the fourth transistor T4 is electrically connected to the first node N1.
The control electrode of the fifth transistor T5 is electrically connected to the enable signal line Em, the first electrode of the fifth transistor T5 is electrically connected to the third node N3, the second electrode of the fifth transistor T5 is electrically connected to the fourth node N4, and the fourth node N4 is electrically connected to the light emitting device 2.
The control electrode of the sixth transistor T6 is electrically connected to the first reset signal line Rst1, the first electrode of the sixth transistor T6 is electrically connected to the initialization signal line Vint, and the second electrode of the sixth transistor T6 is electrically connected to the first node N1.
The control electrode of the seventh transistor T7 is electrically connected to the second reset signal line Rst2, the first electrode of the seventh transistor T7 is electrically connected to the initialization signal line Vint, and the second electrode of the seventh transistor T7 is electrically connected to the fourth node N4.
In some examples, the first transistor T1 is a P-type transistor, the second transistor T2 is a P-type transistor, the third transistor T3 is an N-type transistor, the fourth transistor T4 and the fifth transistor T5 are P-type transistors, the sixth transistor T6 is an N-type transistor and the seventh transistor T7 is a P-type transistor.
In some embodiments, in the case where the first switch 31 and the second switch 31 are thin film transistors, the first switch 31 and the second switch 32 may be located in the same layer as the transistors in the pixel circuit 1 and formed by the same process, thereby simplifying the manufacturing process of the display panel 100.
As shown in fig. 9, 10 and 11: the embodiment of the invention also provides a display device 1000, where the display device 1000 includes the display panel 100 and a control chip 200 electrically connected to the display panel 100, the control chip 200 is electrically connected to the constant voltage signal line 5, the first switch control bus 6 and the second switch control bus 7, and the control chip 200 is configured to provide a constant voltage signal to the constant voltage signal line 5, provide a first switch signal to the first switch control bus 6, and provide a second switch signal to the second switch control bus 7.
The display device 1000 has the same effects as the display panel 100 described above, namely: the pixel circuit 1 of the sub-pixel P is subjected to bias stress, and when refreshing the next frame of picture, the data signal writing provides a balanced, stable and single bias state of the pixel circuit 1, so that the problems of picture afterimage, flicker and slow response time of the first frame are solved.
The display device 1000 also has the advantages of a narrow frame and high overall transmittance of the pixel circuit 1 layout of the display area 10 a.
In addition, the pixel circuit 1 of the display device 1000 has the advantages of simple layout design, mature and reliable processing scheme, and high yield and low cost of the display device 1000.
In some examples, as shown in fig. 10: the display device 1000 further includes a source driving chip electrically connected to the plurality of source driving signal lines 4, the source driving chip configured to supply data signals to the source driving signal lines 4.
In other examples, as shown in fig. 11: the control chip 200 integrates a source driving module 201 and a control module 202. Wherein the source driving module 201 is configured to supply a data signal to the source driving signal line 4; the control module 202 is configured to provide a constant voltage signal to the constant voltage signal line 5, a first switching signal to the first switching control bus 6, and a second switching signal to the second switching control bus 7.
The embodiment of the invention also provides a driving method of the display panel 100, as shown in fig. 12: the display process of the display panel 100 includes a plurality of scan periods S, each including a refresh stage E1 and at least one hold stage E2. During the display process, each sub-pixel P of the display panel 100 includes a refresh stage E1 and at least one hold stage E2 located after the refresh stage E1 in one scan period S. The refresh stage E1 of the pixel circuit 1 is included in the refresh stage E1 of the display panel 100, and the hold stage E2 of the pixel circuit 1 is included in the hold stage E2 of the display panel 100.
The driving method of the display panel 100 includes: in the refresh phase E1, the conversion module 3 transmits a data signal to the data line L. In the hold phase E2, the conversion module 3 transmits a constant voltage signal to the data line L.
In combination with the timing signal diagrams shown in fig. 12 and 13, and the conversion module 3 shown in fig. 5 and the pixel circuit 1 shown in fig. 8, the driving method of the display panel 100 includes: during the refresh period E1, the second switching signal is at a high level, and the second switch 32 disconnects the current paths of the constant voltage signal line 5 and the data line L under the control of the second switching signal; the first switch signal is at a low level, and the first switch 31 turns on the current paths of the source driving signal line 4 and the data line L under the control of the first switch signal, so that the first switch 31 transmits the data signal supplied from the source driving signal line 4 to the data line L.
The refresh stage E1 for each pixel circuit 1 includes an initialization stage E11, a data signal writing stage E12, and a light emitting stage E13.
In the initialization stage E11, the reset sub-circuit 11 writes the initialization signal transmitted by the initialization signal line Vint into the driving sub-circuit 14 under the control of the first reset signal line Rst 1; the reset sub-circuit 11 disconnects the current paths of the initialization signal line Vint and the light emitting device 2 under the control of the second reset signal line Rst 2. The light emission control sub-circuit 13 opens a current path between the first voltage trace ELVdd and the light emitting device 2 under the control of the enable signal line Em. The write compensation sub-circuit 12 opens a current path between the data line L and the driving sub-circuit 14 under the control of the first scanning signal line G1 and the second scanning signal line G2.
In the data signal writing stage E12, the reset sub-circuit 11 disconnects the current paths of the initialization signal line Vint and the driving sub-circuit 14 under the control of the first reset signal line Rst 1; the reset sub-circuit 11 disconnects the current paths of the initialization signal line Vint and the light emitting device 2 under the control of the second reset signal line Rst 2. The write compensation sub-circuit 12 is turned on under the control of the first scan signal line G1 and the second scan signal line G2, turns on a current path between the data line L and the driving sub-circuit 14, writes a data signal into the driving sub-circuit 14, and performs threshold voltage compensation on the driving sub-circuit 14.
In the light emission stage E13, the write compensation sub-circuit 12 breaks the current path between the data line L and the driving sub-circuit 14 under the control of the first scanning signal line G1 and the second scanning signal line G2. The light emission control sub-circuit 13 is turned on under control of the enable signal line Em, and conducts a current path between the first voltage wiring ELVdd and the light emitting device 2, and transmits a driving current supplied from the driving sub-circuit 14 to the light emitting device 2, so that the light emitting device 2 emits light.
It should be noted that: in some examples, in the data signal writing stage E12, the reset sub-circuit 11 turns on a current path between the initialization signal line Vint and the light emitting device 2 under the control of the second reset signal, and the initialization signal supplied from the initialization signal line Vint is transmitted to the light emitting device 2.
In the hold phase E2, the first switch 31 disconnects the source drive signal line 4 from the data line L. The conversion module 3 transmits a constant voltage signal to the data line L. As shown in fig. 13: the hold phase E2 comprises: a first holding phase E21 and a second holding phase E22.
In the first stage E21, the second switch 32 turns on the constant voltage signal line 5 and the data line L, and the data line L transmits the constant voltage signal to the pixel circuit 1. The light emission control sub-circuit 13 disconnects the current path between the first voltage trace ELVdd and the light emitting device 2 under the control of the enable signal line Em. The reset sub-circuit 11 disconnects the current path between the initialization signal line Vint and the driving sub-circuit 14 under the control of the first reset signal line Rst 1. The reset sub-circuit 11 is turned on under the control of the second reset signal line Rst2, and transmits an initialization signal to the light emitting device 2. The write compensation sub-circuit 12 is turned on under the control of the first scanning signal line G1 and the second scanning signal line G2, and writes a constant voltage signal to a connection point of the driving sub-circuit 14 and the light emission control sub-circuit 13; the light emitting device 2 does not emit light.
In the second stage E22, the second switch 32 disconnects the constant voltage signal line 5 from the data line L. The write compensation sub-circuit 12 breaks the current path between the data line L and the driving sub-circuit 14 under the control of the first scanning signal line G1 and the second scanning signal line G2. The light emission control sub-circuit 13 conducts a current path between the first voltage trace ELVdd and the light emitting device 2 under control of the enable signal line Em, and transmits a driving current supplied from the driving sub-circuit to the light emitting device 2, and the light emitting device 2 emits light.
In some examples, a driving method of the display panel is exemplarily described with reference to the pixel circuit 1 shown in fig. 9 in combination with the timing signal diagram shown in fig. 12, taking the refresh rate of the display panel 100 as an example of 1 Hz. The display panel 100 is refreshed once in a second. As shown in fig. 12, the pixel circuit 1 includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7, and the pixel circuit 1 operates as follows: the 1 second is divided into 60 Frame periods Frame, with one scan period S within 1 second, the 60 Frame periods Frame including an initial 1 refresh stage E1 and 59 hold stages E2 located after the refresh stage E1.
The refresh stage E1 includes: an initialization stage E11, a data signal writing stage E12, and a light emitting stage E13. In the entire refresh period E1, the first switch 31 turns on the current path between the source drive signal line 4 and the data line L under the control of the first switch signal, and the data signal is transmitted to the pixel circuit 1 through the data line L.
As shown in fig. 14 a: in the initialization stage E11, the sixth transistor T6 is turned on under the control of the first reset signal transmitted by the first reset signal line Rst1, and the first node N1 inputs the initialization signal transmitted by the initialization signal line Vint to the first node N1. The seventh transistor T7 is turned off under the control of the second reset signal transmitted by the second reset signal line Rst2, and disconnects the current path between the initialization signal line Vint and the light emitting device 2. The fourth transistor T4 and the fifth transistor T5 are turned off under the control of the enable signal transmitted by the enable signal line Em, interrupting the current path between the first voltage trace ELVdd and the light emitting device 2. The second transistor T2 is turned off under the control of the first scan signal transmitted by the first scan signal line G1, interrupting a current path between the data line L and the second node N2. The third transistor T3 is turned off under control of the second scan signal transmitted by the second scan signal line G2, interrupting a current path between the first node N1 and the third node N3.
As shown in fig. 14 b: in the data signal writing stage E12, the sixth transistor T6 is turned off under the control of the first reset signal transmitted by the first reset signal line Rst 1. The seventh transistor T7 is turned on under the control of the second reset signal transmitted from the second reset signal line Rst2, turns on a current path between the initialization signal line Vint and the light emitting device 2, and transmits an initialization signal to the light emitting device 2. The second transistor T2 is turned on under the control of the first scan signal transmitted by the first scan signal line G1, the third transistor T3 is turned on under the control of the second scan signal transmitted by the second scan signal line G2, the data signal transmitted by the data line L is transmitted to the first node N1, the third transistor T3 electrically connects the control electrode and the second electrode of the first transistor T1, the threshold voltage of the first transistor T1 is written into the first node N1, the first transistor T1 is turned off when the voltage of the first node N1 is the sum of the voltage of the data signal and the threshold voltage of the first transistor, and the storage capacitor Cst stores and maintains the voltage of the first node N1.
As shown in fig. 14 c: in the light emitting stage E13, the seventh transistor T7 is turned off under the control of the second reset signal transmitted by the second reset signal line Rst2, the second transistor T2 is turned off under the control of the first scan signal transmitted by the first scan signal line G1, and the third transistor T3 is turned off under the control of the second scan signal transmitted by the second scan signal line G2. The fourth transistor T4 and the fifth transistor T5 are turned on under the control of an enable signal transmitted from the enable signal line Em, a current path between the first voltage trace ELVdd and the light emitting device 2 is turned on, the first transistor T1 is turned on under the control of the voltages of the first voltage trace ELVdd and the first node N1, a driving current is generated, and the driving current is transmitted to the light emitting device, and the light emitting device 2 emits light.
The hold phase E2 comprises: during the first and second phases, the first switch 31 opens the current path between the source driving signal line 4 and the data line L under the control of the first switch control signal throughout the holding phase E2.
As shown in fig. 14 d: in the first stage E21, the second switch 32 turns on the current path between the constant voltage signal line 5 and the data line L under the control of the second switch signal, and the data line L transmits the constant voltage signal. The fourth transistor T4 and the fifth transistor T5 are turned off under the control of the enable signal transmitted by the enable signal line Em, interrupting the current path between the first voltage trace ELVdd and the light emitting device 2. The second transistor T2 is turned on under the control of the first scan signal transmitted from the first scan signal line G1, and turns on a current path between the data line L and the second node N2, and transmits a constant voltage signal to the second node N2. The first node N1 voltage maintains the sum of the data signal voltage and the threshold voltage of the first transistor T1, and the second node N2 voltage is the voltage of the constant voltage signal. The seventh transistor T7 is turned on under the control of the second reset signal line Rst2, and a current path between the initialization signal line Vint and the light emitting device 2 is turned on to transmit an initialization signal to the light emitting device.
As shown in fig. 14 e: in the second stage E22, the second switch 32 is turned off under the control of the second switching signal, and the current path between the constant voltage signal line 5 and the data line L is disconnected. The fourth transistor T4 and the fifth transistor T5 are turned on under control of an enable signal transmitted by the enable signal line Em. Meanwhile, the second transistor T2 is turned off under the control of the first scan signal transmitted by the first scan signal line G1, and the current path between the data line L and the second node N2 is disconnected, and the first node N1 voltage maintains the sum of the data signal voltage and the threshold voltage of the first transistor T1. The first transistor T1 is turned on under the control of the first voltage trace ELVdd and the voltage of the first node N1 to generate a driving current, and the turned-on fourth and fifth transistors T4 and T5 transmit the driving current to the light emitting device 2, and the light emitting device 2 emits light. The seventh transistor T7 is turned off under the control of the second reset signal transmitted by the second reset signal line Rst 2.
In some examples, taking the refresh rate of the display panel 100 as 2Hz and the highest compatible 60Hz as an example, the pictures of the display panel 100 are refreshed twice within one second, divided into 60 Frame periods frames within one second. As shown in fig. 15: the operation of the pixel circuit 1 shown in fig. 8 is as follows: the method comprises the steps that 1 second is divided into 60 Frame periods, two scanning periods S are arranged in 1 second, a first scanning period S1 is located in a first Frame period to a thirty-th Frame period, and the first Frame period to the thirty-th Frame period comprise an initial refreshing stage E1 and a twenty-ninth holding stage E2 located after the refreshing stage E1; the second scan period S2 is located within thirty-first to sixtieth frame periods including an initial one refresh period E1 and twenty-nine hold periods E2 located after the refresh period E1. The driving process of the display panel 100 in each scan period S is as described above, and will not be described here. In addition, the pixel circuit 1 may have 3 scan periods S, 30 scan periods S, 60 scan periods S, or 120 scan periods S depending on the highest refresh frequency compatible within 1 second.
In some embodiments, the voltage of the constant voltage signal for different holding phases E2 may be different. For example, the voltage of the constant voltage signal of at least one holding stage E2 located after the refresh stage E1 is greater than the voltage of the constant voltage signal of the other holding stages E2. The voltage of the constant voltage signal of at least one holding stage E2 located before the refresh stage E1 is smaller than the voltage of the constant voltage signal of the other holding stages E2. And the voltage of the constant voltage signal of the holding phases E2 between the adjacent two refresh phases E1 is in a decreasing state. Illustratively, as shown in fig. 16: there is one scan period S within 1 second. In one scan period S, the voltage of the constant voltage signal of the first holding stage E2 after the refresh stage E1 is greater than the voltage of the other constant voltage signals in the scan period S. In one scan period S, the voltage of the constant voltage signal at the last holding stage E2 is smaller than the voltages of the other constant voltage signals in the scan period S. For example: in one scan period S, the voltage of the constant voltage signal of the first holding stage E2 after the refresh stage E1 may be 6V, 8V, or 10V; the voltage of the constant voltage signal at the last holding stage E2 may be 2V, 4V or 5V; the voltage of the constant voltage signal of the plurality of holding stages E2 between the first holding stage E2 and the last holding stage E2 may be 4V, 6V, or 8V. Through the arrangement, the required voltage can be dynamically adjusted according to the needs, the display effect is further improved, and the power consumption is saved.
In the refresh stage E1, the characteristic of the first transistor T1 changes during the writing of the data signal into the driving sub-circuit 14, especially when the gray scale difference between two adjacent frames of the sub-pixel P is larger, the characteristic of the first transistor T1 changes more differently. In the first stage, the constant voltage signal is supplied to the first pole of the first transistor T1 at a logic high voltage to counteract the differential characteristic variation generated by the transistors during the refresh stage E1, so as to ensure the bias uniformity of the transistors, i.e. the transistors of the sub-pixels P have better uniformity, thereby improving the problem of poor display caused by hysteresis, for example: the problems of slow first frame response time and short-term ghost.
In addition, in some embodiments, during the holding period E2 (e.g., the first period E21), the level of the second scan signal transmitted by the second scan signal line G2 may be set to the on level of the third transistor T3, and the third transistor T3 is turned on under the control of the second scan signal transmitted by the second scan signal line G2, and at this time, the second transistor T2 is also turned on, so that the current path between the data line L and the second node N2 and the first node N1 is turned on, and the constant voltage signal is transmitted to the second node N2 and then to the first node N1. Thus, the constant voltage signal can compensate the voltage loss caused by the leakage of the first node N1 when the light emitting device 2 emits light, so that the voltage of the first node N1 is maintained, that is, the voltage of the first node N1 is compensated in a manner of directly compensating the data signal (the constant voltage signal acts as the data signal at this time), and the voltage value of the constant voltage signal is approximately equal to the voltage loss value of the first node N1, which achieves better brightness uniformity of the sub-pixel P and improves the low-frequency flicker phenomenon.
The foregoing is merely illustrative of the present invention, and the present invention is not limited thereto, and any changes or substitutions easily contemplated by those skilled in the art within the scope of the present invention should be included in the scope of the present invention. Therefore, the protection scope of the invention is subject to the protection scope of the claims.

Claims (13)

1. A display panel, wherein a scan cycle of the display panel includes a refresh phase and a plurality of hold phases; the display panel includes:
a plurality of sub-pixels arranged in an array, each sub-pixel including a pixel circuit and a light emitting device electrically connected;
a plurality of data lines, each data line being electrically connected to a column of sub-pixels;
a plurality of conversion modules, each conversion module being electrically connected to one data line, the conversion modules being configured to transmit data signals to the data line during the refresh phase and to transmit constant voltage signals to the data line during the hold phase;
the display panel comprises a display area and a peripheral area which is at least arranged at one side of the display area;
the peripheral area comprises a bending area and a first non-bending area, the first non-bending area is positioned at one side of the bending area away from the display area, the first non-bending area can be bent to the non-light-emitting side of the display panel through the bending area, and the plurality of conversion modules are positioned at the first non-bending area;
The voltages of the constant voltage signals of the different holding stages are different.
2. The display panel of claim 1, further comprising:
a plurality of source driving signal lines configured to transmit data signals;
a constant voltage signal line configured to transmit a constant voltage signal;
the conversion module is electrically connected with a source driving signal line and the constant voltage signal line.
3. The display panel of claim 2, wherein the conversion module includes a first switch and a second switch, the first switch being electrically connected between the source driving signal line and the data line; the second switch is electrically connected between the constant voltage signal line and the data line.
4. The display panel according to claim 3, wherein,
the first switch is configured to turn on the source driving signal line and the data line under control of a first switching signal;
the second switch is configured to turn on the constant voltage signal line and the data line under control of a second switching signal.
5. The display panel of claim 4, wherein the first switch and the second switch are thin film transistors.
6. The display panel of claim 4, further comprising a first switch control bus and a second switch control bus, the first switch control bus electrically connected to the first switch, the first switch control bus configured to provide the first switch signal; the second switch control bus is electrically connected to the second switch, the second switch control bus configured to provide the second switch signal.
7. The display panel of claim 6, wherein the display panel comprises,
the plurality of conversion modules, the plurality of source drive signal lines, the constant voltage signal line, the first switch control bus and the second switch control bus are located in the peripheral region.
8. The display panel according to any one of claims 1 to 7, wherein the pixel circuit includes: a reset sub-circuit, a write compensation sub-circuit, a light emission control sub-circuit, and a drive sub-circuit;
the reset sub-circuit is electrically connected with a first reset signal line, an initialization signal line and the driving sub-circuit, and is configured to input an initialization signal transmitted by the initialization signal line to the driving sub-circuit under the control of a first reset signal transmitted by the first reset signal line;
The reset sub-circuit is further electrically connected with a second reset signal line and the light emitting device, and is configured to input the initialization signal to the light emitting device under the control of a second reset signal transmitted by the second reset signal line;
the write compensation sub-circuit is electrically connected with the first scanning signal line, the second scanning signal line, the data line and the driving sub-circuit, and is configured to write the data signal transmitted by the data line into the driving sub-circuit and perform threshold voltage compensation on the driving sub-circuit under the control of the first scanning signal transmitted by the first scanning signal line and the second scanning signal transmitted by the second scanning signal line;
the driving sub-circuit is configured to supply a driving current to the light emitting device under the control of the light emission control sub-circuit and the write compensation sub-circuit;
the light emitting control sub-circuit is electrically connected with the enable signal line, the first voltage wiring, the driving sub-circuit and the light emitting device, and is configured to conduct a current path between the first voltage wiring and the light emitting device and transmit a driving current provided by the driving sub-circuit to the light emitting device under the control of an enable signal transmitted by the enable signal line.
9. The display panel of claim 8, wherein the display panel comprises,
the driving sub-circuit includes: a first transistor and a storage capacitor, the write compensation subcircuit comprising: a second transistor and a third transistor, the light emission control sub-circuit including: a fourth transistor and a fifth transistor; the reset sub-circuit includes: a sixth transistor and a seventh transistor;
the control electrode of the first transistor is electrically connected with a first node, the first electrode of the first transistor is electrically connected with a second node, and the second electrode of the first transistor is electrically connected with a third node;
the storage capacitor is electrically connected between the first node and the first voltage trace;
the control electrode of the second transistor is electrically connected with the first scanning signal line, the first electrode of the second transistor is electrically connected with the data line, and the second electrode of the second transistor is electrically connected with the second node;
a control electrode of the third transistor is electrically connected to the second scan signal line, a first electrode of the third transistor is electrically connected to the first node, and a second electrode of the third transistor is electrically connected to the third node;
the control electrode of the fourth transistor is electrically connected with the enabling signal line, the first electrode of the fourth transistor is electrically connected with the first voltage wiring, and the second electrode of the fourth transistor is electrically connected with the second node;
A control electrode of the fifth transistor is electrically connected with the enable signal line, a first electrode of the fifth transistor is electrically connected with the third node, a second electrode of the fifth transistor is electrically connected with a fourth node, and the fourth node is electrically connected with the light emitting device;
a control electrode of the sixth transistor is electrically connected to the first reset signal line, a first electrode of the sixth transistor is electrically connected to the initialization signal line, and a second electrode of the sixth transistor is electrically connected to the first node;
the control electrode of the seventh transistor is electrically connected with the second reset signal line, the first electrode of the seventh transistor is electrically connected with the initialization signal line, and the second electrode of the seventh transistor is electrically connected with the fourth node.
10. A display device, comprising:
the display panel of any one of the preceding claims 1 to 9; the display panel includes: a constant voltage signal line, a first switch control bus and a second switch control bus;
and the control chip is electrically connected with the constant voltage signal line, the first switch control bus and the second switch control bus, and is configured to provide electric signals for the constant voltage signal line, the first switch control bus and the second switch control bus.
11. A driving method of a display panel, wherein the display panel includes a refresh stage and a plurality of hold stages in one scan period, the display panel comprising:
a plurality of sub-pixels arranged in an array, each sub-pixel including a pixel circuit and a light emitting device electrically connected;
a plurality of data lines, each data line being electrically connected to a column of sub-pixels;
a plurality of conversion modules, each conversion module being electrically connected to one of the data lines;
the driving method of the display panel comprises the following steps:
in the refreshing stage, the conversion module transmits a data signal to the data line;
in the holding stage, the conversion module transmits a constant voltage signal to the data line;
the voltages of the constant voltage signals of the different holding stages are different.
12. The driving method of a display panel according to claim 11, wherein the display panel further comprises:
a plurality of source driving signal lines configured to transmit data signals;
a constant voltage signal line configured to transmit a constant voltage electric signal;
the conversion module is electrically connected with a source driving signal line and the constant voltage signal line, and comprises:
a first switch and a second switch, the first switch being electrically connected between the source driving signal line and the data line; the second switch is electrically connected between the constant voltage signal line and the data line;
The driving method of the display panel comprises the following steps: the first switch turns on the source driving signal line and the data line in the refresh stage, and the second switch turns on the constant voltage signal line and the data line in the hold stage.
13. The method of driving a display panel according to claim 12, wherein,
the pixel circuit includes: a reset sub-circuit, a write compensation sub-circuit, a light emission control sub-circuit, and a drive sub-circuit;
the reset sub-circuit is electrically connected with a first reset signal line, an initialization signal line and the driving sub-circuit, and is configured to input an initialization signal transmitted by the initialization signal line to the driving sub-circuit under the control of a first reset signal transmitted by the first reset signal line;
the reset sub-circuit is electrically connected with a second reset signal line, the initialization signal line and the light emitting device, and is configured to input the initialization signal to the light emitting device under the control of a second reset signal transmitted by the second reset signal line;
the write compensation sub-circuit is electrically connected with the first scanning signal line, the second scanning signal line, the data line and the driving sub-circuit, and is configured to write the signal transmitted by the data line into the driving sub-circuit and perform threshold voltage compensation on the driving sub-circuit under the control of the first scanning signal transmitted by the first scanning signal line and the second scanning signal transmitted by the second scanning signal line;
The driving sub-circuit is configured to provide a driving current for the light emitting device under the control of the light emission control sub-circuit and the write compensation sub-circuit;
the light-emitting control sub-circuit is electrically connected with the enabling signal line, the first voltage wiring, the driving sub-circuit and the light-emitting device, and is configured to conduct a current path between the first voltage wiring and the light-emitting device and transmit a driving current provided by the driving sub-circuit to the light-emitting device under the control of an enabling signal transmitted by the enabling signal line;
the driving method of the display panel comprises the following steps: the holding stage includes a first stage and a second stage;
in the hold phase, the first switch opens a path between the source driving signal line and the data line;
in the first stage, the second switch turns on the constant voltage signal line and the data line; for each pixel circuit, the light emission control sub-circuit disconnects a current path between the first voltage trace and the light emitting device under control of the enable signal line; the reset sub-circuit disconnects a current path between the initialization signal line and the driving sub-circuit under the control of the first reset signal line; the reset sub-circuit transmits the initialization signal to the light emitting device under the control of the second reset signal line; the write compensation sub-circuit writes the constant voltage signal to a connection point of the driving sub-circuit and the light emission control sub-circuit under the control of the first scanning signal line and the second scanning signal line; the light emitting device does not emit light;
The second stage, the second switch breaks the path between the constant voltage signal line and the data line; for each pixel circuit, the write compensation sub-circuit disconnects a current path between the data line and the driving sub-circuit under the control of the first scanning signal line and the second scanning signal line, and the light emission control sub-circuit conducts the current path between the first voltage line and the light emitting device under the control of the enabling signal line; the driving signal generated by the driving sub-circuit is transmitted to the light emitting device; the light emitting device emits light.
CN202111406863.5A 2021-11-24 2021-11-24 Display panel, driving method and display device Active CN114038429B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202111406863.5A CN114038429B (en) 2021-11-24 2021-11-24 Display panel, driving method and display device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202111406863.5A CN114038429B (en) 2021-11-24 2021-11-24 Display panel, driving method and display device

Publications (2)

Publication Number Publication Date
CN114038429A CN114038429A (en) 2022-02-11
CN114038429B true CN114038429B (en) 2023-06-13

Family

ID=80145440

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202111406863.5A Active CN114038429B (en) 2021-11-24 2021-11-24 Display panel, driving method and display device

Country Status (1)

Country Link
CN (1) CN114038429B (en)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113823222B (en) * 2021-09-26 2023-08-18 合肥维信诺科技有限公司 Driving method and driving device of display panel and display device
CN114495836B (en) * 2022-02-23 2022-11-29 武汉天马微电子有限公司 Pixel circuit, driving method thereof, display panel and electronic equipment
WO2023216175A1 (en) * 2022-05-12 2023-11-16 京东方科技集团股份有限公司 Display substrate and driving method therefor, and display apparatus
CN114863875B (en) * 2022-05-25 2023-05-05 武汉天马微电子有限公司 Display panel, driving method thereof and display device
CN115064118B (en) * 2022-06-23 2023-06-02 合肥维信诺科技有限公司 Driving method and driving device of display panel and display device
WO2024007818A1 (en) * 2022-07-04 2024-01-11 华为技术有限公司 Display driving circuit, integrated circuit, oled screen, device and method

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111710299A (en) * 2020-06-30 2020-09-25 厦门天马微电子有限公司 Display panel, driving method thereof and display device
CN113012643A (en) * 2021-03-01 2021-06-22 上海天马微电子有限公司 Display panel, driving method thereof and display device

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102646389B (en) * 2011-09-09 2014-07-23 京东方科技集团股份有限公司 Organic light emitting diode (OLED) panel and OLED panel driving method
CN109148548B (en) * 2018-09-28 2020-05-19 昆山国显光电有限公司 Array substrate and display panel
CN112102785B (en) * 2020-10-15 2024-04-16 厦门天马微电子有限公司 Pixel circuit, display panel, driving method of display panel and display device
CN112509519A (en) * 2020-10-20 2021-03-16 厦门天马微电子有限公司 Display panel driving method and display device
CN112634832B (en) * 2020-12-31 2022-05-31 武汉天马微电子有限公司 Display panel, driving method and display device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111710299A (en) * 2020-06-30 2020-09-25 厦门天马微电子有限公司 Display panel, driving method thereof and display device
CN113012643A (en) * 2021-03-01 2021-06-22 上海天马微电子有限公司 Display panel, driving method thereof and display device

Also Published As

Publication number Publication date
CN114038429A (en) 2022-02-11

Similar Documents

Publication Publication Date Title
CN114038429B (en) Display panel, driving method and display device
US20240119897A1 (en) Pixel Circuit and Driving Method Therefor and Display Panel
WO2019062579A1 (en) Pixel circuit and driving method thereof, and display device
WO2019062255A1 (en) Array substrate, driving method, display panel and display device
CN112435622B (en) Display substrate, driving method thereof and display device
CN107507574B (en) OLED display panel and its compensation method and device, display device
US20150029238A1 (en) Drive circuit, optoelectronic device, electronic device, and drive method
CN112365843B (en) Pixel driving circuit and driving method thereof, display panel and device
CN111354314A (en) Pixel circuit, driving method of pixel circuit and display panel
CN112289269A (en) Pixel circuit, control method thereof and display panel
CN111354315B (en) Display panel, display device and pixel driving method
GB2620507A (en) Pixel circuit and driving method therefor and display panel
CN116110335A (en) Display device, display panel, and display driving method
CN113658554B (en) Pixel driving circuit, pixel driving method and display device
US11508290B2 (en) Pixel, display device, and method of driving display device
KR20210014262A (en) Display apparatus and method of driving the same
US11961458B2 (en) Display apparatus and control method therefor
US11935475B2 (en) Display device, driving circuit and display driving method
US11676539B2 (en) Pixel circuit configured to control light-emitting element
CN114078441B (en) Pixel circuit, display panel and display device
US20230397459A1 (en) Display module and display device
CN115410531A (en) Pixel circuit, driving method thereof, silicon-based display panel and display device
JP2024514718A (en) Pixel circuit, backlight module and display panel
KR20180078932A (en) Method for driving organic light emitting diode display device
US11929025B2 (en) Display device comprising pixel driving circuit

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant