CN114078441B - Pixel circuit, display panel and display device - Google Patents

Pixel circuit, display panel and display device Download PDF

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Publication number
CN114078441B
CN114078441B CN202111434174.5A CN202111434174A CN114078441B CN 114078441 B CN114078441 B CN 114078441B CN 202111434174 A CN202111434174 A CN 202111434174A CN 114078441 B CN114078441 B CN 114078441B
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circuit
sub
transistor
electrically connected
control
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CN114078441A (en
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胡宏锦
左堃
张斌
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BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
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BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix

Abstract

The invention provides a pixel circuit, a display panel and a display device, which are applied to the field of display and aim to solve the problem that the picture quality of the display device is low finally due to the fact that the gray scale of a light-emitting device is changed due to the fact that a thin film transistor in the pixel circuit is cut off and then the problem of electric leakage exists. Provided is a pixel circuit including: a write sub-circuit, a drive sub-circuit, and a shunt sub-circuit; the shunt sub-circuit is electrically connected to the driving sub-circuit, the write sub-circuit, the control signal terminal, and the second voltage signal terminal, and the shunt sub-circuit is configured to transmit a leakage voltage input from the write sub-circuit to the second voltage signal terminal in response to a control signal received at the control signal terminal in a state where the write sub-circuit is off, to prevent the leakage voltage from being transmitted to the driving sub-circuit, and to prevent the driving sub-circuit from leaking electricity to the second voltage signal terminal.

Description

Pixel circuit, display panel and display device
Technical Field
The invention relates to the technical field of display, in particular to a pixel circuit, a display panel and a display device.
Background
At present, an OLED (Organic Light-Emitting Diode) display device is widely used because it has the characteristics of self-luminescence, fast response, wide viewing angle, and can be manufactured on a flexible substrate. The display device controls the light emitting diodes to emit light through the pixel circuits, and forms a display picture on the whole display panel by controlling the brightness of light rays emitted by the light emitting diodes. The pixel circuit controls the on and off of the current signal by using a thin film transistor.
Disclosure of Invention
The invention provides a pixel circuit, a display panel and a display device, which are used for solving the problem of low display picture quality caused by electric leakage of a transistor in the pixel circuit.
In order to achieve the purpose, the invention adopts the following technical scheme:
in one aspect, the present invention provides a pixel circuit, including: a write sub-circuit, a drive sub-circuit, and a shunt sub-circuit. Wherein the write sub-circuit is electrically connected to the data signal terminal and the scan signal terminal, the write sub-circuit being configured to transmit the data signal received at the data signal terminal in response to the scan signal received at the scan signal terminal. The drive sub-circuit is electrically connected to the write sub-circuit and the first voltage signal terminal, and is configured to receive the data signal transmitted by the write sub-circuit and generate a drive current under control of the data signal and the first voltage signal received at the first voltage signal terminal. The shunt sub-circuit is electrically connected with the driving sub-circuit, the write-in sub-circuit, the control signal end and the second voltage signal end. The shunt sub-circuit is configured to transmit the leakage voltage signal input by the write sub-circuit to the second voltage signal terminal in response to the control signal received at the control signal terminal in a state where the write sub-circuit is off, to prevent the leakage voltage signal from being transmitted to the drive sub-circuit, and to prevent the drive sub-circuit from leaking electricity to the second voltage signal terminal.
The pixel circuit has the following beneficial effects: when the writing sub-circuit of a certain row of pixel circuits is in an off state, the data signal passes through the writing sub-circuit in the off state to form a leakage voltage signal. At the moment, the shunt sub-circuit is opened, the leakage voltage signal is guided to the second voltage signal end, meanwhile, the shunt sub-circuit prevents the data signal written into the driving sub-circuit from leaking electricity to the second voltage signal end, the data signal written into the driving sub-circuit is prevented from being changed due to interference of external factors, the stability of driving current is kept, and the brightness of a light-emitting device electrically connected with the pixel circuit is kept stable.
In some embodiments, the shunt subcircuit includes a switch control subcircuit and a unidirectional conducting subcircuit. The switch control sub-circuit is electrically connected with the write-in sub-circuit, the control signal terminal and the second voltage signal terminal, and the switch control sub-circuit is configured to be turned on when the write-in sub-circuit is in an off state, direct the leakage voltage of the write-in sub-circuit to the second voltage signal terminal, and be turned off when the write-in sub-circuit is in an on state under the control of the control signal. And the node of the switch control sub-circuit electrically connected with the write-in sub-circuit is a fourth node. The unidirectional turn-on sub-circuit is electrically connected between the fourth node and the driving sub-circuit, and the unidirectional turn-on sub-circuit is configured to turn off a current path leading from the driving sub-circuit to the second voltage signal terminal.
In some embodiments, the drive sub-circuit comprises a drive transistor and a storage capacitor. The control electrode of the driving transistor is electrically connected with the first node, the first electrode of the driving transistor is electrically connected with the second node, and the second electrode of the driving transistor is electrically connected with the third node. The first end of the storage capacitor is electrically connected with the first node, and the second end of the storage capacitor is electrically connected with the first voltage signal end.
In some embodiments, the write subcircuit includes a first transistor and a second transistor. The control electrode of the first transistor is electrically connected with the scanning signal end, the first electrode of the first transistor is electrically connected with the data signal end, and the second electrode of the first transistor is electrically connected with the second node; the control electrode of the second transistor is electrically connected with the scanning signal end, the first electrode of the second transistor is electrically connected with the third node, and the second electrode of the second transistor is electrically connected with the fourth node.
In some embodiments, the unidirectional conducting sub-circuit comprises a diode, the anode of the diode is electrically connected with the fourth node, and the cathode of the diode is electrically connected with the first node.
In some embodiments, the switch control sub-circuit includes a switch transistor having a control electrode electrically connected to the control signal terminal, a first electrode electrically connected to the fourth node, and a second electrode electrically connected to the second voltage signal terminal.
In some embodiments, the pixel circuit further includes an emission control sub-circuit and a reset sub-circuit.
The light-emitting control sub-circuit is electrically connected with the driving sub-circuit, the first voltage signal end, the light-emitting control signal end and the light-emitting device; the light emission control sub-circuit is configured to transmit a driving current to the light emitting device in response to a light emission control signal received at the light emission control terminal to cause the light emitting device to emit light during a light emission phase. The light emission control sub-circuit includes a third transistor and a fourth transistor. The control electrode of the third transistor is electrically connected with the light-emitting control signal end, the first electrode of the third transistor is electrically connected with the first voltage signal end, and the second electrode of the third transistor is electrically connected with the second node. The control electrode of the fourth transistor is electrically connected with the light-emitting control signal end, the first electrode of the fourth transistor is electrically connected with the third node, and the second electrode of the fourth transistor is electrically connected with the light-emitting device.
The reset sub-circuit is electrically connected with the driving sub-circuit, the first reset signal terminal, the second reset signal terminal, the initialization signal terminal and the light-emitting device. The reset sub-circuit is configured to transmit an initialization signal received at the initialization signal terminal to the first node in response to a first reset signal received at the first reset signal terminal, and to transmit the initialization signal to the light emitting device in response to a second reset signal received at the second reset signal terminal. The reset sub-circuit includes a fifth transistor and a sixth transistor. The control electrode of the fifth transistor is electrically connected with the first reset signal end, the first electrode of the fifth transistor is electrically connected with the initialization signal end, and the second electrode of the fifth transistor is electrically connected with the first node. The control electrode of the sixth transistor is electrically connected with the second reset signal end, the first electrode of the sixth transistor is electrically connected with the initialization signal end, and the second electrode of the sixth transistor is electrically connected with the light-emitting device.
In another aspect, the present invention provides a display panel including: the array structure comprises a plurality of sub-pixels, a plurality of data lines and a plurality of groups of grid lines, wherein each data line is electrically connected with one column of sub-pixels, and one group of grid lines is electrically connected with one row of sub-pixels; each sub-pixel includes a light emitting device and a pixel circuit of any one of the above-described aspects.
The display panel has stable gray scale of pixels in one frame of picture and high quality of each frame of picture.
In some embodiments, the write sub-circuit in the pixel circuit is electrically connected to the scan signal terminal, and the shunt sub-circuit is electrically connected to the control signal terminal. The write sub-circuit includes a second transistor and the shunt sub-circuit includes a switching transistor.
In some embodiments, the set of gate lines includes a first scan signal line electrically connected to the write sub-circuit through a scan signal terminal, the first scan signal line electrically connected to the shunt sub-circuit through a control signal terminal, the first scan signal line configured to transmit a first scan signal to the scan signal terminal and to transmit a control signal for the control signal terminal. The conduction types of the second transistor and the switching transistor are opposite.
In other embodiments, the set of gate lines includes a first scan signal line electrically connected to the write sub-circuit through a scan signal terminal, the first scan signal line configured to transmit a first scan signal to the scan signal terminal, and a second scan signal line electrically connected to the shunt sub-circuit through a control signal terminal, the second scan signal line configured to transmit a control signal to the control signal terminal, and the levels of the first scan signal and the control signal are opposite. The conduction type of the second transistor and the switching transistor is the same.
In still other embodiments, a set of gate lines includes a first scan signal line; the first scanning signal line is electrically connected with the write-in sub-circuit through a scanning signal terminal, and the first scanning signal line is configured to transmit a first scanning signal to the scanning signal terminal. The conduction type of the switching transistor and the second transistor is the same.
The display panel also comprises a shunt control sub-circuit. The input end of the shunt control sub-circuit is electrically connected with the first scanning signal line, the output end of the shunt control sub-circuit is electrically connected with the control signal end, and the shunt control sub-circuit is also electrically connected with the third voltage signal line and the fourth voltage signal line. The shunt control sub-circuit is configured to output a control signal having a level opposite to that of the first scan signal under control of the first scan signal, the third voltage signal transmitted by the third voltage signal line, and the fourth voltage signal transmitted by the fourth voltage signal line.
In some examples, the shunt control subcircuit includes: a seventh transistor and an eighth transistor. A control electrode of the seventh transistor is electrically connected to the fifth node, a first electrode of the seventh transistor is electrically connected to the third voltage signal line, and a second electrode of the seventh transistor is electrically connected to the sixth node. A control electrode of the eighth transistor is electrically connected to the fifth node, a first electrode of the eighth transistor is electrically connected to the fourth voltage signal line, and a second electrode of the eighth transistor is electrically connected to the sixth node. The fifth node is an input end of the shunt control sub-circuit, and the sixth node is an output end of the shunt control sub-circuit.
In some examples, the seventh transistor is an N-type transistor, the eighth transistor is a P-type transistor, and a voltage of the third voltage signal is lower than a voltage of the fourth voltage signal.
In other examples, the seventh transistor is a P-type transistor, the eighth transistor is an N-type transistor, and the voltage of the third voltage signal is higher than the voltage of the fourth voltage signal.
In some embodiments, the display panel includes a display area and a peripheral area disposed at least on one side of the display area, and the shunt control sub-circuit is provided in plurality. Each shunt control sub-circuit is electrically connected with one pixel circuit, and the shunt control sub-circuits are arranged in the display area. Or each shunt control sub-circuit is electrically connected with one row of pixel circuits, and the shunt control sub-circuits are arranged in the peripheral area.
In another aspect, the present invention provides a display device comprising the display panel according to any one of the above aspects.
The display device adopts the display panel and has the same beneficial effects as the display panel.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a plan view of a display device provided in some embodiments of the present invention;
FIG. 2 is a plan view of a display panel according to some embodiments of the present invention;
fig. 3 is a block diagram of a pixel circuit according to some embodiments of the invention;
FIG. 4a is a block diagram of another pixel circuit provided in some embodiments of the invention;
FIG. 4b is a timing diagram for the pixel circuit of FIG. 4a according to the present invention;
FIG. 5 is a block diagram of a pixel circuit according to some embodiments of the invention;
FIG. 6 is a block diagram of another pixel circuit provided by some embodiments of the invention;
FIG. 7 is a timing diagram according to some embodiments of the present invention;
FIG. 8 is a block diagram of yet another pixel circuit provided by some embodiments of the invention;
FIG. 9 is another timing signal diagram provided by some embodiments of the present invention;
fig. 10 is a block diagram of a pixel circuit and a shunt control sub-circuit according to some embodiments of the present invention;
FIG. 11 is a diagram of yet another timing signal provided by some embodiments of the present invention;
fig. 12 is a circuit diagram of a shunt control sub-circuit according to some embodiments of the present invention;
fig. 13 is a circuit diagram of another shunt control sub-circuit provided in some embodiments of the present invention;
FIG. 14 is a plan view of a display panel with a shunt control sub-circuit according to some embodiments of the present invention;
fig. 15 is a plan view of another display panel with a shunt control sub-circuit according to some embodiments of the present invention.
Detailed Description
Technical solutions in some embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings, and it is obvious that the described embodiments are only a part of the embodiments of the present disclosure, and not all of the embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments provided by the present disclosure belong to the protection scope of the present disclosure.
Unless the context requires otherwise, throughout the description and the claims, the term "comprise" and its other forms, such as the third person's singular form "comprising" and the present participle form "comprising" are to be interpreted in an open, inclusive sense, i.e. as "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "example", "specific example" or "some examples" and the like are intended to indicate that a particular feature, structure, material, or characteristic associated with the embodiment or example is included in at least one embodiment or example of the present disclosure. The schematic representations of the terms are not necessarily referring to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics may be included in any suitable manner in any one or more embodiments or examples.
In the following, the terms "first", "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the embodiments of the present disclosure, "a plurality" means two or more unless otherwise specified.
In describing some embodiments, the expressions "coupled" and "connected," along with their derivatives, may be used. For example, the term "connected" may be used in describing some embodiments to indicate that two or more elements are in direct physical or electrical contact with each other. As another example, some embodiments may be described using the term "coupled" to indicate that two or more elements are in direct physical or electrical contact. However, the terms "coupled" or "communicatively coupled" may also mean that two or more elements are not in direct contact with each other, but yet still co-operate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents herein.
The use of "adapted to" or "configured to" herein is meant to be an open and inclusive language that does not exclude devices adapted to or configured to perform additional tasks or steps.
Additionally, the use of "based on" means open and inclusive, as a process, step, calculation, or other action that is "based on" one or more stated conditions or values may in practice be based on additional conditions or values beyond those stated.
As shown in fig. 1: some embodiments of the present invention provide a display device 1000, and the display device 1000 may be, for example, a mobile phone, a tablet computer, a Personal Digital Assistant (PDA), a television, an in-vehicle computer, a wearable display device, and the like, and may be, for example, a watch. The embodiment of the present invention does not particularly limit the specific form of the display device 1000.
In some examples, the display device 1000 may be an electroluminescent display device. For example, the display device may be a self-luminous display device such as an OLED (Organic Light-Emitting Diode) display device, a Micro Organic Light-Emitting Diode (Micro OLED) display device, a Quantum Dot Organic Light-Emitting Diode (QLED) display device, a Mini Light-Emitting Diode (Mini LED) display device, or a Micro LED (Micro Light-Emitting Diode).
The display device 1000 includes a display panel 100. Illustratively, the display panel 100 may be an OLED (Organic Light-Emitting Diode) display panel, and the AMOLED display panel is taken as an example below.
As shown in fig. 2: the display panel 100 includes a display area 10a and a peripheral area 10b disposed at least on one side of the display area 10a, and illustratively, the peripheral area 10b is disposed on one side of the display area 10a, or the peripheral area 10b is disposed around one circumference of the display area 10a.
The display panel 100 further includes: a plurality of data lines L and a plurality of groups of gate lines disposed in the display region 10a. The display region 10a is further provided with a plurality of sub-pixels P arranged in an array, each data line L is electrically connected to a column of sub-pixels P, the data lines L are configured to transmit data signals, and each group of gate lines is electrically connected to a row of sub-pixels P. Illustratively, a group of gate lines is divided into a first scanning signal line G1, a first reset signal line Rst1, a second reset signal line Rst2 and an enable signal line Em according to a function of a signal supplied from each of the gate lines among a group of gate lines connected to the subpixels P, the signal lines being electrically connected to a row of the subpixels P, respectively. Here, as shown in fig. 3, the sub-pixel P includes a pixel circuit 20 and a light emitting device 30 electrically connected.
The display panel 100 further includes a plurality of first voltage traces VDD and a plurality of second voltage traces VSS, and a plurality of initialization signal lines Vint, etc., the pixel circuit 20 is electrically connected to the first voltage traces VDD and the initialization signal lines Vint, and the light emitting device 30 is electrically connected to the second voltage traces VSS. The first voltage trace VDD is configured to provide a first voltage signal, the initialization signal line Vint is configured to provide an initialization signal, and the second voltage trace VSS is configured to provide a second voltage signal, where the level of the second voltage signal is lower than that of the first voltage signal. For example, the level of the first voltage signal is +3V, and the level of the second voltage signal is-3V.
In some embodiments of the present invention, the pixel circuit 20 may be a 6T1C, 7T1C, and 6T2C type pixel circuit. Exemplarily, taking a pixel circuit of 7T1C type as an example, as shown in fig. 3: the pixel circuit 20 includes: a write sub-circuit 21, a drive sub-circuit 22, a light emission control sub-circuit 23, and a reset sub-circuit 24. The write sub-circuit 21 is electrically connected to the data signal terminal v, the scan signal terminal g, and the drive sub-circuit 22. Wherein the data signal terminal v is electrically connected with the data line L, and the data line L is configured to transmit a data signal to the data signal terminal v. The scanning signal terminal G is electrically connected to a first scanning signal line G1, and the first scanning signal line G1 is configured to transmit a scanning signal to the scanning signal terminal G. The write sub-circuit 21 is configured to transmit a data signal received at the data signal terminal v to the drive sub-circuit 22 in response to a first scan signal received at the scan signal terminal g.
The drive sub-circuit 22 is electrically connected to the write sub-circuit 21 and the first voltage signal terminal vdd, and the data signal transmitted from the write sub-circuit 21 is written in the drive sub-circuit 22. The driving sub-circuit 22 is configured to receive the data signal transmitted by the writing sub-circuit 21, and generate a driving current under the control of the data signal and the first voltage signal received at the first voltage signal terminal vdd.
The light emission control sub-circuit 23 is electrically connected to the driving sub-circuit 22, the first voltage signal terminal vdd, the light emission control signal terminal em, and the light emitting device 30. The first voltage signal terminal VDD is electrically connected to the first voltage trace VDD, the light emission control signal terminal Em is electrically connected to the enable signal line Em, and the enable signal line Em is configured to transmit the light emission control signal to the light emission control signal terminal Em. The light emission control sub-circuit 23 is configured such that, in the light emission phase t3, in response to the light emission control signal received at the light emission control terminal em, the light emission control sub-circuit 23 receives the first voltage signal at the first voltage signal terminal vdd and transmits the same to the driving sub-circuit 22, and transmits the driving current to the light emitting device 30. The anode of each light emitting device 30 is electrically connected to the light emission control sub-circuit 23, the cathode of the light emitting device 30 is electrically connected to the second voltage trace terminal Vss, the second voltage trace terminal Vss is electrically connected to the second voltage trace Vss, and the light emitting device 30 emits light under the action of the driving current.
The reset sub-circuit 24 is electrically connected to the driving sub-circuit 22, the first reset signal terminal rst1, the second reset signal terminal rst2, the initialization signal terminal vint, and the light emitting device 30. Wherein the first reset signal terminal Rst1 is electrically connected to a first reset signal line Rst1, the first reset signal line Rst1 being configured to supply a first reset signal to the first reset signal terminal Rst 1. The second reset signal terminal Rst2 is electrically connected to a second reset signal line Rst2, and the second reset signal line Rst2 is configured to supply a second reset signal to the second reset signal terminal Rst 2. The initialization signal terminal Vint is electrically connected to an initialization signal line Vint, and the initialization signal line Vint is configured to provide an initialization signal to the initialization signal terminal Vint. The reset sub-circuit 24 is configured to transmit an initialization signal received at the initialization signal terminal vint to the drive sub-circuit 22 in response to a first reset signal received at the first reset signal terminal rst 1. And the reset sub-circuit 24 is further configured to transmit an initialization signal to the light emitting device 30 in response to a second reset signal received at the second reset signal terminal rst 2.
Illustratively, as shown in FIG. 4 a: the write sub-circuit 21 includes: a first transistor T1 and a second transistor T2; the driving sub-circuit 22 includes a driving transistor Tq and a storage capacitor Cst; the light emission control sub-circuit 23 includes a third transistor T3 and a fourth transistor T4; the reset sub-circuit 24 includes a fifth transistor T5 and a sixth transistor T6. And the first transistor T1, the second transistor T2, the driving transistor Tq, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 are all thin film transistors.
A control electrode of the first transistor T1 is electrically connected to the scan signal terminal g, a first electrode of the first transistor T1 is electrically connected to the data signal terminal v, and a second electrode of the first transistor T1 is electrically connected to the second node N2. A control electrode of the second transistor T2 is electrically connected to the scan signal terminal g, a first electrode of the second transistor T2 is electrically connected to the third node N3, and a second electrode of the second transistor T2 is electrically connected to the first node N1.
A control electrode of the driving transistor Tq is electrically connected to the first node N1, a first electrode of the driving transistor Tq is electrically connected to the second node N2, and a second electrode of the driving transistor Tq is electrically connected to the third node N3. A first terminal of the storage capacitor Cst is electrically connected to the first node N1, and a second terminal of the storage capacitor Cst is electrically connected to the first voltage signal terminal vdd.
A control electrode of the third transistor T3 is electrically connected to the light emission control signal terminal em, a first electrode of the third transistor T3 is electrically connected to the first voltage signal terminal vdd, and a second electrode of the third transistor T3 is electrically connected to the second node N2. A control electrode of the fourth transistor T4 is electrically connected to the light emission control signal terminal em, a first electrode of the fourth transistor T4 is electrically connected to the third node N3, and a second electrode of the fourth transistor T4 is electrically connected to the light emitting device 30.
A control electrode of the fifth transistor T5 is electrically connected to the first reset signal terminal rst1, a first electrode of the fifth transistor T5 is electrically connected to the initialization signal terminal vint, and a second electrode of the fifth transistor T5 is electrically connected to the first node N1. A control electrode of the sixth transistor T6 is electrically connected to the second reset signal terminal rst2, a first electrode of the sixth transistor T6 is electrically connected to the initialization signal terminal vint, and a second electrode of the sixth transistor T6 is electrically connected to the light emitting device 30.
An OLED (Organic Light-Emitting Diode) display device usually employs a 7T1C type pixel circuit 20. In the above circuit configuration, as shown in fig. 4 a: the first transistor T1, the second transistor T2, the driving transistor Tq, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 are P-type thin film transistors. Due to the characteristics of the P-type thin film transistor material and the high carrier mobility rate, the P-type transistor has the defect of electric leakage after being cut off. The current leakage problem causes a change in the current signal in the pixel circuit 20, which in turn causes a change in the luminance of the light emitting device 30, and ultimately causes a problem of low picture quality of the display apparatus 1000.
In some embodiments, as shown in fig. 4b, the driving process of the pixel circuit 20 includes a reset phase, a data writing phase and a light emitting phase within one frame (1 frame), wherein the light emitting phase includes at least one light emitting sub-phase and at least one non-light emitting sub-phase.
In the data writing stage, the write sub-circuit 21 is turned on under the control of the first scan signal to write the data signal D of the period x Writing into the driving sub-circuit 22, the driving sub-circuit 22 displaying the data signal D x The driving current is generated under control, the light emitting device 30 can emit light under the driving current in the subsequent stage, and the brightness of the emitted light is controlled by the written data signal Dx. In the light emitting stage, the driving current generated by the driving sub-circuit 22 is transmitted to the light emitting device 30 to make the light emitting device 30 emit light, and the writing sub-circuit 21 is turned off under the control of the first scan signal, so that the writing sub-circuit 21 cannot be completely turned off due to the material and structural characteristics of the writing sub-circuit 21, and the data signal D transmitted by the data line L in the light emitting stage x+1 There is a phenomenon of leakage of current to the driving sub-circuit 22 through the writing sub-circuit 21, resulting in a change in voltage written to the driving sub-circuit 22 during the data writing phase, and thus a change in brightness of the emitted light of the light emitting device 30.
Illustratively, the specific working process of each transistor is as follows: in the data writing stage, the first transistor T1 and the second transistor T2 are turned on under the control of the first scan signal to convert the data signal D into the first signal x The drive subcircuit 22 is written and threshold voltage compensation is done. When the driving transistor Tq is turned off, the voltage of the first node N1 is the data signal D x And the sum of the threshold voltages of the driving transistors Tq, the voltage of the first node N1 can control the magnitude of the driving current. In the light emitting stage, the first transistor T1 and the second transistor T2 are turned off under the control of the first scan signal, however, the first transistor T1 and the second transistor T2 are not completely turned offAnd when the circuit is closed, the leakage current is small, and a leakage voltage signal can be transmitted under the action of a data signal. In the light emitting sub-phase of the light emitting phase, the third transistor T3 and the fourth transistor T4 are turned on under the control of the enable signal, the driving transistor Tq is turned on and generates a driving current, the driving current is transmitted to the light emitting device 30, and the leakage voltage signal transmitted by the first transistor T1 is conducted to the second voltage signal terminal vss through the fourth transistor T4 and the light emitting device 30. In the non-light-emitting sub-stage of the light-emitting stage, the third transistor T3 and the fourth transistor T4 are turned off under the control of the enable signal, and at this time, the first transistor T1, the second transistor T2, the third transistor T3 and the fourth transistor T4 are all in an off state, and the data signal D is generated x+1 The first transistor T1 and the second transistor T2 which are turned off generate a leakage voltage signal, the leakage voltage signal is written into the first node N1 again, the voltage of the first node N1 is changed, the driving transistor Tq generates a new driving current under the control of the voltage of the first node N1, and the light emitting device 30 emits light under the control of the new driving current, which affects the luminance of the light emission and causes abnormal light emission of the light emitting device.
In a single frame picture, as shown in fig. 4b, the enable signal includes four low levels and three high levels within a single frame timing signal, and the high levels and the low levels are alternately performed. In the data writing phase t2, the data signal is written into the driving sub-circuit 22, and the voltage at the first node N1 changes for the first time; in the first non-light-emitting sub-phase T32 of the light-emitting phase T3, the data signal is generated into the leakage voltage signal through the first transistor T1 and the second transistor T2 and is written into the driving sub-circuit 22 again, and the voltage at the first node N1 changes for the second time; in the second non-emitting sub-period T32 of the emitting period T3, the data signal is written into the driving sub-circuit 22 after passing through the first transistor T1 and the second transistor T2 again to generate a leakage voltage signal, and the voltage at the first node N1 is changed for the third time. After the voltage of the first node N1 changes each time, the magnitude of the driving current changes, and the brightness of the light emitting device 30 also changes. Therefore, under the condition of a non-specifically set time sequence, three sections of abnormal picture display areas appear in the same frame of picture, and with continuous switching and repeated superposition of the frames and the frame pictures, a four-screen-division phenomenon is finally generated on the display panel 100, namely three obvious horizontal stripes are formed on the display panel 100, and the picture display effect is influenced.
Based on this, on the one hand, as shown in fig. 5: some embodiments of the invention provide a pixel circuit 20, the pixel circuit 20 further comprising a shunting sub-circuit 25. The shunt sub-circuit 25 is electrically connected to the drive sub-circuit 22, the write sub-circuit 21, the control signal terminal k, and the second voltage signal terminal vss. And the shunt sub-circuit 25 and the drive sub-circuit 22 are electrically connected at a first node N1. The shunt sub-circuit 25 is configured to transmit the leakage voltage signal input by the write sub-circuit 21 to the second voltage signal terminal vss in response to the control signal received at the control signal terminal k when the write sub-circuit 21 is in the off state, so as to prevent the leakage voltage signal from being transmitted to the driving sub-circuit 22 and prevent the driving sub-circuit 22 from leaking to the second voltage signal terminal vss.
The shunt sub-circuit 25 guides the leakage voltage signal written into the sub-circuit 21 to the second voltage signal terminal vss, so as to prevent the voltage signal written into the driving sub-circuit 22 from being changed under the influence of the leakage voltage signal, thereby affecting the magnitude of the driving current, so that the driving current can be kept stable, thereby ensuring that the light emitted by the light emitting device 30 has stable brightness, i.e. the light emitting device 30 emits light without abnormality. Meanwhile, the shunt sub-circuit 25 can also prevent the driving sub-circuit 22 from leaking electricity to the second voltage signal terminal vss, so as to avoid the problem that the driving sub-circuit 22 leaks electricity to the second voltage signal terminal vss, which causes unstable voltage and affects the magnitude of the driving current. In summary, the shunting subcircuit 25 can ensure the normal light emission of the light emitting device 30, and improve the stability of the light emitting brightness of the light emitting device 30.
In some embodiments, shunt subcircuit 25 includes switch control subcircuit 252 and unidirectional conduction subcircuit 251. The switch control sub-circuit 252 is electrically connected to the write sub-circuit 21, the control signal terminal k, and the second voltage signal terminal vss, and the switch control sub-circuit 252 is configured to be turned on when the write sub-circuit 21 is in an off state, to direct the leakage voltage signal of the write sub-circuit 21 to the second voltage signal terminal vss, and to be turned off when the write sub-circuit 21 is in an on state, under the control of the control signal. The node of the switch control sub-circuit 252 electrically connected to the write sub-circuit 21 is a fourth node N4.
The unidirectional turn-on sub-circuit 251 is electrically connected between the fourth node N4 and the driving sub-circuit 22, and the unidirectional turn-on sub-circuit 251 is configured to turn off a current path leading from the driving sub-circuit 22 to the second voltage signal terminal vss.
The switch control sub-circuit 252 operates in cooperation with the write sub-circuit 21 to direct the write sub-circuit 21 to the second voltage signal terminal vss when a leakage voltage signal is present. Meanwhile, the one-way conduction sub-circuit 251 can close the current path between the driving sub-circuit 22 and the second voltage signal terminal vss, so that the shunting sub-circuit 25 can transmit the leakage voltage signal input by the writing sub-circuit 21 to the second voltage signal terminal vss, thereby preventing the leakage voltage signal from being transmitted to the driving sub-circuit 22 and preventing the driving sub-circuit 22 from leaking electricity to the second voltage signal terminal vss.
In some embodiments, as shown in fig. 6: the one-way conduction sub-circuit 251 includes a diode D, an anode of the diode D is electrically connected to the fourth node N4, and a cathode of the diode D is electrically connected to the first node N1. Illustratively, the diode D may be formed by doping preparation using a process for generating a transistor at the same film layer as the transistor in the pixel circuit 20.
The diode D has the characteristic of one-way conduction, and a signal input into the diode D can be transmitted only from the anode of the diode D to the cathode of the diode D but cannot be transmitted reversely, so that the functions can be realized, and the diode D has the advantages of stable and mature process and low cost.
In some embodiments, the switch control sub-circuit 252 includes a switch transistor K, the switch transistor K is a thin film transistor, a control electrode of the switch transistor K is electrically connected to the control signal terminal K, a first electrode of the switch transistor K is electrically connected to the fourth node N4, and a second electrode of the switch transistor K is electrically connected to the second voltage signal terminal vss. The switching transistor K is turned on or off under the control of the control signal transmitted from the control signal terminal K, thereby realizing the purpose of directing the leakage voltage signal written into the sub-circuit 21 to the second voltage signal terminal vss.
Illustratively, the switching transistor K and the second transistor T2 are alternately turned on or off, that is, the switching transistor K is turned off when the second transistor T2 is in an on state; when the second transistor T2 is turned off, the switching transistor K is turned on. The on or off states of the second transistor T2 and the first transistor T1 are kept identical.
As shown in fig. 7: in a single frame picture, the timing signal includes a reset phase t1, a data write phase t2, and a light emitting phase t3. In the reset phase T1, the fifth transistor T5 is turned on under the control of the first reset signal, and the initialization signal is written into the first node N1. In the data writing period T2, the fifth transistor T5 is turned off under the control of the first reset signal, the first transistor T1 and the second transistor T2 are turned on under the control of the first scan signal, the data signal is written into the storage capacitor Cst, i.e., the first node N1, and the threshold voltage compensation is performed on the driving transistor Tq, and when the driving transistor Tq is turned off, the voltage of the first node N1 is the sum of the data signal and the threshold voltage of the driving transistor Tq. The light emitting period T3 includes a light emitting sub-period T31 and a non-light emitting sub-period T32, and in the light emitting sub-period T31, the third transistor T3 and the fourth transistor T4 are turned on under the control of the enable signal, the first voltage signal of the first voltage signal terminal vdd is transmitted to the driving transistor Tq, and the driving current generated by the driving transistor Tq under the control of the voltage of the first node N1 is transmitted to the light emitting device 30, and the light emitting device 30 emits light. In the non-light emitting sub-period T32, the third transistor T3 and the fourth transistor T4 are turned off under the control of the enable signal, the first transistor T1 and the second transistor T2 are turned off under the control of the first scan signal, and the data signal provided from the data signal terminal generates a leakage voltage signal through the turned-off first transistor T1 and the turned-off second transistor T2. The switching transistor K is turned on under the control of the control signal to conduct the leakage voltage signal to the second voltage signal terminal vss, and the voltage of the first node N1 is maintained under the action of the diode D.
In another aspect, some embodiments of the invention provide a display panel 100, the display panel 100 including the pixel circuit 20 as described in any one of the above aspects.
The display panel 100 has the advantages of the pixel circuit 20, and the four-screen-division phenomenon disappears in the display screen of the display panel 100 when the pixel circuit 20 is not abnormal.
In some embodiments, the conduction types of the second transistor T2 and the switching transistor K are opposite. For example, the second transistor T2 is a P-type thin film transistor, and the switching transistor K is an N-type thin film transistor; or the second transistor T2 is an N-type thin film transistor, and the switching transistor K is a P-type thin film transistor.
As shown in fig. 8: the write-in sub-circuit 21 in the pixel circuit 20 is electrically connected to the scanning signal terminal g, and the shunt sub-circuit 25 is electrically connected to the control signal terminal k; the write sub-circuit 21 comprises a second transistor T2 and the shunt sub-circuit 25 comprises a switching transistor K.
The gate lines include a first scan signal line G1, the first scan signal line G1 is electrically connected to the write-in sub-circuit 21 through a scan signal terminal G, and the first scan signal line G1 is electrically connected to the shunt sub-circuit 25 through a control signal terminal k. The first scanning signal line G1 is configured to transmit a first scanning signal to the scanning signal terminal G, and the first scanning signal line G1 is configured to transmit a control signal to the control signal terminal k, the control signal and the first scanning signal being at the same level.
Exemplarily, as shown in fig. 8 and 9: in the reset phase, the operation of the pixel circuit 20 is the same as that described above, and will not be described herein. In the data writing phase, the switching transistor K is turned off under the control of the control signal, and the first transistor T1 and the second transistor T2 are turned on under the control of the first scan signal, writing the data signal into the storage capacitor Cst. In the light emitting period T3, the first transistor T1 and the second transistor T2 are turned off under the control of the first scan signal, the data signal generates a leakage voltage signal through the turned-off first transistor T1 and the turned-off second transistor T2, and the switching transistor K is turned on under the control of the control signal. In the light emitting sub-phase T31, the third transistor T3 and the fourth transistor T4 are turned on under the control of the enable signal, and the leakage voltage signal is conducted to the light emitting device 30 through the turned-on fourth transistor T4, so that the leakage voltage signal does not affect the potential of the first node. In the non-emitting sub-period T32, the third transistor T3 and the fourth transistor T4 are turned off under the control of the enable signal, and the leakage voltage signal is conducted to the second voltage signal terminal vss through the turned-on switch transistor K. Meanwhile, in the light emitting period t3, the diode D can only conduct in a single direction, so that the leakage of the first node to the second voltage signal terminal vss is prevented, and the voltage of the first node N1 can be kept stable.
In other embodiments, the second transistor T2 and the switching transistor K are of the same conduction type. For example: the second transistor T2 is a P-type thin film transistor, and the switch transistor K is a P-type thin film transistor; or the second transistor T2 is an N-type thin film transistor, and the switching transistor K is an N-type thin film transistor.
In some examples, as shown in fig. 6: the write sub-circuit 21 in the pixel circuit 20 is electrically connected to the scanning signal terminal g, and the shunt sub-circuit 25 is electrically connected to the control signal terminal k; the write sub-circuit 21 comprises a second transistor T2 and the shunt sub-circuit 25 comprises a switching transistor K.
The group of gate lines includes a first scanning signal line G1 and a second scanning signal line G2, the first scanning signal line G1 is electrically connected to the write sub-circuit 21 through a scanning signal terminal G, and the first scanning signal line G1 is configured to transmit a first scanning signal to the scanning signal terminal G. The second scanning signal line G2 is electrically connected to the shunt sub-circuit 25 through the control signal terminal k. The second scanning signal line G2 is configured to transmit a control signal to the control signal terminal k, and the levels of the first scanning signal and the control signal are opposite. In the above embodiments, the second transistor T2 and the switching transistor K are of the same conduction type, and a group of gate lines includes the first scanning signal line G1 and the second scanning signal line G2, that is, a row of pixel circuits 20 is electrically connected to one first scanning signal line G1 and one second scanning signal line G2, and in some embodiments, a gate driving circuit of the display panel 100, such as a Gate On Array (GOA) circuit, is configured to provide the first scanning signal and the second scanning signal, and includes a plurality of shift register units, each of which is electrically connected to one first scanning signal line G1 and one second scanning signal line G2, provides the first scanning signal to the first scanning signal line G1, and provides the second scanning signal to the second scanning signal line G2.
Illustratively, as shown in fig. 6 and 7: in the reset phase t1, the operation state of the pixel circuit 20 is the same as that described above, and is not described herein again. In the data writing period T2, the first transistor T1 and the second transistor T2 are turned on under the control of the first scan signal transmitted from the first scan signal line G1 to write the data signal into the storage capacitor Cst. In the light emitting period T3, the first transistor T1 and the second transistor T2 are turned off under the control of the first scan signal, the data signal generates a leakage voltage signal through the turned-off first transistor T1 and the turned-off second transistor T2, and the switching transistor K is turned on under the control of the control signal transmitted through the second scan signal line G2. In the light emitting sub-phase T31, the third transistor T3 and the fourth transistor T4 are turned on under the control of the enable signal, and the leakage voltage signal is conducted to the light emitting device 30 through the turned-on fourth transistor T4, so that the leakage voltage signal does not affect the potential of the first node N1. In the non-emitting sub-period T32, the third transistor T3 and the fourth transistor T4 are turned off under the control of the enable signal, and the leakage voltage signal is conducted to the second voltage signal terminal vss through the turned-on switch transistor K. Meanwhile, in the light emitting period t3, the diode D can only conduct in a single direction, so that the leakage of the first node N1 to the second voltage signal terminal vss is prevented, and the voltage of the first node N1 can be kept stable.
In still other embodiments, the switch transistor K and the second transistor T2 are of the same conduction type. The specific examples are the same as above, and are not described herein.
In some examples, as shown in fig. 10, the write sub-circuit 21 in the pixel circuit 20 is electrically connected to the scan signal terminal g, and the shunt sub-circuit 25 is electrically connected to the control signal terminal k; the write sub-circuit 21 comprises a second transistor T2 and the shunt sub-circuit 25 comprises a switching transistor K.
One group of gate lines includes a first scanning signal line G1; the first scanning signal line G1 is electrically connected to the write sub-circuit 21 through a scanning signal terminal G, and the first scanning signal line 21 is configured to transmit a first scanning signal to the scanning signal terminal G.
As shown in fig. 10: the display panel 100 further includes a shunt control sub-circuit 40, and the shunt control sub-circuit 40 is configured to receive the first scan signal line 21, transmit the first scan signal to the control signal terminal k, and provide the control signal to the control signal terminal k under the control of the first scan signal. The input terminal of the shunt control sub-circuit 40 is electrically connected to the first scanning signal line G1, and the output terminal of the shunt control sub-circuit 40 is electrically connected to the control signal terminal k. The shunt control sub-circuit 40 is also electrically connected with a third voltage signal line VG1 and a fourth voltage signal line VG 2; the shunt control sub-circuit 40 is configured to output a control signal having a level opposite to that of the first scan signal under the control of the first scan signal, the third voltage signal transmitted through the third voltage signal line VG1, and the fourth voltage signal transmitted through the fourth voltage signal line VG 2.
Illustratively, as shown in fig. 10 and 11: in the reset phase t1, the operation state of the pixel circuit 20 is the same as that described above, and is not described herein again. In the data writing period T2, the first transistor T1 and the second transistor T2 are turned on under the control of the first scan signal transmitted from the first scan signal line G1 to write the data signal into the storage capacitor Cst. In the light emitting period T3, the first transistor T1 and the second transistor T2 are turned off under the control of the first scan signal, and the data signal generates a leakage voltage signal through the turned-off first transistor T1 and the turned-off second transistor T2. The shunt control sub-circuit 40 receives the first scanning signal and outputs a control signal having a level opposite to that of the first scanning signal. The switching transistor K is turned on under the control of the control signal. In the light emitting sub-phase T31, the third transistor T3 and the fourth transistor T4 are turned on under the control of the enable signal, and the leakage voltage signal is conducted to the light emitting device 30 through the turned-on fourth transistor T4, so that the leakage voltage signal does not affect the potential of the first node. In the non-emitting sub-period T32, the third transistor T3 and the fourth transistor T4 are turned off under the control of the enable signal, and the leakage voltage signal is conducted to the second voltage signal terminal vss through the turned-on switch transistor K. Meanwhile, in the light emitting period t3, the diode D can only conduct in a single direction, so that the leakage of the first node N1 to the second voltage signal terminal vss is prevented, and the voltage of the first node N1 can be kept stable.
Under the condition that the conduction types of the second transistor T2 and the switch transistor K are the same, the shunting control sub-circuit 40 is adopted, the second transistor T2 and the switch transistor K can be controlled to be alternately turned on or turned off through the first scanning signal line G1, the shunting control sub-circuit 40 can realize simultaneous control of the shunting sub-circuit 25 and the writing sub-circuit 21, development of new Gate Driver on Array (GOA) timing sequence setting is not needed, development time is greatly saved, and rapid introduction and popularization of a new technology are facilitated.
In some examples, the shunt control subcircuit 40 is a push-pull circuit, which includes: a seventh transistor T7 and an eighth transistor T8. As shown in fig. 12: the seventh transistor T7 is an N-type thin film transistor, a control electrode of the seventh transistor T7 is electrically connected to the fifth node N5, a first electrode of the seventh transistor T7 is electrically connected to the third voltage signal line VG1, and a second electrode of the seventh transistor T7 is electrically connected to the sixth node N6. The eighth transistor T8 is a P-type thin film transistor, a control electrode of the eighth transistor T8 is electrically connected to the fifth node N5, a first electrode of the eighth transistor T8 is electrically connected to the fourth voltage signal line VG2, and a second electrode of the eighth transistor T8 is electrically connected to the sixth node N6.
The voltage of the third voltage signal is lower than the voltage of the fourth voltage signal, which is 7V and-7V, for example.
In other examples, the shunt control subcircuit 40 is a push-pull circuit, which includes: a seventh transistor T7 and an eighth transistor T8. As shown in fig. 13: the seventh transistor T7 is a P-type thin film transistor, a control electrode of the seventh transistor T7 is electrically connected to the fifth node N5, a first electrode of the seventh transistor T7 is electrically connected to the third voltage signal line VG1, and a second electrode of the seventh transistor T7 is electrically connected to the sixth node N6. The eighth transistor T8 is an N-type thin film transistor, a control electrode of the eighth transistor T8 is electrically connected to the fifth node N5, a first electrode of the eighth transistor T8 is electrically connected to the fourth voltage signal line VG2, and a second electrode of the eighth transistor T8 is electrically connected to the sixth node N6.
The voltage of the third voltage signal is higher than the voltage of the fourth voltage signal, and illustratively, the voltage of the third voltage signal is 7V and the voltage of the fourth voltage signal is-7V.
In some embodiments, each of the shunt control sub-circuits 40 is electrically connected to one of the pixel circuits 20, and the shunt control sub-circuits 40 are disposed in the display area 10a. Illustratively, as shown in fig. 14: a shunt control sub-circuit 40 is disposed in the layout area of each pixel circuit 20, and each shunt control sub-circuit 40 in the layout area of the pixel circuits 20 in the same row is electrically connected to the first scanning signal line G1. The third voltage signal line VG1 and the fourth voltage signal line VG2 are signal lines parallel to the gate lines. After a first scanning signal supplied from one first scanning signal line G1 passes through the plurality of shunt control sub-circuits 40, each shunt control sub-circuit 40 supplies a control signal to the pixel circuit 20 electrically connected thereto. In other embodiments, each of the shunt control sub-circuits 40 is electrically connected to a row of the pixel circuits 20, and the shunt control sub-circuits 40 are disposed in the peripheral region 10b. Each of the first scanning signal lines G1 is electrically connected to one of the shunt control sub-circuits 40, each of the shunt control sub-circuits 40 is electrically connected to a third voltage signal line VG1 and a fourth voltage signal line VG2, the third voltage signal line VG1 and the fourth voltage signal line VG2 are disposed in the peripheral region 10b, an output end of each of the shunt control sub-circuits 40 is electrically connected to a control signal line CL parallel to the gate line, the control signal line CL is disposed in the display region 10a, and each of the control signal lines CL is electrically connected to each of the control signal terminals k in one row of the pixel circuits 20.
Illustratively, as shown in FIG. 15: the peripheral area 10b is provided with a plurality of shunt control sub-circuits 40, each shunt control sub-circuit 40 is electrically connected to all the control signal terminals k in one row of the pixel circuits 20, and each shunt control sub-circuit 40 and one row of the pixel circuits 20 are electrically connected to one first scanning signal line G1. The third voltage signal line VG1 and the fourth voltage signal line VG2 are disposed in the peripheral region 10b.
The shunt control sub-circuit 40 is located in the peripheral region 10b, and does not affect the pixel arrangement density of the display region 10a, which is beneficial to improving the light transmittance of the display panel, i.e. the application of the present invention on the display panel 100 with high resolution pixels is not affected.
In yet another aspect, as shown in fig. 1, some embodiments of the invention provide a display device 1000, the display device 1000 comprising the display panel 100 of any one of the above.
The display device 1000 using the display panel 100 has the same advantageous effects as the display panel 100.
The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are also within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims (12)

1. A pixel circuit, comprising:
a write sub-circuit electrically connected to a data signal terminal and a scan signal terminal, the write sub-circuit configured to transmit a data signal received at the data signal terminal in response to a scan signal received at the scan signal terminal;
a driving sub-circuit electrically connected to the writing sub-circuit and a first voltage signal terminal, the driving sub-circuit configured to receive a data signal transmitted by the writing sub-circuit and generate a driving current under control of the data signal and a first voltage signal received at the first voltage signal terminal;
a shunt sub-circuit electrically connected to the driving sub-circuit, the write sub-circuit, a control signal terminal, and a second voltage signal terminal, the shunt sub-circuit configured to, in response to a control signal received at the control signal terminal, transmit a leakage voltage signal input by the write sub-circuit to the second voltage signal terminal in an off state of the write sub-circuit, so as to prevent the leakage voltage signal from being transmitted to the driving sub-circuit, and prevent the driving sub-circuit from leaking electricity to the second voltage signal terminal;
the shunt sub-circuit comprises a switch control sub-circuit and a unidirectional conduction sub-circuit;
the switch control sub-circuit is electrically connected with the write-in sub-circuit, the control signal terminal and the second voltage signal terminal, and the switch control sub-circuit is configured to be turned on when the write-in sub-circuit is in an off state, direct a leakage voltage of the write-in sub-circuit to the second voltage signal terminal, and be turned off when the write-in sub-circuit is in an on state under the control of the control signal; the node electrically connected with the switch control sub-circuit and the write-in sub-circuit is a fourth node;
the unidirectional turn-on sub-circuit is electrically connected between the fourth node and the driving sub-circuit, and the unidirectional turn-on sub-circuit is configured to cut off a current path leading from the driving sub-circuit to the second voltage signal terminal.
2. The pixel circuit of claim 1,
the driving sub-circuit comprises a driving transistor and a storage capacitor;
the control electrode of the driving transistor is electrically connected with the first node, the first electrode of the driving transistor is electrically connected with the second node, and the second electrode of the driving transistor is electrically connected with the third node; the first end of the storage capacitor is electrically connected with the first node, and the second end of the storage capacitor is electrically connected with the first voltage signal end;
the write sub-circuit includes a first transistor and a second transistor;
a control electrode of the first transistor is electrically connected with the scanning signal end, a first electrode of the first transistor is electrically connected with the data signal end, and a second electrode of the first transistor is electrically connected with the second node; and the control electrode of the second transistor is electrically connected with the scanning signal end, the first electrode of the second transistor is electrically connected with the third node, and the second electrode of the second transistor is electrically connected with the fourth node.
3. The pixel circuit of claim 2, wherein the unidirectional-conducting sub-circuit comprises a diode, an anode of the diode being electrically connected to the fourth node, and a cathode of the diode being electrically connected to the first node.
4. The pixel circuit according to claim 2 or 3, wherein the switch control sub-circuit comprises a switch transistor, a control electrode of the switch transistor is electrically connected to the control signal terminal, a first electrode of the switch transistor is electrically connected to the fourth node, and a second electrode of the switch transistor is electrically connected to a second voltage signal terminal.
5. The pixel circuit of claim 4, further comprising: the pixel circuit further comprises a light-emitting control sub-circuit and a reset sub-circuit;
the light-emitting control sub-circuit is electrically connected with the driving sub-circuit, the first voltage signal end, the light-emitting control signal end and the light-emitting device; the light emission control sub-circuit is configured to transmit the driving current to the light emitting device in response to a light emission control signal received at the light emission control signal terminal to cause the light emitting device to emit light during a light emission phase;
the light emitting control sub-circuit comprises a third transistor and a fourth transistor, wherein a control electrode of the third transistor is electrically connected with the light emitting control signal end, a first electrode of the third transistor is electrically connected with the first voltage signal end, and a second electrode of the third transistor is electrically connected with the second node; a control electrode of the fourth transistor is electrically connected with the light-emitting control signal end, a first electrode of the fourth transistor is electrically connected with the third node, and a second electrode of the fourth transistor is electrically connected with the light-emitting device;
the reset sub-circuit is electrically connected with the driving sub-circuit, the first reset signal end, the second reset signal end, the initialization signal end and the light-emitting device; the reset sub-circuit is configured to transmit an initialization signal received at the initialization signal terminal to the first node in response to a first reset signal received at the first reset signal terminal, and to transmit the initialization signal to the light emitting device in response to a second reset signal received at the second reset signal terminal;
the reset sub-circuit comprises a fifth transistor and a sixth transistor, wherein the control electrode of the fifth transistor is electrically connected with the first reset signal end, the first electrode of the fifth transistor is electrically connected with the initialization signal end, and the second electrode of the fifth transistor is electrically connected with the first node; the control electrode of the sixth transistor is electrically connected with the second reset signal end, the first electrode of the sixth transistor is electrically connected with the initialization signal end, and the second electrode of the sixth transistor is electrically connected with the light-emitting device.
6. A display panel, comprising: the array pixel structure comprises a plurality of sub-pixels, a plurality of data lines and a plurality of groups of grid lines, wherein each data line is electrically connected with one column of sub-pixels, and one group of grid lines is electrically connected with one row of sub-pixels;
each sub-pixel comprises a light emitting device and a pixel circuit as claimed in any one of claims 1 to 5.
7. The display panel according to claim 6, wherein the write sub-circuit in the pixel circuit is electrically connected to a scan signal terminal, and the shunt sub-circuit is electrically connected to a control signal terminal; the write subcircuit includes a second transistor, and the shunt subcircuit includes a switch transistor;
the group of grid lines comprises a first scanning signal line; the first scanning signal line is electrically connected with the writing sub-circuit through the scanning signal terminal, is also electrically connected with the shunt sub-circuit through the control signal terminal, and is configured to transmit a first scanning signal to the scanning signal terminal and transmit a control signal to the control signal terminal;
the conduction types of the second transistor and the switching transistor are opposite.
8. The display panel according to claim 6, wherein the write sub-circuit in the pixel circuit is electrically connected to a scan signal terminal, and the shunt sub-circuit is electrically connected to a control signal terminal; the write subcircuit includes a second transistor, and the shunt subcircuit includes a switch transistor;
the group of grid lines comprises a first scanning signal line and a second scanning signal line; the first scanning signal line is electrically connected with the writing sub-circuit through the scanning signal terminal, the first scanning signal line is configured to transmit a first scanning signal to the scanning signal terminal, the second scanning signal line is electrically connected with the shunt sub-circuit through the control signal terminal, the second scanning signal line is configured to transmit a control signal to the control signal terminal, and the levels of the first scanning signal and the control signal are opposite;
the conduction types of the second transistor and the switching transistor are the same.
9. The display panel according to claim 6, wherein the write sub-circuit in the pixel circuit is electrically connected to a scan signal terminal, and the shunt sub-circuit is electrically connected to a control signal terminal; the write subcircuit includes a second transistor, and the shunt subcircuit includes a switch transistor;
the group of grid lines comprises a first scanning signal line; the first scanning signal line is electrically connected with the writing sub-circuit through the scanning signal terminal, and the first scanning signal line is configured to transmit a first scanning signal to the scanning signal terminal;
the conduction types of the switch transistor and the second transistor are the same;
the display panel also comprises a shunt control sub-circuit; the input end of the shunt control sub-circuit is electrically connected with the first scanning signal line, the output end of the shunt control sub-circuit is electrically connected with the control signal end, and the shunt control sub-circuit is also electrically connected with a third voltage signal line and a fourth voltage signal line; the shunt control sub-circuit is configured to output a control signal having a level opposite to that of the first scan signal under control of the first scan signal, a third voltage signal transmitted by the third voltage signal line, and a fourth voltage signal transmitted by the fourth voltage signal line.
10. The display panel according to claim 9, wherein the current division control sub-circuit comprises:
a seventh transistor having a control electrode electrically connected to a fifth node, a first electrode electrically connected to the third voltage signal line, and a second electrode electrically connected to a sixth node;
a fifth transistor, a control electrode of which is electrically connected to the fifth node, a first electrode of which is electrically connected to the fourth voltage signal line, and a second electrode of which is electrically connected to the sixth node;
the fifth node is an input end of the shunt control sub-circuit, and the sixth node is an output end of the shunt control sub-circuit;
the seventh transistor is an N-type transistor, the eighth transistor is a P-type transistor, and the voltage of the third voltage signal is lower than the voltage of the fourth voltage signal; alternatively, the first and second electrodes may be,
the seventh transistor is a P-type transistor, the eighth transistor is an N-type transistor, and the voltage of the third voltage signal is higher than the voltage of the fourth voltage signal.
11. The display panel according to claim 9 or 10, wherein the display panel comprises a display region and a peripheral region disposed at least on one side of the display region, and the shunt control sub-circuit comprises a plurality of sub-circuits;
each shunt control sub-circuit is electrically connected with one pixel circuit, and the shunt control sub-circuits are arranged in the display area;
or each shunt control sub-circuit is electrically connected with one row of the pixel circuits, and the shunt control sub-circuits are arranged in the peripheral area.
12. A display device characterized by comprising the display panel according to any one of claims 6 to 11.
CN202111434174.5A 2021-11-29 2021-11-29 Pixel circuit, display panel and display device Active CN114078441B (en)

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