CN114974133A - Display panel and display device - Google Patents
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- CN114974133A CN114974133A CN202210744641.2A CN202210744641A CN114974133A CN 114974133 A CN114974133 A CN 114974133A CN 202210744641 A CN202210744641 A CN 202210744641A CN 114974133 A CN114974133 A CN 114974133A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3266—Details of drivers for scan electrodes
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
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- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
- Control Of El Displays (AREA)
Abstract
The invention discloses a display panel and a display device. The display panel includes: a display area and a non-display area surrounding the display area; the display area includes a plurality of rows of pixels arranged in a column direction; the non-display area comprises a first scanning driving circuit and a second scanning driving circuit, the first scanning driving circuit comprises a first scanning driving unit which is cascaded, and the second scanning driving circuit comprises a second scanning driving unit which is cascaded; the first-stage first scanning driving unit provides first scanning signals for two adjacent rows of pixels, and the second-stage second scanning driving unit provides second scanning signals for at least two interlaced rows of pixels. In the invention, the first-stage first scanning driving unit adopts a 1-drive-2 design, and the second-stage second scanning driving unit adopts a 1-drive-n (n is more than or equal to 2) design, so that the occupied area of the scanning driving unit on the frame can be reduced, and the narrow frame is realized.
Description
Technical Field
The invention relates to the technical field of display, in particular to a display panel and a display device.
Background
With the rapid development of display technology, people have higher and higher requirements on the performance and appearance of display devices. For example, a screen-to-very high full-face screen occupies almost a large percentage of the consumer market. Therefore, the frame occupation ratio of the display device is further reduced, and the frame occupation ratio is always a hot development direction of the current display screen.
In the current manufacturing process of display panels, how to reduce the frame occupation ratio of the display panels becomes a problem to be solved urgently.
Disclosure of Invention
The invention provides a display panel and a display device, which are used for realizing a narrow frame.
According to an aspect of the present invention, there is provided a display panel including: a display area and a non-display area surrounding the display area;
the display area comprises a plurality of rows of pixels arranged along a column direction;
the non-display area comprises a first scanning driving circuit and a second scanning driving circuit, the first scanning driving circuit comprises a first scanning driving unit which is cascaded, and the second scanning driving circuit comprises a second scanning driving unit which is cascaded;
the first scanning driving unit provides first scanning signals for two adjacent lines of pixels, and the second scanning driving unit provides second scanning signals for at least two lines of pixels.
According to another aspect of the present invention, there is provided a display device including the display panel as described above.
In the invention, the non-display area of the display panel comprises a first scanning driving circuit and a second scanning driving circuit, the first scanning driving circuit comprises cascaded first scanning driving units, and a first-stage first scanning driving unit provides a first scanning signal for two adjacent rows of pixels, so that the first-stage first scanning driving unit adopts a 1-drive-2 design, thereby reducing the number of the first scanning driving units in the non-display area; the second scanning driving circuit comprises cascaded second scanning driving units, the first-stage second scanning driving unit provides second scanning signals for at least two rows of pixels, and the first-stage second scanning driving unit adopts a 1-to-n (n is greater than or equal to 2) design, so that the number of the second scanning driving units in the non-display area is reduced. In the invention, the design that the number of the scanning driving units in the non-display area is 1 is more than that of the scanning driving units, so that the occupied area of the scanning driving units in the frame can be reduced, and the narrow frame is realized.
It should be understood that the statements in this section do not necessarily identify key or critical features of the embodiments of the present invention, nor do they necessarily limit the scope of the invention. Other features of the present invention will become apparent from the following description.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the description below are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a schematic diagram of a display panel according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of another display panel provided in an embodiment of the invention;
FIG. 3 is a schematic diagram of another display panel according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of another display panel according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of another display panel according to an embodiment of the present invention;
FIG. 6 is a schematic diagram of another display panel according to an embodiment of the present invention;
FIG. 7 is a schematic diagram of a pixel in a display panel according to an embodiment of the invention;
FIG. 8 is a timing diagram of a display panel according to an embodiment of the present invention;
FIG. 9 is a timing diagram of another display panel according to an embodiment of the present invention;
fig. 10 is a schematic diagram of a display device according to an embodiment of the present invention.
Detailed Description
In order to make the technical solutions of the present invention better understood, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that the terms "first," "second," and the like in the description and claims of the present invention and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the invention described herein are capable of operation in sequences other than those illustrated or described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
Fig. 1 is a schematic view of a display panel according to an embodiment of the present invention, and fig. 2 is a schematic view of another display panel according to an embodiment of the present invention. The present embodiment can be applied to any display panel, such as an organic light emitting display panel, but is not limited thereto. As shown in fig. 1 and 2, the display panel includes: a display area 11 and a non-display area 12 surrounding the display area 11; the display area 11 includes a plurality of rows of pixels 13 arranged in a column direction; the non-display area 12 includes a first scan driving circuit 21 and a second scan driving circuit 22, the first scan driving circuit 21 including a cascade of first scan driving units 23, the second scan driving circuit 22 including a cascade of second scan driving units 24; the one-stage first scan driving unit 23 supplies a first scan signal to the adjacent two rows of pixels 13, and the one-stage second scan driving unit 24 supplies a second scan signal to the interlaced at least two rows of pixels 13.
In this embodiment, the display area 11 of the display panel displays. The display region 11 includes a plurality of pixels 13 arranged in an array, and a plurality of rows of pixels 13 arranged in a column direction may be sequentially labeled as a1 st row pixel P1, a2 nd row pixel P2, a3 rd row pixel P3, a4 th row pixel P4, P5, P6, P7, P8, P9, P10, P11, and a 12 th row pixel P12, …. However, the pixel arrangement in the display panel is not limited to the array arrangement, and may be other pixel arrangements, which are not described herein again. The selectable pixels 13 comprise signal inputs such as SN1, with SN1 for the pixels of row 1 in fig. 2 referring to the signal input SN1 for each pixel in the row, and with SN1 for the pixels of row 1 referring to the signal input SN1 for each pixel in the row; the selectable pixel 13 further comprises a signal input such as SP2, the SP2 of the pixels of row 1 in fig. 2 referring to the signal input SP2 of each pixel in the row, connected to the SP2 of the pixels of row 1, i.e. to the signal input SP2 of each pixel in the row.
The non-display area 12 of the display panel is provided with circuit structures such as peripheral circuits for driving the pixels 13 of the display area 11 to perform display. The non-display region 12 includes a first scan driving circuit 21 and a second scan driving circuit 22, and the first scan driving circuit 21 and the second scan driving circuit 22 respectively supply scan signals to the plurality of rows of pixels 13 in the display region 11 to drive the display region 11 to perform display.
The first scan driving circuit 21 includes cascaded first scan driving units 23, and the cascaded first scan driving units 23 may be sequentially labeled as a1 st-stage first scan driving unit scan-a1, a2 nd-stage first scan driving unit scan-a2, a3 rd-stage first scan driving unit scan-a3, a4 th-stage first scan driving unit scan-a4, a5 th-stage first scan driving unit scan-a5, a6 th-stage first scan driving unit scan-a6, …. The one-stage first scan driving unit 23 supplies the first scan signal to the adjacent two rows of pixels 13, the signal input terminal SN1 of the selectable pixel 13 receives the first scan signal, and then the one-stage first scan driving unit 23 supplies the first scan signal to the SN1 of each pixel 13 in the adjacent two rows of pixels 13. Alternatively, the scan-a1 supplies a first scan signal to the SN1 of each pixel 13 in the adjacent P1 and P2; the scan-a2 supplies a first scan signal to the SN1 of each pixel 13 in the adjacent P3 and P4; the scan-a3 supplies a first scan signal to the SN1 of each pixel 13 in the adjacent P5 and P6; and so on.
The second scan driving circuit 22 includes cascaded second scan driving units 24, and the cascaded second scan driving units 24 may be sequentially labeled as a1 st-stage second scan driving unit scan-b1, a2 nd-stage second scan driving unit scan-b2, a3 rd-stage second scan driving unit scan-b3, a4 th-stage second scan driving unit scan-b4, a5 th-stage second scan driving unit scan-b5, a6 th-stage second scan driving unit scan-b6, …. The one-stage second scan driving unit 24 supplies the second scan signal to the pixels 13 of the at least two interlaced rows, the signal input terminal SP2 of the selectable pixel 13 receives the second scan signal, and then the one-stage second scan driving unit 24 supplies the second scan signal to the SP2 of each pixel 13 of the at least two interlaced rows of pixels 13. Alternatively, the scan-b1 provides the second scan signal to the SP2 of each pixel 13 in the interlaced P1 and P3; the scan-b2 supplies a second scan signal to the SP2 of each pixel 13 of the interlaced P2 and P4; the scan-b3 supplies a second scan signal to the SP2 of each pixel 13 of the interlaced P5 and P7; the scan-b4 supplies a second scan signal to the SP2 of each pixel 13 of the interlaced P6 and P8; and so on.
In the invention, a non-display area of a display panel comprises a first scanning driving circuit and a second scanning driving circuit, wherein the first scanning driving circuit comprises cascaded first scanning driving units, and a first-stage first scanning driving unit provides a first scanning signal for two adjacent rows of pixels, so that the first-stage first scanning driving unit adopts a 1-drive-2 design, thereby reducing the number of the first scanning driving units in the non-display area; the second scanning driving circuit comprises cascaded second scanning driving units, the first-stage second scanning driving unit provides second scanning signals for at least two lines of pixels, and the first-stage second scanning driving unit adopts a 1-drive-n (n is greater than or equal to 2) design, so that the number of the second scanning driving units in the non-display area is reduced. In the invention, the design that the number of the scanning driving units in the non-display area is 1 is more than that of the scanning driving units, so that the occupied area of the scanning driving units in the frame can be reduced, and the narrow frame is realized.
The selectable pixels comprise reset control terminals; the output end of the ith-stage first scanning driving unit is electrically connected with the reset control ends of the 2i-1 th and 2i th row pixels, the value of i is a positive integer which is greater than or equal to 1, and the first scanning signal is a reset control signal.
Referring to fig. 2, the signal input SN1 of the selectable pixel is a reset control terminal, the reset control SN1 of the pixel is used for receiving a reset control signal, and when the reset control signal received by the reset control SN1 of the pixel is an active reset signal, the pixel will perform a reset operation. The output end of the ith stage first scan driving unit 23 is electrically connected to the reset control ends SN1 of the 2i-1 th and 2 i-th row pixels, so that the first scan signal output to the pixels by the first scan driving unit 23 is a reset control signal. The first scan driving unit 23 simultaneously provides the reset control signals to the reset control terminals SN1 of the pixels in two adjacent rows, and the pixels in the two adjacent rows can synchronously perform the reset operation when the reset control signals are valid reset signals. Then, the first scan driving unit 23 at one stage drives two rows of pixels to perform a reset operation by using a 1-to-2 design, so that the number of the first scan driving units 23 in the non-display area can be reduced, and a narrow frame can be realized.
Specifically, the 1 st-stage first scan driving unit scan-a1 is connected to the reset control terminal SN1 of each pixel in the 1 st and 2 nd rows of pixels P1& P2 and provides a reset control signal, scan-a2 is connected to the reset control terminal SN1 of each pixel in the 3 rd and 4 th rows of pixels P3& P4 and provides a reset control signal, scan-a3 is connected to the reset control terminal SN1 of each pixel in the 5 th and 6 th rows of pixels P5& P6 and provides a reset control signal, and so on.
The selectable reset control signal is a pulse signal. The first scan driving circuit includes cascaded first scan driving units 23, and the cascaded first scan driving units 23 sequentially output an effective reset signal. The reset process of the rows of pixels in the display area is that scan-a1 provides an active reset signal to make the 1 st and 2 nd row pixels P1& P2 perform the reset operation simultaneously; sequentially, scan-a2 provides an active reset signal to cause the pixels P3& P4 of rows 3 and 4 to perform reset operations simultaneously; sequentially, scan-a3 provides an active reset signal causing row 5 and row 6 pixels P5& P6 to perform a reset operation simultaneously, and so on.
The selectable pixels comprise compensation control terminals; the output end of the ith-stage first scanning driving unit is electrically connected with the compensation control ends of the 2i-1 th and 2i th row pixels, the value of i is a positive integer which is greater than or equal to 1, and the first scanning signal is a compensation control signal.
Fig. 3 is a schematic diagram of another display panel according to an embodiment of the present invention. As shown in fig. 3, the selectable pixel 13 further comprises a signal input SN2, the SN2 of the pixels of row 1 in fig. 3 refers to the signal input SN2 of each pixel in the row, and the connection to the SN2 of the pixels of row 1 refers to the connection to the signal input SN2 of each pixel in the row.
Referring to fig. 3, the signal input terminal SN2 of the selectable pixel is a compensation control terminal, the compensation control terminal SN2 of the pixel is used for receiving a compensation control signal, and when the compensation control signal received by the compensation control terminal SN2 of the pixel is an effective compensation signal, the pixel performs a threshold compensation operation. The output terminal of the ith-stage first scan driving unit 23 is electrically connected to the compensation control terminals SN2 of the 2i-1 and 2 i-th rows of pixels, so that the first scan signal output by the first scan driving unit 23 to the pixels is the compensation control signal. The first scan driving unit 23 provides the compensation control signals to the compensation control terminals SN2 of two adjacent rows of pixels, so that the two adjacent rows of pixels can synchronously perform the threshold compensation operation when the compensation control signals are effective compensation signals. Then, the first scan driving unit 23 at one stage drives two rows of pixels to perform the threshold compensation operation by using the design of 1 driving 2, so that the number of the first scan driving units 23 in the non-display area can be reduced, and a narrow frame can be realized.
Specifically, the 1 st-stage first scan driving unit scan-a1 connects the compensation control terminals SN2 of the pixels in the 1 st and 2 nd rows of pixels P1& P2 and provides a compensation control signal, scan-a2 connects the compensation control terminals SN2 of the pixels in the 3 rd and 4 th rows of pixels P3& P4 and provides a compensation control signal, scan-a3 connects the compensation control terminals SN2 of the pixels in the 5 th and 6 th rows of pixels P5& P6 and provides a compensation control signal, and so on.
The optional compensation control signal is a pulsed signal. The first scan driving circuit includes cascaded first scan driving units 23, and the cascaded first scan driving units 23 sequentially output effective compensation signals. The threshold compensation process for the rows of pixels in the display area is that scan-a1 provides an effective compensation signal to make the 1 st and 2 nd row pixels P1& P2 perform the threshold compensation operation simultaneously; sequentially, the scan-a2 provides an effective compensation signal to cause the pixels P3& P4 of the 3 rd and 4 th rows to simultaneously perform the threshold compensation operation; sequentially, scan-a3 provides an active compensation signal that causes pixels P5& P6 in rows 5 and 6 to perform the threshold compensation operation simultaneously, and so on.
As described above, alternatively, the first scan driving circuit may be used as a reset control circuit of the pixel as shown in fig. 2, wherein the first scan signal output by each stage of the first scan driving unit 23 is the reset control signal provided to the reset control terminal SN1 of the pixel. Alternatively, the first scan driving circuit can be used as a compensation control circuit for the pixel as shown in fig. 3, wherein the first scan signal output by each stage of the first scan driving unit 23 is a compensation control signal provided to the compensation control terminal SN2 of the pixel.
Fig. 4 is a schematic diagram of another display panel according to an embodiment of the present invention. As shown in fig. 4, the non-display area may also optionally include two different sets of first scan driving circuits scan-a and scan-c.
Specifically, the first scan driving circuit scan-a can be used as a reset control circuit of the pixel, wherein the first scan signals output by the first scan driving units (scan-a1, scan-a2, scan-a3, scan-a4, …) of each stage are reset control signals provided for the reset control terminal SN1 of the pixel, the output terminal of the ith stage of first scan driving unit is electrically connected with the reset control terminals SN1 of the 2 i-th and 2 i-th row pixels, and the first stage of first scan driving unit adopts a design of 1 driving the pixels of the adjacent 2 rows, so that the number of the first scan driving units in the first scan driving circuit scan-a can be reduced, and a narrow frame can be realized.
In addition, the first scan driving circuit scan-c can be used as a compensation control circuit of the pixel, wherein the first scan signals output by the first scan driving units (scan-c1, scan-c2, scan-c3, scan-c4, …) of each stage are compensation control signals provided for the compensation control terminal SN2 of the pixel, the output terminal of the ith stage of first scan driving unit is electrically connected with the compensation control terminals SN2 of the 2i-1 and 2 i-th row of pixels, and the first scan driving unit of one stage adopts a design of 1 driving the pixels of the adjacent 2 rows, so that the number of the first scan driving units in the first scan driving circuit scan-c can be reduced, and a narrow frame can be realized.
The selectable pixel comprises a reset control terminal and a compensation control terminal; the output end of the ith-stage first scanning driving unit is electrically connected with the reset control ends of the pixels in the 2i-1 th and 2 i-th rows; the output end of the ith-stage first scanning driving unit is also electrically connected with the compensation control ends of the pixels in the 2i-3 th and 2i-2 nd rows; i is a positive integer greater than or equal to 1.
Fig. 5 is a schematic diagram of another display panel according to an embodiment of the present invention. As shown in fig. 5, the selectable pixel includes signal inputs SN1 and SN2, where SN1 is the reset control terminal and SN2 is the compensation control terminal. The pixel reset control terminal SN1 is used for receiving a reset control signal, and when the reset control signal received by the pixel reset control terminal SN1 is an active reset signal, the pixel will perform a reset operation. The compensation control terminal SN2 of the pixel is used for receiving the compensation control signal, and when the compensation control signal received by the compensation control terminal SN2 of the pixel is an effective compensation signal, the pixel performs a threshold compensation operation.
The output terminal of the optional ith-stage first scan driving unit 23 is electrically connected to the reset control terminals SN1 of the pixels in the 2i-1 th and 2 i-th rows, and the output terminal of the ith-stage first scan driving unit 23 is also electrically connected to the compensation control terminals SN2 of the pixels in the 2i-3 th and 2i-2 nd rows. Based on this, the first scan driving circuit serves as a reset control circuit for the pixel, and is also multiplexed as a compensation control circuit for the pixel. The first scan signals output by the first scan driving units 23 at different stages are not only used as the reset control signals provided to the reset control terminals SN1 of the pixels, but also multiplexed as the compensation control signals provided to the compensation control terminals SN2 of the pixels.
It can be understood that the output terminal of the 1 st stage first scan driving unit 23 is electrically connected to the reset control terminal SN1 of the pixels P1& P2 of the 1 st and 2 nd rows only; the output terminal of the last stage 1 first scan driving unit 23 is electrically connected to the compensation control terminals SN2 of only the last 2 rows of pixels. For example, as shown in fig. 5, the display panel includes 12 rows of pixels, the first scan driving circuit includes 7 cascaded stages of the first scan driving unit 23, and the output terminal of the 1 st stage first scan driving unit scan-a1 is electrically connected to the reset control terminal SN1 of the 1 st and 2 nd rows of pixels P1& P2; the output terminal of the 7 th stage first scan driving unit scan-a7 is electrically connected with the compensation control terminal SN2 of the pixels P11& P12 of the 11 th and 12 th rows; when i is not less than 2 and not more than 6, the output terminal of the i-th stage first scan driving unit 23 is electrically connected to the reset control terminals SN1 of the 2i-1 and 2 i-th rows of pixels, and the output terminal of the i-th stage first scan driving unit is also electrically connected to the compensation control terminals SN2 of the 2i-3 and 2i-2 th rows of pixels. It should be noted that the 1 st stage first scan driving unit and the last 1 st stage first scan driving unit are dummy scan driving units responsible for filling the table blank, so the output tubes of the dummy scan driving units can be drawn very small, and the frame can be reduced. For example, output tubes of other scan units are usually W/L192 um/4um, while output tubes of dummy scan driving units can be designed to be 8um/4um, which greatly reduces the size of the scan unit.
Specifically, the 1 st-stage first scan driving unit scan-a1 is connected to the reset control terminal SN1 of each pixel in the 1 st and 2 nd rows of pixels P1& P2, scan-a2 is connected to the reset control terminal SN1 of each pixel in the 3 rd and 4 th rows of pixels P3& P4, scan-a3 is connected to the reset control terminal SN1 of each pixel in the 5 th and 6 th rows of pixels P5& P6, and so on. Meanwhile, the 2 nd-stage first scan driving unit scan-a2 is connected to the compensation control terminal SN2 of each pixel in the 1 st and 2 nd rows of pixels P1& P2, scan-a3 is connected to the compensation control terminal SN2 of each pixel in the 3 rd and 4 th rows of pixels P3& P4, scan-a4 is connected to the compensation control terminal SN2 of each pixel in the 5 th and 6 th rows of pixels P5& P6, and so on.
The first scanning signal may be selected to be a pulse signal. The first scan signal includes an active pulse signal and an inactive pulse signal.
The working process of a plurality of rows of pixels in the display area is as follows: the first scanning signal output by the scan-a1 is an effective pulse signal, so that each pixel in P1 and P2 simultaneously executes reset operation; sequentially, the first scan signal output by the scan-a2 is an active pulse signal, so that the pixels in P3 and P4 simultaneously perform the reset operation, and the pixels in P1 and P2 simultaneously perform the threshold compensation operation; sequentially, the first scan signal output by the scan-a3 is an active pulse signal, so that the pixels in P5 and P6 simultaneously perform the reset operation, and the pixels in P3 and P4 simultaneously perform the threshold compensation operation; sequentially, the first scan signal output by the scan-a4 is an active pulse signal, so that the pixels in P7 and P8 simultaneously perform the reset operation, and the pixels in P5 and P6 simultaneously perform the threshold compensation operation; and so on.
As described above, the first scan driving circuit serves as both the reset control circuit and the compensation control circuit, and the first scan driving unit of the first stage adopts a design of 1 drive, which can reduce the occupied area of the scan driving circuit in the non-display region and realize a narrow frame.
The selectable pixels include a write control terminal; the display area comprises a plurality of pixel groups arranged along the column direction, the cascaded second scanning driving unit comprises a plurality of second scanning driving groups which are respectively arranged corresponding to the pixel groups, the second scanning driving group comprises two cascaded second scanning driving units, the pixel groups comprise adjacent 2x rows of pixels, and x is a positive integer; in the second scanning driving group, the first 1-stage second scanning driving unit provides a second scanning signal to the writing control end of the odd-numbered pixels in the corresponding pixel group, and the last 1-stage second scanning driving unit provides a second scanning signal to the writing control end of the even-numbered pixels in the corresponding pixel group. The alternative x is 2.
Referring to fig. 5, the selectable pixel 13 further includes a signal input terminal SP2, the SP2 of the pixels of row 1 in fig. 5 refers to the signal input terminal SP2 of each pixel in the row, and the connection with the SP2 of the pixels of row 1 refers to the connection with the signal input terminal SP2 of each pixel in the row. The signal input terminal SP2 of the selectable pixel is a write control terminal, the write control terminal SP2 of the pixel is used for receiving a write control signal, and when the write control signal received by the write control terminal SP2 of the pixel is an active write signal, the pixel performs a data write operation.
The plurality of rows of pixels in the display area are divided into a plurality of pixel groups arranged in a column direction, and each pixel group comprises adjacent 2x rows of pixels. The alternative x is 2, and one pixel group includes 4 adjacent rows of pixels. As shown in fig. 5, row 1 pixels P1 through row 4 pixels P4 form a row 1 pixel group 131, sequentially row 5 pixels P5 through row 8 pixels P8 form a row 2 pixel group 132, sequentially row 9 pixels P9 through row 12 pixels P12 form a row 3 pixel group 133, and so on. The display area includes a plurality of pixel groups arranged in a column direction.
The second scan driving units 24 cascaded in the second scan driving circuit are divided into a plurality of second scan driving groups, and each second scan driving group includes two second scan driving units 24 cascaded. As shown in fig. 5, the non-display area includes at least 3 second scan driving groups, which are a second scan driving group 241, a second scan driving group 242, and a second scan driving group 243.
The second scan driving group 241 includes two cascaded second scan driving units scan-b1 and scan-b2, the second scan driving group 241 corresponds to the 1 st pixel group 131, and the two cascaded second scan driving units scan-b1 and scan-b2 drive the 1 st to 4 th rows of pixels P1 to P4. The first-stage second scan driving unit 24 supplies the second scan signal to the pixels 13 of at least two interlaced rows, and then the second scan driving unit scan-b1 connects the write control terminals SP2 of the pixels P1 and P3 of the 1 st row and the pixels P8526 of the 3 rd row and supplies the second scan signal, and the second scan driving unit scan-b2 connects the write control terminals SP2 of the pixels P2 and P4 of the 4 th row and supplies the second scan signal.
The second scan driving group 242 includes two cascaded second scan driving units scan-b3 and scan-b4, the second scan driving group 242 corresponds to the 2 nd pixel group 132, and the two cascaded second scan driving units scan-b3 and scan-b4 drive the pixels P5 of the 5 th row to the pixels P8 of the 8 th row. The first-stage second scan driving unit 24 supplies the second scan signal to the pixels 13 of at least two interlaced rows, and then the second scan driving unit scan-b3 connects the write control terminals SP2 of the pixels P5 of the 5 th row and the pixels P7 of the 7 th row and supplies the second scan signal, and the second scan driving unit scan-b4 connects the write control terminals SP2 of the pixels P6 of the 6 th row and the pixels P8 of the 8 th row and supplies the second scan signal.
The second scan driving group 243 includes two cascaded second scan driving units scan-b5 and scan-b6, the second scan driving group 243 corresponds to the 3 rd pixel group 133, and the two cascaded second scan driving units scan-b5 and scan-b6 drive the 9 th to 12 th row pixels P9 to P12. The first-stage second scan driving unit 24 supplies the second scan signal to the pixels 13 of at least two interlaced rows, and then the second scan driving unit scan-b5 connects the write control terminals SP2 of the pixels P9 of the 9 th row and the pixels P11 of the 11 th row and supplies the second scan signal, and the second scan driving unit scan-b6 connects the write control terminals SP2 of the pixels P10 of the 10 th row and the pixels P12 of the 12 th row and supplies the second scan signal.
The output end of the second scan driving unit 24 is electrically connected to the write control end SP2 of two interlaced rows of pixels, and the second scan signal output by the second scan driving unit 24 to the pixels is the write control signal. The second scanning signal is selected to be a pulse signal, and the second scanning signal comprises an effective writing signal and an ineffective writing signal. The cascaded second scan driving units 24 sequentially output valid write signals to drive a plurality of rows of pixels to perform a data write operation. The one-stage second scanning driving unit 24 simultaneously supplies the writing control signal to the writing control terminal SP2 of every pixel of every two interlaced lines, and the data writing operation can be synchronously performed for every pixel of every two interlaced lines when the writing control signal is the effective writing signal.
Based on this, the data writing process of a plurality of rows of pixels in the display area is that scan-b1 outputs an effective writing signal to enable each pixel in P1 and P3 to simultaneously execute data writing operation; sequentially, scan-b2 outputs an active write signal to cause each pixel in P2 and P4 to simultaneously perform a data write operation; sequentially, scan-b3 outputs an active write signal to cause each pixel in P5 and P7 to simultaneously perform a data write operation; sequentially, scan-b4 outputs an active write signal to cause each pixel in P6 and P8 to simultaneously perform a data write operation; sequentially, scan-b5 outputs an active write signal to cause each pixel in P9 and P11 to simultaneously perform a data write operation; sequentially, scan-b6 outputs an active write signal to cause each pixel in P10 and P12 to simultaneously perform a data write operation; and so on.
As described above, the second scan driving circuit can be used as a writing control circuit for pixels, wherein the second scan signal output by each stage of the second scan driving unit 24 is a writing control signal provided to the writing control terminal SP2 of the pixel, and the one-stage second scan driving unit 24 simultaneously drives two rows of pixels to perform a data writing operation by adopting a 1-to-2 design, so that the number of the second scan driving units 24 in the non-display area can be reduced, and a narrow frame can be realized.
The selectable pixels include a write control terminal; the display area comprises a plurality of pixel groups arranged along the column direction, the cascaded second scanning driving unit comprises a plurality of second scanning driving groups which are respectively arranged corresponding to the pixel groups, the second scanning driving group comprises two cascaded second scanning driving units, the pixel groups comprise adjacent 2x rows of pixels, and x is a positive integer; in the second scanning driving group, the first 1-stage second scanning driving unit provides a second scanning signal to the writing control end of the odd-numbered pixels in the corresponding pixel group, and the second 1-stage second scanning driving unit provides a second scanning signal to the writing control end of the even-numbered pixels in the corresponding pixel group. The alternative x is 3.
Fig. 6 is a schematic diagram of another display panel according to an embodiment of the present invention. Fig. 6 differs from fig. 5 in that x is 3. Each pixel group comprises 2x adjacent rows of pixels and one pixel group comprises 6 adjacent rows of pixels. Where row 1 pixels P1 through row 6 pixels P6 form row 1 pixel group 134, sequentially row 7 pixels P7 through row 12 pixels P12 form row 2 pixel group 135, and so on. The display area includes a plurality of pixel groups arranged in a column direction.
Each of the second scan driving groups includes two second scan driving units 24 cascaded. The non-display area includes at least a second scan driving group 244 corresponding to the 1 st pixel group 134, and a second scan driving group 245 corresponding to the 2 nd pixel group 135, and so on.
Two second scan driving units scan-b1 and scan-b2 cascaded in the second scan driving group 244 are used to drive P1 to P6 in the 1 st pixel group 134. The primary second scan driving unit 24 supplies the second scan signal to the pixels 13 of at least two interlaced rows, then scan-b1 connects the write control terminals SP2 of P1, P3 and P5 and supplies the second scan signal, and scan-b2 connects the write control terminals SP2 of P2, P4 and P6 and supplies the second scan signal.
Two second scan driving units scan-b3 and scan-b4 cascaded in the second scan driving group 245 are used to drive P7 to P12 in the 2 nd pixel group 135. The primary second scan driving unit 24 supplies the second scan signal to the pixels 13 of at least two interlaced rows, then scan-b3 connects the write control terminals SP2 of P7, P9 and P11 and supplies the second scan signal, and scan-b4 connects the write control terminals SP2 of P8, P10 and P12 and supplies the second scan signal.
Based on this, the data writing process of a plurality of rows of pixels in the display area is that scan-b1 outputs effective writing signals to enable each pixel in P1, P3 and P5 to simultaneously execute data writing operation; sequentially, the scan-b2 outputs an active write signal to cause each pixel in P2, P4, and P6 to simultaneously perform a data write operation; sequentially, the scan-b3 outputs an active write signal to cause each pixel in P7, P9, and P11 to simultaneously perform a data write operation; sequentially, the scan-b4 outputs an active write signal, causing each pixel in P8, P10, and P12 to simultaneously perform a data write operation, and so on.
As described above, the second scan driving circuit can be used as a writing control circuit for pixels, and the first-stage second scan driving unit 24 adopts a 1-to-3 design to simultaneously drive 3 rows of pixels to perform data writing operation, so that the number of the second scan driving units 24 in the non-display area can be reduced, and a narrow frame can be realized.
The selectable pixels include a pixel circuit and a light emitting element; the pixel circuit comprises a driving module, a data writing module, a resetting module and a compensating module; the data writing module is connected between the data signal line and the first end of the driving module; the reset module is connected between the reset signal line and the control end of the drive module; the compensation module is connected between the second end and the control end of the driving module; the second end of the driving module is coupled with the light-emitting element; the control end of the reset module is electrically connected with the output end of the first scanning driving unit, the control end of the compensation module is electrically connected with the output end of the next-stage first scanning driving unit, and the control end of the data writing module is electrically connected with the output end of the second scanning driving unit.
Fig. 7 is a schematic diagram of a pixel in a display panel according to an embodiment of the invention. As shown in fig. 5 and 7 in combination, the selectable pixel includes a pixel circuit 31 and a light emitting element 32; the pixel circuit 31 includes a driving module 33, a data writing module 34, a resetting module 35, and a compensation module 36.
The first end N2 of the driving module 33 is coupled to the power voltage terminal PVDD, and the second end N3 of the driving module 33 is coupled to the light emitting device 32. The driving module 33 is used for providing a driving current for the light emitting element 32.
The data writing module 34 is connected between the data signal line Vdata and the first end N2 of the driving module 33, and the control end of the data writing module 34 is a writing control end of the pixel and is electrically connected to the output end of the second scan driving unit 24. The second scan driving unit 24 provides a second scan signal to the control terminal of the data writing module 34, when the second scan signal is an active writing signal, the data writing module 34 is turned on, and the data signal of the data signal line Vdata is written into the first terminal N2 of the driving module 33 through the data writing module 34; further, if the driving module 33 and the compensation module 36 are turned on, the data signal of the data signal line Vdata is written into the control terminal N1 of the driving module 33.
The reset module 35 is connected between the reset signal line Vref and the control terminal N1 of the driving module 33, and the control terminal of the reset module 35 is the reset control terminal of the pixel and is electrically connected to the output terminal of the first scan driving unit 23. The first scan driving unit 23 provides a first scan signal to the control terminal of the reset module 35, when the first scan signal is an effective reset signal, the reset module 35 is turned on, and the reset signal of the reset signal line Vref resets the control terminal N1 of the driving module 33; further, if the driving module 33 and the compensation module 36 are turned on, the reset signal of the reset signal line Vref resets N1, N2, and N3 of the driving module 33.
The compensation module 36 is connected between the second terminal N3 and the control terminal N1 of the driving module 33, and the control terminal of the compensation module 36 is a compensation control terminal of the pixel and is electrically connected to the output terminal of the next-stage first scan driving unit 23. The first scan driving unit 23 provides a first scan signal to the control terminal of the compensation module 36, and when the first scan signal is an effective scan signal, the compensation module 36 is turned on; the signal at the second terminal N3 of the driving module 33 is written into the control terminal N1 of the driving module 33, or the signal at the control terminal N1 of the driving module 33 is written into the second terminal N3 of the driving module 33.
In this embodiment, the first scan driving circuit is multiplexed into a reset control circuit and a compensation control circuit, and the first scan signal output by the first scan driving circuit controls the reset module 35 of the pixel and also controls the compensation module 36 of the pixel. In other embodiments, the optional non-display area includes two sets of independent first scan driving circuits scan-a and scan-c as shown in fig. 4; one set of the first scan driving circuits scan-a is used as a reset control circuit, and the first-stage scan driving unit scan-a provides a reset control signal for the reset control terminals SN1 of two adjacent rows of pixels; the other set of first scan driving circuits scan-c is used as a compensation control circuit, and the first scan driving unit scan-c of one stage provides a compensation control signal to the compensation control terminals SN2 of two adjacent rows of pixels.
The optional driving module 33 includes a driving transistor M1, the data writing module 34 includes a data writing transistor M2, the reset module 35 includes a reset transistor M3, and the compensation module 36 includes a compensation transistor M4; the driving transistor M1 and the data writing transistor M2 are P-type transistors, and the reset transistor M3 and the compensation transistor M4 are N-type transistors. The optional reset transistor and the compensation transistor are IGZO-TFTs.
The selectable pixel circuit 31 also includes a light emission control module 37 and an initialization module 38. The light emission control module 37 includes a first light emitting transistor M5 and a second light emitting transistor M6; the first light emitting transistor M5 is connected between the power supply voltage terminal PVDD and the first terminal N2 of the driving transistor M1, and the control terminal of the first light emitting transistor M5 is electrically connected to the light emission control signal line E1; the second light emitting transistor M6 is connected between the second terminal N3 of the driving transistor M1 and the light emitting element 32, and the control terminal of the second light emitting transistor M6 is electrically connected to the light emitting control signal line E1; in other embodiments, the first light emitting transistor M5 and the second light emitting transistor M6 may be electrically connected to different light emitting control signal lines. The initialization module 38 includes an initialization transistor M7; the initialization transistor M7 is connected between the reset signal line Vref and the light emitting element 32, and the control terminal of the initialization transistor M7 is electrically connected to the second scan driving unit scan-b; in other embodiments, the input terminal of the initialization transistor M7 may be connected to an initialization signal line different from the reset signal line Vref, and the control terminal of the initialization transistor M7 may be connected to a scan driving unit different from the second scan driving unit.
It is understood that the structure of the pixel circuit in the display panel is not limited to that shown in fig. 7, and the pixel circuit suitable for the display panel falls within the scope of the present invention.
The operation of the selectable pixel circuit 31 includes a reset phase and a data write phase; in the reset phase, the reset module 35 is turned on, and the reset signal provided by the reset signal line Vref is input to the control terminal N1 of the driving module 33; in the data writing phase, the data writing module 34 and the compensation module 36 are turned on, and the data signal provided by the data signal line Vdata is written into the control terminal N1 of the driving module 33.
The output end of the optional ith-stage first scanning driving unit 23 is electrically connected with the control end SN1 of the reset module 35 in the 2i-1 th and 2 i-th row pixels; while the 2i-1 and 2 i-th row pixels are in the reset phase, the 2i-3 and 2i-2 row pixels sequentially perform a data write phase. The start times of the output effective signals of the first scan driving units 23 of the two stages which are optionally adjacent differ by a first period T1; the first width of the effective signal output by the first-stage first scan driving unit 23 is W1; t1 ═ W1. The start time of the valid signal output by the two stages of second scan driving units 24 which are adjacent to each other selectively differs by a second period T2; the second width of the effective signal output by the first-stage second scanning driving unit is W2; t2 is more than or equal to W2. The start times of the output effective signals of the first scan driving units 24 of the two stages which are optionally adjacent differ by a first period T1; the start time of the effective signal output by the two adjacent stages of the second scan driving units 24 differs by a second period T2; t1-2 × T2.
Fig. 8 is a timing diagram of a display panel according to an embodiment of the present invention, and in the display panel corresponding to fig. 8, a design of driving 1 and driving 2 is adopted for a first-stage second scan driving unit. Fig. 9 is a timing diagram of another display panel according to an embodiment of the present invention, and in the display panel corresponding to fig. 9, the first-stage second scan driving unit adopts a design of 1-drive-3.
In this embodiment, the timing sequence of the display panel is described by taking the design of the first-stage second scan driving unit scan-b in fig. 8 using 1-to-2 as an example. As shown in fig. 5, 7 and 8, the first scan driving unit scan-a and the second scan driving unit scan-b both adopt a 1-drive 2 design, scan-a connects two adjacent rows of pixels, and scan-b connects two interlaced rows of pixels, so that the effective pulse signal output by scan-a spans two consecutive rows in time sequence, the effective pulse signal output by scan-b is one row in time sequence, and the pixel charging is performed by using the overlapping time of scan-a and scan-b, thereby saving the number of scan driving units in the non-display area. While the 2i-1 and 2 i-th row pixels are in the reset phase, the 2i-3 and 2i-2 row pixels sequentially perform a data write phase.
The driving timing of the display panel is as follows:
in the stage ta, when the scan-b1 outputs a low level, each pixel in P1 and P3 performs operation, specifically, when the data writing transistor M2 of the pixel circuit is turned on, the Vdata voltage of the Vdata signal line Vdata is written into the first terminal N2 of the driving transistor M1, so as to reset the data of the N2 node of the driving transistor M1 in P1 and P3, thereby improving the first frame brightness problem during black and white cut, i.e., the problem of image switching smear retention. Through the reset of the data voltage to the N2 node of the driving transistor M1 in P1 and P3, the data voltage of the current picture can be biased to the driving transistor M1 in advance, and the state of the first end N2 of the driving transistor M1 of each pixel in P1 and P3 is set to the state of the current picture in advance.
the tb stage, scan-b2 outputs a low level, performs the operation of the P1 and P3 in the same ta stage for each pixel of P2 and P4, i.e., Vdata reset for the N2 node of the driving transistor M1 in P2 and P4, biases the driving transistor M1 by the Vdata voltage, and sets the state of the first terminal N2 of the driving transistor M1 of each pixel of P2 and P4 to the state of the current picture in advance.
In the stage t1, when the scan-a2 outputs a high level and the scan-b1 outputs a low level, the compensation transistors M4 of the P1 and the P2 are turned on, the data writing transistors M2 of the P1 and the P3 are turned on, and the Vdata voltage is written into the control terminal N1 of the driving transistor M1 of the P1 to perform Vth compensation on the N1 node of the driving transistor M1; meanwhile, the reset transistors M3 of P3 and P4 are turned on, and the Vref voltage resets the control terminal N1 of the driving transistor M1 of P3 and P4.
In the stage t2, when the scan-a2 outputs a high level and the scan-b2 outputs a low level, the compensation transistors M4 of the P1 and the P2 are turned on, the data writing transistors M2 of the P2 and the P4 are turned on, and the Vdata voltage is written into the control terminal N1 of the driving transistor M1 of the P2 to perform Vth compensation on the N1 node of the driving transistor M1; meanwhile, the reset transistors M3 of P3 and P4 remain turned on, and the Vref voltage continues to reset the control terminal N1 of the driving transistor M1 of P3 and P4.
At the stage t3, when the scan-a3 outputs high level, the scan-b1 and scan-b3 output low level, the compensation transistors M4 of the P3 and P4 are turned on, the data writing transistors M2 of the P1, P3, P5 and P7 are turned on, and Vdata voltage is written into the control terminal N1 of the driving transistor M1 of the P3 to perform Vth compensation on the N1 node of the driving transistor M1; meanwhile, the reset transistors M3 of P5 and P6 are turned on, and the Vref voltage resets the control terminal N1 of the driving transistor M1 of P5 and P6; meanwhile, the Vdata voltage is written into the first end N2 of the driving transistor M1 of the P1, the brightness difference between a low-frequency writing data frame and a maintaining frame can be improved, the flicker characteristic is improved, a low pulse still exists in the maintaining frame scan-b1, and a certain set voltage reset is carried out on the N2 node.
At the stage t4, when the scan-a3 outputs high level, the scan-b2 and scan-b4 output low level, the compensation transistors M4 of the P3 and P4 are turned on, the data writing transistors M2 of the P2, P4, P6 and P8 are turned on, and Vdata voltage is written into the control terminal N1 of the driving transistor M1 of the P4 to perform Vth compensation on the N1 node of the driving transistor M1; meanwhile, the reset transistors M3 of P5 and P6 remain turned on, and the Vref voltage continues to reset the control terminal N1 of the driving transistor M1 of P5 and P6.
At the stage t5, when the scan-a4 outputs high level, the scan-b1 and scan-b3 output low level, the compensation transistors M4 of the P5 and P6 are turned on, the data writing transistors M2 of the P1, P3, P5 and P7 are turned on, and Vdata voltage is written into the control terminal N1 of the driving transistor M1 of the P5 to perform Vth compensation on the N1 node of the driving transistor M1; meanwhile, the reset transistors M3 of P7 and P8 are turned on, and the Vref voltage resets the control terminal N1 of the driving transistor M1 of P7 and P8. The OBS after the Vdata voltage is written is performed on P3, thereby improving the low-frequency flicker characteristic of the pixel.
And in the same way, the first scanning driving circuit and the second scanning driving circuit drive a plurality of rows of pixels in the display area to work.
In this embodiment, when the P3 and the P4 perform the reset operation of the control terminal N1 of the driving transistor M1, the Vdata voltage sequentially performs Vth compensation on the N1 node of the driving transistor M1 of the P1 and the P2. When the P5 and the P6 perform the reset operation of the control terminal N1 of the driving transistor M1, the Vdata voltage sequentially performs Vth compensation on the N1 node of the driving transistor M1 of the P3 and the P4. And so on.
As described above, for the LTPO mainly applied to low frequencies, a setting is set in the timing to specifically improve the low frequency characteristics and the low frequency smear problem. That is, while the second scan driving unit performs 1-drive more, the pulse of the second scan driving unit is set in advance, and the Vdata voltage is written into the node N2. The reset of the node N2 can not only improve the lag problem during the picture switching, but also improve the smear problem during the low-frequency picture switching, and can improve the brightness difference between the data frame and the holding frame, and the voltage Vdata is written into the node N2 to realize the OBS bias voltage of the driving transistor, thereby improving the low-frequency flicker.
Based on the same inventive concept, an embodiment of the present invention further provides a display device, including the display panel. The display panel may be an organic light emitting display panel or a micro LED display panel, but is not limited thereto. Fig. 10 is a schematic diagram of a display device according to an embodiment of the present invention, and as shown in fig. 10, the display device may be applied to an electronic device 1 such as a smart phone and a tablet computer. It can be understood that the above embodiments only provide a part of the structures of the display panel and the pixel circuit, and the display panel further includes other structures, which are not described in detail herein.
It should be understood that various forms of the flows shown above may be used, with steps reordered, added, or deleted. For example, the steps described in the present invention may be executed in parallel, sequentially, or in different orders, and are not limited herein as long as the desired results of the technical solution of the present invention can be achieved.
The above-described embodiments should not be construed as limiting the scope of the invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions may be made in accordance with design requirements and other factors. Any modification, equivalent replacement, and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (14)
1. A display panel, comprising: a display area and a non-display area surrounding the display area;
the display area comprises a plurality of rows of pixels arranged along a column direction;
the non-display area comprises a first scanning driving circuit and a second scanning driving circuit, the first scanning driving circuit comprises a first scanning driving unit which is cascaded, and the second scanning driving circuit comprises a second scanning driving unit which is cascaded;
the first scanning driving unit provides first scanning signals for two adjacent lines of pixels, and the second scanning driving unit provides second scanning signals for at least two lines of pixels.
2. The display panel according to claim 1, wherein the pixel includes a reset control terminal;
the output end of the ith-stage first scanning driving unit is electrically connected with the reset control ends of the 2i-1 th and 2i th row pixels, the value of i is a positive integer which is greater than or equal to 1, and the first scanning signal is a reset control signal.
3. The display panel of claim 1, wherein the pixel comprises a compensation control terminal;
the output end of the ith-stage first scanning driving unit is electrically connected with the compensation control ends of the 2i-1 th and 2i th row pixels, the value of i is a positive integer greater than or equal to 1, and the first scanning signal is a compensation control signal.
4. The display panel according to claim 1, wherein the pixel includes a reset control terminal and a compensation control terminal;
the output end of the ith-stage first scanning driving unit is electrically connected with the reset control ends of the pixels in the 2i-1 th and 2 i-th rows;
the output end of the ith-stage first scanning driving unit is also electrically connected with the compensation control ends of the pixels in the 2i-3 th and 2i-2 nd rows;
i is a positive integer greater than or equal to 1.
5. The display panel according to claim 1, wherein the pixel comprises a write control terminal;
the display area comprises a plurality of pixel groups arranged along the column direction, the cascaded second scanning driving units comprise a plurality of second scanning driving groups which are respectively arranged corresponding to the pixel groups, the second scanning driving groups comprise two cascaded second scanning driving units, the pixel groups comprise adjacent 2x rows of pixels, and x is a positive integer;
in the second scanning driving group, the first 1-stage second scanning driving unit provides the second scanning signal to the writing control end of the odd-numbered line of pixels in the corresponding pixel group, and the second scanning driving unit in the last 1-stage second scanning driving unit provides the second scanning signal to the writing control end of the even-numbered line of pixels in the corresponding pixel group.
6. The display panel according to claim 5, wherein x is 2 or x is 3.
7. The display panel according to claim 1, wherein the pixel includes a pixel circuit and a light-emitting element;
the pixel circuit comprises a driving module, a data writing module, a resetting module and a compensating module;
the data writing module is connected between a data signal line and the first end of the driving module;
the reset module is connected between a reset signal line and the control end of the drive module;
the compensation module is connected between the second end and the control end of the driving module;
the second end of the driving module is coupled with the light-emitting element;
the control end of the reset module is electrically connected with the output end of the first scanning driving unit, the control end of the compensation module is electrically connected with the output end of the next scanning driving unit, and the control end of the data writing module is electrically connected with the output end of the second scanning driving unit.
8. The display panel according to claim 7, wherein the driving module comprises a driving transistor, the data writing module comprises a data writing transistor, the resetting module comprises a resetting transistor, and the compensating module comprises a compensating transistor;
the driving transistor and the data writing transistor are P-type transistors, and the reset transistor and the compensation transistor are N-type transistors.
9. The display panel according to claim 7, wherein the operation process of the pixel circuit includes a reset phase and a data write phase;
in the reset stage, the reset module is started, and a reset signal provided by the reset signal line is input to the control end of the drive module;
and in the data writing stage, the data writing module and the compensation module are started, and the data signal provided by the data signal line is written into the control end of the driving module.
10. The display panel according to claim 9, wherein the output terminal of the first scan driving unit of the ith stage is electrically connected to the control terminal of the reset module in the pixels of the 2i-1 th and 2i th rows;
and sequentially executing the data writing phase by the 2i-3 and 2i-2 rows of pixels while the 2i-1 and 2i-2 rows of pixels are in the reset phase.
11. The display panel according to claim 1, wherein start times of the first scan driving units of adjacent two stages outputting effective signals are different by a first period T1;
the first width of the effective signal output by the first scanning driving unit at one stage is W1;
T1＝W1。
12. the display panel according to claim 1, wherein start times of outputting effective signals by the second scan driving units of two adjacent stages are different by a second period T2;
the second width of the effective signal output by the second scanning driving unit of one stage is W2;
T2≥W2。
13. the display panel according to claim 1, wherein start times of the first scan driving units of adjacent two stages outputting effective signals are different by a first period T1;
the start time of the effective signal output by the second scanning driving units of two adjacent stages differs by a second period T2;
T1＝2*T2。
14. a display device characterized by comprising the display panel according to any one of claims 1 to 13.
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| WO2024198161A1 (en) * | 2023-03-31 | 2024-10-03 | 昆山国显光电有限公司 | Display panel and display device |
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