CN215577702U - Shifting register unit, grid driving circuit and display panel - Google Patents
Shifting register unit, grid driving circuit and display panel Download PDFInfo
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- CN215577702U CN215577702U CN202120572907.0U CN202120572907U CN215577702U CN 215577702 U CN215577702 U CN 215577702U CN 202120572907 U CN202120572907 U CN 202120572907U CN 215577702 U CN215577702 U CN 215577702U
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Abstract
The utility model relates to the technical field of display equipment and discloses a shift register unit, a grid drive circuit and a display panel, wherein the shift register unit comprises an input module, a pull-up control module, at least one noise reduction module and an output module; the input module is connected with the input signal end and the pull-up node; the pull-up control module and the pull-up resetting terminal; each noise reduction module is connected with a pull-up node, a first negative polarity voltage end, a second negative polarity voltage end and a first output signal end, and the output module is connected with a clock signal end, a first output signal end and the pull-up node. According to the shift register unit, the second thin film transistor is arranged between the first thin film transistor and the third thin film transistor as well as between the first thin film transistor and the fourth thin film transistor, so that the pressure difference of a source electrode and a drain electrode at the third thin film transistor is reduced, the voltage at a pull-up node can be prevented from being influenced after the third thin film transistor fails, the signal abnormality at the output signal end is avoided, and the display panel can normally display.
Description
Technical Field
The utility model relates to the technical field of display equipment, in particular to a shift register unit, a grid driving circuit and a display panel.
Background
With the increase of the requirement of consumers for the image quality of the display, the driving capability of the conventional a-si thin film transistor has been difficult to achieve the technical requirements of high resolution and high frame frequency. Oxide thin film transistors are being applied to display panels due to their high mobility and low leakage.
However, the high mobility oxide device still has some difficult problems in process and design, for example, the device has weaker voltage endurance, when the thin film transistor device is subjected to a high voltage pulse signal, the oxide device is more likely to be abnormal than the a-si device, and the smaller the size of the thin film transistor is, the more likely the oxide device is to be abnormal when the temperature is lower;
as shown in fig. 1, which is a schematic structural diagram of a shift register unit in the prior art, when an oxide thin film transistor shift register unit is used, under a low temperature condition, a gate of a thin film transistor M01 in the shift register unit is affected by a high-level pulse signal which is suddenly increased and a large current which is passed through by a source and a drain, so that the thin film transistor M01 loses normal switching characteristics and is easy to fail, and a voltage at a pull-down node PD cannot keep a long high state, so that a signal at the pull-up node PU is forced to be pulled down by the thin film transistor M02 when the signal at the pull-up node PU is pulled up, and a signal at the pull-up node PU is abnormal, and finally, signals at OUTPUT signal terminals OUTPUT and OUT _ C are abnormal, and normal display cannot be performed.
SUMMERY OF THE UTILITY MODEL
The utility model provides a shift register unit, a gate drive circuit and a display panel, wherein the shift register unit can avoid signal abnormality at OUTPUT signal ends OUTPUT and OUT _ C, so that the display panel can normally display.
In order to achieve the purpose, the utility model provides the following technical scheme:
a shift register unit comprises an input module, a pull-up control module, at least one noise reduction module and an output module;
the input module is connected with an input signal end and a pull-up node;
the pull-up control module is connected with the pull-up reset end, the pull-up node and the first negative voltage end;
each noise reduction module comprises a first thin film transistor, a second thin film transistor, a third thin film transistor, a fourth thin film transistor, a fifth thin film transistor, a sixth thin film transistor, a positive polarity voltage end and a pull-down node; the grid electrode and the source electrode of the first thin film transistor are connected with a positive polarity voltage end, and the drain electrode of the first thin film transistor is connected with the source electrode of the second thin film transistor; the drain electrode of the second thin film transistor is connected with a pull-down node; the grid electrode of the third thin film transistor is connected with the pull-up node, the source electrode of the third thin film transistor is connected with the pull-down node, and the drain electrode of the third thin film transistor is connected with the first negative polarity voltage end; a source electrode of the fourth thin film transistor is connected with the pull-down node, a gate electrode of the fourth thin film transistor is connected with the input signal end, a source electrode of the fourth thin film transistor is connected with the pull-down node, and a drain electrode of the fourth thin film transistor is connected with the first negative polarity voltage end; the source electrode of the fifth thin film transistor is connected with the pull-up node, the drain electrode of the fifth thin film transistor is connected with the first cathode thin film transistor, and the grid electrode of the fifth thin film transistor is connected with the pull-down node and the grid electrode of the sixth thin film transistor; the source electrode of the sixth thin film transistor is connected with the first output signal end, and the drain electrode of the sixth thin film transistor is connected with the second negative polarity voltage end;
the output module is connected with the clock signal end, the first output signal end and the pull-up node.
The shift register unit provided by the embodiment of the utility model comprises at least one noise reduction module, wherein each noise reduction module comprises a first thin film transistor, a second thin film transistor, a third thin film transistor, a fourth thin film transistor, a fifth thin film transistor, a sixth thin film transistor, a positive polarity voltage end and a pull-down node; because the second thin film transistor is arranged between the first thin film transistor and the third thin film transistor as well as between the first thin film transistor and the fourth thin film transistor, when the noise reduction module works, the signal voltage of a pull-down node at the source electrode of the third thin film transistor can be reduced through the second thin film transistor, so that the differential pressure of the source electrode and the drain electrode at the third thin film transistor is reduced, the voltage at the pull-up node can be prevented from being influenced after the third thin film transistor is failed, the abnormal signals at the OUTPUT signal end OUTPUT and the OUT _ C are avoided, and the display panel can normally display.
Optionally, a gate of the second thin film transistor is connected to the positive polarity voltage terminal, or a gate of the second thin film transistor is connected to a drain of the first thin film transistor.
Optionally, two noise reduction modules are included.
Optionally, the input module includes a seventh thin film transistor, a gate and a source of the seventh thin film transistor are connected to the input signal terminal, and a drain of the seventh thin film transistor is connected to the pull-up node.
Optionally, the pull-up control module includes an eighth thin film transistor, a gate of the eighth thin film transistor is connected to the pull-up reset terminal, a source of the eighth thin film transistor is connected to the pull-up node, and a drain of the eighth thin film transistor is connected to the first negative voltage terminal.
Optionally, the output module includes a ninth thin film transistor and a capacitor, a first end of the capacitor is connected to the pull-up node, a second end of the capacitor is connected to the first output signal end, a source of the ninth thin film transistor is connected to the clock signal end, a gate of the ninth thin film transistor is connected to the first end of the capacitor, and a drain of the ninth thin film transistor is connected to the second end of the capacitor.
Optionally, each noise reduction module further includes a tenth thin film transistor, the output module further includes an eleventh thin film transistor, a gate of the tenth thin film transistor is connected to the pull-down node, a source of the tenth thin film transistor is connected to the second output signal terminal, a drain of the tenth thin film transistor is connected to the first negative-polarity voltage terminal, a gate of the eleventh thin film transistor is connected to the pull-up node, a source of the eleventh thin film transistor is connected to the clock signal terminal, and a drain of the eleventh thin film transistor is connected to the second output signal terminal.
Optionally, the reset module further includes a reset module, the reset module includes a twelfth thin film transistor, a gate of the twelfth thin film transistor is connected to the reset signal terminal, a source of the twelfth thin film transistor is connected to the pull-up node, and a drain of the second thin film transistor is connected to the first negative-polarity voltage terminal.
The embodiment of the utility model also provides a gate driving circuit, which comprises at least two cascaded shift register units of any one of the shift register units provided in the technical scheme.
The utility model also provides a display panel comprising any one of the gate driving circuits provided in the above technical scheme.
Drawings
Fig. 1 is a schematic structural diagram of a shift register unit provided in the prior art;
fig. 2 is a schematic structural diagram of a shift register unit according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of another shift register unit according to an embodiment of the present invention;
fig. 4 is a timing diagram of a portion of nodes of a shift register unit according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 2, the present invention provides a shift register unit, which includes an input module, a pull-up control module, at least one noise reduction module, and an output module;
the INPUT module is connected with an INPUT signal end INPUT and a pull-up node PU;
the pull-up control module is connected with a pull-up reset terminal RST _ PU, a pull-up node PU and a first negative polarity voltage terminal LVSS;
each noise reduction module includes a first thin film transistor M1, a second thin film transistor M2, a third thin film transistor M3, a fourth thin film transistor M4, a fifth thin film transistor M5, a sixth thin film transistor M6, a positive polarity voltage terminal VDD, and a pull-down node PD; the gate and source of the first thin film transistor M1 are connected to the positive polarity voltage terminal VDD, and the drain of the first thin film transistor M1 is connected to the source of the second thin film transistor M2; the drain of the second thin film transistor M2 is connected to the pull-down node PD; the gate of the third thin film transistor M3 is connected to the pull-up node PU, the source of the third thin film transistor M3 is connected to the pull-down node PD, and the drain of the third thin film transistor M3 is connected to the first negative polarity voltage terminal LVSS; a source of the fourth thin film transistor M4 is connected to the pull-down node PD, a gate of the fourth thin film transistor M4 is connected to the INPUT signal terminal INPUT, a source of the fourth thin film transistor M4 is connected to the pull-down node PD, and a drain of the fourth thin film transistor M4 is connected to the first negative polarity voltage terminal LVSS; the source of the fifth thin film transistor M5 is connected to the pull-up node PU, the drain of the fifth thin film transistor M5 is connected to the first cathode thin film transistor, and the gate of the fifth thin film transistor M5 is connected to the pull-down node PD and the gate of the sixth thin film transistor M6; a source of the sixth thin film transistor M6 is connected to the first OUTPUT signal terminal OUTPUT, and a drain of the sixth thin film transistor M6 is connected to the second negative polarity voltage terminal VSS;
the OUTPUT module is connected to the clock signal terminal CLK, the first OUTPUT signal terminal OUTPUT and the pull-up node PU.
The shift register unit provided in the embodiment of the present invention includes at least one noise reduction module, each noise reduction module includes a first thin film transistor M1, a second thin film transistor M2, a third thin film transistor M3, a fourth thin film transistor M4, a fifth thin film transistor M5, a sixth thin film transistor M6, a positive polarity voltage terminal VDD, and a pull-down node PD; because the second thin film transistor M2 is arranged between the first thin film transistor M1 and the third thin film transistor M3 and the fourth thin film transistor M4, when the noise reduction module works, the signal voltage of the pull-down node PD at the source of the third thin film transistor M3 can be reduced through the second thin film transistor M2, so that the voltage difference of the source and the drain at the position of the third thin film transistor M3 is reduced, the voltage at the position of the pull-up node PU can be prevented from being influenced after the third thin film transistor M3 is failed, and the abnormal signals at the OUTPUT signal ends OUTPUT and OUT _ C are avoided, so that the display panel can normally display.
In the embodiment of the present invention, as shown in fig. 2, the gate of the second thin film transistor M2 can be connected to the positive polarity voltage terminal VDD; alternatively, as shown in fig. 3, the gate electrode of the second thin film transistor M2 is connected to the drain electrode of the first thin film transistor M1. When the positive voltage terminal VDD is at a high level, the second tft M2 is turned on, which is equivalent to a resistor, so as to reduce the drain voltage of the third tft M3, thereby ensuring that the third tft M3 is not subjected to an excessive voltage surge, and avoiding the abnormal display problem.
Specifically, the shift register unit may include two noise reduction modules, the two noise reduction modules have the same circuit structure and function, and in order to reduce the dc bias state of the positive polarity voltage terminal VDD for a long time using the same noise reduction module, two sets of noise reduction circuits may be provided to reduce noise in a time-sharing manner, thereby prolonging the device life. As shown in fig. 2, one of the noise reduction modules is composed of a first thin film transistor M1, a second thin film transistor M2, a third thin film transistor M3, a fourth thin film transistor M4, a fifth thin film transistor M5, a sixth thin film transistor M6, a positive polarity voltage terminal VDD, and a pull-down node PD; the other noise reduction module comprises a first thin film transistor M1 ', a second thin film transistor M2', a third thin film transistor M3 ', a fourth thin film transistor M4', a fifth thin film transistor M5 ', a sixth thin film transistor M6', a positive polarity voltage terminal VDD ', and a pull-down node PD'. The positive polarity voltage terminal VDD and the positive polarity voltage terminal VDD' may operate in a time-sharing manner, and switch between a high level and a low level in a fixed time period, wherein the high level is a noise reduction operating state, and the first negative polarity voltage terminal LVSS and the second negative polarity voltage terminal VSS are at a low level. The signals of the pull-down node PD and the pull-up node PU are in competition state with each other.
Referring to fig. 4, taking the positive voltage terminal VDD as a high level as an example, timing diagrams of the positive voltage terminal VDD, the positive voltage terminal VDD', the pull-up node PU, the pull-down node PD, and the first negative voltage terminal LVSS can be shown in fig. 4.
Specifically, in the first stage, the positive polarity voltage end VDD high level signal is transmitted to the pull-down node PD through the first thin film transistor M1, the pull-down node PD is at a high level at this time, and the pull-up node PU signal is still at a low level;
in the second stage, the pull-up node PU is pulled high, turning on the third tft M3, and the third tft pulls the potential of the pull-up node PD from high level to low level state of the first negative voltage terminal LVSS.
And a third stage: the pull-up node PU point level is pulled down, the third thin film transistor is closed, and the pull-down node PD level is pulled up by the positive polarity voltage end VDD level.
In one possible embodiment, the INPUT module may include a seventh thin film transistor M7, a gate and a source of the seventh thin film transistor M7 are connected to the INPUT signal terminal INPUT, and a drain of the seventh thin film transistor M7 is connected to the pull-up node PU.
In one possible embodiment, the pull-up control module may include an eighth tft M8, a gate of the eighth tft M8 is connected to the pull-up reset terminal RST _ PU, a source of the eighth tft M8 is connected to the pull-up node PU, and a drain of the eighth tft M8 is connected to the first negative voltage terminal LVSS.
In one possible implementation, the OUTPUT module may include a ninth thin film transistor M9 and a capacitor C, a first terminal of the capacitor C is connected to the pull-up node PU, a second terminal of the capacitor C is connected to the first OUTPUT signal terminal OUTPUT, a source of the ninth thin film transistor M9 is connected to the clock signal terminal CLK, a gate of the ninth thin film transistor M9 is connected to the first terminal of the capacitor C, and a drain of the ninth thin film transistor M9 is connected to the second terminal of the capacitor C.
In one possible embodiment, each noise reduction module may further include a tenth thin film transistor M10, the output module further includes an eleventh thin film transistor M11, a gate of the tenth thin film transistor M10 is connected to the pull-down node PD, a source of the tenth thin film transistor M10 is connected to the second output signal terminal OUT _ C, a drain of the tenth thin film transistor M10 is connected to the first negative polarity voltage terminal LVSS, a gate of the eleventh thin film transistor M11 is connected to the pull-up node PU, a source of the eleventh thin film transistor M11 is connected to the clock signal terminal CLK, and a drain of the eleventh thin film transistor M11 is connected to the second output signal terminal OUT _ C.
In one possible implementation, the shift register unit further includes a reset module, the reset module includes a twelfth thin film transistor M12, a gate of the twelfth thin film transistor M12 is connected to the reset signal terminal STV, a source of the twelfth thin film transistor M12 is connected to the pull-up node PU, and a drain of the second thin film transistor M2 is connected to the first negative polarity voltage terminal LVSS.
The embodiment of the utility model also provides a gate driving circuit, which comprises at least two cascaded shift register units of any one of the shift register units provided in the technical scheme.
The utility model also provides a display panel comprising any one of the gate driving circuits provided in the above technical scheme.
It will be apparent to those skilled in the art that various changes and modifications may be made in the embodiments of the present invention without departing from the spirit and scope of the utility model. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (10)
1. A shift register unit is characterized by comprising an input module, a pull-up control module, at least one noise reduction module and an output module;
the input module is connected with an input signal end and a pull-up node;
the pull-up control module is connected with the pull-up reset end, the pull-up node and the first negative voltage end;
each noise reduction module comprises a first thin film transistor, a second thin film transistor, a third thin film transistor, a fourth thin film transistor, a fifth thin film transistor, a sixth thin film transistor, a positive polarity voltage end and a pull-down node; the grid electrode and the source electrode of the first thin film transistor are connected with a positive polarity voltage end, and the drain electrode of the first thin film transistor is connected with the source electrode of the second thin film transistor; the drain electrode of the second thin film transistor is connected with a pull-down node; the grid electrode of the third thin film transistor is connected with the pull-up node, the source electrode of the third thin film transistor is connected with the pull-down node, and the drain electrode of the third thin film transistor is connected with the first negative polarity voltage end; a gate of the fourth thin film transistor is connected with the input signal end, a source of the fourth thin film transistor is connected with the pull-down node, and a drain of the fourth thin film transistor is connected with the first negative polarity voltage end; a source electrode of the fifth thin film transistor is connected with the pull-up node, a drain electrode of the fifth thin film transistor is connected with the first negative polarity voltage end, and a grid electrode of the fifth thin film transistor is connected with the pull-down node and a grid electrode of the sixth thin film transistor; the source electrode of the sixth thin film transistor is connected with the first output signal end, and the drain electrode of the sixth thin film transistor is connected with the second negative polarity voltage end;
the output module is connected with the clock signal end, the first output signal end and the pull-up node.
2. The shift register cell according to claim 1, wherein a gate of the second thin film transistor is connected to the positive polarity voltage terminal, or a gate of the second thin film transistor is connected to a drain of the first thin film transistor.
3. The shift register cell of claim 1, comprising two noise reduction modules.
4. The shift register cell according to claim 1, wherein the input block includes a seventh thin film transistor, a gate and a source of the seventh thin film transistor are connected to the input signal terminal, and a drain of the seventh thin film transistor is connected to the pull-up node.
5. The shift register cell according to claim 1, wherein the pull-up control module comprises an eighth thin film transistor, a gate of the eighth thin film transistor is connected to the pull-up reset terminal, a source of the eighth thin film transistor is connected to the pull-up node, and a drain of the eighth thin film transistor is connected to the first negative polarity voltage terminal.
6. The shift register unit according to claim 1, wherein the output module includes a ninth thin film transistor and a capacitor, a first end of the capacitor is connected to the pull-up node, a second end of the capacitor is connected to the first output signal terminal, a source of the ninth thin film transistor is connected to the clock signal terminal, a gate of the ninth thin film transistor is connected to the first end of the capacitor, and a drain of the ninth thin film transistor is connected to the second end of the capacitor.
7. The shift register unit according to claim 1, wherein each of the noise reduction modules further includes a tenth thin film transistor, the output module further includes an eleventh thin film transistor, a gate of the tenth thin film transistor is connected to the pull-down node, a source of the tenth thin film transistor is connected to a second output signal terminal, a drain of the tenth thin film transistor is connected to the first negative polarity voltage terminal, a gate of the eleventh thin film transistor is connected to the pull-up node, a source of the eleventh thin film transistor is connected to the clock signal terminal, and a drain of the eleventh thin film transistor is connected to the second output signal terminal.
8. The shift register unit according to claim 1, further comprising a reset module, wherein the reset module includes a twelfth thin film transistor, a gate of the twelfth thin film transistor is connected to a reset signal terminal, a source of the twelfth thin film transistor is connected to the pull-up node, and a drain of the second thin film transistor is connected to the first negative polarity voltage terminal.
9. A gate drive circuit comprising at least two cascaded shift register cells according to any of claims 1-8.
10. A display panel comprising the gate driver circuit according to claim 9.
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| CN202120572907.0U CN215577702U (en) | 2021-03-19 | 2021-03-19 | Shifting register unit, grid driving circuit and display panel |
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| CN202120572907.0U CN215577702U (en) | 2021-03-19 | 2021-03-19 | Shifting register unit, grid driving circuit and display panel |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114613341A (en) * | 2022-04-20 | 2022-06-10 | 京东方科技集团股份有限公司 | Array grid driving unit, circuit and driving method thereof and display device |
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2021
- 2021-03-19 CN CN202120572907.0U patent/CN215577702U/en active Active
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114613341A (en) * | 2022-04-20 | 2022-06-10 | 京东方科技集团股份有限公司 | Array grid driving unit, circuit and driving method thereof and display device |
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