CN110444179B

CN110444179B - Shifting register, driving method thereof and grid driving circuit

Info

Publication number: CN110444179B
Application number: CN201910774893.8A
Authority: CN
Inventors: 刘子正; 赵剑; 毛大龙; 袁东旭
Original assignee: BOE Technology Group Co Ltd; Wuhan BOE Optoelectronics Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Wuhan BOE Optoelectronics Technology Co Ltd
Priority date: 2019-08-21
Filing date: 2019-08-21
Publication date: 2021-08-31
Anticipated expiration: 2039-08-21
Also published as: CN110444179A

Abstract

The shift register comprises an input sub-circuit, an output sub-circuit, a reset sub-circuit, a pull-up sub-circuit, a pull-down sub-circuit and a control sub-circuit, wherein the control sub-circuit is respectively connected with a pull-up node, a second power supply end and a pull-down node and is used for providing a signal of the second power supply end to the pull-down node under the control of the pull-up node. The signal that this application provided the second power end through the control sub-circuit node that draws downwards, when the voltage that draws the node appears undulant or unusual high potential, in time draws down the voltage that draws the node, has effectively avoided a plurality of outputs, has improved display panel's picture quality.

Description

Shifting register, driving method thereof and grid driving circuit

Technical Field

The present invention relates to, but not limited to, the field of display technologies, and in particular, to a shift register unit, a driving method thereof, and a gate driving circuit.

Background

With the rapid development of flat panel display technology, the demand for the picture quality of a Thin film transistor liquid crystal display (TFT-LCD) panel is increasing. The Gate Driver On Array (GOA) technology integrates a Gate Driver Circuit (IC) of a display device On an Array substrate, and the GOA technology can reduce the usage amount of the IC, thereby reducing the production cost and power consumption of the product, and can also realize a narrow frame of the display device.

The display panel consists of vertical and horizontal array pixel matrixes, and grid scanning signals are output through a grid driving circuit in the display process to access each pixel in a line-by-line scanning mode; the gate driving circuit is used for generating gate scanning voltages of the pixels, each shift register is used as a shift register to sequentially transmit scanning signals to the next shift register, and Thin Film Transistor (TFT) switches are turned on row by row to complete data signal input of the pixels.

The inventor has found that, in the shift register provided in the related art, when the pull-up node PU has other abnormal high potentials, such as noise, the pull-down node PD may not pull down the potential of the pull-up node PU due to the low potential, which may cause multiple outputs (Multi-outputs) on the display panel, and affect the display quality of the display panel.

Disclosure of Invention

The application provides a shift register, a driving method thereof and a grid driving circuit, which can improve the display quality of a display panel.

In a first aspect, an embodiment of the present application provides a shift register, including: input sub-circuit, output sub-circuit, pull-up sub-circuit, pull-down sub-circuit, reset sub-circuit and control sub-circuit, wherein:

the input sub-circuit is respectively connected with the signal input end, the pull-up node and the second clock signal input end and is used for providing a signal of the signal input end to the pull-up node under the control of the signal input end and the second clock signal input end; the output sub-circuit is respectively connected with the first clock signal input end, the pull-up node and the signal output end and is used for providing a signal of the first clock signal input end for the signal output end under the control of the pull-up node; the reset sub-circuit is respectively connected with the reset signal input end, the first power end, the signal output end and the pull-up node, and is used for providing signals of the first power end to the pull-up node and the signal output end under the control of the reset signal input end; the pull-up sub-circuit is respectively connected with the second clock signal input end and the pull-down node and is used for providing a signal of the second clock signal input end to the pull-down node under the action of the second clock signal input end; the pull-down sub-circuit is respectively connected with the pull-up node, the pull-down node, the first power end, the second clock signal input end and the signal output end, and is used for providing signals of the first power end for the pull-up node and the signal output end under the control of the pull-up node, the pull-down node and the second clock signal input end; and the control sub-circuit is respectively connected with the pull-up node, the second power supply end and the pull-down node and is used for providing a signal of the second power supply end to the pull-down node under the control of the pull-up node.

Optionally, the input sub-circuit comprises: a first transistor and a second transistor, wherein: the control electrode and the first electrode of the first transistor are connected with the signal input end, and the second electrode of the first transistor is connected with the pull-up node; the control electrode of the second transistor is connected with the second clock signal input end, the first electrode of the second transistor is connected with the signal input end, and the second electrode of the second transistor is connected with the pull-up node.

Optionally, the output sub-circuit comprises: a third transistor and a capacitor, the reset sub-circuit including: a fourth transistor and a fifth transistor, wherein: the control electrode of the third transistor is connected with the pull-up node, the first electrode of the third transistor is connected with the first clock signal input end, and the second electrode of the third transistor is connected with the signal output end; one end of the capacitor is connected with the pull-up node, and the other end of the capacitor is connected with the signal output end; a control electrode of the fourth transistor is connected with the reset signal input end, a first electrode of the fourth transistor is connected with the pull-up node, and a second electrode of the fourth transistor is connected with the first power supply end; and a control electrode of the fifth transistor is connected with the reset signal input end, a first electrode of the fifth transistor is connected with the signal output end, and a second electrode of the fifth transistor is connected with the first power supply end.

Optionally, the pull-up sub-circuit comprises: a sixth transistor and a seventh transistor, the pull-down sub-circuit comprising: an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, and a twelfth transistor, wherein: a control electrode of the sixth transistor is connected with the third node, a first electrode of the sixth transistor is connected with the second clock signal input end, and a second electrode of the sixth transistor is connected with the pull-down node; a control electrode and a first electrode of the seventh transistor are connected with the second clock signal input end, and a second electrode of the seventh transistor is connected with the third node; a control electrode of the eighth transistor is connected with the pull-up node, a first electrode of the eighth transistor is connected with the pull-down node, and a second electrode of the eighth transistor is connected with the first power supply end; a control electrode of the ninth transistor is connected with the pull-up node, a first electrode of the ninth transistor is connected with the third node, and a second electrode of the ninth transistor is connected with the first power supply end; a control electrode of the tenth transistor is connected with the pull-down node, a first electrode of the tenth transistor is connected with the pull-up node, and a second electrode of the tenth transistor is connected with the first power supply end; a control electrode of the eleventh transistor is connected with the pull-down node, a first electrode of the eleventh transistor is connected with the signal output end, and a second electrode of the eleventh transistor is connected with the first power supply end; and a control electrode of the twelfth transistor is connected with the second clock signal input end, a first electrode of the twelfth transistor is connected with the signal output end, and a second electrode of the twelfth transistor is connected with the first power supply end.

Optionally, the control sub-circuit comprises: a thirteenth transistor, wherein: a control electrode of the thirteenth transistor is connected with the pull-up node, a first electrode of the thirteenth transistor is connected with the second power supply terminal, and a second electrode of the thirteenth transistor is connected with the pull-down node.

Optionally, the input sub-circuit comprises: a first transistor and a second transistor, the output sub-circuit including: a third transistor and a capacitor, the reset sub-circuit including: a fourth transistor and a fifth transistor, the pull-up sub-circuit comprising: a sixth transistor and a seventh transistor, the pull-down sub-circuit comprising: an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, and a twelfth transistor, the control sub-circuit including: a thirteenth transistor, wherein:

the control electrode and the first electrode of the first transistor are connected with the signal input end, and the second electrode of the first transistor is connected with the pull-up node; the control electrode of the second transistor is connected with the second clock signal input end, the first electrode of the second transistor is connected with the signal input end, and the second electrode of the second transistor is connected with the pull-up node; the control electrode of the third transistor is connected with the pull-up node, the first electrode of the third transistor is connected with the first clock signal input end, and the second electrode of the third transistor is connected with the signal output end; one end of the capacitor is connected with the pull-up node, and the other end of the capacitor is connected with the signal output end; a control electrode of the fourth transistor is connected with the reset signal input end, a first electrode of the fourth transistor is connected with the pull-up node, and a second electrode of the fourth transistor is connected with the first power supply end; a control electrode of the fifth transistor is connected with the reset signal input end, a first electrode of the fifth transistor is connected with the signal output end, and a second electrode of the fifth transistor is connected with the first power supply end; a control electrode of the sixth transistor is connected with the third node, a first electrode of the sixth transistor is connected with the second clock signal input end, and a second electrode of the sixth transistor is connected with the pull-down node; a control electrode and a first electrode of the seventh transistor are connected with the second clock signal input end, and a second electrode of the seventh transistor is connected with the third node; a control electrode of the eighth transistor is connected with the pull-up node, a first electrode of the eighth transistor is connected with the pull-down node, and a second electrode of the eighth transistor is connected with the first power supply end; a control electrode of the ninth transistor is connected with the pull-up node, a first electrode of the ninth transistor is connected with the third node, and a second electrode of the ninth transistor is connected with the first power supply end; a control electrode of the tenth transistor is connected with the pull-down node, a first electrode of the tenth transistor is connected with the pull-up node, and a second electrode of the tenth transistor is connected with the first power supply end; a control electrode of the eleventh transistor is connected with the pull-down node, a first electrode of the eleventh transistor is connected with the signal output end, and a second electrode of the eleventh transistor is connected with the first power supply end; a control electrode of the twelfth transistor is connected with the second clock signal input end, a first electrode of the twelfth transistor is connected with the signal output end, and a second electrode of the twelfth transistor is connected with the first power supply end; a control electrode of the thirteenth transistor is connected with the pull-up node, a first electrode of the thirteenth transistor is connected with the second power supply terminal, and a second electrode of the thirteenth transistor is connected with the pull-down node.

Optionally, the second power supply terminal continuously provides an active level, and the width-length ratio of the thirteenth transistor satisfies: when the signal of the pull-up node is a first signal, the tenth transistor and the eleventh transistor cannot be conducted by the signal of the pull-down node, when the signal of the pull-up node is a second signal, the tenth transistor and the eleventh transistor are conducted by the signal of the pull-down node, the first signal is a signal when the shift register is in an input stage or an output stage, and the second signal is a signal when the shift register is in a stage except the input stage and the output stage.

Optionally, the signal of the second power supply terminal is the same as the signal of the third node, and the width-to-length ratio of the thirteenth transistor satisfies: when the signal of the pull-up node is a first signal, the tenth transistor and the eleventh transistor cannot be conducted by the signal of the pull-down node, when the signal of the pull-up node is a second signal, the tenth transistor and the eleventh transistor are conducted by the signal of the pull-down node, the first signal is a signal when the shift register is in an input stage or an output stage, and the second signal is a signal when the shift register is in a stage except the input stage and the output stage.

In a second aspect, an embodiment of the present application further provides a gate driving circuit, including: a plurality of cascaded shift registers as described in any of the above.

In a third aspect, an embodiment of the present application further provides a method for driving a shift register, where the method is applied to a shift register as described in any one of the above, and the method includes: the input sub-circuit provides a signal of the signal input end to the pull-up node under the control of the signal input end; the output sub-circuit provides a signal of the first clock signal input end to the signal output end under the control of the pull-up node; the reset sub-circuit provides a signal of a first power supply end to the pull-up node and the signal output end under the control of the reset signal input end; the pull-up sub-circuit provides a signal of the second clock signal input end to a pull-down node under the action of the second clock signal input end; the pull-down sub-circuit provides a signal of a first power supply end to the pull-up node and the signal output end under the control of the pull-down node; the control sub-circuit provides a signal of the second power supply terminal to the pull-down node under the control of the pull-up node.

Compared with the prior art, the shift register, the driving method thereof and the grid driving circuit are respectively connected with the pull-up node, the second power supply end and the pull-down node through the control sub-circuit, and are used for providing a signal of the second power supply end to the pull-down node under the control of the pull-up node and pulling down the voltage of the pull-up node in time, so that multiple outputs are effectively avoided, and the stability of the shift register and the display quality of the display panel are improved.

Additional features and advantages of the application will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by the practice of the application. Other advantages of the application may be realized and attained by the instrumentalities and combinations particularly pointed out in the specification, claims, and drawings.

Drawings

The accompanying drawings are included to provide an understanding of the present disclosure and are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the examples serve to explain the principles of the disclosure and not to limit the disclosure.

FIG. 1 is a diagram illustrating an exemplary shift register according to an embodiment of the present disclosure;

fig. 2 is an equivalent circuit diagram of an input sub-circuit provided in an embodiment of the present application;

fig. 3 is an equivalent circuit diagram of an output sub-circuit and a reset sub-circuit provided in an embodiment of the present application;

fig. 4 is an equivalent circuit diagram of a pull-up sub-circuit and a pull-down sub-circuit provided in the embodiment of the present application;

fig. 5 is an equivalent circuit diagram of a control sub-circuit provided in an embodiment of the present application;

fig. 6 is an equivalent circuit diagram of a shift register according to an embodiment of the present application;

FIG. 7 is a first timing diagram illustrating an operation of a shift register according to an embodiment of the present invention;

FIG. 8 is a second timing diagram illustrating operation of a shift register according to an embodiment of the present invention;

fig. 9 is a flowchart of a driving method of a shift register according to an embodiment of the present application;

fig. 10 is a schematic structural diagram of a gate driving circuit according to an embodiment of the present application.

Description of reference numerals:

INPUT-signal INPUT; OUTPUT-signal OUTPUT terminal;

CLKA-a first clock signal input terminal; CLKB — a second clock signal input;

RESET-RESET signal input; VSS — first power supply terminal;

v-a second power supply terminal; PU — pull-up node;

PD — pull down node; PD _ CN — third node;

c-capacitance; M1-M13-transistor.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be noted that the embodiments and features of the embodiments in the present application may be arbitrarily combined with each other without conflict.

Unless otherwise defined, technical or scientific terms used in the disclosure of the embodiments of the present application should have the ordinary meaning as understood by those having ordinary skill in the art to which the present invention belongs. The use of "first," "second," and similar terms in the embodiments of the present application do not denote any order, quantity, or importance, but rather the terms are used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that a particular element or item appears in front of the word or is detected by mistake, and that the word or item appears after the word or item and its equivalents, but does not exclude other elements or misdetections.

It will be appreciated by those skilled in the art that the transistors employed in all embodiments of the present application may be thin film transistors or field effect transistors or other devices having the same characteristics. Preferably, the thin film transistor used in the embodiment of the present application may be an oxide semiconductor transistor. Since the source and drain of the transistor used herein are symmetrical, the source and drain may be interchanged. In the embodiment of the present application, in order to distinguish two electrodes of a transistor except for a gate, one of the electrodes is referred to as a first electrode, the other electrode is referred to as a second electrode, the first electrode may be a source or a drain, and the second electrode may be a drain or a source.

Fig. 1 is a schematic structural diagram of a shift register provided in an embodiment of the present application, and as shown in fig. 1, the shift register provided in the embodiment of the present application includes: the circuit comprises an input sub-circuit, an output sub-circuit, a pull-up sub-circuit, a pull-down sub-circuit, a reset sub-circuit and a control sub-circuit.

Specifically, the INPUT sub-circuit is respectively connected to the signal INPUT terminal INPUT, the pull-up node PU and the second clock signal INPUT terminal CLKB, and is configured to provide a signal of the signal INPUT terminal INPUT to the pull-up node PU under the control of the signal INPUT terminal INPUT and the second clock signal INPUT terminal CLKB; the OUTPUT sub-circuit is respectively connected with the first clock signal input end CLKA, the pull-up node PU and the signal OUTPUT end OUTPUT, and is used for providing a signal of the first clock signal input end CLKA to the signal OUTPUT end OUTPUT under the control of the pull-up node PU; the RESET sub-circuit is respectively connected with the RESET signal input end RESET, the first power supply end VSS, the signal OUTPUT end OUTPUT and the pull-up node PU and is used for providing signals of the first power supply end VSS for the pull-up node PU and the signal OUTPUT end OUTPUT under the control of the RESET signal input end RESET; the pull-up sub-circuit is respectively connected with the second clock signal input end CLKB and the pull-down node PD and is used for providing a signal of the second clock signal input end CLKB to the pull-down node PD under the action of the second clock signal input end CLKB; the pull-down sub-circuit is respectively connected with the pull-up node PU, the pull-down node PD, the first power end VSS, the second clock signal input end CLKB and the signal OUTPUT end OUTPUT, and is used for providing signals of the first power end VSS for the pull-up node PU and the signal OUTPUT end OUTPUT under the control of the pull-up node PU, the pull-down node PD and the second clock signal input end CLKB; and the control sub-circuit is respectively connected with the pull-up node PU, the second power supply end V and the pull-down node PD and is used for providing a signal of the second power supply end V to the pull-down node PD under the control of the pull-up node PU.

The shift register of this application, under the control of the node of pulling up through control sub-circuit, pull down the node and provide the signal of second power end, in time pulled down the voltage of the node of pulling up, effectively avoided a plurality of outputs, improved shift register's stability and display panel's display quality.

Optionally, fig. 2 is an equivalent circuit diagram of an input sub-circuit provided in the embodiment of the present application, and as shown in fig. 2, the input sub-circuit provided in the embodiment of the present application includes: a first transistor M1 and a second transistor M2.

Specifically, a control electrode and a first electrode of the first transistor M1 are connected to the signal INPUT terminal INPUT, and a second electrode of the first transistor M1 is connected to the pull-up node PU; a control electrode of the second transistor M2 is connected to the second clock signal INPUT terminal CLKB, a first electrode of the second transistor M2 is connected to the signal INPUT terminal INPUT, and a second electrode of the second transistor M2 is connected to the pull-up node PU.

An exemplary structure of the input sub-circuit is specifically shown in fig. 2. Those skilled in the art will readily appreciate that the implementation of the input sub-circuits is not so limited, so long as their respective functions are achieved.

Optionally, fig. 3 is an equivalent circuit diagram of an output sub-circuit and a reset sub-circuit provided in the embodiment of the present application, and as shown in fig. 3, the output sub-circuit provided in the embodiment of the present application includes: a third transistor and a capacitor C, the reset sub-circuit includes: a fourth transistor M4 and a fifth transistor M5, wherein:

specifically, a control electrode of the third transistor M3 is connected to the pull-up node PU, a first electrode of the third transistor M3 is connected to the first clock signal input terminal CLKA, and a second electrode of the third transistor M3 is connected to the signal OUTPUT terminal OUTPUT; one end of the capacitor C is connected with the pull-up node PU, and the other end of the capacitor C is connected with the signal OUTPUT end OUTPUT; a control electrode of the fourth transistor M4 is connected to the RESET signal input terminal RESET, a first electrode of the fourth transistor M4 is connected to the pull-up node PU, and a second electrode of the fourth transistor M4 is connected to the first power source terminal VSS; a control electrode of the fifth transistor M5 is connected to the RESET signal input terminal RESET, a first electrode of the fifth transistor M5 is connected to the signal OUTPUT terminal OUTPUT, and a second electrode of the fifth transistor M5 is connected to the first power source terminal VSS.

One exemplary structure of the output and reset sub-circuits is specifically shown in fig. 3. It is easily understood by those skilled in the art that the implementation of the output sub-circuit and the reset sub-circuit is not limited thereto as long as their respective functions can be implemented.

Optionally, fig. 4 is an equivalent circuit diagram of a pull-up sub-circuit and a pull-down sub-circuit provided in the embodiment of the present application, and as shown in fig. 4, the pull-up sub-circuit provided in the embodiment of the present application includes: a sixth transistor M6 and a seventh transistor M7; the pull-down sub-circuit includes: an eighth transistor M8, a ninth transistor M9, a tenth transistor M10, an eleventh transistor M11, and a twelfth transistor M12.

Specifically, a control electrode of the sixth transistor M6 is connected to the third node PD _ CN, a first electrode of the sixth transistor M6 is connected to the second clock signal input terminal CLKB, and a second electrode of the sixth transistor M6 is connected to the pull-down node PD; a control electrode and a first electrode of the seventh transistor M7 are connected to the second clock signal input terminal CLKB, and a second electrode of the seventh transistor M7 is connected to the third node PD _ CN; a control electrode of the eighth transistor M8 is connected to the pull-up node PU, a first electrode of the eighth transistor M8 is connected to the pull-down node PD, and a second electrode of the eighth transistor M8 is connected to the first power source terminal VSS; a control electrode of the ninth transistor M9 is connected to the pull-up node PU, a first electrode of the ninth transistor M9 is connected to the third node PD _ CN, and a second electrode of the ninth transistor M9 is connected to the first power source terminal VSS; a control electrode of the tenth transistor M10 is connected to the pull-down node PD, a first electrode of the tenth transistor M10 is connected to the pull-up node PU, and a second electrode of the tenth transistor M10 is connected to the first power source terminal VSS; a control electrode of the eleventh transistor M11 is connected to the pull-down node PD, a first electrode of the eleventh transistor M11 is connected to the signal OUTPUT terminal OUTPUT, and a second electrode of the eleventh transistor M11 is connected to the first power source terminal VSS; a control electrode of the twelfth transistor M12 is connected to the second clock signal input terminal CLKB, a first electrode of the twelfth transistor M12 is connected to the signal OUTPUT terminal OUTPUT, and a second electrode of the twelfth transistor M12 is connected to the first power source terminal VSS.

One exemplary structure of the pull-up and pull-down sub-circuits is specifically shown in fig. 4. It is easily understood by those skilled in the art that the implementation of the pull-up sub-circuit and the pull-down sub-circuit is not limited thereto as long as their respective functions can be realized.

Optionally, fig. 5 is an equivalent circuit diagram of the control sub-circuit provided in the embodiment of the present application, and as shown in fig. 5, the control sub-circuit provided in the embodiment of the present application includes: a thirteenth transistor M13.

Specifically, a control electrode of the thirteenth transistor M13 is connected to the pull-up node PU, a first electrode of the thirteenth transistor M13 is connected to the second power source terminal V, and a second electrode of the thirteenth transistor M13 is connected to the pull-down node PD.

One exemplary structure of the control sub-circuit is specifically shown in fig. 5. It is easily understood by those skilled in the art that the implementation of the control sub-circuits is not limited thereto as long as their respective functions can be realized.

Fig. 6 is an equivalent circuit diagram of a shift register according to an embodiment of the present application, and as shown in fig. 6, an input sub-circuit in the shift register according to the embodiment of the present application includes: a first transistor M1 and a second transistor M2, the output sub-circuit comprising: a third transistor M3 and a capacitor C, the reset sub-circuit comprising: a fourth transistor M4 and a fifth transistor M5, the pull-up sub-circuit comprising: a sixth transistor M6 and a seventh transistor M7, the pull-down sub-circuit comprising: an eighth transistor M8, a ninth transistor M9, a tenth transistor M10, an eleventh transistor M11, and a twelfth transistor M12, and the control sub-circuit includes a thirteenth transistor M13.

Specifically, a control electrode and a first electrode of the first transistor M1 are connected to the signal INPUT terminal INPUT, and a second electrode of the first transistor M1 is connected to the pull-up node PU; a control electrode of the second transistor M2 is connected to the second clock signal INPUT terminal CLKB, a first electrode of the second transistor M2 is connected to the signal INPUT terminal INPUT, and a second electrode of the second transistor M2 is connected to the pull-up node PU; a control electrode of the third transistor M3 is connected to the pull-up node PU, a first electrode of the third transistor M3 is connected to the first clock signal input terminal CLKA, and a second electrode of the third transistor M3 is connected to the signal OUTPUT terminal OUTPUT; one end of the capacitor C is connected with the pull-up node PU, and the other end of the capacitor C is connected with the signal OUTPUT end OUTPUT; a control electrode of the fourth transistor M4 is connected to the RESET signal input terminal RESET, a first electrode of the fourth transistor M4 is connected to the pull-up node PU, and a second electrode of the fourth transistor M4 is connected to the first power source terminal VSS; a control electrode of the fifth transistor M5 is connected to the RESET signal input terminal RESET, a first electrode of the fifth transistor M5 is connected to the signal OUTPUT terminal OUTPUT, and a second electrode of the fifth transistor M5 is connected to the first power source terminal VSS; a first pole of the sixth transistor M6 is connected to the second clock signal input terminal CLKB, and a second pole of the sixth transistor M6 is connected to the pull-down node PD. A control electrode and a first electrode of the seventh transistor M7 are connected to the second clock signal input terminal CLKB, and a second electrode of the seventh transistor M7 is connected to a control electrode of the sixth transistor M6; a control electrode of the eighth transistor M8 is connected to the pull-up node PU, a first electrode of the eighth transistor M8 is connected to the pull-down node PD, and a second electrode of the eighth transistor M8 is connected to the first power source terminal VSS. A control electrode of the ninth transistor M9 is connected to the pull-up node PU, a first electrode of the ninth transistor M9 is connected to a control electrode of the sixth transistor M6, and a second electrode of the ninth transistor M9 is connected to the first power source terminal VSS. A control electrode of the tenth transistor M10 is connected to the pull-down node PD, a first electrode of the tenth transistor M10 is connected to the pull-up node PU, and a second electrode of the tenth transistor M10 is connected to the first power source terminal VSS; a control electrode of the eleventh transistor M11 is connected to the pull-down node PD, a first electrode of the eleventh transistor M11 is connected to the signal OUTPUT terminal OUTPUT, and a second electrode of the eleventh transistor M11 is connected to the first power source terminal VSS; a control electrode of the twelfth transistor M12 is connected to the second clock signal input terminal CLKB, a first electrode of the twelfth transistor M12 is connected to the signal OUTPUT terminal OUTPUT, and a second electrode of the twelfth transistor M12 is connected to the first power source terminal VSS; a control electrode of the thirteenth transistor M13 is connected to the pull-up node PU, a first electrode of the thirteenth transistor M13 is connected to the second power source terminal V, and a second electrode of the thirteenth transistor M13 is connected to the pull-down node PD.

Exemplary structures of the input sub-circuit, the output sub-circuit, the reset sub-circuit, the pull-up sub-circuit, the pull-down sub-circuit, and the control sub-circuit are specifically shown in fig. 6. Those skilled in the art will readily appreciate that the implementation of each of the above sub-circuits is not limited thereto as long as their respective functions can be achieved.

As shown in fig. 6, the pull-down node PD voltage VPD provided by the embodiment of the present application is a result of voltage division by R8 and R13, where R8 and R13 are resistances of the eighth transistor M8 and the thirteenth transistor M13, respectively.

To describe the voltage division of the eighth transistor M8 and the thirteenth transistor M13 in detail, when the pull-up node PU is abnormally high, the ninth transistor M9 is turned on, the third node PD _ CN is at low potential, the sixth transistor M6 is turned off, and the pull-down node PD voltage VPD is divided by the eighth transistor M8 and the thirteenth transistor M13, so that: VPD ═ V × R8/(R8+ R13) + VSS × R13/(R8+ R13).

According to the current-voltage (I-V) curves, the TFT resistances are different at different VPDs, and the width and length (W/L) of the thirteenth transistor M13 are reasonably matched, so that when an interference wave or other high level occurs at the pull-up node PU, the pull-down node PD can turn on the tenth transistor M10 and the eleventh transistor M11, and timely reset the pull-up node PU and the signal OUTPUT terminal OUTPUT, thereby preventing the occurrence of erroneous OUTPUT and Multi-OUTPUT of the shift register.

The shift register of the embodiment of the present application adds a thirteenth transistor M13 and a second power supply terminal V, relative to the shift register of the related art. The thirteenth transistor M13 and the second power supply terminal V are configured to turn on the thirteenth transistor M13 when the pull-up node PU fluctuates or has an abnormal high potential due to noise or the like, and the pull-down node PD rises in potential through voltage division with the eighth transistor M8, and turns on the tenth transistor M10 and the eleventh transistor M11, so as to pull down the abnormal high potential of the pull-up node PU in time, and ensure normal output of the display panel.

In the embodiment, the transistors M1 to M13 may be both N-type thin film transistors or P-type thin film transistors, so that the process flow can be unified, the process can be reduced, and the yield of the product can be improved. In addition, in consideration of the fact that the low-temperature polysilicon thin film transistor has a small leakage current, all transistors are preferably low-temperature polysilicon thin film transistors in the embodiments of the present application, and the thin film transistor may specifically be a thin film transistor with a bottom gate structure or a thin film transistor with a top gate structure, as long as the switching function can be achieved.

The capacitor C may be a liquid crystal capacitor formed by the pixel electrode and the common electrode, or may be an equivalent capacitor formed by a liquid crystal capacitor formed by the pixel electrode and the common electrode and a storage capacitor, which is not limited in the present invention.

In an exemplary embodiment, the second power supply terminal V continuously supplies the active level, and the width-to-length ratio of the thirteenth transistor M13 satisfies: when the signal of the pull-up node PU is a first signal, the tenth transistor M10 and the eleventh transistor M11 cannot be turned on by the signal of the pull-down node PD, and when the signal of the pull-up node PU is a second signal, the tenth transistor M10 and the eleventh transistor M11 are turned on by the signal of the pull-down node PD, the first signal is a signal when the shift register is in the input stage or the output stage, and the second signal is a signal when the shift register is in a stage other than the input stage and the output stage.

The technical solution of the embodiment of the present application is further described below by the working process of the shift register. The following description is given by taking an example of an operation process of the first stage shift register.

Taking the transistors M1 to M13 in the shift register provided in the embodiment of the present application as an example, and fig. 7 is a first operation timing diagram of the shift register provided in the embodiment of the present application, as shown in fig. 6 and 7, the shift register provided in the embodiment of the present application includes 13 transistor units (M1 to M13), 1 capacitor unit (C), 4 INPUT terminals (INPUT, RESET, CLKA, and CLKB), 1 OUTPUT terminal (OUTPUT), and 2 power supply terminals (VSS and V), and an operation process thereof includes:

specifically, the second power source terminal V continuously supplies a high level signal, and the first power source terminal VSS continuously supplies a low level signal.

In the first stage S1, i.e., the INPUT stage, the INPUT signal at the signal INPUT terminal INPUT is at a high level, the first transistor M1 is turned on, the INPUT signal at the second clock signal INPUT terminal CLKB is at a high level, the twelfth transistor M12 and the second transistor M2 are turned on, the potential of the pull-up node PU is pulled up, and the pull-up node PU charges the capacitor C. Since the voltage level of the pull-up node PU is pulled high, the eighth transistor M8, the ninth transistor M9 and the thirteenth transistor M13 are turned on, and at this time, the tenth transistor M10 and the eleventh transistor M11 cannot be turned on by the voltage level of the pull-down node PD, and the voltage level of the pull-up node PU is not pulled low.

In the second stage S2, i.e., the output stage, the INPUT signal at the signal INPUT terminal INPUT is at a low level, the first transistor M1 is turned off, the pull-up node PU continues to keep at a high level under the bootstrap action of the capacitor C, the eighth transistor M8, the ninth transistor M9 and the thirteenth transistor M13 are turned on, at this time, the potential of the pull-down node PD cannot turn on the tenth transistor M10 and the eleventh transistor M11, and the potential of the pull-up node PU cannot be pulled down. Since the pull-up node PU is at a high level, the third transistor M3 is turned on, the input signal of the first clock signal input terminal CLKA is at a high level, and the signal OUTPUT terminal OUTPUT OUTPUTs the signal of the first clock signal input terminal CLKA, i.e., the gate driving signal.

In the third stage S3, namely, in the RESET stage, the input signal of the RESET signal input terminal RESET is at a high level, the fourth transistor M4 and the fifth transistor M5 are turned on, the fourth transistor M4 starts to discharge the pull-up node PU, and pulls down the potential of the pull-up node PU to a low level of the first power terminal VSS, the fifth transistor M5 starts to discharge the signal OUTPUT terminal OUTPUT, and pulls down the potential of the signal OUTPUT terminal OUTPUT to a low level of the first power terminal VSS, so as to reduce noise, the second clock signal input terminal CLKB is at a high level, the sixth transistor M6, the seventh transistor M7, the twelfth transistor M12, and the second transistor M2 are turned on, and further pulls down the potentials of the pull-up node PU and the signal OUTPUT terminal OUTPUT, and the ninth transistor M9 and the eighth transistor M8 are turned off because the pull-up node PU node is at a low level; since the ninth transistor M9 and the eighth transistor M8 are turned off, the potential of the pull-down node PD is pulled high, the tenth transistor M10 and the eleventh transistor M11 are turned on, and the potentials of the pull-up node PU and the signal OUTPUT terminal OUTPUT are further pulled low.

In the fourth stage S4, since the potential of the pull-up node PU is at a low level, the third transistor M3 is turned off, the input signal of the first clock signal input terminal CLKA is at a high level, the high level of the first clock signal input terminal CLKA cannot be OUTPUT to the signal OUTPUT terminal OUTPUT, the signal OUTPUT terminal OUTPUT maintains the low level OUTPUT of the upper stage, the input signal of the second clock signal input terminal CLKB is at a low level, and the pull-down node PD is pulled down to a low level.

In the fifth stage S5, the input signal of the second clock signal input terminal CLKB is at a high level, and at this time, the ninth transistor M9 and the eighth transistor M8 are turned off, so that the potential of the pull-down node PD is at the high level of the input signal of the second clock signal input terminal CLKB, the tenth transistor M10 and the eleventh transistor M11 are turned on, the potential of the pull-up node PU is continuously pulled down to the first power terminal VSS, the eleventh transistor M11 is turned on, and the potential of the signal OUTPUT terminal OUTPUT is continuously pulled down to the low level of the first power terminal VSS, so as to avoid noise.

In this embodiment, after the first stage S1, the INPUT signal at the signal INPUT terminal INPUT is continuously at a low level; after the second stage S2, the OUTPUT signal of the signal OUTPUT terminal OUTPUT continues to be at the low level; after the third stage S3, the input signal of the RESET signal input terminal RESET continues to be at a low level; in all the stages, the input signal of the first power source terminal VSS continues to be at a low level; the input signal of the second power source terminal V is continuously high. After the fifth stage S5, the INPUT signals of the first clock signal INPUT terminal CLKA and the second clock signal INPUT terminal CLKB are repeated one or more times in the fourth stage S4 and the fifth stage S5 in sequence until the INPUT signal of the signal INPUT terminal INPUT is at a high level, and then the process is restarted from the first stage.

According to the working process of the shift register, after the output stage is finished and until the next frame signal INPUT end INPUT signal is INPUT, the potential of the pull-down node PD changes synchronously with the second clock signal INPUT end CLKB signal, and both the duty ratios are 50%.

If the pull-up node PU has an abnormal high potential when the pull-down node PD is at a low potential, the working process of the shift register provided in the embodiment of the present application includes: when the pull-up node PU has an abnormally high potential, the thirteenth transistor M13, the eighth transistor M8, and the ninth transistor M9 are turned on, and at this time, the potential of the pull-down node PD causes the tenth transistor M10 and the eleventh transistor M11 to be turned on, and the potentials of the pull-up node PU and the signal OUTPUT terminal OUTPUT are pulled down by the first power source terminal VSS, thereby preventing multiple OUTPUTs.

It should be noted that, when the pull-up node PU has an abnormal potential when the pull-down node PD is at a high potential, the tenth transistor M10 and the eleventh transistor M11 are turned on because the pull-down node PD is at a high potential, and the potentials of the pull-up node PU and the signal OUTPUT terminal OUTPUT are pulled down by the first power source terminal VSS.

In another exemplary embodiment, the second power source terminal V is the same as the signal of the third node PD _ CN, i.e., provides an inactive level in the input stage and the output stage and provides an active level in the other stages except the input stage and the output stage, and the width-to-length ratio of the thirteenth transistor M13 satisfies: when the signal of the pull-up node PU is a first signal, the tenth transistor M10 and the eleventh transistor M11 cannot be turned on by the signal of the pull-down node PD, and when the signal of the pull-up node PU is a second signal, the tenth transistor M10 and the eleventh transistor M11 are turned on by the signal of the pull-down node PD, the first signal is a signal when the shift register is in the input stage or the output stage, and the second signal is a signal when the shift register is in a stage other than the input stage and the output stage.

Taking the transistors M1 to M13 in the shift register provided in the embodiment of the present application as an example, and fig. 8 is a second operation timing diagram of the shift register provided in the embodiment of the present application, as shown in fig. 6 and 8, the shift register provided in the embodiment of the present application includes 13 transistor units (M1 to M13), 1 capacitor unit (C), 4 INPUT terminals (INPUT, RESET, CLKA, and CLKB), 1 OUTPUT terminal (OUTPUT), and 2 power supply terminals (VSS and V), and an operation process thereof includes:

specifically, the input signal of the second power source terminal V is the same as the signal of the third node PD _ CN. As shown in fig. 6, the third node PD _ CN is a connection interface between the control electrode of the sixth transistor M6 and the second electrode of the seventh transistor M7.

In the first stage S11, i.e., the INPUT stage, the INPUT signal at the signal INPUT terminal INPUT is at a high level, the first transistor M1 is turned on, the INPUT signal at the second clock signal INPUT terminal CLKB is at a high level, the twelfth transistor M12 and the second transistor M2 are turned on, the potential of the pull-up node PU is pulled up, and the pull-up node PU charges the capacitor C. Since the voltage level of the pull-up node PU is pulled high, the eighth transistor M8, the ninth transistor M9, and the thirteenth transistor M13 are turned on, and since the signal of the second power source terminal V is at a low level, the voltage level of the pull-down node PD is pulled low, at this time, the voltage level of the pull-down node PD cannot turn on the tenth transistor M10 and the eleventh transistor M11, and the voltage level of the pull-up node PU is not pulled low.

In the second stage S12, i.e., the output stage, the INPUT signal at the signal INPUT terminal INPUT is at a low level, the first transistor M1 is turned off, the pull-up node PU continues to keep at a high level under the bootstrap action of the capacitor C, the eighth transistor M8, the ninth transistor M9 and the thirteenth transistor M13 are turned on, since the signal at the second power terminal V is at a low level, the potential of the pull-down node PD is continuously pulled down, at this time, the potential of the pull-down node PD cannot turn on the tenth transistor M10 and the eleventh transistor M11, and the potential of the pull-up node PU cannot be pulled down. Since the pull-up node PU is at a high level, the third transistor M3 is turned on, the input signal of the first clock signal input terminal CLKA is at a high level, and the signal OUTPUT terminal OUTPUT OUTPUTs the signal of the first clock signal input terminal CLKA, i.e., the gate driving signal.

In the third stage S13, namely, in the RESET stage, the input signal of the RESET signal input terminal RESET is at a high level, the fourth transistor M4 and the fifth transistor M5 are turned on, the fourth transistor M4 starts to discharge the pull-up node PU, and pulls down the potential of the pull-up node PU to a low level of the first power terminal VSS, the fifth transistor M5 starts to discharge the signal OUTPUT terminal OUTPUT, and pulls down the potential of the signal OUTPUT terminal OUTPUT to a low level of the first power terminal VSS, so as to reduce noise, the second clock signal input terminal CLKB is at a high level, the sixth transistor M6, the seventh transistor M7, the twelfth transistor M12, and the second transistor M2 are turned on, and further pulls down the potentials of the pull-up node PU and the signal OUTPUT terminal OUTPUT, and the ninth transistor M9 and the eighth transistor M8 are turned off because the pull-up node PU node is at a low level; since the ninth transistor M9 and the eighth transistor M8 are turned off, the potential of the pull-down node PD is pulled high, the tenth transistor M10 and the eleventh transistor M11 are turned on, and the potentials of the pull-up node PU and the signal OUTPUT terminal OUTPUT are further pulled low.

In this embodiment, the RESET signal input terminal RESET is connected to the signal OUTPUT terminal OUTPUT of the next-stage shift register, and the high-level signal of the RESET signal input terminal RESET is the high level OUTPUT by the signal OUTPUT terminal OUTPUT of the next-stage shift register.

In the fourth stage S14, since the potential of the pull-up node PU is at a low level, the third transistor M3 is turned off, the input signal of the first clock signal input terminal CLKA is at a high level, the high level of the first clock signal input terminal CLKA cannot be OUTPUT to the signal OUTPUT terminal OUTPUT, the signal OUTPUT terminal OUTPUT maintains the low level OUTPUT of the upper stage, the input signal of the second clock signal input terminal CLKB is at a low level, and the pull-down node PD is pulled down to a low level.

In the fifth stage S15, the input signal of the second clock signal input terminal CLKB is at a high level, and at this time, the ninth transistor M9 and the eighth transistor M8 are turned off, so that the potential of the pull-down node PD is at the high level of the input signal of the second clock signal input terminal CLKB, the tenth transistor M10 and the eleventh transistor M11 are turned on, the potential of the pull-up node PU is continuously pulled down to the first power terminal VSS, the eleventh transistor M11 is turned on, and the potential of the signal OUTPUT terminal OUTPUT is continuously pulled down to the low level of the first power terminal VSS, so as to avoid noise.

In this embodiment, after the first stage S11, the INPUT signal at the signal INPUT terminal INPUT is continuously at a low level; after the second stage S12, the OUTPUT signal of the signal OUTPUT terminal OUTPUT continues to be at the low level; the input signal of the second power supply terminal V is continuously at a high level; after the third stage S13, the input signal of the RESET signal input terminal RESET continues to be at a low level; the input signal of the first power source terminal VSS continues to be low level at all stages. After the fifth stage S15, the INPUT signals of the first clock signal INPUT terminal CLKA and the second clock signal INPUT terminal CLKB are sequentially repeated one or more times for the fourth stage S14 and the fifth stage S15 until the INPUT signal of the signal INPUT terminal INPUT is at a high level, and then restarted from the first stage S11.

In this embodiment, the structure of the shift register is still as shown in fig. 6, and only the timing of the second power supply terminal V is slightly adjusted to make the timing of the second power supply terminal V and the timing of the third node PD _ CN consistent, as shown in fig. 8, that is, when the pull-up node PU and the signal OUTPUT terminal OUTPUT are high, the second power supply terminal V is low, and then high, so that when the pull-up node PU is at normal high, since the second power supply terminal V is low, the tenth transistor M10 and the eleventh transistor M11 cannot be turned on by the second power supply terminal V, and the pull-up node PU and the signal OUTPUT terminal OUTPUT cannot be pulled down by mistake, which affects normal OUTPUT. After the OUTPUT of the signal OUTPUT terminal OUTPUT, and before the next time the INPUT signal arrives, once the pull-up node PU has a fluctuating or abnormally high potential, the second power supply terminal V will raise the potential of the pull-down node PD through the thirteenth transistor M13, so as to lower the potentials of the pull-up node PU and the signal OUTPUT terminal OUTPUT, and avoid the occurrence of erroneous OUTPUT of the shift register and Multi-OUTPUT.

The shift register pulls up the potential of the pull-down node PD under the condition that the pull-up node PU has abnormal high potentials such as fluctuation through the control sub-circuit, so that the potential of the pull-up node PU is pulled down in time, Multi-Output is effectively avoided, normal Output of a display panel is guaranteed, and the stability of the shift register and the picture quality of the display panel are improved.

Based on the same inventive concept, some embodiments of the present invention further provide a driving method of a shift register, which is applied to the shift register provided in the foregoing embodiments, and the shift register includes: fig. 9 is a flowchart of a driving method of a shift register according to an embodiment of the present invention, and as shown in fig. 9, the method specifically includes the following steps:

step 100, the input sub-circuit provides the signal of the signal input end to the pull-up node under the control of the signal input end.

Specifically, the input signal at the signal input terminal is a pulse signal, and in step 100, the input signal at the signal input terminal is at a high level, and the input sub-circuit pulls up the potential of the pull-up node.

Step 200, the output sub-circuit provides a signal of a first clock signal input end to a signal output end under the control of a pull-up node;

specifically, in this step, the input signal of the first clock signal input terminal is at a high level, and the output signal of the signal output terminal is at a high level.

Step 300, the reset sub-circuit provides the signal of the first power end to the pull-up node and the signal output end under the control of the reset signal input end.

Specifically, the input signal of the reset signal input terminal is a pulse signal, and in step 300, the input signal of the reset signal input terminal is a high level, and the reset sub-circuit pulls down the levels of the pull-up node and the signal output terminal to a low level signal of the first power terminal, so as to avoid noise.

In step 400, the pull-up sub-circuit provides a signal at the second clock signal input terminal to the pull-down node under the action of the second clock signal input terminal.

Specifically, in this step, the input signal at the second clock signal input end is at a high level, and the pull-up sub-circuit pulls up the potential of the pull-down node under the control of the second clock signal input end.

500, the pull-down sub-circuit provides a signal of a first power supply end to the pull-up node and the signal output end under the control of the pull-down node;

specifically, the pull-down sub-circuit pulls down the levels of the pull-up node and the signal output terminal to a low level signal of the first power supply terminal to avoid noise.

And step 600, the control sub-circuit provides a signal of a second power supply end to the pull-down node under the control of the pull-up node.

According to the technical scheme provided by the invention, the pull-down node is controlled by the control sub circuit to provide the signal of the second power supply end to the pull-down node, so that the potential of the pull-down node is pulled up, the problem of abnormal output of the display panel caused by the fact that the potential of the pull-up node cannot be pulled down when the pull-down node is at a low potential is solved, and the display quality of the liquid crystal panel is improved.

Based on the same inventive concept, an embodiment of the present application further provides a gate driving circuit, and fig. 10 is a schematic structural diagram of the gate driving circuit provided in the embodiment of the present application, as shown in fig. 10, the gate driving circuit includes: a plurality of cascaded shift registers, comprising: the shift register comprises a first-stage shift register GOA (1), a second-stage shift register GOA (2), a third-stage shift register GOA (3), a fourth-stage shift register GOA (4) and the like.

Specifically, a signal INPUT end INPUT of a first-stage shift register GOA (1) is connected with an initial signal INPUT end STV; the signal OUTPUT end OUTPUT is connected with the signal INPUT end INPUT of the second-stage shift register GOA (2), and the RESET signal INPUT end RESET is connected with the signal OUTPUT end OUTPUT of the second-stage shift register GOA (2); a signal OUTPUT end OUTPUT of the second-stage shift register GOA (2) is connected with a signal INPUT end INPUT of the third-stage shift register GOA (3), and a RESET signal INPUT end RESET is connected with a signal OUTPUT end OUTPUT of the third-stage shift register GOA (3); and so on.

The shift register is provided in the first embodiment, and the implementation principle and the implementation effect are similar, which are not described herein again.

The following points need to be explained:

the drawings of the embodiments of the present application relate only to the structures related to the embodiments of the present application, and other structures may refer to general designs.

Without conflict, features of embodiments of the present invention, that is, embodiments, may be combined with each other to arrive at new embodiments.

Although the embodiments of the present invention have been described above, the above description is only for the convenience of understanding the present invention, and is not intended to limit the present invention. It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.

Claims

1. A shift register, comprising: input sub-circuit, output sub-circuit, pull-up sub-circuit, pull-down sub-circuit, reset sub-circuit and control sub-circuit, wherein:

the input sub-circuit is respectively connected with the signal input end, the pull-up node and the second clock signal input end and is used for providing a signal of the signal input end to the pull-up node under the control of the signal input end and the second clock signal input end;

the output sub-circuit is respectively connected with the first clock signal input end, the pull-up node and the signal output end and is used for providing a signal of the first clock signal input end for the signal output end under the control of the pull-up node;

the reset sub-circuit is respectively connected with the reset signal input end, the first power end, the signal output end and the pull-up node, and is used for providing signals of the first power end to the pull-up node and the signal output end under the control of the reset signal input end;

the pull-up sub-circuit is respectively connected with the second clock signal input end and the pull-down node and is used for providing a signal of the second clock signal input end to the pull-down node under the action of the second clock signal input end;

the pull-down sub-circuit is respectively connected with the pull-up node, the pull-down node, the first power end, the second clock signal input end and the signal output end, and is used for providing signals of the first power end for the pull-up node and the signal output end under the control of the pull-up node, the pull-down node and the second clock signal input end;

the control sub-circuit is respectively connected with the pull-up node, the second power end and the pull-down node, and is used for pulling up the potential of the pull-down node to pull down the potential of the pull-up node when the pull-up node has a high potential after the output sub-circuit outputs a signal and before the input sub-circuit inputs a signal next time.

2. The shift register of claim 1, wherein the input sub-circuit comprises: a first transistor and a second transistor, wherein:

the control electrode and the first electrode of the first transistor are connected with the signal input end, and the second electrode of the first transistor is connected with the pull-up node;

the control electrode of the second transistor is connected with the second clock signal input end, the first electrode of the second transistor is connected with the signal input end, and the second electrode of the second transistor is connected with the pull-up node.

3. The shift register of claim 1, wherein the output sub-circuit comprises: a third transistor and a capacitor, the reset sub-circuit including: a fourth transistor and a fifth transistor, wherein:

the control electrode of the third transistor is connected with the pull-up node, the first electrode of the third transistor is connected with the first clock signal input end, and the second electrode of the third transistor is connected with the signal output end;

one end of the capacitor is connected with the pull-up node, and the other end of the capacitor is connected with the signal output end;

a control electrode of the fourth transistor is connected with the reset signal input end, a first electrode of the fourth transistor is connected with the pull-up node, and a second electrode of the fourth transistor is connected with the first power supply end;

and a control electrode of the fifth transistor is connected with the reset signal input end, a first electrode of the fifth transistor is connected with the signal output end, and a second electrode of the fifth transistor is connected with the first power supply end.

4. The shift register of claim 1, wherein the pull-up subcircuit comprises: a sixth transistor and a seventh transistor, the pull-down sub-circuit comprising: an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, and a twelfth transistor, wherein:

a control electrode of the sixth transistor is connected with the third node, a first electrode of the sixth transistor is connected with the second clock signal input end, and a second electrode of the sixth transistor is connected with the pull-down node;

a control electrode and a first electrode of the seventh transistor are connected with the second clock signal input end, and a second electrode of the seventh transistor is connected with the third node;

a control electrode of the eighth transistor is connected with the pull-up node, a first electrode of the eighth transistor is connected with the pull-down node, and a second electrode of the eighth transistor is connected with the first power supply end;

a control electrode of the ninth transistor is connected with the pull-up node, a first electrode of the ninth transistor is connected with the third node, and a second electrode of the ninth transistor is connected with the first power supply end;

a control electrode of the tenth transistor is connected with the pull-down node, a first electrode of the tenth transistor is connected with the pull-up node, and a second electrode of the tenth transistor is connected with the first power supply end;

a control electrode of the eleventh transistor is connected with the pull-down node, a first electrode of the eleventh transistor is connected with the signal output end, and a second electrode of the eleventh transistor is connected with the first power supply end;

and a control electrode of the twelfth transistor is connected with the second clock signal input end, a first electrode of the twelfth transistor is connected with the signal output end, and a second electrode of the twelfth transistor is connected with the first power supply end.

5. The shift register of claim 1, wherein the control subcircuit comprises: a thirteenth transistor, wherein:

a control electrode of the thirteenth transistor is connected with the pull-up node, a first electrode of the thirteenth transistor is connected with the second power supply terminal, and a second electrode of the thirteenth transistor is connected with the pull-down node.

6. The shift register of claim 1, wherein the input sub-circuit comprises: a first transistor and a second transistor, the output sub-circuit including: a third transistor and a capacitor, the reset sub-circuit including: a fourth transistor and a fifth transistor, the pull-up sub-circuit comprising: a sixth transistor and a seventh transistor, the pull-down sub-circuit comprising: an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, and a twelfth transistor, the control sub-circuit including: a thirteenth transistor, wherein:

the control electrode of the second transistor is connected with the second clock signal input end, the first electrode of the second transistor is connected with the signal input end, and the second electrode of the second transistor is connected with the pull-up node;

a control electrode of the fifth transistor is connected with the reset signal input end, a first electrode of the fifth transistor is connected with the signal output end, and a second electrode of the fifth transistor is connected with the first power supply end;

a control electrode of the twelfth transistor is connected with the second clock signal input end, a first electrode of the twelfth transistor is connected with the signal output end, and a second electrode of the twelfth transistor is connected with the first power supply end;

7. The shift register of claim 6, wherein the second power supply terminal continuously provides an active level, and the width-to-length ratio of the thirteenth transistor satisfies: when the signal of the pull-up node is a first signal, the tenth transistor and the eleventh transistor cannot be turned on by the signal of the pull-down node, when the signal of the pull-up node is a second signal, the tenth transistor and the eleventh transistor are turned on by the signal of the pull-down node, the first signal is a signal when the shift register is in an input stage or an output stage, and the second signal is a signal when the shift register is in a stage other than the input stage and the output stage.

8. The shift register of claim 6, wherein the signal of the second power supply terminal is the same as the signal of the third node, and the ratio of width to length of the thirteenth transistor satisfies: when the signal of the pull-up node is a first signal, the tenth transistor and the eleventh transistor cannot be turned on by the signal of the pull-down node, when the signal of the pull-up node is a second signal, the tenth transistor and the eleventh transistor are turned on by the signal of the pull-down node, the first signal is a signal when the shift register is in an input stage or an output stage, and the second signal is a signal when the shift register is in a stage other than the input stage and the output stage.

9. A gate drive circuit, comprising: a plurality of cascaded shift registers as claimed in any one of claims 1 to 8.

10. A method for driving a shift register, which is applied to the shift register according to any one of claims 1 to 8, the method comprising:

the input sub-circuit provides a signal of the signal input end to the pull-up node under the control of the signal input end;

the output sub-circuit provides a signal of the first clock signal input end to the signal output end under the control of the pull-up node;

the reset sub-circuit provides a signal of a first power supply end to the pull-up node and the signal output end under the control of the reset signal input end;

the pull-up sub-circuit provides a signal of the second clock signal input end to a pull-down node under the action of the second clock signal input end;

the pull-down sub-circuit provides a signal of a first power supply end to the pull-up node and the signal output end under the control of the pull-down node;

and the control sub-circuit pulls up the potential of the pull-down node after the output sub-circuit outputs the signal and before the input sub-circuit inputs the signal next time when the pull-up node has high potential so as to pull down the potential of the pull-up node.