CN110910813B

CN110910813B - Shifting register, driving method thereof and grid driving circuit

Info

Publication number: CN110910813B
Application number: CN201911320645.2A
Authority: CN
Inventors: 闫伟; 王珍; 王争奎; 张寒; 秦文文; 张健; 王德帅; 孙建
Original assignee: BOE Technology Group Co Ltd
Current assignee: BOE Technology Group Co Ltd
Priority date: 2019-12-19
Filing date: 2019-12-19
Publication date: 2023-06-09
Anticipated expiration: 2039-12-19
Also published as: CN110910813A

Abstract

A shift register, a driving method thereof and a gate driving circuit, wherein the shift register comprises: an input sub-circuit for providing a signal of a first signal terminal to a pull-up node under control of a signal input terminal, an output sub-circuit for providing a signal of a first clock terminal to a signal output terminal under control of the pull-up node and the first power terminal, a pull-up sub-circuit for providing a signal of a second clock terminal to a pull-down node under control of a second clock terminal, a node pull-down sub-circuit for providing a signal of a second power terminal to the pull-down node under control of the pull-up node and the signal output terminal, and a noise reduction sub-circuit for providing a signal of the second power terminal to the pull-up node and the signal output terminal under control of the pull-down node and the signal output terminal. The method and the device avoid large current in the shift register, further reduce the power consumption of the shift register, and improve the working stability, the use reliability and the display effect of the display panel.

Description

Shifting register, driving method thereof and grid driving circuit

Technical Field

The present disclosure relates to the field of display technologies, and in particular, to a shift register, a driving method thereof, and a gate driving circuit.

Background

In recent years, flat panel displays, such as thin film transistor liquid crystal display panels (Thin Film Transistor-Liquid Crystal Display, TFT-LCDs) and active matrix organic light emitting diode display panels (Active Matrix Organic Light Emitting Diode, AMOLEDs), have been widely used in electronic products such as televisions, cellular phones, and the like due to their light weight, thin thickness, and low power consumption.

With the development of technology, high resolution and narrow frame display panels have been developed, and for this reason, array substrate gate driving (Gate Driver on Array, GOA) technology has been developed, in which GOA circuits for driving gate lines are disposed on both sides of an effective display area of an array substrate in a display panel, wherein the GOA circuits include a plurality of shift registers.

In the related art, large current exists in the working process of the shift register, so that the power consumption of the shift register is larger, and the working stability, the use reliability and the display effect of the display panel are reduced.

Content of the application

The embodiment of the application provides a shift register, a driving method thereof and a grid driving circuit, which can reduce the power consumption of the shift register and improve the working stability, the use reliability and the display effect of a display panel.

In a first aspect, the present application provides a shift register, comprising: an input sub-circuit, an output sub-circuit, a node pull-up sub-circuit, a node pull-down sub-circuit and a noise reduction sub-circuit;

the input sub-circuit is respectively connected with the signal input end, the first signal end and the pull-up node and is used for providing a signal of the first signal end for the pull-up node under the control of the signal input end;

the output sub-circuit is respectively connected with the first power supply end, the first clock end, the pull-up node and the signal output end and is used for providing signals of the first clock end for the signal output end under the control of the pull-up node and the first power supply end;

the node pull-up sub-circuit is respectively connected with the second clock end and the pull-down node and is used for providing a signal of the second clock end for the pull-down node under the control of the second clock end;

the node pull-down sub-circuit is respectively connected with the pull-up node, the pull-down node, the signal output end and the second power end and is used for providing signals of the second power end for the pull-down node under the control of the pull-up node and the signal output end;

the noise reduction sub-circuit is respectively connected with the pull-up node, the pull-down node, the signal output end and the second power end and is used for providing signals of the second power end for the pull-up node and the signal output end under the control of the pull-down node and the signal output end.

Optionally, the shift register further includes: the touch control circuit comprises a first reset sub-circuit, a second reset sub-circuit and a touch control sub-circuit;

the first reset sub-circuit is respectively connected with the first reset end, the pull-up node and the second signal end and is used for providing signals of the second signal end for the pull-up node under the control of the first reset end;

the second reset sub-circuit is respectively connected with the second reset end, the pull-up node and the second power end and is used for providing a signal of the second power end for the pull-up node under the control of the second reset end;

the touch sub-circuit is respectively connected with the touch enabling end, the signal output end and the second power end and is used for providing signals of the second power end for the signal output end under the control of the touch enabling end.

Optionally, the input sub-circuit includes: a first transistor;

the control electrode of the first transistor is connected with the signal input end, the first electrode of the first transistor is connected with the first signal end, and the second electrode of the first transistor is connected with the pull-up node;

the output sub-circuit includes: a second transistor, a third transistor, and a first capacitor;

the control electrode of the second transistor is connected with the first end of the first capacitor, the first electrode of the second transistor is connected with the first clock end, and the second electrode of the second transistor is connected with the signal output end;

The control electrode of the third transistor is connected with the first power supply end, the first electrode of the third transistor is connected with the pull-up node, and the second electrode of the third transistor is connected with the first end of the first capacitor;

the second end of the first capacitor is connected with the signal output end.

Optionally, the node pull-up sub-circuit includes: a fourth transistor;

the control electrode and the first electrode of the fourth transistor are connected with the second clock end, and the second electrode of the fourth transistor is connected with the pull-down node;

the noise reduction sub-circuit includes: fifth to seventh transistors and a second capacitor;

the control electrode of the fifth transistor is connected with the pull-down node, the first electrode of the fifth transistor is connected with the second electrode of the sixth transistor, and the second electrode of the fifth transistor is connected with the second power supply end;

the control electrode of the sixth transistor is connected with the signal output end, and the first electrode of the sixth transistor is connected with the pull-up node;

the control electrode of the seventh transistor is connected with the pull-down node, the first electrode of the seventh transistor is connected with the signal output end, and the second electrode of the seventh transistor is connected with the second power supply end;

the first end of the second capacitor is connected with the pull-down node, and the second end of the second capacitor is connected with the signal output end.

Optionally, the node pull-down subcircuit includes: eighth to tenth transistors;

the control electrode of the eighth transistor is connected with the signal output end, the first electrode of the eighth transistor is connected with the pull-down node, and the second electrode of the eighth transistor is connected with the first electrode of the ninth transistor;

the control electrode of the ninth transistor is connected with the pull-up node, and the second electrode of the ninth transistor is connected with the second power supply end;

the control electrode of the tenth transistor is connected with the signal output end, the first electrode of the tenth transistor is connected with the pull-down node, and the second electrode of the tenth transistor is connected with the second power end.

Optionally, the first reset sub-circuit includes: an eleventh transistor;

the control electrode of the eleventh transistor is connected with the first reset end, the first electrode of the eleventh transistor is connected with the pull-up node, and the second electrode of the eleventh transistor is connected with the second signal end;

the second reset sub-circuit includes: a twelfth transistor;

the control electrode of the twelfth transistor is connected with the second reset end, the first electrode of the twelfth transistor is connected with the pull-up node, and the second electrode of the twelfth transistor is connected with the second power end;

The touch sub-circuit includes: a thirteenth transistor;

the control electrode of the thirteenth transistor is connected with the touch control enabling end, the first electrode of the thirteenth transistor is connected with the signal output end, and the second electrode of the thirteenth transistor is connected with the second power supply end.

Optionally, the shift register further includes: the touch control circuit comprises a first reset sub-circuit, a second reset sub-circuit and a touch control sub-circuit; the input sub-circuit includes: a first transistor; the output sub-circuit includes: a second transistor, a third transistor, and a first capacitor; the node pull-up sub-circuit includes: a fourth transistor; the noise reduction sub-circuit includes: fifth to seventh transistors and a second capacitor; the node pull-down subcircuit includes: eighth to tenth transistors; the first reset sub-circuit includes: an eleventh transistor; the second reset sub-circuit includes: a twelfth transistor; the touch sub-circuit includes: a thirteenth transistor;

the second end of the first capacitor is connected with the signal output end;

The first end of the second capacitor is connected with the pull-down node, and the second end of the second capacitor is connected with the signal output end;

the control electrode of the tenth transistor is connected with the signal output end, the first electrode of the tenth transistor is connected with the pull-down node, and the second electrode of the tenth transistor is connected with the second power end;

Optionally, when the level of the clock signal at the first clock terminal is an active level, the level of the clock signal at the second clock terminal is an inactive level, and when the level of the clock signal at the second clock terminal is an active level, the level of the clock signal at the first clock terminal is an inactive level.

In a second aspect, the present application further provides a gate driving circuit, including: a plurality of cascaded shift registers.

Optionally, the gate driving circuit includes: an initial signal end and a reset control end;

the signal input end of the first stage shift register is connected with the initial signal end, the signal output end of the N stage shift register is connected with the signal input end of the (n+1) stage shift register, and the signal output end of the (n+1) stage shift register is connected with the first reset end of the N stage shift register; the second reset ends of all the stages of shift registers are connected with the reset control end.

In a third aspect, the present application further provides a driving method of a shift register, applied to the shift register, where in a display period, the method includes:

under the control of the signal input end, the input sub-circuit provides a signal of the first signal end for the pull-up node; under the control of the second clock end, the node pull-up sub-circuit provides a signal of the second clock end for the pull-down node;

Under the control of the pull-up node and the first power supply end, the output sub-circuit provides a signal of the first clock end for the signal output end; under the control of the pull-up node and the signal output end, the node pull-down sub-circuit provides a signal of the second power supply end for the pull-down node;

the noise reduction sub-circuit provides signals of the second power supply terminal to the pull-up node and the signal output terminal under the control of the pull-down node and the signal output terminal.

Optionally, the method further comprises: the first reset sub-circuit provides a signal of the second signal terminal to the pull-up node under control of the first reset terminal.

The embodiment of the application provides a shift register, a driving method thereof and a gate driving circuit, wherein the shift register comprises: an input sub-circuit, an output sub-circuit, a node pull-up sub-circuit, a node pull-down sub-circuit and a noise reduction sub-circuit; the input sub-circuit is respectively connected with the signal input end, the first signal end and the pull-up node and is used for providing a signal of the first signal end for the pull-up node under the control of the signal input end; the output sub-circuit is respectively connected with the first power supply end, the first clock end, the pull-up node and the signal output end and is used for providing signals of the first clock end for the signal output end under the control of the pull-up node and the first power supply end; the node pull-up sub-circuit is respectively connected with the second clock end and the pull-down node and is used for providing a signal of the second clock end for the pull-down node under the control of the second clock end; the node pull-down sub-circuit is respectively connected with the pull-up node, the pull-down node, the signal output end and the second power end and is used for providing signals of the second power end for the pull-down node under the control of the pull-up node and the signal output end; and the noise reduction sub-circuit is respectively connected with the pull-up node, the pull-down node, the signal output end and the second power end and is used for providing signals of the second power end for the pull-up node and the signal output end under the control of the pull-down node and the signal output end. According to the embodiment of the application, through setting the node pull-down sub-circuit, the pull-up node and the signal output end simultaneously control the signal of the pull-down node, so that the large current in the shift register is avoided, the power consumption of the shift register is further reduced, and the working stability, the use reliability and the display effect of the display panel are improved.

Additional features and advantages of the application will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the application. Other advantages of the present application may be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.

Drawings

The accompanying drawings are included to provide an understanding of the technical aspects of the present application, and are incorporated in and constitute a part of this specification, illustrate the technical aspects of the present application and together with the examples of the present application, and not constitute a limitation of the technical aspects of the present application.

Fig. 1 is a schematic structural diagram of a shift register according to an embodiment of the present application;

FIG. 2 is a schematic diagram of another structure of a shift register according to an embodiment of the present disclosure;

FIG. 3 is an equivalent circuit diagram of an input sub-circuit provided in an embodiment of the present application;

fig. 4 is an equivalent circuit diagram of an output sub-circuit according to an embodiment of the present application;

fig. 5 is an equivalent circuit diagram of a node pull-up sub-circuit according to an embodiment of the present application;

fig. 6 is an equivalent circuit diagram of a noise reduction sub-circuit provided in an embodiment of the present application;

fig. 7 is an equivalent circuit diagram of a node pull-down sub-circuit according to an embodiment of the present application;

fig. 8 is an equivalent circuit diagram of a first reset sub-circuit provided in an embodiment of the present application;

Fig. 9 is an equivalent circuit diagram of a second reset sub-circuit provided in an embodiment of the present application;

fig. 10 is an equivalent circuit diagram of a touch sub-circuit provided in an embodiment of the present application;

FIG. 11 is an equivalent circuit diagram of a shift register according to an embodiment of the present disclosure;

FIG. 12 is a timing chart of the shift register according to the embodiment of the present application;

fig. 13 is a schematic structural diagram of a gate driving circuit according to an embodiment of the present disclosure;

fig. 14 is a flowchart of a driving method of a shift register according to an embodiment of the present application.

Detailed Description

The present application describes a number of embodiments, but the description is illustrative and not limiting and it will be apparent to those of ordinary skill in the art that many more embodiments and implementations are possible within the scope of the embodiments described herein. Although many possible combinations of features are shown in the drawings and discussed in the detailed description, many other combinations of the disclosed features are possible. Any feature or element of any embodiment may be used in combination with or in place of any other feature or element of any other embodiment unless specifically limited.

The present application includes and contemplates combinations of features and elements known to those of ordinary skill in the art. The embodiments, features and elements of the present disclosure may also be combined with any conventional features or elements to form a unique claim as defined by the claims. Any feature or element of any embodiment may also be combined with features or elements from other claims to form another unique claim as defined in the claims. Thus, it should be understood that any of the features shown and/or discussed in this application may be implemented alone or in any suitable combination. Accordingly, the embodiments are not to be restricted except in light of the attached claims and their equivalents. Further, various modifications and changes may be made within the scope of the appended claims.

Furthermore, in describing representative embodiments, the specification may have presented the method and/or process as a particular sequence of steps. However, to the extent that the method or process does not rely on the particular order of steps set forth herein, the method or process should not be limited to the particular sequence of steps described. Other sequences of steps are possible as will be appreciated by those of ordinary skill in the art. Accordingly, the particular order of the steps set forth in the specification should not be construed as limitations on the claims. Furthermore, the claims directed to the method and/or process should not be limited to the performance of their steps in the order written, and one skilled in the art can readily appreciate that the sequences may be varied and still remain within the spirit and scope of the embodiments of the present application.

Unless otherwise defined, technical or scientific terms used in the disclosure of the embodiments of the present application should be given the ordinary meaning as understood by one of ordinary skill in the art to which the present application belongs. The terms "first," "second," and the like, as used in embodiments of the present application, do not denote any order, quantity, or importance, but rather are used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that elements or items preceding the word are included in the element or item listed after the word and equivalents thereof, but does not exclude other elements or items. The terms "connected" or "connected," and the like, are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

Those skilled in the art will appreciate that the transistors used in all embodiments of the present application may be thin film transistors or field effect transistors or other devices having the same characteristics. Preferably, the thin film transistor used in the embodiments of the present application may be an oxide semiconductor transistor. Since the source and drain of the transistor used herein are symmetrical, the source and drain may be interchanged. In the embodiment of the present application, to distinguish between two electrodes of the transistor except the gate electrode, one of the electrodes is referred to as a first electrode, the other electrode is referred to as a second electrode, the first electrode may be a source electrode or a drain electrode, the second electrode may be a drain electrode or a source electrode, and in addition, the gate electrode of the transistor is referred to as a control electrode.

Some embodiments of the present application provide a shift register, fig. 1 is a schematic structural diagram of the shift register provided in the embodiments of the present application, as shown in fig. 1, where the shift register provided in the embodiments of the present application includes: an input sub-circuit, an output sub-circuit, a node pull-up sub-circuit, a node pull-down sub-circuit, and a noise reduction sub-circuit.

Specifically, the INPUT sub-circuit is respectively connected with the signal INPUT end INPUT, the first signal end CN and the pull-up node PU, and is configured to provide a signal of the first signal end CN to the pull-up node PU under the control of the signal INPUT end INPUT; an output sub-circuit connected to the first power supply terminal VGH, the first clock terminal CLK1, the pull-up node PU, and the signal output terminal OUT, respectively, for providing a signal of the first clock terminal CLK1 to the signal output terminal OUT under control of the pull-up node PU and the first power supply terminal VGH; the node pull-up sub-circuit is respectively connected with the second clock terminal CLK2 and the pull-down node PD and is used for providing a signal of the second clock terminal CLK2 to the pull-down node PD under the control of the second clock terminal CLK 2; the node pull-down sub-circuit is respectively connected with the pull-up node PU, the pull-down node PD, the signal output end OUT and the second power end VGL and is used for providing signals of the second power end VGL for the pull-down node PD under the control of the pull-up node PU and the signal output end OUT; and the noise reduction sub-circuit is respectively connected with the pull-up node PU, the pull-down node PD, the signal output end OUT and the second power supply end VGL and is used for providing signals of the second power supply end VGL for the pull-up node PU and the signal output end OUT under the control of the pull-down node PD and the signal output end OUT.

In this embodiment, the shift register includes: the display stage and the touch stage, in the display stage, the first power supply end VGH continuously provides a first level signal, the second power supply end VGL continuously provides a second level signal, the output signal of the signal output end OUT is a pulse signal, and in the touch stage, the signal output end OUT does not output a signal.

The shift register provided by the embodiment of the application comprises: an input sub-circuit, an output sub-circuit, a node pull-up sub-circuit, a node pull-down sub-circuit and a noise reduction sub-circuit; the input sub-circuit is respectively connected with the signal input end, the first signal end and the pull-up node and is used for providing a signal of the first signal end for the pull-up node under the control of the signal input end; the output sub-circuit is respectively connected with the first power supply end, the first clock end, the pull-up node and the signal output end and is used for providing signals of the first clock end for the signal output end under the control of the pull-up node and the first power supply end; the node pull-up sub-circuit is respectively connected with the second clock end and the pull-down node and is used for providing a signal of the second clock end for the pull-down node under the control of the second clock end; the node pull-down sub-circuit is respectively connected with the pull-up node, the pull-down node, the signal output end and the second power end and is used for providing signals of the second power end for the pull-down node under the control of the pull-up node and the signal output end; and the noise reduction sub-circuit is respectively connected with the pull-up node, the pull-down node, the signal output end and the second power end and is used for providing signals of the second power end for the pull-up node and the signal output end under the control of the pull-down node and the signal output end. According to the embodiment of the application, through setting the node pull-down sub-circuit, the pull-up node and the signal output end simultaneously control the signal of the pull-down node, so that the large current in the shift register is avoided, the power consumption of the shift register is further reduced, and the working stability, the use reliability and the display effect of the display panel are improved.

Optionally, fig. 2 is another schematic structural diagram of a shift register provided in an embodiment of the present application, as shown in fig. 2, where the shift register provided in the embodiment of the present application further includes: the touch control circuit comprises a first reset sub-circuit, a second reset sub-circuit and a touch control sub-circuit.

Specifically, the first reset sub-circuit is respectively connected with the first reset terminal RST1, the pull-up node PU and the second signal terminal CNB, and is configured to provide a signal of the second signal terminal CNB to the pull-up node PU under the control of the first reset terminal RST 1; the second reset sub-circuit is respectively connected with the second reset terminal RST2, the pull-up node PU and the second power supply terminal VGL and is used for providing a signal of the second power supply terminal VGL for the pull-up node PU under the control of the second reset terminal RST 2; the touch sub-circuit is respectively connected with the touch enabling end EN, the signal output end OUT and the second power supply end VGL and is used for providing signals of the second power supply end VGL for the signal output end OUT under the control of the touch enabling end EN.

In this embodiment, in the display stage, the level of the input signals of the touch enable terminal EN and the second reset terminal RST2 is an inactive level, and in the touch stage, the level of the input signals of the touch enable terminal EN and the second reset terminal RST2 is an active level.

According to the embodiment of the application, the first reset sub-circuit and the second reset sub-circuit are added in the shift register, so that noise in the shift register can be reduced, the working stability, the use reliability and the display effect of the display panel are further improved, and in addition, the touch sub-circuit is added in the shift register, so that the application range of the display panel can be further improved.

Optionally, fig. 3 is an equivalent circuit diagram of an input sub-circuit provided in an embodiment of the present application, as shown in fig. 3, an input sub-circuit in a shift register provided in an embodiment of the present application includes: a first transistor M1.

Specifically, the control electrode of the first transistor M1 is connected to the signal INPUT terminal INPUT, the first electrode of the first transistor M1 is connected to the first signal terminal CN, and the second electrode of the first transistor M1 is connected to the pull-up node PU.

In this embodiment, an exemplary structure of the input sub-circuit is specifically shown in fig. 3. Those skilled in the art will readily appreciate that the implementation of the input subcircuit is not limited thereto, so long as it is capable of performing its functions.

Optionally, fig. 4 is an equivalent circuit diagram of an output sub-circuit provided in an embodiment of the present application, as shown in fig. 4, an output sub-circuit in a shift register provided in an embodiment of the present application includes: a second transistor M2, a third transistor M3 and a first capacitor C1.

Specifically, the control electrode of the second transistor M2 is connected to the first end of the first capacitor C1, the first electrode of the second transistor M2 is connected to the first clock end CLK1, and the second electrode of the second transistor M2 is connected to the signal output end OUT; the control electrode of the third transistor M3 is connected to the first power supply terminal VGH, the first electrode of the third transistor M3 is connected to the pull-up node PU, and the second electrode of the third transistor M3 is connected to the first terminal of the first capacitor C1; the second terminal of the first capacitor C1 is connected to the signal output terminal OUT.

In the present embodiment, an exemplary structure of the output sub-circuit is specifically shown in fig. 4. Those skilled in the art will readily appreciate that the implementation of the output subcircuit is not limited thereto, so long as it is capable of performing its functions.

Optionally, fig. 5 is an equivalent circuit diagram of a node pull-up sub-circuit provided in an embodiment of the present application, as shown in fig. 5, a node pull-up sub-circuit in a shift register provided in an embodiment of the present application includes: and a fourth transistor M4.

Specifically, the control electrode and the first electrode of the fourth transistor M4 are connected to the second clock terminal CLK2, and the second electrode of the fourth transistor M4 is connected to the pull-down node PD.

In this embodiment, an exemplary structure of the node pull-up sub-circuit is specifically shown in fig. 5. Those skilled in the art will readily appreciate that the implementation of the node pull-up subcircuit is not limited thereto, so long as it is capable of performing its functions.

Optionally, fig. 6 is an equivalent circuit diagram of a noise reduction sub-circuit provided in an embodiment of the present application, as shown in fig. 6, the noise reduction sub-circuit in the shift register provided in the embodiment of the present application includes: fifth to seventh transistors M5 to M7 and a second capacitor C2.

Specifically, the control electrode of the fifth transistor M5 is connected to the pull-down node PD, the first electrode of the fifth transistor M5 is connected to the second electrode of the sixth transistor M6, and the second electrode of the fifth transistor M5 is connected to the second power supply terminal VGL; the control electrode of the sixth transistor M6 is connected with the signal output end OUT, and the first electrode of the sixth transistor M6 is connected with the pull-up node PU; the control electrode of the seventh transistor M7 is connected to the pull-down node PD, the first electrode of the seventh transistor M7 is connected to the signal output terminal OUT, and the second electrode of the seventh transistor M7 is connected to the second power supply terminal VGL; the first terminal of the second capacitor C2 is connected to the pull-down node PD, and the second terminal of the second capacitor C2 is connected to the signal output terminal OUT.

In the present embodiment, an exemplary structure of the noise reduction sub-circuit is specifically shown in fig. 6. Those skilled in the art will readily appreciate that the implementation of the input subcircuit is not limited thereto, so long as it is capable of performing its functions.

Optionally, fig. 7 is an equivalent circuit diagram of a node pull-down sub-circuit provided in an embodiment of the present application, as shown in fig. 7, a node pull-down sub-circuit in a shift register provided in an embodiment of the present application includes: eighth to tenth transistors M8 to M10.

Specifically, the control electrode of the eighth transistor M8 is connected to the signal output terminal OUT, the first electrode of the eighth transistor M8 is connected to the pull-down node PD, and the second electrode of the eighth transistor M8 is connected to the first electrode of the ninth transistor M9; a control electrode of the ninth transistor M9 is connected to the pull-up node PU, and a second electrode of the ninth transistor M9 is connected to the second power supply terminal VGL; the control electrode of the tenth transistor M10 is connected to the signal output terminal OUT, the first electrode of the tenth transistor M10 is connected to the pull-down node PD, and the second electrode of the tenth transistor M10 is connected to the second power supply terminal VGL.

In the present embodiment, an exemplary structure of the node pull-down sub-circuit is specifically shown in fig. 7. Those skilled in the art will readily appreciate that the implementation of the node drop-down subcircuit is not limited thereto, so long as it is capable of performing its functions.

Optionally, fig. 8 is an equivalent circuit diagram of a first reset sub-circuit provided in an embodiment of the present application, as shown in fig. 8, where the first reset sub-circuit in the shift register provided in the embodiment of the present application includes: an eleventh transistor M11.

Specifically, the control electrode of the eleventh transistor M11 is connected to the first reset terminal RST1, the first electrode of the eleventh transistor M11 is connected to the pull-up node PU, and the second electrode of the eleventh transistor M11 is connected to the second signal terminal CNB.

In the present embodiment, an exemplary structure of the first reset sub-circuit is specifically shown in fig. 8. It will be readily appreciated by those skilled in the art that the implementation of the first reset sub-circuit is not limited thereto, as long as its function can be implemented.

Optionally, fig. 9 is an equivalent circuit diagram of a second reset sub-circuit provided in an embodiment of the present application, as shown in fig. 9, where the second reset sub-circuit in the shift register provided in the embodiment of the present application includes: a twelfth transistor M12.

Specifically, the control electrode of the twelfth transistor M12 is connected to the second reset terminal RST2, the first electrode of the twelfth transistor M12 is connected to the pull-up node PU, and the second electrode of the twelfth transistor M12 is connected to the second power supply terminal VGL.

In the present embodiment, an exemplary structure of the second reset sub-circuit is specifically shown in fig. 9. It will be readily appreciated by those skilled in the art that the implementation of the second reset sub-circuit is not limited thereto, as long as it is capable of performing its function.

Optionally, fig. 10 is an equivalent circuit diagram of a touch sub-circuit provided in an embodiment of the present application, as shown in fig. 10, the touch sub-circuit in the shift register provided in the embodiment of the present application includes: thirteenth transistor M13.

Specifically, the control electrode of the thirteenth transistor M13 is connected to the touch enable terminal EN, the first electrode of the thirteenth transistor M13 is connected to the signal output terminal OUT, and the second electrode of the thirteenth transistor M13 is connected to the second power supply terminal VGL.

In this embodiment, an exemplary structure of the touch sub-circuit is specifically shown in fig. 10. Those skilled in the art will readily appreciate that the implementation of the touch sub-circuit is not limited thereto, as long as its functionality can be implemented.

Fig. 11 is an equivalent circuit diagram of a shift register provided in an embodiment of the present application, as shown in fig. 11, where the shift register provided in the embodiment of the present application further includes: the touch control circuit comprises a first reset sub-circuit, a second reset sub-circuit and a touch control sub-circuit; the input sub-circuit includes: a first transistor M1; the output sub-circuit includes: a second transistor M2, a third transistor M3, and a first capacitor C1; the node pull-up sub-circuit includes: a fourth transistor M4; the noise reduction sub-circuit includes: fifth to seventh transistors M5 to M7 and a second capacitor C2; the node pull-down subcircuit includes: eighth to tenth transistors M8 to M10; the first reset sub-circuit includes: an eleventh transistor M11; the second reset sub-circuit includes: a twelfth transistor M12; the touch sub-circuit includes: thirteenth transistor M13.

Specifically, the control electrode of the first transistor M1 is connected to the signal INPUT terminal INPUT, the first electrode of the first transistor M1 is connected to the first signal terminal CN, and the second electrode of the first transistor M1 is connected to the pull-up node PU; the control electrode of the second transistor M2 is connected with the first end of the first capacitor C1, the first electrode of the second transistor M2 is connected with the first clock end CLK1, and the second electrode of the second transistor M2 is connected with the signal output end OUT; the control electrode of the third transistor M3 is connected to the first power supply terminal VGH, the first electrode of the third transistor M3 is connected to the pull-up node PU, and the second electrode of the third transistor M3 is connected to the first terminal of the first capacitor C1; the second end of the first capacitor C1 is connected with the signal output end OUT; the control pole and the first pole of the fourth transistor M4 are connected to the second clock terminal CLK2, and the second pole of the fourth transistor M4 is connected to the pull-down node PD; the control electrode of the fifth transistor M5 is connected to the pull-down node PD, the first electrode of the fifth transistor M5 is connected to the second electrode of the sixth transistor M6, and the second electrode of the fifth transistor M5 is connected to the second power supply terminal VGL; the control electrode of the sixth transistor M6 is connected with the signal output end OUT, and the first electrode of the sixth transistor M6 is connected with the pull-up node PU; the control electrode of the seventh transistor M7 is connected to the pull-down node PD, the first electrode of the seventh transistor M7 is connected to the signal output terminal OUT, and the second electrode of the seventh transistor M7 is connected to the second power supply terminal VGL; a first end of the second capacitor C2 is connected with the pull-down node PD, and a second end of the second capacitor C2 is connected with the signal output end OUT; a control electrode of the eighth transistor M8 is connected to the signal output terminal OUT, a first electrode of the eighth transistor M8 is connected to the pull-down node PD, and a second electrode of the eighth transistor M8 is connected to a first electrode of the ninth transistor M9; a control electrode of the ninth transistor M9 is connected to the pull-up node PU, and a second electrode of the ninth transistor M9 is connected to the second power supply terminal VGL; a control electrode of the tenth transistor M10 is connected to the signal output terminal OUT, a first electrode of the tenth transistor M10 is connected to the pull-down node PD, and a second electrode of the tenth transistor M10 is connected to the second power supply terminal VGL; the control electrode of the eleventh transistor M11 is connected to the first reset terminal RST1, the first electrode of the eleventh transistor M11 is connected to the pull-up node PU, and the second electrode of the eleventh transistor M11 is connected to the second signal terminal CNB; the control electrode of the twelfth transistor M12 is connected with the second reset end RST2, the first electrode of the twelfth transistor M12 is connected with the pull-up node PU, and the second electrode of the twelfth transistor M12 is connected with the second power end VGL; the control electrode of the thirteenth transistor M13 is connected to the touch enable terminal EN, the first electrode of the thirteenth transistor M13 is connected to the signal output terminal OUT, and the second electrode of the thirteenth transistor M13 is connected to the second power supply terminal VGL.

Alternatively, when the level of the clock signal of the first clock terminal CLK1 is an active level, the level of the clock signal of the second clock terminal CLK2 is an inactive level, and when the level of the clock signal of the second clock terminal CLK2 is an active level, the level of the clock signal of the first clock terminal CLK1 is an inactive level.

The pulse duration of the clock signal of the first clock terminal CLK1 is equal to the pulse duration of the clock signal of the second clock terminal CLK 2.

In this embodiment, the transistors M1 to M13 may be N-type thin film transistors or P-type thin film transistors, which may unify the process flows, reduce the process steps, and help to improve the yield of the product. In addition, considering that the leakage current of the low-temperature polysilicon thin film transistor is small, it is preferable in the embodiments of the present application that all the transistors are low-temperature polysilicon thin film transistors, and the thin film transistor may specifically be a thin film transistor with a bottom gate structure or a thin film transistor with a top gate structure, so long as a switching function can be realized.

The technical scheme of the embodiment of the application is further described through the working process of the shift register.

Taking the example that the transistors M1 to M13 in the shift register provided in the embodiment of the present application are all N-type thin film transistors, fig. 12 is a working timing chart of the shift register provided in the embodiment of the present application, as shown in fig. 11 and fig. 12, the shift register provided in the embodiment of the present application includes 13 transistor units (M1 to M13), 1 capacitor (C1 and C2), 8 signal INPUT ends (INPUT, RST1, RST2, CN, CNB, CLK1, CLK2 and EN), 1 signal output end (OUT) and 2 power supply ends (VGH and VGL).

Specifically, the working process of the shift register includes a display stage and a touch stage, in the touch stage, the level of the input signal of the touch enable terminal EN is continuously high, and the thirteenth transistor M13 is continuously turned on, and at this time, the shift register does not output. In the display stage, the working process of the display stage comprises the following steps: the first stage to the sixth stage.

In the display stage, the first power supply end VGH continuously provides a high level signal; the second power supply terminal VGL continuously provides the low level signal, and the third transistor M3 is continuously turned on because the first power supply terminal VGH continuously provides the high level signal, and the level of the pull-up node PU is equal to the level of the first terminal of the first capacitor C1.

Specifically, the working process of the display stage includes:

the first stage T1, i.e., the INPUT stage, the level of the INPUT signals of the signal INPUT terminal INPUT and the first signal terminal CN is high, the level of the clock signal of the second clock terminal CLK2 is high half of the time, the level of the INPUT signal of the signal INPUT terminal INPUT is low half of the time, the first transistor M1 is turned on, the level of the pull-up node PU is pulled high, the first capacitor C1 is charged, the second transistor M2 is turned on, since the level of the clock signal of the first clock terminal CLK1 is low, the level of the output signal of the signal output terminal OUT is low, i.e., the signal output terminal OUT does not output a signal, the fourth transistor M4 is turned on when the level of the clock signal of the second clock terminal CLK2 is high, the pull-down node PD is pulled high, the second capacitor C2 is charged, when the level of the clock signal of the second clock terminal CLK2 is low, the fourth transistor M4 is turned off, the second capacitor C2 is discharged, the level of the pull-down node PD is still high, that is, the level of the pull-down node PD is continuously high in this stage, the fifth transistor M5 and the seventh transistor M7 are continuously turned on, the level of the pull-up node PU is high, the ninth transistor M9 is turned on, but the sixth transistor M6, the eighth transistor M8 and the tenth transistor M10 are turned off, the level of the pull-down node PD is not pulled low in this stage, the level of the pull-up node PU is not pulled low because the sixth transistor M6 is turned off, the seventh transistor M7 is turned on, the level of the input signal of the signal output terminal OUT is further pulled down.

In the second stage T2, i.e. the output stage, the level of the clock signal of the first clock terminal CLK1 is high, the level of the signal INPUT terminal INPUT is low, the first transistor M1 is turned off, the level of the clock signal of the first clock terminal CLK1 is high, the level of the pull-up node PU is continuously pulled up under the bootstrap action of the first capacitor C1, the second transistor M2 and the ninth transistor M9 are turned on by the high level of the pull-up node PU, the signal output terminal OUT outputs the signal of the first clock terminal CLK1, i.e. the level of the output signal of the signal output terminal OUT is high, in addition, the level of the pull-up node PU is raised, the turn-on capability of the second transistor M2 is improved, and the pixel charging is ensured. The level of the clock signal of the second clock terminal CLK2 is low, the fourth transistor M4 is turned off, the sixth transistor M6, the eighth transistor M8 and the tenth transistor M10 are turned on because the level of the output signal of the signal output terminal OUT is high, the pull-down node PD is low because the eighth transistor M8, the ninth transistor M9 and the tenth transistor M10 are turned on, and the fifth transistor M5 and the seventh transistor M7 are turned off, so that the levels of the signals of the pull-up node PU and the signal output terminal OUT are not pulled low, and the normal output of the shift register can be ensured.

In the third stage T3, the level of the clock signal of the first clock terminal CLK1 is low, the level of the pull-up node PU starts to decrease, but does not decrease to the level of the signal of the second power terminal, the low level of the pull-up node PU turns off the second transistor M2 and the ninth transistor M9, the signal output terminal OUT does not output, the level of the clock signal of the second clock terminal CLK2 is low, the level of the pull-down node PD continues to be low, and the fifth transistor M5 and the seventh transistor M7 are turned off.

The fourth stage T4, i.e., the reset stage, the level of the input signal of the first reset terminal RST1 is high, the level of the clock signal of the second clock terminal CLK2 is high, the level of the input signal of the first reset terminal RST1 is high, the eleventh transistor M11 is turned on, the level of the pull-up node PU is pulled down due to the low level of the input signal of the second signal terminal CNB, the second transistor M2 and the ninth transistor M9 are turned off, the signal output terminal OUT does not output a signal because the second transistor M2 is turned off, the fourth transistor M4 is turned on because the level of the clock signal of the second clock terminal CLK2 is high, the pull-down node PD is pulled high, the level of the pull-down node PD is high in this stage, the level of the pull-down node PD is continuously high, the fifth transistor M5 and the seventh transistor M7 are continuously turned on because the level of the output signal of the signal output terminal OUT is low, the eighth transistor M6 and the eighth transistor M8 and the eighth transistor M7 are continuously turned off because the level of the output signal of the signal output terminal OUT is low, the eighth transistor M8 and the eighth transistor M7 is continuously turned off because the level of the pull-down node M8 and the eighth transistor M9 is continuously turned off.

In the fifth stage T5, the level of the clock signal of the first clock terminal CLK1 is at a high level for half of the time, and at a low level for half of the time, but since the level of the pull-up node PU is at a low level, the second transistor M2 and the ninth transistor M9 are turned off, so that the signal output terminal OUT is not outputting a signal, since the level of the pull-down node PD is at a high level, the fifth transistor M5 and the seventh transistor M7 are continuously turned on, since the level of the output signal of the signal output terminal OUT is at a low level, the sixth transistor M6, the eighth transistor M8 and the tenth transistor M10 are turned off, since the eighth transistor M8, the ninth transistor M9 and the tenth transistor M10 are turned off, in this stage, the level of the pull-down node PD is not pulled down, the seventh transistor M7 is continuously turned on, and the level of the input signal of the signal output terminal OUT is continuously pulled down to reduce noise.

In the sixth stage T6, the level of the clock signal of the second clock terminal CLK2 is high for half of the time, low for half of the time, the second transistor M2 and the ninth transistor M9 are turned off because the level of the pull-up node PU is pulled down, the signal output terminal OUT has no output signal because the second transistor M2 is turned off, the fourth transistor M4 is turned on when the level of the clock signal of the second clock terminal CLK2 is high, the pull-down node PD is pulled up, the second capacitor C2 is charged, the fourth transistor M4 is turned off when the level of the clock signal of the second clock terminal CLK2 is low, the second capacitor C2 is discharged, the level of the pull-down node PD is still high, that is, the level of the pull-down node PD is continuously high in this stage, the fifth transistor M5 and the seventh transistor M7 are continuously turned on because the level of the output signal of the signal output terminal OUT is low, the sixth transistor M6, the eighth transistor M8 and the eighth transistor M10 are continuously turned off because the level of the pull-down node PD is continuously turned off, the eighth transistor M10 is continuously turned off because the level of the output signal of the eighth transistor M8 and the pull-down node PD is continuously turned off, and the signal of the eighth transistor M9 is continuously turned off.

After the reset phase T4, the shift register of this stage continues to perform the fifth and sixth phases until the signal INPUT terminal INPUT receives the high level signal again.

In the first stage T1, by setting the eighth transistor M8 controlled by the signal output terminal OUT, the large current generated by the path formed between the fourth transistor M4 and the ninth transistor M9 is avoided, the power consumption generated by the shift register is greatly reduced, and meanwhile, by setting the sixth transistor M6 controlled by the signal output terminal OUT, the path between the pull-up node PU and the fifth transistor M5 is avoided, the level of the pull-up node PU is prevented from being pulled down, and the shift register is ensured to work normally.

In this embodiment, in the display stage, the signal of the signal INPUT terminal INPUT is a pulse signal, and is only at a high level in the INPUT stage; the output signal of the signal output end OUT is a pulse signal and is high level only in the output stage; the input signal of the first reset terminal RST1 is a pulse signal and is high only in the reset phase.

Based on the same application concept, the embodiment of the present application further provides a gate driving circuit, fig. 13 is a schematic structural diagram of the gate driving circuit provided in the embodiment of the present application, and as shown in fig. 13, the gate driving circuit provided in the embodiment of the present application includes: a plurality of cascaded shift registers.

The shift register provided in the foregoing embodiment has similar implementation principles and implementation effects, and is not described herein.

Optionally, as shown in fig. 13, the gate driving circuit provided in the embodiment of the present application includes: an initial signal terminal STV and a reset control terminal RST.

Specifically, the signal INPUT terminal INPUT of the first stage shift register GOA (1) is connected to the initial signal terminal STV, the signal output terminal OUT of the nth stage shift register GOA (N) is connected to the signal INPUT terminal INPUT of the n+1th stage shift register GOA (n+1), and the signal output terminal OUT of the n+1th stage shift register GOA (n+1) is connected to the first reset terminal RST1 of the nth stage shift register GOA (N); the second reset terminal RST2 of all the stage shift registers is connected to the reset control terminal RST.

Based on the same application concept, the embodiment of the present application further provides a driving method of a shift register, which is applied to the shift register, and fig. 14 is a flowchart of the driving method of the shift register provided in the embodiment of the present application, as shown in fig. 14, where in a display period, the driving method of the shift register provided in the embodiment of the present application specifically includes the following steps:

step 100, under the control of a signal input end, an input sub-circuit provides a signal of a first signal end for a pull-up node; the node pull-up subcircuit provides a signal at the second clock terminal to the pull-down node under control of the second clock terminal.

Step 200, under the control of a pull-up node and a first power supply end, an output sub-circuit provides a signal of a first clock end for a signal output end; the node pull-down subcircuit provides a signal at the second power supply terminal to the pull-down node under control of the pull-up node and the signal output terminal.

Step 300, under the control of the pull-down node and the signal output end, the noise reduction sub-circuit provides the signal of the second power supply end to the pull-up node and the signal output end.

Optionally, the driving method of the shift register provided in the embodiment of the present application further includes: the first reset sub-circuit provides a signal of the second signal terminal to the pull-up node under control of the first reset terminal.

Optionally, in the driving method of the shift register provided in the embodiment of the present application, in a touch stage, the method further includes: and under the control of the touch control enabling end, providing a signal of the second power supply end for the signal output end.

Optionally, in the touch stage, the driving method of the shift register provided in the embodiment of the present application further includes: and under the control of the second reset terminal, providing a signal of the second power terminal to the pull-up node.

The drawings in the embodiments of the present application relate only to the structures to which the embodiments of the present application relate, and reference may be made to the general design for other structures.

Although the embodiments disclosed in the present application are described above, the embodiments are only used for facilitating understanding of the present application, and are not intended to limit the present application. Any person skilled in the art to which this application pertains will be able to make any modifications and variations in form and detail of implementation without departing from the spirit and scope of the disclosure, but the scope of the application is still subject to the scope of the claims appended hereto.

Claims

1. A shift register, comprising: an input sub-circuit, an output sub-circuit, a node pull-up sub-circuit, a node pull-down sub-circuit and a noise reduction sub-circuit;

the noise reduction sub-circuit is respectively connected with the pull-up node, the pull-down node, the signal output end and the second power end and is used for providing signals of the second power end for the pull-up node and the signal output end under the control of the pull-down node and the signal output end;

the node pull-down subcircuit includes: eighth to tenth transistors;

2. The shift register of claim 1, wherein the shift register further comprises: the touch control circuit comprises a first reset sub-circuit, a second reset sub-circuit and a touch control sub-circuit;

3. The shift register of claim 1, wherein the input sub-circuit comprises: a first transistor;

the second end of the first capacitor is connected with the signal output end.

4. The shift register of claim 1, wherein the node pull-up sub-circuit comprises: a fourth transistor;

the first end of the second capacitor is connected with the pull-down node, and the second end of the second capacitor is connected with the second power supply end.

5. The shift register of claim 2, wherein the first reset sub-circuit comprises: an eleventh transistor;

the second reset sub-circuit includes: a twelfth transistor;

the touch sub-circuit includes: a thirteenth transistor;

6. The shift register of claim 1, wherein the shift register further comprises: the touch control circuit comprises a first reset sub-circuit, a second reset sub-circuit and a touch control sub-circuit; the input sub-circuit includes: a first transistor; the output sub-circuit includes: a second transistor, a third transistor, and a first capacitor; the node pull-up sub-circuit includes: a fourth transistor; the noise reduction sub-circuit includes: fifth to seventh transistors and a second capacitor; the first reset sub-circuit includes: an eleventh transistor; the second reset sub-circuit includes: a twelfth transistor; the touch sub-circuit includes: a thirteenth transistor;

The second end of the first capacitor is connected with the signal output end;

the first end of the second capacitor is connected with the pull-down node, and the second end of the second capacitor is connected with the second power supply end;

7. The shift register of claim 1, wherein the level of the clock signal at the second clock terminal is an inactive level when the level of the clock signal at the first clock terminal is an active level, and wherein the level of the clock signal at the first clock terminal is an inactive level when the level of the clock signal at the second clock terminal is an active level.

8. A gate driving circuit, comprising: a plurality of cascaded shift registers according to any one of claims 1 to 7.

9. The gate drive circuit of claim 8, wherein the gate drive circuit comprises: an initial signal end and a reset control end;

10. A method of driving a shift register as claimed in any one of claims 1 to 7, wherein the method comprises, during a display period:

11. The method according to claim 10, wherein the method further comprises: the first reset sub-circuit provides a signal of the second signal terminal to the pull-up node under control of the first reset terminal.