CN110070822A

CN110070822A - A kind of shift register cell and its driving method, gate driving circuit

Info

Publication number: CN110070822A
Application number: CN201910506211.5A
Authority: CN
Inventors: 谢勇贤; 王慧; 刘强; 吕凤珍
Original assignee: BOE Technology Group Co Ltd; Hefei Xinsheng Optoelectronics Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Hefei Xinsheng Optoelectronics Technology Co Ltd
Priority date: 2019-06-12
Filing date: 2019-06-12
Publication date: 2019-07-30

Abstract

The present invention discloses a kind of shift register cell and its driving method, gate driving circuit, it is related to field of display technology, it is more to solve the number of transistors for including in existing shift register cell, circuit structure is complicated, the area for causing gate driving circuit to occupy in array substrate is larger, is unfavorable for showing the problem of product realizes narrow frame.The shift register cell includes: input sub-circuit, storage sub-circuit, output sub-circuit and control sub-circuit, it is coupled respectively with control sub-circuit pull-up node, gate drive signal output end, the first level signal input terminal and second clock signal input part, for in input period and output period, under the control of second clock signal, control disconnects the coupling between pull-up node and the first level signal input terminal, and control disconnects the coupling between gate drive signal output end and the first level signal input terminal.Shift register cell provided by the invention is for providing gate drive signal.

Description

Shifting register unit, driving method thereof and grid driving circuit

Technical Field

The invention relates to the technical field of display, in particular to a shift register unit, a driving method thereof and a grid driving circuit.

Background

The Array substrate line driving technology (Gate Driver on Array, hereinafter referred to as GOA) is a process technology for directly manufacturing a Gate driving circuit on an Array substrate to replace a driving chip manufactured by an external silicon chip. At present, a gate driving circuit generally includes a plurality of cascaded shift register units, and each shift register unit is connected to a gate line in a display panel in a one-to-one correspondence manner, and is used for driving the display panel line by line to realize a display function. However, the number of transistors included in the conventional shift register unit is large, and the circuit structure is complex, so that the area occupied by the gate driving circuit on the array substrate is large, and narrow-frame development of display products is not facilitated.

Disclosure of Invention

The invention aims to provide a shift register unit, a driving method thereof and a gate driving circuit, which are used for solving the problems that the existing shift register unit comprises a large number of transistors and a complex circuit structure, so that the area occupied by the gate driving circuit on an array substrate is large, and narrow frame of a display product is not facilitated.

In order to achieve the above purpose, the invention provides the following technical scheme:

a first aspect of the present invention provides a shift register unit comprising:

the input sub-circuit is respectively coupled with an input signal terminal and a pull-up node and is used for controlling the connection or disconnection of the input signal terminal and the pull-up node under the control of an input signal provided by the input signal terminal;

one end of the storage sub-circuit is coupled with the pull-up node, and the other end of the storage sub-circuit is coupled with a grid driving signal output end;

the output sub-circuit is respectively coupled with the pull-up node, the grid driving signal output end and the first clock signal input end and is used for controlling the connection or disconnection between the grid driving signal output end and the first clock signal input end under the control of the potential of the pull-up node;

and the control sub-circuit is respectively coupled with the pull-up node, the gate driving signal output end, the first level signal input end and the second clock signal input end, and is used for controlling to disconnect the coupling between the pull-up node and the first level signal input end and the coupling between the gate driving signal output end and the first level signal input end under the control of a second clock signal provided by the second clock signal input end in an input period and an output period.

Optionally, the control sub-circuit comprises a first transistor and a second transistor; wherein,

a gate of the first transistor is coupled to the second clock signal input terminal, a first pole of the first transistor is coupled to the pull-up node, and a second pole of the first transistor is coupled to the first level signal input terminal;

the gate of the second transistor is coupled to the second clock signal input terminal, the first pole of the second transistor is coupled to the gate driving signal output terminal, and the second pole of the second transistor is coupled to the first level signal input terminal.

Optionally, the shift register unit is formed on a substrate, and an overlapping region of a gate layer of the first transistor and an active layer of the first transistor in a direction perpendicular to the substrate is formed as a first channel region; an overlapping region of a gate layer of the second transistor and an active layer of the second transistor in a direction perpendicular to a substrate is formed as a second channel region; an area of the first channel region and an area of the second channel region are both greater than a threshold.

Optionally, the shift register unit further includes:

a first pre-frame noise reduction sub-circuit, coupled to the pull-up node, the first level signal input terminal, and the pre-frame noise reduction control terminal, respectively, for controlling to turn on or off the coupling between the pull-up node and the first level signal input terminal under the control of a pre-frame noise reduction control signal provided by the pre-frame noise reduction control terminal;

and the second pre-frame noise reduction sub-circuit is respectively coupled with the grid driving signal output end, the first level signal input end and the pre-frame noise reduction control end and is used for controlling the connection or disconnection of the grid driving signal output end and the first level signal input end under the control of the pre-frame noise reduction control signal.

Optionally, the first pre-frame noise reduction sub-circuit includes a third transistor, a gate of the third transistor is coupled to the pre-frame noise reduction control terminal, a first pole of the third transistor is coupled to the pull-up node, and a second pole of the third transistor is coupled to the first level signal input terminal;

the second pre-frame noise reduction sub-circuit comprises a fourth transistor, a gate of the fourth transistor is coupled to the pre-frame noise reduction control terminal, a first pole of the fourth transistor is coupled to the gate driving signal output terminal, and a second pole of the fourth transistor is coupled to the first level signal input terminal.

Optionally, the shift register unit further includes:

the first reset sub-circuit is respectively coupled with the pull-up node, the first level signal input end and the reset control end, and is used for controlling to switch on or off the coupling between the pull-up node and the first level signal input end under the control of a reset control signal provided by the reset control end;

and the second reset sub-circuit is respectively coupled with the grid driving signal output end, the first level signal input end and the reset control end and is used for controlling the connection or disconnection between the grid driving signal output end and the first level signal input end under the control of the reset control signal.

Optionally, the input sub-circuit includes a fifth transistor, a gate of the fifth transistor and a first pole of the fifth transistor are both coupled to the input signal terminal, and a second pole of the fifth transistor is coupled to the pull-up node;

the output sub-circuit comprises a sixth transistor, a gate of the sixth transistor is coupled to the pull-up node, a first pole of the sixth transistor is coupled to the first clock signal input terminal, and a second pole of the sixth transistor is coupled to the gate drive signal output terminal;

the first reset sub-circuit comprises a seventh transistor, a gate of the seventh transistor is coupled to the reset control terminal, a first pole of the seventh transistor is coupled to the pull-up node, and a second pole of the seventh transistor is coupled to the first level signal input terminal;

the second reset sub-circuit comprises an eighth transistor, a gate of the eighth transistor is coupled to the reset control terminal, a first terminal of the eighth transistor is coupled to the gate driving signal output terminal, and a second pole of the eighth transistor is coupled to the first level signal input terminal.

A second aspect of the present invention provides a gate driving circuit, which includes the above shift register unit, wherein a plurality of shift register units are sequentially cascaded, and a gate driving signal output terminal of a previous shift register unit is coupled to an input signal terminal of an adjacent next shift register unit.

A third aspect of the present invention provides a driving method of a shift register unit, which is applied to the shift register unit, the driving method including:

in an input period, an input sub-circuit in the shift register unit is controlled to conduct coupling between an input signal terminal and a pull-up node under the control of an input signal provided by the input signal terminal; a control sub-circuit in the shift register unit controls to disconnect the coupling between the pull-up node and the first level signal input end and controls to disconnect the coupling between the grid driving signal output end and the first level signal input end under the control of a second clock signal provided by a second clock signal input end;

in an output period, the input sub-circuit controls to disconnect the coupling between the input signal terminal and the pull-up node under the control of the input signal; an output sub-circuit in the shift register unit controls and conducts coupling between the grid driving signal output end and the first clock signal input end under the control of the electric potential of the pull-up node; the control sub-circuit continues to control to disconnect the coupling between the pull-up node and the first level signal input end and the coupling between the gate driving signal output end and the first level signal input end under the control of the second clock signal;

in a reset period, the output sub-circuit controls to disconnect the coupling between the grid driving signal output end and the first clock signal input end under the control of the potential of the pull-up node; the control sub-circuit controls to conduct coupling between the pull-up node and the first level signal input end and controls to conduct coupling between the grid driving signal output end and the first level signal input end under the control of the second clock signal;

in a holding period, the control sub-circuit periodically controls to conduct the coupling between the pull-up node and the first level signal input terminal and periodically controls to conduct the coupling between the gate driving signal output terminal and the first level signal input terminal under the control of the second clock signal.

Optionally, the frequency of the first clock signal input by the first clock signal input end is an integer multiple of the frequency of the second clock signal input by the second clock signal input end.

In the technical scheme provided by the invention, a control sub-circuit is arranged and is respectively coupled with a pull-up node, a grid driving signal output end, a first level signal input end and a second clock signal input end, and the control sub-circuit can control to disconnect the coupling between the pull-up node and the first level signal input end and the coupling between the grid driving signal output end and the first level signal input end under the control of a second clock signal in an input period and an output period, so that the potentials of the pull-up node and the grid driving signal output end cannot be pulled down in the input period and the output period, namely the problem that the charging of the pull-up node is influenced due to the potential influence of a pull-down node in the related technology is avoided; therefore, the problems that a large number of transistors for controlling the potential of the pull-down node are introduced into the shift register unit and the transistors are required to be added for ensuring the stable work of the power supply chip are further solved; therefore, the technical scheme provided by the invention reduces the circuit complexity of the shift register unit and simultaneously well improves the charging capability of the pull-up node, so that when the shift register is applied to a display product, the driving performance of the display product is ensured, and the narrow frame of the display product is more facilitated.

In addition, compared with the application of the display product in a normal temperature environment, when the display product is applied in a low temperature environment, the charging capability of the pull-up node is weakened, and because the shift register unit has stronger charging capability in the technical scheme provided by the invention, the display product is more beneficial to the low-temperature start of the display product when the shift register unit provided by the invention is adopted.

In addition, in the technical scheme provided by the invention, in the shift register unit, because the second clock signal input by the second clock signal input end is in an inactive level in both the input period and the output period, the second clock signal has a lower frequency than the first clock signal and the inverted clock signal in the related art, therefore, when the shift register unit provided by the invention is applied to a display product, the display product can realize lower power consumption during operation.

Drawings

The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the invention and not to limit the invention. In the drawings:

FIG. 1 is a schematic diagram of a shift register unit according to the related art;

FIG. 2 is a timing flow chart of the related art;

FIG. 3 is a first basic structure diagram of a shift register unit according to an embodiment of the present invention;

fig. 4 is a first specific structural diagram of a shift register unit according to an embodiment of the present invention;

FIG. 5 is a diagram illustrating a second basic structure of a shift register unit according to an embodiment of the present invention;

FIG. 6 is a diagram illustrating a third basic structure of a shift register unit according to an embodiment of the present invention;

fig. 7 is a schematic diagram of a second specific structure of a shift register unit according to an embodiment of the present invention;

fig. 8 is a schematic structural diagram of a gate driving circuit according to an embodiment of the invention;

FIG. 9 is a timing flow chart of a first row of shift register units according to an embodiment of the present invention;

FIG. 10 is a timing flow chart of the second row shift register unit according to the embodiment of the present invention.

Reference numerals:

1-an input sub-circuit, 2-a memory sub-circuit,

3-an output sub-circuit, 4-a control sub-circuit,

5-a first frame pre-noise reduction sub-circuit, 6-a second frame pre-noise reduction sub-circuit,

7-a first reset sub-circuit, 8-a second reset sub-circuit,

m1-first transistor, M2-second transistor,

m3-third transistor, M4-fourth transistor,

m5-fifth transistor, M6-sixth transistor,

m7-seventh transistor, M8-eighth transistor,

m9-ninth transistor, M10-tenth transistor,

m11-eleventh transistor, M12-twelfth transistor,

c1-first capacitor, PU-pull-up node,

PD-pull-down node, PD _ CN-pull-down control node,

an INPUT-INPUT signal terminal, an OUTPUT-gate drive signal OUTPUT terminal,

Reset-Reset control terminal, CLK-first clock signal input terminal,

CLKB-inverted clock signal input terminal, VGL-first level signal input terminal,

STV 1-frame start signal input, CLKC-second clock signal input,

STV 0-frame front noise reduction control terminal, P1-frame front period,

p2-input period, P3-output period,

p4-reset period, P5-hold period.

Detailed Description

In order to further explain the shift register unit, the driving method thereof and the gate driving circuit provided by the embodiment of the invention, the following detailed description is made with reference to the accompanying drawings.

In the related art, the GOA architecture is originally conceived as the basic architecture of 4T1C, and as shown in fig. 1 and fig. 2, the 4T1C architecture only includes the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, the eighth transistor M8 and the storage capacitor C1 in fig. 1; wherein the fifth transistor M5 is used to charge the pull-up node PU during the input period P2, the sixth transistor M6 is used to control the gate driving signal OUTPUT terminal OUTPUT to OUTPUT the gate driving signal during the OUTPUT period P3, and the seventh transistor M7 and the eighth transistor M8 are respectively used to reset the pull-up node PU and the gate driving signal OUTPUT terminal OUTPUT during the reset period P4; the limitation of this 4T1C architecture is that the pull-down of the pull-up node PU and the gate driving signal OUTPUT terminal OUTPUT is only achieved by the reset control signal controlling the seventh transistor M7 and the eighth transistor M8 to be turned on, and there is no other signal to keep the pull-down of the pull-up node PU and the gate driving signal OUTPUT terminal OUTPUT during the rest of a frame. In the gate driving circuit, a parasitic capacitance is easily generated between the clock signal line and the pull-up node PU, so that the pull-up node PU is easily noisy, and thus the gate driving circuit is easily abnormal in operation, which affects the quality of the display product.

In order to improve the above problem, the related art introduces a pull-down node PD, and with continued reference to fig. 1 and 2, a first transistor M1, a second transistor M2, a ninth transistor M9, a tenth transistor M10, an eleventh transistor M11, and a twelfth transistor M12 are added, and an inverted clock signal input terminal CLKB is added, and a phase of an inverted clock signal input from the inverted clock signal input terminal CLKB is opposite to a phase of a first clock signal input from the first clock signal input terminal CLK.

In more detail, since the added inverted clock signal is at a high level in the input period P2, so that the pull-down node PD will have a high level (as part a in fig. 2) at the beginning of the input period P2, and the high level will control the first transistor M1 to be turned on, thereby affecting the charging of the pull-up node PU, in order to solve this problem, a twelfth transistor M12 is needed, the pull-down node PD is pulled down in the input period P2 by the twelfth transistor M12, but when the twelfth transistor M12 is turned on, the inverted clock signal input terminal CLKB is directly connected to the first level signal input terminal VGL, the current is large, thereby affecting the normal operation of the power chip, and therefore, in order to ensure the normal operation of the power chip, the tenth transistor M10 is added, and in order to prevent the drift of the characteristics of the tenth transistor M10TFT, a pull-down control node PD _ CN, a pull-down control node, a, A ninth transistor M9 and an eleventh transistor M11. Obviously, the design results in more redundant transistors in the gate driving architecture, the design can be normally used when no special requirements are made on the frame, but with the development of a full-screen, the occupied area of the gate driving circuit cannot be further compressed due to the design of more transistors, and the narrow frame is not beneficial to the realization of smaller products.

Referring to fig. 3, an embodiment of the present invention provides a shift register unit, including:

an INPUT sub-circuit 1, coupled to the INPUT signal terminal INPUT and the pull-up node PU, respectively, for controlling to turn on or off the coupling between the INPUT signal terminal INPUT and the pull-up node PU under the control of an INPUT signal provided by the INPUT signal terminal INPUT;

one end of the storage sub-circuit 2 is coupled to the pull-up node PU, and the other end of the storage sub-circuit 2 is coupled to the gate driving signal OUTPUT terminal OUTPUT;

the OUTPUT sub-circuit 3 is respectively coupled with the pull-up node PU, the gate driving signal OUTPUT end OUTPUT and the first clock signal input end CLK, and is used for controlling to switch on or off the coupling between the gate driving signal OUTPUT end OUTPUT and the first clock signal input end CLK under the control of the potential of the pull-up node PU;

the control sub-circuit 4 is coupled to the pull-up node PU, the gate driving signal OUTPUT terminal OUTPUT, the first level signal input terminal VGL, and the second clock signal input terminal CLKC, respectively, and is configured to control to disconnect the coupling between the pull-up node PU and the first level signal input terminal VGL and to control to disconnect the coupling between the gate driving signal OUTPUT terminal OUTPUT and the first level signal input terminal VGL under the control of the second clock signal provided by the second clock signal input terminal CLKC in the input period P2 and the OUTPUT period P3.

As shown in fig. 9, in practical application, one duty cycle of the shift register unit sequentially includes: the input period P2, the output period P3, the reset period P4, and the hold period P5, the operation of the shift register unit in one duty cycle is:

in the INPUT period P2, under the control of the INPUT signal provided by the INPUT signal terminal INPUT, the INPUT sub-circuit 1 controls to turn on the coupling between the INPUT signal terminal INPUT and the pull-up node PU, pull up the potential of the pull-up node PU, and charge the storage sub-circuit 2; under the control of the second clock signal provided by the second clock signal input terminal CLKC (e.g., CLK1C in fig. 9 and CLK2C in fig. 10), the control sub-circuit 4 controls to disconnect the coupling between the pull-up node PU and the first level signal input terminal VGL, and the control sub-circuit 4 controls to disconnect the coupling between the gate driving signal OUTPUT terminal OUTPUT and the first level signal input terminal VGL.

In the output period P3, under the control of the INPUT signal provided by the INPUT signal terminal INPUT, the INPUT sub-circuit 1 controls to disconnect the coupling between the INPUT signal terminal INPUT and the pull-up node PU; the OUTPUT sub-circuit 3 controls and conducts the coupling between the gate driving signal OUTPUT terminal OUTPUT and the first clock signal input terminal CLK under the control of the potential of the pull-up node PU, so that the gate driving signal OUTPUT terminal OUTPUT OUTPUTs the gate driving signal, and the potential of the pull-up node PU is further pulled up due to the bootstrap action of the storage sub-circuit 2; under the control of the second clock signal provided by the second clock signal input terminal CLKC, the control sub-circuit 4 continues to control to disconnect the coupling between the pull-up node PU and the first level signal input terminal VGL, and continues to control to disconnect the coupling between the gate driving signal OUTPUT terminal OUTPUT and the first level signal input terminal VGL.

In the reset period P4, under the control of the second clock signal provided by the second clock signal input terminal CLKC, the control sub-circuit 4 controls to turn on the coupling between the pull-up node PU and the first level signal input terminal VGL, and pull down the potential of the pull-up node PU, and at the same time, the control sub-circuit 4 also controls to turn on the coupling between the gate driving signal OUTPUT terminal OUTPUT and the first level signal input terminal VGL, and pull down the potential of the gate driving signal OUTPUT terminal OUTPUT; the OUTPUT sub-circuit 3 controls to disconnect the coupling between the gate driving signal OUTPUT terminal OUTPUT and the first clock signal input terminal CLK under the control of the pull-up node PU having a low potential.

In the holding period P5, under the control of the second clock signal provided by the second clock signal input terminal CLKC, the control sub-circuit 4 periodically controls to turn on the coupling between the pull-up node PU and the first level signal input terminal VGL, that is, when the second clock signal is at an active level, the coupling between the pull-up node PU and the first level signal input terminal VGL is controlled to be turned on, and when the second clock signal is at an inactive level, the coupling between the pull-up node PU and the first level signal input terminal VGL is controlled to be turned off; the control sub-circuit 4 also controls to turn on the coupling between the gate driving signal OUTPUT terminal OUTPUT and the first level signal input terminal VGL periodically, that is, when the second clock signal is at an active level, the coupling between the gate driving signal OUTPUT terminal OUTPUT and the first level signal input terminal VGL is controlled to be turned on, and when the second clock signal is at an inactive level, the coupling between the gate driving signal OUTPUT terminal OUTPUT and the first level signal input terminal VGL is controlled to be turned off.

It should be noted that, each clock cycle of the second clock signal includes a high level for 50% of the time and a low level for 50% of the time, so that when the operating state of the control sub-circuit 4 is controlled by the second clock signal, the second clock signal will be at an active level for half of the time in the whole operating cycle, that is, the control sub-circuit 4 will pull down the potentials of the pull-up node PU and the gate driving signal OUTPUT terminal OUTPUT for half of the time in the whole operating cycle, so as to implement noise reduction on the pull-up node PU and the gate driving signal OUTPUT terminal OUTPUT.

It should be noted that the frequency of the second clock signal inputted from the second clock signal input terminal CLKC can be set according to actual needs, and it is only necessary that the second clock signal can be at an inactive level in the input period P2 and the output period P3.

As can be seen from the specific structure and operation process of the shift register unit provided in the above embodiment, the control sub-circuit 4 coupled to the pull-up node PU, the gate driving signal OUTPUT terminal OUTPUT, the first level signal input terminal VGL and the second clock signal input terminal CLKC is provided in the shift register unit provided in the embodiment of the present invention, and the control sub-circuit 4 can control to disconnect the coupling between the pull-up node PU and the first level signal input terminal VGL and to disconnect the coupling between the gate driving signal OUTPUT terminal OUTPUT and the first level signal input terminal VGL under the control of the second clock signal provided by the second clock signal input terminal CLKC in the input period P2 and the OUTPUT period P3, so that the potentials of the pull-up node PU and the gate driving signal OUTPUT terminal OUTPUT are not pulled down in the input period P2 and the OUTPUT period P3, that is, the influence of the potential of the pull-down node PD in the related art is avoided, the charging of the pull-up node PU is influenced; therefore, the problems that a large number of transistors for controlling the potential of the pull-down node PD are introduced into the shift register unit and the transistors are required to be added for ensuring the stable work of the power supply chip are further solved; therefore, the shift register unit provided by the embodiment of the invention can well improve the charging capability of the pull-up node PU while reducing the circuit complexity, so that when the shift register unit is applied to a display product, the driving performance of the display product is ensured, and the narrow frame of the display product is facilitated.

In addition, compared with the application of the display product in a normal temperature environment, when the display product is applied in a low temperature environment, the charging capability of the pull-up node PU is weakened, and the shift register unit provided by the embodiment of the invention has stronger charging capability, so that the display product is more favorable for low-temperature start of the display product when the shift register unit provided by the embodiment of the invention is adopted.

In addition, in the shift register unit provided in the embodiment of the present invention, since the second clock signal input by the second clock signal input terminal CLKC is at the inactive level in both the input period P2 and the output period P3, the second clock signal has a lower frequency than the first clock signal, and the clock signal and the inverted clock signal in the related art, and therefore, when the shift register unit provided in the embodiment of the present invention is applied to a display product, the display product can achieve lower power consumption during operation.

The specific structure of the control sub-circuit 4 provided in the above embodiments is various, and as shown in fig. 4, in some embodiments, the control sub-circuit 4 may include a first transistor M1 and a second transistor M2; a gate of the first transistor M1 is coupled to the second clock signal input terminal CLKC, a first pole of the first transistor M1 is coupled to the pull-up node PU, and a second pole of the first transistor M1 is coupled to the first level signal input terminal VGL; the gate of the second transistor M2 is coupled to the second clock signal input terminal CLKC, the first pole of the second transistor M2 is coupled to the gate driving signal OUTPUT terminal OUTPUT, and the second pole of the second transistor M2 is coupled to the first level signal input terminal VGL.

Specifically, when the control sub-circuit 4 includes the first transistor M1 and the second transistor M2, the operation process of the control sub-circuit 4 specifically includes:

the second clock signal input from the second clock signal input terminal CLKC controls the first transistor M1 to be turned off, thereby controlling the coupling between the pull-up node PU and the first level signal input terminal VGL to be turned off, during the input period P2 and the output period P3; meanwhile, the second clock signal also controls the second transistor M2 to be turned off to control the coupling between the gate driving signal OUTPUT terminal OUTPUT and the first level signal input terminal VGL to be disconnected.

In the reset period P4, the second clock signal controls the first transistor M1 to be turned on, thereby controlling the coupling between the turn-on pull-up node PU and the first level signal input terminal VGL; meanwhile, the second clock signal also controls the second transistor M2 to be turned on, so as to control the coupling between the gate-on driving signal OUTPUT terminal OUTPUT and the first level signal input terminal VGL.

In the holding period P5, the first transistor M1 periodically controls to turn on the coupling between the pull-up node PU and the first level signal input terminal VGL under the control of the second clock signal, i.e., when the second clock signal is at an active level, the first transistor M1 is turned on, thereby controlling to turn on the coupling between the pull-up node PU and the first level signal input terminal VGL, and when the second clock signal is at an inactive level, the first transistor M1 is turned off, thereby controlling to turn off the coupling between the pull-up node PU and the first level signal input terminal VGL.

Meanwhile, in the holding period P5, the second transistor M2 periodically controls the coupling between the gate driving signal OUTPUT terminal OUTPUT and the first level signal input terminal VGL to be turned on under the control of the second clock signal, that is, when the second clock signal is at an active level, the second transistor M2 is turned on, thereby controlling the coupling between the gate driving signal OUTPUT terminal OUTPUT and the first level signal input terminal VGL to be turned on, and when the second clock signal is at an inactive level, the second transistor M2 is turned off, thereby controlling the coupling between the gate driving signal OUTPUT terminal OUTPUT and the first level signal input terminal VGL to be turned off.

When the control sub-circuit 4 provided by the above embodiment includes the first transistor M1 and the second transistor M2, the circuit structure is simplified to the maximum extent while the working performance of the control sub-circuit 4 is ensured, so that when the shift register unit provided by the above embodiment is applied to a display product, it is more beneficial to realizing a narrow frame of the display product.

In some embodiments, the shift register unit may be formed on a substrate, and an overlapping region of a gate layer of the first transistor M1 and an active layer of the first transistor M1 in a direction perpendicular to the substrate is formed as a first channel region; an overlapping region of the gate layer of the second transistor M2 and the active layer of the second transistor M2 in a direction perpendicular to the substrate is formed as a second channel region; the area of the first channel region and the area of the second channel region are both greater than a threshold value.

Specifically, since the shift register unit provided by the above embodiment has a simple structure and a small overall occupied area, the noise reduction performance of the first transistor M1 and the second transistor M2 can be improved by appropriately enlarging the channel areas of the first transistor M1 and the second transistor M2. For example, the area of the first channel region corresponding to the first transistor M1 and the area of the second channel region corresponding to the second transistor M2 may be set to be larger than a threshold value, which may be set according to actual needs, for example, the threshold value may be set to be larger than the area of a channel region of a conventional size corresponding to a transistor employed in the related art.

The area of the first channel region corresponding to the first transistor M1 and the area of the second channel region corresponding to the second transistor M2 are both larger than the threshold, so that the first transistor M1 and the second transistor M2 have better driving performance, and thus when the first transistor M1 and the second transistor M2 are controlled to be turned on through the second clock signal input terminal CLKC, the first transistor M1 can better pull down the potential of the pull-up node PU, and the second transistor M2 can better pull down the potential of the gate driving signal OUTPUT terminal OUTPUT, so that the noise reduction effect on the pull-up node PU and the gate driving signal OUTPUT terminal OUTPUT is better ensured.

It is to be noted that, in the shift register unit provided in the above embodiment, when the first channel region and the second channel region are controlled to have a larger area, the first reset sub-circuit 7 and the second reset sub-circuit 8 described below are omitted, so that the noise reduction effect is also good.

As shown in fig. 5, in some embodiments, the shift register unit provided in the above embodiments further includes:

the first pre-frame noise reduction sub-circuit 5 is respectively coupled to the pull-up node PU, the first level signal input terminal VGL and the pre-frame noise reduction control terminal STV0, and is configured to turn on or off the coupling between the pull-up node PU and the first level signal input terminal VGL under the control of a pre-frame noise reduction control signal provided by the pre-frame noise reduction control terminal STV 0;

the second pre-frame noise reduction sub-circuit 6 is coupled to the gate driving signal OUTPUT terminal OUTPUT, the first level signal input terminal VGL, and the pre-frame noise reduction control terminal STV0, and is configured to control to switch on or off the coupling between the gate driving signal OUTPUT terminal OUTPUT and the first level signal input terminal VGL under the control of the pre-frame noise reduction control signal provided by the pre-frame noise reduction control terminal STV 0.

Specifically, as shown in fig. 9, in a pre-frame period P1 before the input period P2 in each duty cycle, the first pre-frame noise reduction sub-circuit 5 may be controlled by a pre-frame noise reduction control signal provided from the pre-frame noise reduction control terminal STV0 to turn on the coupling between the pull-up node PU and the first level signal input terminal VGL; meanwhile, the second pre-frame noise reduction sub-circuit 6 can be controlled to conduct the coupling between the gate driving signal OUTPUT terminal OUTPUT and the first level signal input terminal VGL through a pre-frame noise reduction control signal provided by the pre-frame noise reduction control terminal STV0, so that the pre-frame noise reduction of the pull-up node PU and the gate driving signal OUTPUT terminal OUTPUT is realized; in other periods (including the input period P2, the output period P3, the reset period P4, and the hold period P5) than the period before the frame in each operation period, the first frame preceding noise reduction sub-circuit 5 may be controlled by a frame preceding noise reduction control signal supplied from the frame preceding noise reduction control terminal STV0 to turn off the coupling between the pull-up node PU and the first level signal input terminal VGL; meanwhile, the second pre-frame noise reduction sub-circuit 6 can be controlled to disconnect the coupling between the gate driving signal OUTPUT terminal OUTPUT and the first level signal input terminal VGL by the pre-frame noise reduction control signal provided by the pre-frame noise reduction control terminal STV0, so as to ensure that the shift register unit can normally operate in the other periods.

The shift register unit can be better ensured to have better working performance in the following working period by setting the first pre-frame noise reduction sub-circuit 5 to perform pre-frame noise reduction on the pull-up node PU and setting the second pre-frame noise reduction sub-circuit 6 to perform pre-frame noise reduction on the gate drive signal OUTPUT end OUTPUT.

The specific structure of the first and second pre-frame noise reduction sub-circuits 5 and 6 provided in the above embodiments is various, and as shown in fig. 7, in some embodiments, the first pre-frame noise reduction sub-circuit 5 includes a third transistor M3, a gate of the third transistor M3 is coupled to the pre-frame noise reduction control terminal STV0, a first pole of the third transistor M3 is coupled to the pull-up node PU, and a second pole of the third transistor M3 is coupled to the first level signal input terminal VGL; the second pre-frame noise reduction sub-circuit 6 includes a fourth transistor M4, a gate of the fourth transistor M4 is coupled to the pre-frame noise reduction control terminal STV0, a first pole of the fourth transistor M4 is coupled to the gate driving signal OUTPUT terminal OUTPUT, and a second pole of the fourth transistor M4 is coupled to the first level signal input terminal VGL.

When the first pre-frame noise reduction sub-circuit 5 includes the third transistor M3 and the second pre-frame noise reduction sub-circuit 6 includes the fourth transistor M4, the specific operation of the first pre-frame noise reduction sub-circuit 5 and the second pre-frame noise reduction sub-circuit 6 in the pre-frame period P1 includes:

in the pre-frame period P1, under the control of the pre-frame noise reduction control terminal STV0, the third transistor M3 is turned on, so as to control the coupling between the pull-up node PU and the first level signal input terminal VGL to be turned on, thereby realizing the pre-frame noise reduction of the pull-up node PU, and at the same time, under the control of the pre-frame noise reduction control terminal STV0, the fourth transistor M4 is turned on, thereby controlling the coupling between the gate drive signal OUTPUT terminal OUTPUT and the first level signal input terminal VGL to be turned on, thereby realizing the noise reduction of the gate drive signal OUTPUT terminal OUTPUT.

In other periods except for the frame preceding period P1, the third transistor M3 is turned off under the control of the frame preceding noise reduction control terminal STV0, thereby controlling to disconnect the coupling between the pull-up node PU and the first level signal input terminal VGL; meanwhile, under the control of the pre-frame noise reduction control terminal STV0, the fourth transistor M4 is turned off, so that the coupling between the gate driving signal OUTPUT terminal OUTPUT and the first level signal input terminal VGL is controlled to be disconnected, and the noise reduction of the gate driving signal OUTPUT terminal OUTPUT is realized.

When the first pre-frame noise reduction sub-circuit 5 includes the third transistor M3 and the second pre-frame noise reduction sub-circuit 6 includes the fourth transistor M4, the circuit structure is simplified to the maximum extent while the working performance of the first pre-frame noise reduction sub-circuit 5 and the second pre-frame noise reduction sub-circuit 6 is ensured, so that when the shift register unit provided by the above embodiment is applied to a display product, the display product is more facilitated to realize a narrow frame.

As shown in fig. 6, in some embodiments, the shift register unit provided in the above embodiments further includes:

the first Reset sub-circuit 7 is respectively coupled to the pull-up node PU, the first level signal input terminal VGL and the Reset control terminal Reset, and is configured to turn on or off the coupling between the pull-up node PU and the first level signal input terminal VGL under the control of a Reset control signal provided by the Reset control terminal Reset;

the second Reset sub-circuit 8 is coupled to the gate driving signal OUTPUT terminal OUTPUT, the first level signal input terminal VGL, and the Reset control terminal Reset, respectively, and is configured to control to turn on or off the coupling between the gate driving signal OUTPUT terminal OUTPUT and the first level signal input terminal VGL under the control of a Reset control signal provided by the Reset control terminal Reset.

Specifically, as shown in fig. 9, in each duty cycle, in the input period P2, the output period P3, and the holding period P5, the first Reset sub-circuit 7 controls to disconnect the coupling between the pull-up node PU and the first level signal input terminal VGL under the control of the Reset control signal supplied from the Reset control terminal Reset; meanwhile, under the control of the Reset control signal provided by the Reset control terminal Reset, the second Reset sub-circuit 8 controls to disconnect the coupling between the gate driving signal OUTPUT terminal OUTPUT and the first level signal input terminal VGL.

In the Reset period P4, under the control of the Reset control signal provided by the Reset control terminal Reset, the first Reset sub-circuit 7 controls to turn on the coupling between the pull-up node PU and the first level signal input terminal VGL, so as to Reset the pull-up node PU; meanwhile, under the control of the Reset control signal provided by the Reset control terminal Reset, the second Reset sub-circuit 8 controls to turn on the coupling between the gate driving signal OUTPUT terminal OUTPUT and the first level signal input terminal VGL, thereby resetting the gate driving signal OUTPUT terminal OUTPUT.

The first reset sub-circuit 7 and the second reset sub-circuit 8 are arranged in the shift register unit, so that in the reset period P4, the first reset sub-circuit 7 can reset the pull-up node PU, and the second reset sub-circuit 8 can reset the gate driving signal OUTPUT terminal OUTPUT, so that the potentials of the pull-up node PU and the gate driving signal OUTPUT terminal OUTPUT in the reset period P4 are better controlled, and the more stable working performance of the shift register unit is ensured.

The specific structures of the INPUT sub-circuit 1, the output sub-circuit 3, the first reset sub-circuit 7 and the second reset sub-circuit 8 provided in the above embodiments are various, and for example, as shown in fig. 7, the INPUT sub-circuit 1 includes a fifth transistor M5, a gate of the fifth transistor M5 and a first pole of the fifth transistor M5 are both coupled to the INPUT signal terminal INPUT, and a second pole of the fifth transistor M5 is coupled to the pull-up node PU; the OUTPUT sub-circuit 3 includes a sixth transistor M6, a gate of the sixth transistor M6 is coupled to the pull-up node PU, a first pole of the sixth transistor M6 is coupled to the first clock signal input terminal CLK, and a second pole of the sixth transistor M6 is coupled to the gate driving signal OUTPUT terminal OUTPUT; the first Reset sub-circuit 7 includes a seventh transistor M7, a gate of the seventh transistor M7 is coupled to the Reset control terminal Reset, a first pole of the seventh transistor M7 is coupled to the pull-up node PU, and a second pole of the seventh transistor M7 is coupled to the first level signal input terminal VGL; the second Reset sub-circuit 8 includes an eighth transistor M8, a gate of the eighth transistor M8 is coupled to the Reset control terminal Reset, a first terminal of the eighth transistor M8 is coupled to the gate driving signal OUTPUT terminal OUTPUT, and a second terminal of the eighth transistor M8 is coupled to the first level signal input terminal VGL; the storage sub-circuit 2 comprises a storage capacitor C1.

Specifically, when the input sub-circuit 1, the output sub-circuit 3, the first reset sub-circuit 7, and the second reset sub-circuit 8 adopt the above structure, the specific working process of the shift register unit includes:

as shown in fig. 9, in the INPUT period P2, under the control of the INPUT signal provided by the INPUT signal terminal INPUT, the fifth transistor M5 is turned on, thereby controlling to turn on the coupling between the INPUT signal terminal INPUT and the pull-up node PU, pull up the potential of the pull-up node PU, and charge the storage capacitor C1; under the control of the second clock signal provided by the second clock signal input terminal CLKC, the first transistor M1 and the second transistor M2 are both turned off, thereby controlling the coupling between the pull-up node PU and the first level signal input terminal VGL to be disconnected, and controlling the coupling between the gate driving signal OUTPUT terminal OUTPUT and the first level signal input terminal VGL to be disconnected.

In the output period P3, under the control of the INPUT signal terminal INPUT, the fifth transistor M5 is turned off, thereby controlling to disconnect the coupling between the INPUT signal terminal INPUT and the pull-up node PU; under the control of the pull-up node PU, the sixth transistor M6 is turned on, so as to control the coupling between the gate driving signal OUTPUT terminal OUTPUT and the first clock signal input terminal CLK to be turned on, so that the gate driving signal OUTPUT terminal OUTPUT OUTPUTs the gate driving signal, and the potential of the pull-up node PU is further pulled up; under the control of the second clock signal provided by the second clock signal input terminal CLKC, the first transistor M1 and the second transistor M2 continue to be turned off, thereby controlling the coupling between the pull-up node PU and the first level signal input terminal VGL to be disconnected, and controlling the coupling between the gate driving signal OUTPUT terminal OUTPUT and the first level signal input terminal VGL to be disconnected.

In the Reset period P4, both the seventh transistor M7 and the eighth transistor M8 are turned on under the control of the Reset control signal provided from the Reset control terminal Reset, thereby controlling the coupling between the pull-up node PU and the first level signal input terminal VGL, and the coupling between the gate driving signal OUTPUT terminal OUTPUT and the first level signal input terminal VGL to be turned on. Under the control of the second clock signal provided by the second clock signal input terminal CLKC, the first transistor M1 and the second transistor M2 are both turned on, thereby controlling the coupling between the turn-on pull-up node PU and the first level signal input terminal VGL, and controlling the coupling between the turn-on gate driving signal OUTPUT terminal OUTPUT and the first level signal input terminal VGL. Under the control of the pull-up node PU, the sixth transistor M6 is turned off, thereby controlling the decoupling of the gate driving signal OUTPUT terminal OUTPUT and the first clock signal input terminal CLK.

In the holding period P5, under the control of the Reset control signal provided by the Reset control terminal Reset, both the seventh transistor M7 and the eighth transistor M8 are turned off, thereby controlling to disconnect the coupling between the pull-up node PU and the first level signal input terminal VGL and the coupling between the gate driving signal OUTPUT terminal OUTPUT and the first level signal input terminal VGL. The first transistor M1 is turned on periodically under the control of the second clock signal provided by the second clock signal input terminal CLKC, so as to control the coupling between the pull-up node PU and the first level signal input terminal VGL to be turned on periodically, that is, when the second clock signal is at the active level, the first transistor M1 is turned on, so as to control the coupling between the pull-up node PU and the first level signal input terminal VGL to be turned on, and when the second clock signal is at the inactive level, the first transistor M1 is turned off, so as to control the coupling between the pull-up node PU and the first level signal input terminal VGL to be turned off; meanwhile, under the control of the second clock signal provided by the second clock signal input terminal CLKC, the second transistor M2 is turned on periodically, so that the coupling between the gate driving signal OUTPUT terminal OUTPUT and the first level signal input terminal VGL is turned on periodically, that is, when the second clock signal is at an active level, the second transistor M2 is turned on, so that the coupling between the gate driving signal OUTPUT terminal OUTPUT and the first level signal input terminal VGL is controlled to be turned on, and when the second clock signal is at an inactive level, the second transistor M2 is turned off, so that the coupling between the gate driving signal OUTPUT terminal OUTPUT and the first level signal input terminal VGL is controlled to be turned off.

According to the specific structure of the shift register unit provided in the above embodiment, when the shift register unit provided in the above embodiment includes only the input sub-circuit 1, the output sub-circuit 3, the storage sub-circuit 2, and the control sub-circuit 4, the shift register unit includes only four transistors and a first capacitor; when the shift register unit provided in the above embodiment further includes the first reset sub-circuit 7 and the second reset sub-circuit 8, the shift register unit only includes six transistors and one capacitor; when the shift register unit provided in the above embodiment further includes the first frame pre-noise reduction sub-circuit 5 and the second frame pre-noise reduction sub-circuit 6, the above shift register unit includes only eight transistors and one capacitor.

It can be seen that, in the shift register unit provided in the above embodiment, even if the shift register unit includes the input sub-circuit 1, the output sub-circuit 3, the control sub-circuit 4, the first reset sub-circuit 7, the second reset sub-circuit 8, the first frame pre-noise reduction sub-circuit 5, the second frame pre-noise reduction sub-circuit 6, and the storage sub-circuit 2 at the same time, the shift register unit includes only eight transistors and one capacitor.

It should be noted that, in the shift register unit provided in the above embodiments, the specific type of the transistor included in the shift register unit may be selected according to actual needs, and for example, the P-type thin film transistor or the N-type thin film transistor is selected, but not limited thereto; for example, the first pole of the transistor may be a source and the second pole may correspond to a drain, or the first pole may be a drain and the second pole may be a source. The first level signal input by the first level signal input terminal may be a low level signal, but is not limited thereto.

In addition, the signals required by the Shift register units can be generated in various ways, specifically, a timing control chip (TCON IC) can be matched with a Level Shift IC to output a first clock signal to a first clock signal INPUT terminal CLK, output a second clock signal to a second clock signal INPUT terminal CLKC, output an INPUT signal corresponding to the first row of Shift register units to an INPUT signal terminal INPUT of the first row of Shift register units, and output a pre-frame noise reduction control circuit to a pre-frame noise reduction control terminal STV 0; the high level corresponding to each signal is VGH, and the low level is a low level signal input by a first level signal input end VGL; the frequency of each clock signal can be realized by matching a time sequence control chip with a level conversion chip according to actual requirements.

As shown in fig. 8, an embodiment of the present invention further provides a gate driving circuit, which includes a plurality of shift register units provided in the foregoing embodiments, the plurality of shift register units are sequentially cascaded, and a gate driving signal OUTPUT terminal OUTPUT of a previous shift register unit is coupled to an INPUT signal terminal INPUT of an adjacent next shift register unit.

Specifically, when a plurality of shift register units provided in the above embodiments are cascaded to form the gate driving circuit provided in the embodiments of the present invention, the gate driving signal OUTPUT terminal OUTPUT of a previous shift register unit (for example, the nth) may be coupled to the INPUT signal terminal INPUT of an adjacent next shift register unit (for example, the n +1 th) so that the gate driving signal OUTPUT by the previous shift register unit is used as the INPUT signal of the adjacent next shift register unit.

When the shift register unit provided in the above embodiment includes the first Reset sub-circuit 7 and the second Reset sub-circuit 8, in the gate driving circuit provided in the embodiment of the present invention, the gate driving signal OUTPUT terminal OUTPUT of the next shift register unit may be further configured to be coupled to the Reset control terminal Reset of the previous adjacent shift register unit, that is, the gate driving signal OUTPUT by the next shift register unit is used as the Reset control signal of the previous adjacent shift register unit.

It can be seen that, in the gate driving circuit provided in the embodiment of the present invention, when the shift register unit includes no first Reset sub-circuit 7 and no second Reset sub-circuit 8, it is not necessary to set the gate driving signal OUTPUT terminal OUTPUT of the next shift register unit to be coupled to the Reset control terminal Reset of the previous adjacent shift register unit, so as to further simplify the circuit structure of the gate driving circuit.

In addition, the shift register unit provided by the embodiment of the invention well improves the charging capability of the pull-up node PU while reducing the circuit complexity, so that the gate driving circuit provided by the embodiment of the invention has the effects of simple structure and strong driving capability when comprising the shift register unit provided by the embodiment of the invention.

Moreover, because the shift register unit provided by the embodiment of the invention has a strong charging capability, the gate driving circuit provided by the embodiment of the invention is more favorable for low-temperature start of a display product when the gate driving circuit provided by the embodiment of the invention is applied to the display product under the condition that the shift register unit provided by the embodiment of the invention is included.

In more detail, as shown in fig. 8-10, the INPUT signal INPUT from the INPUT signal terminal INPUT1 of the first row shift register unit (GOA1) is the frame start signal INPUT from the frame start signal INPUT terminal STV1, the Reset control terminal Reset1 of the first row shift register unit is coupled to the gate driving signal OUTPUT terminal OUTPUT2 of the second row shift register unit (GOA2), and the gate driving signal OUTPUT terminal OUTPUT1 of the first row shift register unit is coupled to the INPUT signal terminal INPUT2 of the second row shift register unit; in analogy, the gate driving signal OUTPUT terminal OUTPUT2 of the second row of shift register units is coupled to the input signal terminal of the third row of shift register units, and the Reset control terminal Reset2 of the second row of shift register units is coupled to the gate driving signal OUTPUT terminal of the third row of shift register units; and a plurality of shift register units included in the grid driving circuit are driven line by line until all driving work is completed.

In addition, in the above gate driving circuit, at least two second clock signal lines (CLK1C and CLK2C) may be provided, and when two second clock signal lines are provided, one of the second clock signal lines CLK1C may be coupled to the second clock signal input terminals CLKC in the odd-numbered line shift register units in the gate driving circuit, and the other second clock signal line CLK2C may be coupled to the second clock signal input terminals CLKC in the even-numbered line shift register units in the gate driving circuit. Similarly, at least two first clock signal lines (CLK1 and CLK2) are provided in the gate driving circuit, and one of the first clock signal lines CLK1 may be coupled to the first clock signal input terminals CLK in the odd-numbered shift register units in the gate driving circuit, and the other first clock signal line CLK2 may be coupled to the first clock signal input terminals CLK in the even-numbered shift register units in the gate driving circuit.

It should be noted that, in the gate driving circuit provided in the embodiment of the present invention, 4, six or even more first clock signal lines and second clock signal lines may be set according to actual needs, and only the connection relationships between the first clock signal lines and the second clock signal lines and the shift register units in each row need to be set reasonably.

The embodiment of the present invention further provides a driving method for a shift register unit, which is applied to the shift register unit provided in the above embodiment, and the driving method includes:

in the INPUT period P2, the INPUT sub-circuit 1 in the shift register unit controls to turn on the coupling between the INPUT signal terminal INPUT and the pull-up node PU under the control of the INPUT signal provided by the INPUT signal terminal INPUT; the control sub-circuit 4 in the shift register unit controls to disconnect the coupling between the pull-up node PU and the first level signal input terminal VGL and controls to disconnect the coupling between the gate driving signal OUTPUT terminal OUTPUT and the first level signal input terminal VGL under the control of the second clock signal provided by the second clock signal input terminal CLKC;

in the output period P3, the INPUT sub-circuit 1 controls to disconnect the coupling between the INPUT signal terminal INPUT and the pull-up node PU under the control of the INPUT signal terminal INPUT; an OUTPUT sub-circuit 3 in the shift register unit controls the coupling between the gate driving signal OUTPUT terminal OUTPUT and the first clock signal input terminal CLK to be conducted under the control of the potential of the pull-up node PU; the control sub-circuit 4 continues to control to disconnect the coupling between the pull-up node PU and the first level signal input terminal VGL and to control to disconnect the coupling between the gate driving signal OUTPUT terminal OUTPUT and the first level signal input terminal VGL under the control of the second clock signal provided by the second clock signal input terminal CLKC;

in the reset period P4, the OUTPUT sub-circuit 3 controls to disconnect the coupling between the gate driving signal OUTPUT terminal OUTPUT and the first clock signal input terminal CLK under the control of the potential of the pull-up node PU; the control sub-circuit 4 controls to turn on the coupling between the pull-up node PU and the first level signal input terminal VGL and controls to turn on the coupling between the gate driving signal OUTPUT terminal OUTPUT and the first level signal input terminal VGL under the control of a second clock signal provided by a second clock signal input terminal CLKC;

in the holding period P5, the control sub-circuit 4 periodically controls to turn on the coupling between the pull-up node PU and the first level signal input terminal VGL and to turn on the coupling between the gate driving signal OUTPUT terminal OUTPUT and the first level signal input terminal VGL under the control of the second clock signal provided by the second clock signal input terminal CLKC.

In more detail, in a working cycle, the driving method specifically includes:

in the INPUT period P2, under the control of the INPUT signal provided by the INPUT signal terminal INPUT, the INPUT sub-circuit 1 controls to turn on the coupling between the INPUT signal terminal INPUT and the pull-up node PU, pull up the potential of the pull-up node PU, and charge the storage sub-circuit 2; under the control of the second clock signal provided by the second clock signal input terminal CLKC, the control sub-circuit 4 controls to disconnect the coupling between the pull-up node PU and the first level signal input terminal VGL, and the control sub-circuit 4 controls to disconnect the coupling between the gate driving signal OUTPUT terminal OUTPUT and the first level signal input terminal VGL.

In the output period P3, under the control of the INPUT signal terminal INPUT, the INPUT sub-circuit 1 controls to disconnect the coupling between the INPUT signal terminal INPUT and the pull-up node PU; the OUTPUT sub-circuit 3 controls and conducts the coupling between the gate driving signal OUTPUT terminal OUTPUT and the first clock signal input terminal CLK under the control of the pull-up node PU, so that the gate driving signal OUTPUT terminal OUTPUT OUTPUTs the gate driving signal, and the potential of the pull-up node PU is further pulled up due to the bootstrap action of the memory sub-circuit 2; under the control of the second clock signal provided by the second clock signal input terminal CLKC, the control sub-circuit 4 continues to control to disconnect the coupling between the pull-up node PU and the first level signal input terminal VGL, and continues to control to disconnect the coupling between the gate driving signal OUTPUT terminal OUTPUT and the first level signal input terminal VGL.

When the shift register unit provided by the above embodiment is driven by the driving method provided by the embodiment of the present invention, the control sub-circuit 4 can control to disconnect the coupling between the pull-up node PU and the first level signal input terminal VGL and control to disconnect the coupling between the gate driving signal OUTPUT terminal OUTPUT and the first level signal input terminal VGL under the control of the second clock signal provided by the second clock signal input terminal CLKC in the input period P2 and the OUTPUT period P3, so that the potentials of the pull-up node PU and the gate driving signal OUTPUT terminal OUTPUT are not pulled down in the input period P2 and the OUTPUT period P3, that is, the problem that the charging of the pull-up node PU is affected by the potential of the pull-down node PD in the related art is avoided; therefore, the problems that a large number of transistors for controlling the potential of the pull-down node PD are introduced into the shift register unit provided by the embodiment and the transistors are increased for ensuring the stable operation of the power supply chip are further avoided; therefore, when the driving method provided by the embodiment of the present invention is used to drive the shift register unit provided by the above embodiment, the circuit complexity of the shift register unit is reduced, and the charging capability of the pull-up node PU is improved, so that when the shift register is applied to a display product, the driving performance of the display product is ensured, and the narrow frame of the display product is facilitated.

In addition, when the driving method provided by the embodiment of the invention is adopted to drive the shift register unit provided by the embodiment of the invention, the shift register unit has stronger charging capability, thereby being more beneficial to the low-temperature start of a display product.

In addition, when the shift register unit provided by the above embodiment is driven by the driving method provided by the embodiment of the present invention, since the second clock signal input by the second clock signal input terminal CLKC is at the inactive level in both the input period P2 and the output period P3, so that the second clock signal has a lower frequency than the first clock signal, and the clock signal and the inverted clock signal in the related art, in a case where the shift register unit provided by the above embodiment is driven by the driving method provided by the embodiment of the present invention, when the shift register unit provided by the above embodiment is applied to a display product, the display product can realize lower power consumption during operation.

In some embodiments, the above embodiments provide that the frequency of the first clock signal input from the first clock signal input terminal CLK is an integer multiple of the frequency of the second clock signal input from the second clock signal input terminal CLKC.

Specifically, the frequencies and phases of the first clock signal and the second clock signal provided by the above embodiments can be set according to actual needs, and for example, the frequency of the first clock signal input by the first clock signal input terminal CLK can be set to be an integer multiple of the frequency of the second clock signal input by the second clock signal input terminal CLKC, and specifically can be two times, four times, eight times, and the like, but is not limited thereto.

It should be noted that, in the present specification, all the embodiments are described in a progressive manner, and the same and similar parts among the embodiments are referred to each other, and each embodiment focuses on the differences from the other embodiments. In particular, as for the method embodiments, since they are substantially similar to the product embodiments, they are described simply, and reference may be made to the partial description of the product embodiments for relevant points.

Unless defined otherwise, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this invention belongs. The use of "first," "second," and similar terms in this disclosure is not intended to indicate any order, quantity, or importance, but rather is used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", and the like are used merely to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationships may also be changed accordingly.

It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "under" another element, it can be "directly on" or "under" the other element or intervening elements may be present.

In the foregoing description of embodiments, the particular features, structures, materials, or characteristics may be combined in any suitable manner in any one or more embodiments or examples.

The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and all the changes or substitutions should be covered within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.

Claims

1. A shift register cell, comprising:

2. The shift register cell of claim 1, wherein the control subcircuit includes a first transistor and a second transistor; wherein,

3. The shift register cell according to claim 2, wherein the shift register cell is formed over a substrate, and an overlapping region of a gate layer of the first transistor and an active layer of the first transistor in a direction perpendicular to the substrate is formed as a first channel region; an overlapping region of a gate layer of the second transistor and an active layer of the second transistor in a direction perpendicular to a substrate is formed as a second channel region; an area of the first channel region and an area of the second channel region are both greater than a threshold.

4. The shift register unit according to any one of claims 1 to 3, further comprising:

5. The shift register cell of claim 4,

the first pre-frame noise reduction sub-circuit comprises a third transistor, wherein the grid electrode of the third transistor is coupled with the pre-frame noise reduction control end, the first pole of the third transistor is coupled with the pull-up node, and the second pole of the third transistor is coupled with the first level signal input end;

6. The shift register unit according to any one of claims 1 to 3, further comprising:

7. The shift register cell of claim 6,

the input sub-circuit comprises a fifth transistor, a gate of the fifth transistor and a first pole of the fifth transistor are both coupled with the input signal terminal, and a second pole of the fifth transistor is coupled with the pull-up node;

8. A gate driving circuit, comprising a plurality of shift register units according to any one of claims 1 to 7, wherein the plurality of shift register units are sequentially cascaded, and the gate driving signal output terminal of a previous shift register unit is coupled to the input signal terminal of an adjacent next shift register unit.

9. A driving method of a shift register unit, which is applied to the shift register unit according to any one of claims 1 to 7, the driving method comprising:

10. The method according to claim 9, wherein a frequency of the first clock signal input from the first clock signal input terminal is an integer multiple of a frequency of the second clock signal input from the second clock signal input terminal.