CN109584941B - Shift register and driving method thereof, gate drive circuit and display device - Google Patents

Shift register and driving method thereof, gate drive circuit and display device Download PDF

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Publication number
CN109584941B
CN109584941B CN201910002475.7A CN201910002475A CN109584941B CN 109584941 B CN109584941 B CN 109584941B CN 201910002475 A CN201910002475 A CN 201910002475A CN 109584941 B CN109584941 B CN 109584941B
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transistor
electrode
signal
pull
power supply
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CN109584941A (en
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邹宜峰
熊雄
郑敏栋
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BOE Technology Group Co Ltd
Hefei Xinsheng Optoelectronics Technology Co Ltd
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BOE Technology Group Co Ltd
Hefei Xinsheng Optoelectronics Technology Co Ltd
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit

Abstract

The invention discloses a shift register and a driving method thereof, a grid driving circuit and a display device, wherein the shift register comprises: a shift register unit for outputting a gate driving signal and a shutdown control sub-circuit, the shift register unit including: and the signal output end and the shutdown control sub-circuit are respectively connected with the signal output end, the first power end and the second power end and are used for providing a starting signal for the signal output end under the control of the first power end and the second power end when the XON function is started so as to enable the thin film transistors connected with the corresponding row grid lines to be switched on. According to the technical scheme provided by the embodiment of the invention, when the XON function is started, the two signal ends of the first power end and the second power end are used for controlling the supply of the starting signal to the signal output end, so that when the XON function is realized, the driving capability of XON is improved, the pixel can release charges more fully, the generation of charge residue is avoided, and the display effect is further improved.

Description

Shift register and driving method thereof, gate drive circuit and display device
Technical Field
The embodiment of the invention relates to the technical field of display, in particular to a shift register, a driving method thereof, a gate driving circuit and a display device.
Background
The liquid crystal display panel consists of a source drain electrode and a grid array type pixel matrix, and a grid driving circuit is used for generating grid scanning voltage of pixels in the display process so as to scan pixels in rows and columns line by line. Gate Driver on array (GOA) is a technology for integrating a Gate Driver circuit on an array substrate, and each GOA unit is used as a shift register to sequentially transmit a scan signal to a next GOA unit, and a Thin Film Transistor (TFT) switch is turned on line by line to complete data signal input of a pixel. In the related art, the liquid crystal display panel has an XON (gate line on at the moment of shutdown), in which an XON signal triggers each GOA unit to output a TFT on signal at the moment of shutdown, so that TFTs in all rows are turned on, and charges stored in pixel storage capacitors and parasitic capacitors are released, thereby preventing poor shutdown ghost.
The inventor researches and discovers that high-resolution and large-size display products are more and more along with the development of display technology. However, due to the large load in the high-resolution and large-size display product, when the liquid crystal display panel realizes the XON function, the problem of insufficient drive capability of XON exists, all TFTs cannot be turned on, and the pixels cannot fully release charges, so that charge residue is generated, and the display effect is affected.
Disclosure of Invention
In order to solve the above technical problems, embodiments of the present invention provide a shift register, a driving method thereof, a gate driving circuit, and a display device, which can improve the driving capability of XON when implementing the XON function, so that a pixel can release charges more sufficiently, thereby avoiding generating charge residue, and further improving the display effect.
In a first aspect, an embodiment of the present invention provides a shift register, including: a shift register unit and a shutdown control sub-circuit for outputting a gate driving signal, the shift register unit comprising: a signal output terminal;
and the shutdown control sub-circuit is respectively connected with the signal output end, the first power supply end and the second power supply end and is used for providing a starting signal for the signal output end under the control of the first power supply end and the second power supply end when the XON function is started so as to enable the thin film transistors connected with the corresponding row grid lines to be conducted.
Optionally, the shutdown control sub-circuit includes: a first transistor and a first capacitor;
the control electrode of the first transistor is connected with a first power supply end, the first electrode of the first transistor is connected with a signal output end, and the second electrode of the first transistor is connected with a second power supply end;
the first end of the first capacitor is connected with a first power supply end, and the second end of the first capacitor is connected with a second power supply end.
Optionally, the shift register unit includes: an input sub-circuit and an output sub-circuit;
the input sub-circuit is respectively connected with the signal input end and the pull-up node and is used for providing a signal of the signal input end to the pull-up node under the control of the signal input end;
and the output sub-circuit is respectively connected with the pull-up node, the clock signal end and the signal output end and is used for providing the clock signal of the clock signal end for the signal output end under the control of the pull-up node.
Optionally, the shift register unit further includes: a reset sub-circuit and a noise reduction sub-circuit;
the reset sub-circuit is respectively connected with the pull-up node, the reset signal end and the first power end and is used for providing a signal of the first power end to the pull-up node under the control of the reset signal end;
the noise reduction sub-circuit is respectively connected with the first noise reduction signal end, the second noise reduction signal end, the pull-up node, the first power end and the signal output end, and is used for providing signals of the first power end to the pull-up node and the signal output end under the control of the first noise reduction signal end and/or the second noise reduction signal end;
the input signals of the first noise reduction signal end and the second noise reduction signal end are opposite phase signals.
Optionally, the input sub-circuit comprises: a second transistor, the output sub-circuit including: a third transistor and a second capacitor;
the control electrode and the first electrode of the second transistor are connected with the signal input end, and the second electrode of the second transistor is connected with the pull-up node;
the control electrode of the third transistor is connected with the pull-up node, the first electrode of the third transistor is connected with the clock signal end, and the second electrode of the third transistor is connected with the signal output end;
and the first end of the second capacitor is connected with the pull-up node, and the second end of the second capacitor is connected with the signal output end.
Optionally, the reset sub-circuit comprises: a fourth transistor, the noise reduction sub-circuit comprising: a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, and a sixteenth transistor;
a control electrode of the fourth transistor is connected with the reset signal end, a first electrode of the fourth transistor is connected with the pull-up node, and a second electrode of the fourth transistor is connected with the first power supply end;
the control electrode and the first electrode of the fifth transistor are connected with the first noise reduction signal end, and the second electrode of the fifth transistor is connected with the first electrode of the seventh transistor;
a control electrode of the sixth transistor is connected with a second electrode of the fifth transistor, a first electrode of the sixth transistor is connected with the first noise reduction signal end, and a second electrode of the sixth transistor is connected with the first pull-down node;
a control electrode of the seventh transistor is connected with the pull-up node, and a second electrode of the seventh transistor is connected with a first power supply end;
a control electrode of the eighth transistor is connected with the pull-up node, a first electrode of the eighth transistor is connected with the first pull-down node, and a second electrode of the eighth transistor is connected with the first power supply end;
a control electrode of the ninth transistor is connected with the first pull-down node, a first electrode of the ninth transistor is connected with the pull-up node, and a second electrode of the ninth transistor is connected with the first power supply end;
a control electrode of the tenth transistor is connected with the first pull-down node, a first electrode of the tenth transistor is connected with the signal output end, and a second electrode of the tenth transistor is connected with the first power supply end;
a control electrode and a first electrode of the eleventh transistor are connected with the second noise reduction signal end, and a second electrode of the eleventh transistor is connected with a first electrode of the thirteenth transistor;
a control electrode of the twelfth transistor is connected with a second electrode of the eleventh transistor, a first electrode of the twelfth transistor is connected with the second noise reduction signal end, and a second electrode of the twelfth transistor is connected with the second pull-down node;
a control electrode of the thirteenth transistor is connected with the pull-up node, and a second electrode of the thirteenth transistor is connected with the first power supply end;
a control electrode of the fourteenth transistor is connected with the pull-up node, a first electrode of the fourteenth transistor is connected with the second pull-down node, and a second electrode of the fourteenth transistor is connected with the first power supply end;
a control electrode of the fifteenth transistor is connected with the second pull-down node, a first electrode of the fifteenth transistor is connected with the pull-up node, and a second electrode of the fifteenth transistor is connected with the first power supply end;
and a control electrode of the sixteenth transistor is connected with the second pull-down node, a first electrode of the sixteenth transistor is connected with the signal output end, and a second electrode of the sixteenth transistor is connected with the first power supply end.
Optionally, the shutdown control sub-circuit includes: a first transistor and a first capacitor, the shift register unit including: an input sub-circuit, an output sub-circuit, a reset sub-circuit, and a noise reduction sub-circuit, the input sub-circuit comprising: a second transistor, the output sub-circuit including: a third transistor and a second capacitor, the reset sub-circuit including: a fourth transistor, the noise reduction sub-circuit comprising: a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, and a sixteenth transistor;
the control electrode of the first transistor is connected with a first power supply end, the first electrode of the first transistor is connected with a signal output end, and the second electrode of the first transistor is connected with a second power supply end;
the first end of the first capacitor is connected with a first power supply end, and the second end of the first capacitor is connected with a second power supply end;
the control electrode and the first electrode of the second transistor are connected with the signal input end, and the second electrode of the second transistor is connected with the pull-up node;
the control electrode of the third transistor is connected with the pull-up node, the first electrode of the third transistor is connected with the clock signal end, and the second electrode of the third transistor is connected with the signal output end;
the first end of the second capacitor is connected with the pull-up node, and the second end of the second capacitor is connected with the signal output end;
a control electrode of the fourth transistor is connected with the reset signal end, a first electrode of the fourth transistor is connected with the pull-up node, and a second electrode of the fourth transistor is connected with the first power supply end;
the control electrode and the first electrode of the fifth transistor are connected with the first noise reduction signal end, and the second electrode of the fifth transistor is connected with the first electrode of the seventh transistor;
a control electrode of the sixth transistor is connected with a second electrode of the fifth transistor, a first electrode of the sixth transistor is connected with the first noise reduction signal end, and a second electrode of the sixth transistor is connected with the first pull-down node;
a control electrode of the seventh transistor is connected with the pull-up node, and a second electrode of the seventh transistor is connected with a first power supply end;
a control electrode of the eighth transistor is connected with the pull-up node, a first electrode of the eighth transistor is connected with the first pull-down node, and a second electrode of the eighth transistor is connected with the first power supply end;
a control electrode of the ninth transistor is connected with the first pull-down node, a first electrode of the ninth transistor is connected with the pull-up node, and a second electrode of the ninth transistor is connected with the first power supply end;
a control electrode of the tenth transistor is connected with the first pull-down node, a first electrode of the tenth transistor is connected with the signal output end, and a second electrode of the tenth transistor is connected with the first power supply end;
a control electrode and a first electrode of the eleventh transistor are connected with the second noise reduction signal end, and a second electrode of the eleventh transistor is connected with a first electrode of the thirteenth transistor;
a control electrode of the twelfth transistor is connected with a second electrode of the eleventh transistor, a first electrode of the twelfth transistor is connected with the second noise reduction signal end, and a second electrode of the twelfth transistor is connected with the second pull-down node;
a control electrode of the thirteenth transistor is connected with the pull-up node, and a second electrode of the thirteenth transistor is connected with the first power supply end;
a control electrode of the fourteenth transistor is connected with the pull-up node, a first electrode of the fourteenth transistor is connected with the second pull-down node, and a second electrode of the fourteenth transistor is connected with the first power supply end;
a control electrode of the fifteenth transistor is connected with the second pull-down node, a first electrode of the fifteenth transistor is connected with the pull-up node, and a second electrode of the fifteenth transistor is connected with the first power supply end;
and a control electrode of the sixteenth transistor is connected with the second pull-down node, a first electrode of the sixteenth transistor is connected with the signal output end, and a second electrode of the sixteenth transistor is connected with the first power supply end.
In a second aspect, an embodiment of the present invention further provides a gate driving circuit, including: a plurality of cascaded shift registers;
the signal input end of the first-stage shift register is connected with the initial signal end, the signal output end of the Nth-stage shift register is connected with the signal input end of the (N +1) th-stage shift register, the signal output end of the (N +1) th-stage shift register is connected with the reset signal end of the Nth-stage shift register, and N is larger than or equal to 1.
In a third aspect, an embodiment of the present invention further provides a display device, including: the gate driving circuit is provided.
In a fourth aspect, an embodiment of the present invention further provides a driving method for a shift register, which is applied to the shift register, and includes:
when the XON function is activated, the shutdown control sub-circuit provides a turn-on signal to the signal output terminal under the control of the first power supply terminal and the second power supply terminal, so that the thin film transistors connected to the corresponding row gate lines are all turned on.
The embodiment of the invention provides a shift register and a driving method thereof, a grid driving circuit and a display device, wherein the shift register comprises: a shift register unit for outputting a gate driving signal and a shutdown control sub-circuit, the shift register unit including: and the signal output end and the shutdown control sub-circuit are respectively connected with the signal output end, the first power end and the second power end and are used for providing a starting signal for the signal output end under the control of the first power end and the second power end when the XON function is started so as to enable the thin film transistors connected with the corresponding row grid lines to be switched on. Compared with the prior art in which the signal of the first power supply end is used for controlling the supply of the starting signal to the signal output end, the driving capability of XON is improved when the XON function is realized, so that the pixel can release charges more fully, the generation of charge residue is avoided, and the display effect is further improved.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
Drawings
The accompanying drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the example serve to explain the principles of the invention and not to limit the invention.
Fig. 1 is a schematic structural diagram of a shift register according to an embodiment of the present invention;
fig. 2 is an equivalent circuit diagram of a shutdown control sub-circuit according to an embodiment of the present invention;
FIG. 3 is a first schematic structural diagram of a shift register unit according to an embodiment of the present invention;
FIG. 4 is a second schematic structural diagram of a shift register unit according to an embodiment of the present invention;
FIG. 5 is an equivalent circuit diagram of a shift register unit according to an embodiment of the present invention;
FIG. 6 is an equivalent circuit diagram of a shift register according to an embodiment of the present invention;
FIG. 7 is a timing diagram illustrating operation of a shift register according to an embodiment of the present invention;
fig. 8 is a schematic structural diagram of a gate driving circuit according to an embodiment of the invention;
fig. 9 is a timing diagram illustrating an operation of the gate driving circuit according to the embodiment of the invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be noted that the embodiments and features of the embodiments in the present application may be arbitrarily combined with each other without conflict.
The steps illustrated in the flow charts of the figures may be performed in a computer system such as a set of computer-executable instructions. Also, while a logical order is shown in the flow diagrams, in some cases, the steps shown or described may be performed in an order different than here.
Unless defined otherwise, technical or scientific terms used in the disclosure of the embodiments of the present invention should have the same meaning as commonly understood by one of ordinary skill in the art to which the present invention belongs. The use of "first," "second," and similar language in the embodiments of the present invention does not denote any order, quantity, or importance, but rather the terms "first," "second," and similar language are used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", and the like are used merely to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationships may also be changed accordingly.
It will be appreciated by those skilled in the art that the transistors employed in all embodiments of the present application may be thin film transistors or field effect transistors or other devices having the same characteristics. Preferably, the thin film transistor used in the embodiment of the present invention may be an oxide semiconductor transistor. Since the source and drain of the transistor used herein are symmetrical, the source and drain may be interchanged. In the embodiment of the present invention, in order to separate the two poles of the switching transistor except the gate, one of the electrodes is referred to as a first pole, the other electrode is referred to as a second pole, the first pole may be a source or a drain, and the second pole may be a drain or a source.
Example one
An embodiment of the present invention provides a shift register, and fig. 1 is a schematic structural diagram of a shift register provided in an embodiment of the present invention, and as shown in fig. 1, the shift register provided in the embodiment of the present invention includes: a shift register unit for outputting a gate driving signal and a shutdown control sub-circuit, the shift register unit including: and a signal OUTPUT terminal OUTPUT.
Specifically, the shutdown control sub-circuit is respectively connected to the signal OUTPUT terminal OUTPUT, the first power supply terminal VGL and the second power supply terminal VGH, and is configured to provide a startup signal to the signal OUTPUT terminal OUTPUT under the control of the first power supply terminal VGL and the second power supply terminal VGH when the XON function is started, so that the thin film transistors connected to the corresponding row gate lines are all turned on.
Specifically, the signal OUTPUT terminal OUTPUT is used for outputting the gate driving signal.
Optionally, the starting of the XON function is started by detecting a falling edge of the signal, and specifically, the starting of the XON function may occur simultaneously with or after receiving the shutdown control signal.
Preferably, in order to avoid that the XON function is started due to abnormal signal drop caused by voltage instability and influences the normal use of a user, the starting of the XON function is carried out after the shutdown control signal is received.
It should be noted that, during the display period, the first power terminal VGL continuously provides a low level signal, and the second power terminal continuously provides a high level signal, and when the XON function is activated, the signal of the first power terminal VGL is an XON signal, the XON signal is a high level, and the signal of the second power terminal VGH is also a high level, wherein the voltage of the signal of the second power terminal VGH is the same as the voltage of the XON signal.
The shift register provided by the embodiment of the invention comprises: a shift register unit for outputting a gate driving signal and a shutdown control sub-circuit, the shift register unit including: and the signal output end and the shutdown control sub-circuit are respectively connected with the signal output end, the first power end and the second power end and are used for providing a starting signal for the signal output end under the control of the first power end and the second power end when the XON function is started so as to enable the thin film transistors connected with the corresponding row grid lines to be switched on. Compared with the prior art in which the signal of the first power supply end is used for controlling the supply of the starting signal to the signal output end, the driving capability of XON is improved when the XON function is realized, so that the pixel can release charges more fully, the generation of charge residue is avoided, and the display effect is further improved.
Furthermore, the shift register provided by the embodiment of the invention can be applied to products with high resolution and large size, and effectively solves the problem of insufficient driving capability of the XON product with high resolution and large size.
Optionally, fig. 2 is an equivalent circuit diagram of a shutdown control sub-circuit provided in an embodiment of the present invention, and as shown in fig. 2, the shutdown control sub-circuit includes: a first transistor M1 and a first capacitor C1.
Specifically, the gate of the first transistor M1 is connected to the first power supply terminal VGL, the first pole thereof is connected to the signal OUTPUT terminal OUTPUT, and the second pole thereof is connected to the second power supply terminal VGH; the first capacitor C1 has a first terminal connected to the first power supply terminal VGL and a second terminal connected to the second power supply terminal VGH.
Specifically, in the display period, since the first power source terminal VGL continuously supplies the low level, the first transistor M1 is turned off.
In the display stage, the shutdown control sub-circuit in this embodiment has no influence on the output of the signal output terminal in the display stage because the first transistor is always turned off, so that the normal output of the shift register unit is ensured, and each row of pixels is scanned normally.
The shutdown control sub-circuit in this embodiment is configured such that, when the XON function is activated, the signal of the first power supply terminal VGL is pulled up from the low level of the display stage to the XON signal of the high level, the first transistor M1 is turned on, and further, due to the bootstrap action of the first capacitor C1, the voltage at the node N is bootstrapped to the sum of the voltage of the XON signal and the voltage of the signal of the second power supply terminal VGH, the voltage of the OUTPUT signal of the signal OUTPUT terminal OUTPUT is equal to the sum of the voltage of the XON signal and the voltage of the signal of the second power supply terminal VGH, and further, when the XON function is activated, the voltage of the signal of the second power supply terminal VGH is equal to twice the voltage of the XON signal.
In the embodiment of the invention, the second power supply end VGH participates in the driving of XON at the same time, and compared with the prior art that only the first power supply end VGL realizes the XON driving, the driving capability of XON is improved.
It should be noted that fig. 2 specifically shows an exemplary structure of the shutdown control sub-circuit. It is easily understood by those skilled in the art that the implementation of the shutdown control sub-circuit is not limited thereto as long as the function thereof can be realized.
Optionally, fig. 3 is a first schematic structural diagram of a shift register unit according to an embodiment of the present invention, as shown in fig. 3, the shift register unit includes: an input sub-circuit and an output sub-circuit.
Specifically, the INPUT sub-circuit is respectively connected to the signal INPUT terminal INPUT and the pull-up node PU, and is configured to provide a signal of the signal INPUT terminal INPUT to the pull-up node PU under the control of the signal INPUT terminal INPUT; and the OUTPUT sub-circuit is respectively connected with the pull-up node PU, the clock signal end CLK and the signal OUTPUT end OUTPUT and is used for providing the clock signal of the clock signal end CLK to the signal OUTPUT end OUTPUT under the control of the pull-up node PU.
Optionally, in order to reduce noise in the shift register unit, fig. 4 is a schematic structural diagram of a shift register unit provided in the embodiment of the present invention, and as shown in fig. 4, the shift register unit further includes: a reset sub-circuit and a noise reduction sub-circuit.
Specifically, the RESET sub-circuit is respectively connected to the pull-up node PU, the RESET signal terminal RESET and the first power supply terminal VGL, and is configured to provide a signal of the first power supply terminal VGL to the pull-up node PU under the control of the RESET signal terminal RESET; and the noise reduction sub-circuit is respectively connected with the first noise reduction signal terminal VDD1, the second noise reduction signal terminal VDD2, the pull-up node PU, the first power supply terminal VGL and the signal OUTPUT terminal OUTPUT, and is used for providing signals of the first power supply terminal VGL to the pull-up node PU and the signal OUTPUT terminal OUTPUT under the control of the first noise reduction signal terminal VDD1 and/or the second noise reduction signal terminal VDD 2.
Optionally, in order to ensure that the shift register unit can continuously reduce noise, the input signals of the first noise reduction signal terminal VDD1 and the second noise reduction signal terminal VDD2 are mutually inverse signals.
Optionally, fig. 5 is an equivalent circuit diagram of a shift register unit according to an embodiment of the present invention, and as shown in fig. 5, an input sub-circuit in the shift register unit includes: the second transistor M2, the output sub-circuit includes: a third transistor M3 and a second capacitor C2.
Specifically, a control electrode and a first electrode of the second transistor M2 are connected to the signal INPUT terminal INPUT, and a second electrode thereof is connected to the pull-up node PU; a control electrode of the third transistor M3 is connected to the pull-up node PU, a first electrode thereof is connected to the clock signal terminal CLK, and a second electrode thereof is connected to the signal OUTPUT terminal OUTPUT; a first terminal of the second capacitor C2 is connected to the pull-up node PU, and a second terminal thereof is connected to the signal OUTPUT terminal OUTPUT.
It should be noted that fig. 5 specifically shows an exemplary structure of the input sub-circuit and the output sub-circuit. It is easily understood by those skilled in the art that the implementation of the input sub-circuit and the output sub-circuit is not limited thereto as long as the functions thereof can be realized.
As shown in fig. 5, a reset sub-circuit in a shift register unit according to an embodiment of the present invention includes: the fourth transistor M4, the noise reduction sub-circuit, includes: a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, a tenth transistor M10, an eleventh transistor M11, a twelfth transistor M12, a thirteenth transistor M13, a fourteenth transistor M14, a fifteenth transistor M15, and a sixteenth transistor M16.
Specifically, a control electrode of the fourth transistor M4 is connected to the RESET signal terminal RESET, a first electrode thereof is connected to the pull-up node PU, and a second electrode thereof is connected to the first power supply terminal VGL; a control electrode and a first electrode of the fifth transistor M5 are connected to the first noise reduction signal terminal VDD1, and a second electrode thereof is connected to a first electrode of the seventh transistor M7; a control electrode of the sixth transistor M6 is connected to the second electrode of the fifth transistor M5, a first electrode thereof is connected to the first noise reduction signal terminal VDD1, and a second electrode thereof is connected to the first pull-down node PD 1; a control electrode of the seventh transistor M7 is connected to the pull-up node PU, and a second electrode thereof is connected to the first power source terminal VGL; a control electrode of the eighth transistor M8 is connected to the pull-up node PU, a first electrode thereof is connected to the first pull-down node PD1, and a second electrode thereof is connected to the first power source terminal VGL; a control electrode of the ninth transistor M9 is connected to the first pull-down node PD1, a first electrode thereof is connected to the pull-up node PU, and a second electrode thereof is connected to the first power source terminal VGL; a control electrode of the tenth transistor M10 is connected to the first pull-down node PD1, a first electrode thereof is connected to the signal OUTPUT terminal OUTPUT, and a second electrode thereof is connected to the first power source terminal VGL; a control electrode and a first electrode of the eleventh transistor M11 are connected to the second noise reduction signal terminal VDD2, and a second electrode thereof is connected to a first electrode of the thirteenth transistor M13; a control electrode of the twelfth transistor M12 is connected to the second electrode of the eleventh transistor M11, a first electrode thereof is connected to the second noise reduction signal terminal VDD2, and a second electrode thereof is connected to the second pull-down node PD 2; a control electrode of the thirteenth transistor M13 is connected to the pull-up node PU, and a second electrode thereof is connected to the first power source terminal VGL; a control electrode of the fourteenth transistor M14 is connected to the pull-up node PU, a first electrode thereof is connected to the second pull-down node PD2, and a second electrode thereof is connected to the first power source terminal VGL; a control electrode of the fifteenth transistor M15 is connected to the second pull-down node PD2, a first electrode thereof is connected to the pull-up node PU, and a second electrode thereof is connected to the first power source terminal VGL; a control electrode of the sixteenth transistor M16 is connected to the second pull-down node PD2, a first electrode thereof is connected to the signal OUTPUT terminal OUTPUT, and a second electrode thereof is connected to the first power source terminal VGL.
In this embodiment, the shift register unit provided in fig. 5 can continuously reduce noise, and a noise-reduced dc mode is implemented.
Further, it should be noted that the noise reduction sub-circuit may include only: the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, the eighth transistor M8, the ninth transistor M9 and the tenth transistor M10, the noise reduction sub-circuit may further include only: the eleventh transistor M11, the twelfth transistor M12, the thirteenth transistor M13, the fourteenth transistor M14, the fifteenth transistor M15 and the sixteenth transistor M16, wherein the two noise reduction sub-circuits can achieve interval noise reduction and an alternating current noise reduction mode if the working timings of the first noise reduction signal terminal VDD1 and the second noise reduction signal terminal VDD2 provided in this embodiment are adopted. When the noise reduction sub-circuit may include only: the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, the eighth transistor M8, the ninth transistor M9 and the tenth transistor M10, the first noise reduction signal terminal VDD1 may continuously provide a high level signal, and at this time, the shift register unit may continuously reduce noise. Similarly, when the noise reduction sub-circuit includes only: the eleventh transistor M11, the twelfth transistor M12, the thirteenth transistor M13, the fourteenth transistor M14, the fifteenth transistor M15 and the sixteenth transistor M16 may continuously provide a high-level signal to the second noise reduction signal terminal VDD2, and at this time, the shift register unit may continuously reduce noise.
It should be noted that fig. 5 specifically shows an exemplary structure of the reset sub-circuit and the noise reduction sub-circuit. It is readily understood by those skilled in the art that the implementation of the reset sub-circuit and the noise reduction sub-circuit is not limited thereto as long as the functions thereof can be achieved.
Fig. 6 is an equivalent circuit diagram of a shift register according to an embodiment of the present invention, and as shown in fig. 6, a shutdown control sub-circuit in the shift register according to the embodiment of the present invention includes: a first transistor M1 and a first capacitor C1, the shift register unit comprising: input sub-circuit, output sub-circuit, reset sub-circuit and noise reduction sub-circuit, input sub-circuit includes: the second transistor M2, the output sub-circuit includes: a third transistor M3 and a second capacitor C2, the reset sub-circuit includes: the fourth transistor M4, the noise reduction sub-circuit, includes: a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, a tenth transistor M10, an eleventh transistor M11, a twelfth transistor M12, a thirteenth transistor M13, a fourteenth transistor M14, a fifteenth transistor M15, and a sixteenth transistor M16.
Specifically, the gate of the first transistor M1 is connected to the first power supply terminal VGL, the first pole thereof is connected to the signal OUTPUT terminal OUTPUT, and the second pole thereof is connected to the second power supply terminal VGH; a first terminal of the first capacitor C1 is connected to the first power supply terminal VGL, and a second terminal thereof is connected to the second power supply terminal VGH; a control electrode and a first electrode of the second transistor M2 are connected to the signal INPUT terminal INPUT, and a second electrode thereof is connected to the pull-up node PU; a control electrode of the third transistor M3 is connected to the pull-up node PU, a first electrode thereof is connected to the clock signal terminal CLK, and a second electrode thereof is connected to the signal OUTPUT terminal OUTPUT; a first end of the second capacitor C2 is connected to the pull-up node PU, and a second end thereof is connected to the signal OUTPUT terminal OUTPUT; a control electrode of the fourth transistor M4 is connected to the RESET signal terminal RESET, a first electrode thereof is connected to the pull-up node PU, and a second electrode thereof is connected to the first power supply terminal VGL; a control electrode and a first electrode of the fifth transistor M5 are connected to the first noise reduction signal terminal VDD1, and a second electrode thereof is connected to a first electrode of the seventh transistor M7; a control electrode of the sixth transistor M6 is connected to the second electrode of the fifth transistor M5, a first electrode thereof is connected to the first noise reduction signal terminal VDD1, and a second electrode thereof is connected to the first pull-down node PD 1; a control electrode of the seventh transistor M7 is connected to the pull-up node PU, and a second electrode thereof is connected to the first power source terminal VGL; a control electrode of the eighth transistor M8 is connected to the pull-up node PU, a first electrode thereof is connected to the first pull-down node PD1, and a second electrode thereof is connected to the first power source terminal VGL; a control electrode of the ninth transistor M9 is connected to the first pull-down node PD1, a first electrode thereof is connected to the pull-up node PU, and a second electrode thereof is connected to the first power source terminal VGL; a control electrode of the tenth transistor M10 is connected to the first pull-down node PD1, a first electrode thereof is connected to the signal OUTPUT terminal OUTPUT, and a second electrode thereof is connected to the first power source terminal VGL; a control electrode and a first electrode of the eleventh transistor M11 are connected to the second noise reduction signal terminal VDD2, and a second electrode thereof is connected to a first electrode of the thirteenth transistor M13; a control electrode of the twelfth transistor M12 is connected to the second electrode of the eleventh transistor M11, a first electrode thereof is connected to the second noise reduction signal terminal VDD2, and a second electrode thereof is connected to the second pull-down node PD 2; a control electrode of the thirteenth transistor M13 is connected to the pull-up node PU, and a second electrode thereof is connected to the first power source terminal VGL; a control electrode of the fourteenth transistor M14 is connected to the pull-up node PU, a first electrode thereof is connected to the second pull-down node PD2, and a second electrode thereof is connected to the first power source terminal VGL; a control electrode of the fifteenth transistor M15 is connected to the second pull-down node PD2, a first electrode thereof is connected to the pull-up node PU, and a second electrode thereof is connected to the first power source terminal VGL; a control electrode of the sixteenth transistor M16 is connected to the second pull-down node PD2, a first electrode thereof is connected to the signal OUTPUT terminal OUTPUT, and a second electrode thereof is connected to the first power source terminal VGL.
In this embodiment, the shutdown control sub-circuit in the shift register is connected to the signal output end of the shift register unit, and the shift register may be of any architecture, may be a shift register unit that implements the noise reduction dc mode shown in fig. 5, and may also be a register unit that implements the noise reduction ac mode, which is not limited in this embodiment of the present invention.
In the embodiment, the transistors M1 to M16 may be both N-type thin film transistors or P-type thin film transistors, so that the process flow can be unified, the process can be reduced, and the yield of the product can be improved. In addition, in view of the small leakage current of the low temperature polysilicon thin film transistor, in the embodiment of the present invention, it is preferable that all the transistors are low temperature polysilicon thin film transistors, and the thin film transistor may specifically be a thin film transistor with a bottom gate structure or a thin film transistor with a top gate structure as long as a switching function can be implemented.
The first capacitor C1 and the second capacitor C2 may be liquid crystal capacitors formed by the pixel electrode and the common electrode, or may be equivalent capacitors formed by the liquid crystal capacitors formed by the pixel electrode and the common electrode and the storage capacitor, but the present invention is not limited thereto.
The technical solution of the embodiment of the present invention is further explained by the display stage and the shutdown stage of the shift register.
Taking the transistors M1 to M16 in the shift register provided by the embodiment of the present invention are all N-type thin film transistors as an example, fig. 7 is an operation timing diagram of the shift register provided by the embodiment of the present invention, as shown in fig. 6 and fig. 7, the shift register provided by the embodiment of the present invention includes 16 transistor units (M1 to M16), 2 capacitors (C1 and C2), 7 signal INPUT terminals (INPUT, RESET, CLK, VDD1, VDD2, VGL, and VGH), and 1 signal OUTPUT terminal (OUTPUT).
In the display phase, the first power source terminal VGL continuously provides a low level signal, and the second power source terminal VGH continuously increases the level signal. In particular, the method comprises the following steps of,
in the first stage T1, i.e., the INPUT stage, the INPUT signal at the signal INPUT terminal INPUT is at a high level, the second transistor M2 is turned on, and the potential of the pull-up node PU is pulled up to charge the second capacitor C2.
In this stage, the INPUT signals of the signal INPUT terminal INPUT and the second noise reduction signal terminal VDD2 in the INPUT terminal are at a high level, the INPUT signals of the RESET signal terminal RESET, the clock signal terminal CLK and the first noise reduction signal terminal VDD1 are at a low level, and the OUTPUT signal of the signal OUTPUT terminal OUTPUT is at a low level. Although the input signal of the second noise reduction signal terminal VDD2 is at a high level, the eleventh transistor M11 and the twelfth transistor M12 are turned on, and the potential of the second pull-down node PD2 is pulled high, since the potential of the pull-up node PU is at a high level, the thirteenth transistor M13 and the fourteenth transistor M14 are also in a turned-on state, the potential of the second pull-down node PD2 is pulled low, and the fifteenth transistor M15 and the sixteenth transistor M16 are turned off, and the potential of the pull-up node PU is not pulled low.
In the second stage T2, i.e. the OUTPUT stage, the INPUT signal at the signal INPUT terminal INPUT is at a low level, the second transistor M2 is turned off, the INPUT signal at the clock signal terminal CLK becomes at a high level, due to the bootstrap effect of the second capacitor C2, the potential of the pull-up node PU is continuously pulled up, the high level of the pull-up node PU turns on the third transistor M3, the signal OUTPUT terminal OUTPUT OUTPUTs the clock signal at the clock signal terminal CLK, i.e. the present-stage gate driving signal, and in addition, the rising of the potential of the pull-up node PU improves the turn-on capability of the third transistor M3, thereby ensuring the charging of the pixel.
In this stage, the INPUT signals of the clock signal terminal CLK and the first noise reduction signal terminal VDD1 in the INPUT terminal are at a high level, the INPUT signals of the signal INPUT terminal INPUT, the RESET signal terminal RESET and the second noise reduction signal terminal VDD2 are at a low level, and the OUTPUT signal of the signal OUTPUT terminal OUTPUT is at a high level. Although the input signal of the first noise reduction signal terminal VDD1 is at a high level, the fifth transistor M5 and the sixth transistor M5 are turned on, and the potential of the first pull-down node PD1 is pulled high, since the potential of the pull-up node PU is at a high level, the seventh transistor M7 and the eighth transistor M8 are also in an on state, the potential of the first pull-down node PD1 is pulled low, and the ninth transistor M9 and the tenth transistor M10 are turned off, and the potential of the pull-up node PU is not pulled low.
In the third stage T3, i.e., the RESET stage, the signal of the RESET signal terminal RESET is at a high level, the fourth transistor M4 is turned on to pull down the potential of the pull-up node PU to a low level of the first power source terminal VGL, the third transistor M3 is turned off, the seventh transistor M7, the eighth transistor M8, the thirteenth transistor M13 and the fourteenth transistor M14 are turned off because the potential of the pull-up node PU is pulled down, the input signal of the first noise reduction signal terminal VDD1 is at a high level, the fifth transistor M5 and the sixth transistor M5 are turned on, the potential of the first pull-down node PD1 is pulled up, the potential of the first pull-down node PD1 is kept at a high level because the seventh transistor M7 and the eighth transistor M8 are turned off, the ninth transistor M9 and the tenth transistor M10 are turned on, and the signals of the pull-up node PU and the signal OUTPUT terminal OUTPUT are further pulled down to reduce noise.
In this stage, the INPUT signals of the clock signal terminal CLK and the first noise reduction signal terminal VDD1 at the INPUT terminal are at a high level, and the INPUT signals of the signal INPUT terminal INPUT, the RESET signal terminal RESET, and the second noise reduction signal terminal VDD2 are at a low level, but the INPUT signal of the clock signal terminal CLK is at a high level, but the OUTPUT signal of the signal OUTPUT terminal OUTPUT is at a low level because the third transistor M3 is turned off.
In the fourth stage, i.e., the noise reduction stage T4, when the input signal of the first noise reduction signal terminal VDD1 or the second noise reduction signal terminal VDD2 is at a high level, the fifth transistor M5 and the sixth transistor M5 are turned on, the potential of the first pull-down node PD1 is pulled high, since the seventh transistor M7 and the eighth transistor M8 are still in an off state, the potential of the first pull-down node PD1 is kept at a high potential, the ninth transistor M9 and the tenth transistor M10 are turned on, the signals of the pull-up node PU and the signal OUTPUT terminal OUTPUT are further pulled low to reduce noise, when the input signal of the second noise reduction signal terminal VDD2 is at a high level, the eleventh transistor M11 and the twelfth transistor M12 are turned on, the potential of the second pull-down node PD2 is pulled high, since the thirteenth transistor M13 and the fourteenth transistor M14 are still in an off state, the potential of the second pull-down node PD2 is kept at a high potential, the fifteenth transistor M15 and the sixteenth transistor M16 are turned on to further pull down the signals of the pull-up node PU and the signal OUTPUT terminal OUTPUT to reduce noise.
After the reset period T4, the shift register of this stage always maintains the noise reduction period T4 until the signal INPUT terminal INPUT receives a high level signal again.
In the shift register provided by the embodiment of the invention, in the display stage, the signal of the signal INPUT end is a pulse signal, and is high level only in the INPUT stage; the OUTPUT signal of the signal OUTPUT terminal OUTPUT2 is a pulse signal and is high level only in the OUTPUT stage; the RESET signal of the RESET signal end is a pulse signal and is at a high level only in the RESET stage; the signal of the clock signal terminal LCK is a periodic signal,
during the shutdown phase, in particular,
in the first stage S1, which is a protection stage, after receiving the shutdown control signal, the signal of the first power supply terminal VGL is at a low level, the first transistor M1 is turned off, the signal of the second power supply terminal VGH starts to fall, and the signal of the first noise reduction signal terminal or the signal of the second noise reduction signal terminal, where the input signal of the second noise reduction signal terminal is at a high level, starts to fall.
In the second stage S2, which is the stage for implementing the XON function, when the XON function is activated, the signal of the first power source terminal VGL is pulled to the XON signal of high level, the first transistor M1 is turned on, and in addition, due to the bootstrap effect of the first capacitor C1, the voltage of the node N is bootstrapped to the voltage V of the XON signalXONAnd the voltage of the signal of the second power source terminal VGH, the voltage of the OUTPUT signal of the signal OUTPUT terminal OUTPUT is equal to the sum of the voltage of the XON signal and the voltage of the signal of the second power source terminal VGH. In addition, when the XON function is activated, the voltage of the signal of the second power source terminal VGH is the voltage of the XON signal, and thus, the voltage of the OUTPUT signal of the signal OUTPUT terminal OUTPUT is equal to 2VXONAnd when the signals of the first noise reduction signal end, the second noise reduction signal end, the first power supply end VGL and the signal OUTPUT end OUTPUT are reduced to about 3.3V, the XON function is finished.
In the embodiment of the invention, the second power supply end VGH participates in the driving of XON at the same time, and compared with the prior art that only the first power supply end VGL realizes the XON driving, the driving capability of XON is improved.
The signal of the second power source terminal VGH continues to drop until it is 0 in the third stage S3.
Example two
Based on the inventive concept of the foregoing embodiment, an embodiment of the present invention further provides a driving method of a shift register, which is applied to the shift register provided in the first embodiment, where the shift register includes: the driving method of the shift register comprises a signal INPUT end INPUT, a RESET signal end RESET, a clock signal end CLK, a signal OUTPUT end OUTPUT, a first noise reduction signal end VDD1, a second noise reduction signal end VDD2, a first power supply end VGL and a second power supply end VGH, an INPUT sub-circuit, an OUTPUT sub-circuit, a RESET sub-circuit, a noise reduction sub-circuit and a shutdown control sub-circuit, and comprises the following steps:
and when the XON function is started, the shutdown control sub-circuit provides a starting signal to the signal output end under the control of the first power supply end and the second power supply end so as to enable the thin film transistors connected with the corresponding row grid lines to be conducted.
The driving method of the shift register provided in the embodiment of the present invention is applied to the shift register provided in the first embodiment, and the implementation principle and the implementation effect are similar, which are not described herein again.
Specifically, the driving method of the shift register further includes:
in step S1, the input sub-circuit provides the signal of the signal input terminal to the pull-up node under the control of the signal input terminal.
And step S2, the output sub-circuit provides the clock signal of the clock signal end to the signal output end under the control of the pull-up node.
In step S3, the reset sub-circuit provides the signal of the first power source terminal to the pull-up node under the control of the reset signal terminal.
Step S4, the noise reduction sub-circuit provides the signal of the first power terminal to the pull-up node and the signal output terminal under the control of the first noise reduction signal terminal and/or the second noise reduction signal terminal.
In the display stage, the input signals of the first noise reduction signal end and the second noise reduction signal end are mutually inverse signals.
EXAMPLE III
Based on the inventive concept of the foregoing embodiments, an embodiment of the present invention further provides a gate driving circuit, fig. 8 is a schematic structural diagram of the gate driving circuit provided in the embodiment of the present invention, and fig. 9 is a timing diagram of operation of the gate driving circuit provided in the embodiment of the present invention, as shown in fig. 8 and fig. 9, the gate driving circuit provided in the embodiment of the present invention includes a plurality of cascaded shift registers.
As shown in fig. 8, the gate driving circuit according to the embodiment of the present invention includes: an initial signal terminal STV, a first clock terminal CLK1, and a second clock terminal CLK 2.
Specifically, a signal INPUT end INPUT of the first-stage shift register GOA (1) is connected to an initial signal end STV, a signal OUTPUT end OUTPUT of the nth-stage shift register GOA (N) is connected to a signal INPUT end INPUT of the (N +1) th-stage shift register GOA (N +1), a signal OUTPUT end OUTPUT of the (N +1) th-stage shift register GOA (N +1) is connected to a RESET signal end RESET of the (N) th-stage shift register GOA (N), and N is greater than or equal to 1.
The clock signal terminal CLK of the Nth shift register GOA (N) is connected to the first clock terminal CLK1, and the clock signal terminal CLK of the (N +1) th shift register GOA (N) is connected to the second clock terminal CLK 2.
Output (N) in fig. 9 is a signal output terminal of the nth stage shift register goa (N).
The shift register is provided in the first embodiment, and the implementation principle and the implementation effect are similar, which are not described herein again.
Example four
Based on the inventive concept of the above embodiments, an embodiment of the present invention further provides a display device, including a gate driving circuit.
The gate driving circuit is provided in the third embodiment, and the implementation principle and the implementation effect are similar, and are not described herein again.
The drawings of the embodiments of the invention only relate to the structures related to the embodiments of the invention, and other structures can refer to common designs.
Without conflict, features of embodiments of the present invention, that is, embodiments, may be combined with each other to arrive at new embodiments.
Although the embodiments of the present invention have been described above, the above description is only for the convenience of understanding the present invention, and is not intended to limit the present invention. It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.

Claims (9)

1. A shift register, comprising: a shift register unit and a shutdown control sub-circuit for outputting a gate driving signal, the shift register unit comprising: a signal output terminal;
the shutdown control sub-circuit is respectively connected with the signal output end, the first power supply end and the second power supply end, and is used for providing a starting signal to the signal output end under the control of the first power supply end and the second power supply end when the XON function is started, so that the thin film transistors connected with the corresponding row grid lines are all conducted;
the shutdown control sub-circuit comprises a first transistor and a first capacitor; the control electrode of the first transistor is connected with a first power supply end, the first electrode of the first transistor is connected with a signal output end, and the second electrode of the first transistor is connected with a second power supply end; the first end of the first capacitor is connected with a first power supply end, and the second end of the first capacitor is connected with a second power supply end; when the XON function is started, the signal at the first power supply terminal is pulled up to the XON signal at a high level, the first transistor is turned on, under the bootstrap action of the first capacitor, the voltage at the second terminal of the first capacitor is bootstrapped to the sum of the voltage of the XON signal and the voltage of the signal at the second power supply terminal, and the voltage of the output signal at the signal output terminal is equal to the sum of the voltage of the XON signal and the voltage of the signal at the second power supply terminal.
2. The shift register cell according to claim 1, wherein the shift register cell comprises: an input sub-circuit and an output sub-circuit;
the input sub-circuit is respectively connected with the signal input end and the pull-up node and is used for providing a signal of the signal input end to the pull-up node under the control of the signal input end;
and the output sub-circuit is respectively connected with the pull-up node, the clock signal end and the signal output end and is used for providing the clock signal of the clock signal end for the signal output end under the control of the pull-up node.
3. The shift register cell of claim 2, further comprising: a reset sub-circuit and a noise reduction sub-circuit;
the reset sub-circuit is respectively connected with the pull-up node, the reset signal end and the first power end and is used for providing a signal of the first power end to the pull-up node under the control of the reset signal end;
the noise reduction sub-circuit is respectively connected with the first noise reduction signal end, the second noise reduction signal end, the pull-up node, the first power end and the signal output end, and is used for providing signals of the first power end to the pull-up node and the signal output end under the control of the first noise reduction signal end and/or the second noise reduction signal end;
the input signals of the first noise reduction signal end and the second noise reduction signal end are opposite phase signals.
4. The shift register of claim 2, wherein the input sub-circuit comprises: a second transistor, the output sub-circuit including: a third transistor and a second capacitor;
the control electrode and the first electrode of the second transistor are connected with the signal input end, and the second electrode of the second transistor is connected with the pull-up node;
the control electrode of the third transistor is connected with the pull-up node, the first electrode of the third transistor is connected with the clock signal end, and the second electrode of the third transistor is connected with the signal output end;
and the first end of the second capacitor is connected with the pull-up node, and the second end of the second capacitor is connected with the signal output end.
5. The shift register of claim 3, wherein the reset subcircuit comprises: a fourth transistor, the noise reduction sub-circuit comprising: a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, and a sixteenth transistor;
a control electrode of the fourth transistor is connected with the reset signal end, a first electrode of the fourth transistor is connected with the pull-up node, and a second electrode of the fourth transistor is connected with the first power supply end;
the control electrode and the first electrode of the fifth transistor are connected with the first noise reduction signal end, and the second electrode of the fifth transistor is connected with the first electrode of the seventh transistor;
a control electrode of the sixth transistor is connected with a second electrode of the fifth transistor, a first electrode of the sixth transistor is connected with the first noise reduction signal end, and a second electrode of the sixth transistor is connected with the first pull-down node;
a control electrode of the seventh transistor is connected with the pull-up node, and a second electrode of the seventh transistor is connected with a first power supply end;
a control electrode of the eighth transistor is connected with the pull-up node, a first electrode of the eighth transistor is connected with the first pull-down node, and a second electrode of the eighth transistor is connected with the first power supply end;
a control electrode of the ninth transistor is connected with the first pull-down node, a first electrode of the ninth transistor is connected with the pull-up node, and a second electrode of the ninth transistor is connected with the first power supply end;
a control electrode of the tenth transistor is connected with the first pull-down node, a first electrode of the tenth transistor is connected with the signal output end, and a second electrode of the tenth transistor is connected with the first power supply end;
a control electrode and a first electrode of the eleventh transistor are connected with the second noise reduction signal end, and a second electrode of the eleventh transistor is connected with a first electrode of the thirteenth transistor;
a control electrode of the twelfth transistor is connected with a second electrode of the eleventh transistor, a first electrode of the twelfth transistor is connected with the second noise reduction signal end, and a second electrode of the twelfth transistor is connected with the second pull-down node;
a control electrode of the thirteenth transistor is connected with the pull-up node, and a second electrode of the thirteenth transistor is connected with the first power supply end;
a control electrode of the fourteenth transistor is connected with the pull-up node, a first electrode of the fourteenth transistor is connected with the second pull-down node, and a second electrode of the fourteenth transistor is connected with the first power supply end;
a control electrode of the fifteenth transistor is connected with the second pull-down node, a first electrode of the fifteenth transistor is connected with the pull-up node, and a second electrode of the fifteenth transistor is connected with the first power supply end;
and a control electrode of the sixteenth transistor is connected with the second pull-down node, a first electrode of the sixteenth transistor is connected with the signal output end, and a second electrode of the sixteenth transistor is connected with the first power supply end.
6. The shift register of claim 1, wherein the shutdown control subcircuit comprises: a first transistor and a first capacitor, the shift register unit including: an input sub-circuit, an output sub-circuit, a reset sub-circuit, and a noise reduction sub-circuit, the input sub-circuit comprising: a second transistor, the output sub-circuit including: a third transistor and a second capacitor, the reset sub-circuit including: a fourth transistor, the noise reduction sub-circuit comprising: a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, and a sixteenth transistor;
the control electrode of the first transistor is connected with a first power supply end, the first electrode of the first transistor is connected with a signal output end, and the second electrode of the first transistor is connected with a second power supply end;
the first end of the first capacitor is connected with a first power supply end, and the second end of the first capacitor is connected with a second power supply end;
the control electrode and the first electrode of the second transistor are connected with the signal input end, and the second electrode of the second transistor is connected with the pull-up node;
the control electrode of the third transistor is connected with the pull-up node, the first electrode of the third transistor is connected with the clock signal end, and the second electrode of the third transistor is connected with the signal output end;
the first end of the second capacitor is connected with the pull-up node, and the second end of the second capacitor is connected with the signal output end;
a control electrode of the fourth transistor is connected with the reset signal end, a first electrode of the fourth transistor is connected with the pull-up node, and a second electrode of the fourth transistor is connected with the first power supply end;
the control electrode and the first electrode of the fifth transistor are connected with the first noise reduction signal end, and the second electrode of the fifth transistor is connected with the first electrode of the seventh transistor;
a control electrode of the sixth transistor is connected with a second electrode of the fifth transistor, a first electrode of the sixth transistor is connected with the first noise reduction signal end, and a second electrode of the sixth transistor is connected with the first pull-down node;
a control electrode of the seventh transistor is connected with the pull-up node, and a second electrode of the seventh transistor is connected with a first power supply end;
a control electrode of the eighth transistor is connected with the pull-up node, a first electrode of the eighth transistor is connected with the first pull-down node, and a second electrode of the eighth transistor is connected with the first power supply end;
a control electrode of the ninth transistor is connected with the first pull-down node, a first electrode of the ninth transistor is connected with the pull-up node, and a second electrode of the ninth transistor is connected with the first power supply end;
a control electrode of the tenth transistor is connected with the first pull-down node, a first electrode of the tenth transistor is connected with the signal output end, and a second electrode of the tenth transistor is connected with the first power supply end;
a control electrode and a first electrode of the eleventh transistor are connected with the second noise reduction signal end, and a second electrode of the eleventh transistor is connected with a first electrode of the thirteenth transistor;
a control electrode of the twelfth transistor is connected with a second electrode of the eleventh transistor, a first electrode of the twelfth transistor is connected with the second noise reduction signal end, and a second electrode of the twelfth transistor is connected with the second pull-down node;
a control electrode of the thirteenth transistor is connected with the pull-up node, and a second electrode of the thirteenth transistor is connected with the first power supply end;
a control electrode of the fourteenth transistor is connected with the pull-up node, a first electrode of the fourteenth transistor is connected with the second pull-down node, and a second electrode of the fourteenth transistor is connected with the first power supply end;
a control electrode of the fifteenth transistor is connected with the second pull-down node, a first electrode of the fifteenth transistor is connected with the pull-up node, and a second electrode of the fifteenth transistor is connected with the first power supply end;
and a control electrode of the sixteenth transistor is connected with the second pull-down node, a first electrode of the sixteenth transistor is connected with the signal output end, and a second electrode of the sixteenth transistor is connected with the first power supply end.
7. A gate drive circuit, comprising: a plurality of cascaded shift registers according to any one of claims 1 to 6;
the signal input end of the first-stage shift register is connected with the initial signal end, the signal output end of the Nth-stage shift register is connected with the signal input end of the (N +1) th-stage shift register, the signal output end of the (N +1) th-stage shift register is connected with the reset signal end of the Nth-stage shift register, and N is larger than or equal to 1.
8. A display device, comprising: a gate drive circuit as claimed in claim 7.
9. A method for driving a shift register, which is applied to the shift register according to any one of claims 1 to 6, comprising:
when the XON function is started, the shutdown control sub-circuit provides a starting signal to the signal output end under the control of the first power supply end and the second power supply end, so that the thin film transistors connected with the corresponding row grid lines are all conducted;
the shutdown control sub-circuit comprises a first transistor and a first capacitor; the control electrode of the first transistor is connected with a first power supply end, the first electrode of the first transistor is connected with a signal output end, and the second electrode of the first transistor is connected with a second power supply end; the first end of the first capacitor is connected with a first power supply end, and the second end of the first capacitor is connected with a second power supply end; when the XON function is started, the signal at the first power supply terminal is pulled up to the XON signal at a high level, the first transistor is turned on, under the bootstrap action of the first capacitor, the voltage at the second terminal of the first capacitor is bootstrapped to the sum of the voltage of the XON signal and the voltage of the signal at the second power supply terminal, and the voltage of the output signal at the signal output terminal is equal to the sum of the voltage of the XON signal and the voltage of the signal at the second power supply terminal.
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CN107967889A (en) * 2018-01-02 2018-04-27 京东方科技集团股份有限公司 Shift register cell, gate driving circuit and control method

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