CN110648621A

CN110648621A - Shift register and driving method thereof, grid driving circuit and display device

Info

Publication number: CN110648621A
Application number: CN201911047794.6A
Authority: CN
Inventors: 邵林飞; 陶健; 孟小明; 程律; 章善财; 谢王宝; 陈彤; 刘飞; 王发永; 何涌杰; 许超; 张蕾
Original assignee: BOE Technology Group Co Ltd; Hefei BOE Optoelectronics Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Hefei BOE Optoelectronics Technology Co Ltd
Priority date: 2019-10-30
Filing date: 2019-10-30
Publication date: 2020-01-03
Anticipated expiration: 2039-10-30
Also published as: CN110648621B

Abstract

A shift register, comprising: the circuit comprises an input sub-circuit, an output sub-circuit, a pull-down node control sub-circuit and a first reset sub-circuit; the input sub-circuit is used for providing a signal of a first voltage signal end to the pull-up node under the control of the signal input end; the output sub-circuit is used for providing a signal of the clock input end to the signal output end under the control of the pull-up node; the first reset sub-circuit is used for providing signals of a second voltage signal end to the pull-up node and the signal output end under the control of the pull-down node; and the pull-down node control subcircuit is used for providing the signal of the first voltage signal end or the second voltage signal end to the pull-down node under the control of the control end and the signal input end.

Description

Shift register and driving method thereof, grid driving circuit and display device

Technical Field

The present disclosure relates to display driving technologies, and in particular, to a shift register, a driving method thereof, a gate driving circuit and a display device.

Background

With the development of display technology, high resolution and narrow frame display panels are becoming more and more developed, and therefore, a Gate Driver on Array (GOA) technology has emerged. The GOA technology directly integrates a gate driving circuit of the display panel on the array substrate to replace an external driving chip, and has the advantages of low cost, few processes, high productivity and the like.

Most of the current GOA circuits are driver circuits composed of shift registers based on 7T1C (i.e. seven transistors and one capacitor). However, in the shift register having the 7T1C structure, there is a problem that a high-level signal and a low-level signal are simultaneously output to the pull-down node from the input stage to the output stage to form a dc path from a high voltage to a low voltage, so that the pull-down node cannot be sufficiently pulled down to the low level, and an output characteristic curve is distorted.

Disclosure of Invention

The application provides a shift register, a driving method thereof, a grid driving circuit and a display device, and aims to solve the problem that a high-level signal and a low-level signal in the existing structure are simultaneously output to a pull-down node.

The application provides a shift register, including: the circuit comprises an input sub-circuit, an output sub-circuit, a pull-down node control sub-circuit and a first reset sub-circuit; the input sub-circuit is respectively connected with the signal input end, the first voltage signal end and the pull-up node and is used for providing a signal of the first voltage signal end to the pull-up node under the control of the signal input end; the output sub-circuit is respectively connected with the pull-up node, the clock input end and the signal output end and is used for providing a signal of the clock input end for the signal output end under the control of the pull-up node; the first reset sub-circuit is respectively connected with the pull-up node, the pull-down node, the signal output end and the second voltage signal end and is used for providing signals of the second voltage signal end for the pull-up node and the signal output end under the control of the pull-down node; and the pull-down node control sub-circuit is respectively connected with the first voltage signal end, the control end, the signal input end, the pull-down node and the second voltage signal end and is used for providing signals of the first voltage signal end or the second voltage signal end to the pull-down node under the control of the control end and the signal input end.

The present application also provides a gate driving circuit, including: the plurality of shift registers are cascaded, wherein the control end of the nth stage shift register is connected with the signal output end of the (n +3) th stage shift register.

The present application also provides a display device, including: the gate driving circuit as described above.

The present application further provides a driving method of a shift register, which is applied to the shift register described above, and the driving method includes: the input sub-circuit provides a signal of a first voltage signal end to a pull-up node under the control of the signal input end, and the pull-down node control sub-circuit provides a signal of a second voltage signal end to a pull-down node under the control of the control end and the signal input end; the output sub-circuit provides a signal of the clock input end to the signal output end under the control of the pull-up node; the pull-down node control sub-circuit provides a signal of a first voltage signal end to a pull-down node under the control of the control end and the signal input end; the first reset sub-circuit provides signals of the second voltage signal end to the pull-up node and the signal output end under the control of the pull-down node.

This application provides the signal of first voltage signal end or second voltage signal end to the pull-down node through pull-down node control subcircuit under control end and signal input part's control, can avoid high level signal and low level signal to export the pull-down node simultaneously and form the problem of the direct current route from high-voltage to low-voltage.

Additional features and advantages of the application will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by the practice of the application. Other advantages of the application may be realized and attained by the instrumentalities and combinations particularly pointed out in the specification, claims, and drawings.

Drawings

The accompanying drawings are included to provide an understanding of the present disclosure and are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the examples serve to explain the principles of the disclosure and not to limit the disclosure. The shapes and sizes of the various elements in the drawings are not to scale and are merely intended to illustrate the invention.

FIG. 1 is a circuit diagram of a shift register according to the related art;

FIG. 2 is a timing diagram illustrating operation of the shift register shown in FIG. 1;

FIG. 3 is a schematic diagram of a shift register according to an embodiment of the present application;

FIG. 4 is an equivalent circuit diagram of an input sub-circuit, an output sub-circuit and a first reset sub-circuit according to an embodiment of the present disclosure;

FIG. 5 is an equivalent circuit diagram of a pull-down node control sub-circuit according to an embodiment of the present application;

FIG. 6 is a diagram illustrating another structure of a shift register according to an embodiment of the present application;

fig. 7 is an equivalent circuit diagram of a second reset sub-circuit according to an embodiment of the present application;

FIG. 8 is an equivalent circuit diagram of a shift register according to an embodiment of the present application;

FIG. 9 is a timing diagram illustrating an operation of a shift register according to an embodiment of the present application;

FIG. 10 is a flowchart illustrating a method for driving a shift register according to an embodiment of the present disclosure;

fig. 11 is a schematic diagram of a gate driving circuit according to an embodiment of the present application.

Description of reference numerals:

INPUT-signal INPUT; OUTPUT-signal OUTPUT terminal; CLK-clock input; Reset-Reset signal terminal; FW — first reference voltage terminal; BW-second reference voltage terminal; GCH-touch signal terminal; VGH-first voltage signal terminal; VGL-a second voltage signal terminal; IN-control end; t _ RST-reset terminal; PU-pull-up node; PD-a pull-down node; c1 — first capacitance; c2 — second capacitance; m1 — first transistor; m2 — second transistor; m3 — third transistor; m4 — fourth transistor; m5 — fifth transistor; m6 — sixth transistor; m7-seventh transistor; m8 — eighth transistor; m9-ninth transistor.

Detailed Description

The present application describes embodiments, but the description is illustrative rather than limiting and it will be apparent to those of ordinary skill in the art that many more embodiments and implementations are possible within the scope of the embodiments described herein. Although many possible combinations of features are shown in the drawings and discussed in the detailed description, many other combinations of the disclosed features are possible. Any feature or element of any embodiment may be used in combination with or instead of any other feature or element in any other embodiment, unless expressly limited otherwise.

The present application includes and contemplates combinations of features and elements known to those of ordinary skill in the art. The embodiments, features and elements disclosed in this application may also be combined with any conventional features or elements to form a unique inventive concept as defined by the claims. Any feature or element of any embodiment may also be combined with features or elements from other inventive aspects to form yet another unique inventive aspect, as defined by the claims. Thus, it should be understood that any of the features shown and/or discussed in this application may be implemented alone or in any suitable combination. Accordingly, the embodiments are not limited except as by the appended claims and their equivalents. Furthermore, various modifications and changes may be made within the scope of the appended claims.

Further, in describing representative embodiments, the specification may have presented the method and/or process as a particular sequence of steps. However, to the extent that the method or process does not rely on the particular order of steps set forth herein, the method or process should not be limited to the particular sequence of steps described. Other orders of steps are possible as will be understood by those of ordinary skill in the art. Therefore, the particular order of the steps set forth in the specification should not be construed as limitations on the claims. Further, the claims directed to the method and/or process should not be limited to the performance of their steps in the order written, and one skilled in the art can readily appreciate that the sequences may be varied and still remain within the spirit and scope of the embodiments of the present application.

Unless otherwise defined, technical or scientific terms used in the disclosure of the embodiments of the present application should have the ordinary meaning as understood by those having ordinary skill in the art to which the present invention belongs. The use of "first," "second," and similar terms in the embodiments of the present application do not denote any order, quantity, or importance, but rather the terms are used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

It will be appreciated by those skilled in the art that the transistors employed in all embodiments of the present application may be thin film transistors or field effect transistors or other devices having the same characteristics. Illustratively, the thin film transistor used in the embodiment of the present application may be an oxide semiconductor transistor. Since the source and drain of the transistor used herein are symmetrical, the source and drain may be interchanged. In the embodiment of the present application, in order to distinguish two electrodes of a transistor except for a gate, one of the electrodes is referred to as a first electrode, the other electrode is referred to as a second electrode, the first electrode may be a source or a drain, the second electrode may be a drain or a source, and the gate of the transistor is referred to as a control electrode. Meanwhile, the thin film transistor or the field effect transistor can be an N-type transistor or a P-type transistor.

FIG. 1 is a circuit diagram of a shift register according to the related art; fig. 2 is a timing diagram illustrating the operation of the shift register shown in fig. 1. As shown in fig. 1, the shift register includes: seven transistors (a first transistor M1 to a seventh transistor M7) and one capacitor C1. A control electrode of the first transistor M1 is connected to the signal INPUT terminal INPUT, a first electrode of the first transistor M1 is connected to the first reference voltage terminal FW, and a second electrode of the first transistor M1 is connected to the pull-up node PU. A control electrode of the second transistor M2 is connected to the pull-up node PU, a first electrode of the second transistor M2 is connected to the clock input terminal CLK, and a second electrode of the second transistor M2 is connected to the signal OUTPUT terminal OUTPUT. A control electrode of the third transistor M3 is connected to the pull-down node PD, a first electrode of the third transistor M3 is connected to the pull-up node PU, and a second electrode of the third transistor M3 is connected to a power source terminal (ground terminal). A control electrode of the fourth transistor M4 is connected to the pull-down node PD, a first electrode of the fourth transistor M4 is connected to the signal OUTPUT terminal OUTPUT, and a second electrode of the fourth transistor M4 is connected to the power source terminal. A control electrode and a first electrode of the fifth transistor M5 are both connected to the touch signal terminal GCH, and a second electrode of the fifth transistor M5 is connected to the pull-down node PD. A control electrode of the sixth transistor M6 is connected to the pull-up node PU, a first electrode of the sixth transistor M6 is connected to the pull-down node PD, and a second electrode of the sixth transistor M6 is connected to the power source terminal. A control electrode of the seventh transistor M7 is connected to the Reset signal terminal Reset, a first electrode of the seventh transistor M7 is connected to the pull-up node PU, and a second electrode of the seventh transistor M7 is connected to the second reference voltage terminal BW. A first electrode of the capacitor C1 is connected to the pull-up node PU, and a second electrode is connected to the signal OUTPUT terminal OUTPUT. The touch signal terminal GCH can provide a high level signal during the display phase.

As shown in fig. 2, in the first phase T1, i.e., the INPUT phase, the INPUT signal at the signal INPUT terminal INPUT is at a high level, the first transistor M1 is turned on, the potential of the pull-up node PU is pulled up by the INPUT signal at the first reference voltage terminal FW, and the capacitor C1 is charged. Since the potential of the pull-up node PU is pulled high, the second transistor M2 and the sixth transistor M6 are turned on. Since the input signal at the clock input terminal CLK is at a low level, the signal OUTPUT terminal OUTPUT OUTPUTs a low level signal. The sixth transistor M6 is turned on, providing a low signal to the pull-down node PD. The input signal of the Reset signal terminal Reset is low, and the seventh transistor M7 is turned off, so that the pull-up node PU is guaranteed to be high. The input signal of the touch signal terminal GCH is at a high level, and the fifth transistor M5 is turned on.

In the second phase T2, i.e., the output phase, the INPUT signal at the signal INPUT terminal INPUT is at a low level, the first transistor M1 is turned off, the pull-up node PU continues to maintain at a high level due to the function of the capacitor C1, and the high level of the pull-up node PU turns on the second transistor M2. The input signal of the clock input terminal CLK becomes a high level, the potential of the pull-up node PU continues to be pulled up due to the bootstrap effect of the transistor, the voltage of the pull-up node PU is amplified, and the signal OUTPUT terminal OUTPUT normally OUTPUTs a gate driving signal of the high level. The increase of the voltage of the pull-up node PU improves the charging capability of the second transistor M2, ensuring pixel charging.

In the third stage T3, i.e., the reset stage, the INPUT signals at the signal INPUT terminal INPUT and the clock INPUT terminal CLK are both low, and the first transistor M1 and the second transistor M2 are turned off. The input signal at the Reset signal terminal Reset is at a high level, the seventh transistor M7 is turned on, the potential of the pull-up node PU is pulled low, and the sixth transistor M6 is turned off. The input signal of the touch signal terminal GCH is at a high level, the fifth transistor M5 is turned on, the potential of the pull-down node PD is pulled high, and the third transistor M3 and the fourth transistor M4 are turned on, so as to pull the pull-up node PU and the signal OUTPUT terminal OUTPUT low.

In the fourth stage T4, i.e., the sustain stage, the INPUT signals of the signal INPUT terminal INPUT and the Reset signal terminal Reset are both at low level, the INPUT signal of the touch signal terminal GCH is at high level, the fifth transistor M5 is turned on, the pull-down node PD is always at high level, the third transistor M3 and the fourth transistor M4 are turned on, and the pull-up node PU and the signal OUTPUT terminal OUTPUT are both pulled down.

Wherein the shift register repeats the fourth stage until the next frame signal arrives.

In the conventional circuit of the 7T1C shift register, from the input stage T1 to the output stage T2, the fifth transistor M5 and the sixth transistor M6 are turned on simultaneously, and the high level signal and the low level signal are output to the pull-down node PD simultaneously, so that the dc voltage GCH has a dc path to the low voltage, and the pull-down node PD cannot be pulled down to the low level completely, thereby affecting the output characteristic curve. In addition, the reset of the signal OUTPUT terminal OUTPUT is controlled only by the pull-down node PD, and once a problem occurs in a certain frame, the next frame is affected, which results in abnormal display of the screen.

In order to solve the problem that the fifth transistor M5 and the sixth transistor M6 are turned on simultaneously and output a high level signal and a low level signal to a pull-down node simultaneously in the conventional structure, embodiments of the present application provide a shift register, a driving method thereof, a gate driving circuit, and a display device.

First embodiment

Fig. 3 is a schematic structural diagram of a shift register according to an embodiment of the present application. As shown in fig. 3, the shift register provided in this embodiment includes: the circuit comprises an input sub-circuit, an output sub-circuit, a pull-down node control sub-circuit and a first reset sub-circuit.

The INPUT sub-circuit is respectively connected with the signal INPUT end INPUT, the first voltage signal end VGH and the pull-up node PU, and is used for providing a signal of the first voltage signal end VGH to the pull-up node PU under the control of the signal INPUT end INPUT; the OUTPUT sub-circuit is respectively connected with the pull-up node PU, the clock input end CLK and the signal OUTPUT end OUTPUT and is used for providing a signal of the clock input end CLK to the signal OUTPUT end OUTPUT under the control of the pull-up node PU; the first reset sub-circuit is respectively connected with the pull-up node PU, the pull-down node PD, the signal OUTPUT end OUTPUT and the second voltage signal end VGL, and is used for providing signals of the second voltage signal end VGL for the pull-up node PU and the signal OUTPUT end OUTPUT under the control of the pull-down node PD; and the pull-down node control sub-circuit is respectively connected with the first voltage signal end VGH, the control end IN, the signal INPUT end INPUT, the pull-down node PD and the second voltage signal end VGL, and is used for providing signals of the first voltage signal end VGH or the second voltage signal end VGL to the pull-down node PD under the control of the control end IN and the signal INPUT end INPUT.

In an exemplary embodiment, the pull-down node control sub-circuit may include: a first control sub-circuit and a second control sub-circuit; the first control sub-circuit is respectively connected with the first voltage signal terminal VGH, the control terminal IN and the pull-down node PD, and is used for providing a signal of the first voltage signal terminal VGH to the pull-down node PD under the control of the control terminal IN, and is turned off when the second control sub-circuit provides a signal of the second voltage signal terminal VGL to the pull-down node PD; the second control sub-circuit is respectively connected to the signal INPUT terminal INPUT, the second voltage signal terminal VGL and the pull-down node PD, and is configured to provide a signal of the second voltage signal terminal VGL to the pull-down node PD under the control of the signal INPUT terminal INPUT, and is turned off when the first control sub-circuit provides a signal of the first voltage signal terminal VGH to the pull-down node PD.

In this embodiment, the INPUT signal of the signal INPUT terminal INPUT is a pulse signal, the first voltage signal terminal VGH can continuously provide a high level signal, and the second voltage signal terminal VGL can continuously provide a low level signal.

In this embodiment, the pull-down node control sub-circuit outputs one of the high level signal and the low level signal to the pull-down node under the control of the control terminal and the signal input terminal, so that the high level signal and the low level signal can be prevented from being output to the pull-down node at the same time, and the condition that the pull-down node cannot be fully pulled down is avoided.

Fig. 4 is an equivalent circuit of the input sub-circuit, the output sub-circuit and the first reset sub-circuit according to an embodiment of the present disclosure. As shown in fig. 4, the input sub-circuit in the shift register provided in this embodiment includes: a first transistor M1, a control electrode of the first transistor M1 is connected to the signal INPUT terminal INPUT, a first electrode of the first transistor M1 is connected to the first voltage signal terminal VGH, and a second electrode of the first transistor M1 is connected to the pull-up node PU.

As shown in fig. 4, the output sub-circuit in the shift register provided in this embodiment includes: a second transistor M2 and a first capacitor C1; a control electrode of the second transistor M2 is connected to the pull-up node PU, a first electrode of the second transistor M2 is connected to the clock input terminal CLK, and a second electrode of the second transistor M2 is connected to the signal OUTPUT terminal OUTPUT; a first electrode of the first capacitor C1 is connected to the pull-up node PU, and a second electrode of the first capacitor C1 is connected to the signal OUTPUT terminal OUTPUT.

As shown in fig. 4, the first reset sub-circuit in the shift register provided in this embodiment includes: a third transistor M3 and a fourth transistor M4; a control electrode of the third transistor M3 is connected to the pull-down node PD, a first electrode of the third transistor M3 is connected to the pull-up node PU, and a second electrode of the third transistor M3 is connected to the second voltage signal terminal VGL; a control electrode of the fourth transistor M4 is connected to the pull-down node PD, a first electrode of the fourth transistor M4 is connected to the signal OUTPUT terminal OUTPUT, and a second electrode of the fourth transistor M4 is connected to the second voltage signal terminal VGL.

In the present embodiment, an exemplary structure of the input sub-circuit, the output sub-circuit, and the first reset sub-circuit is specifically shown in fig. 4. Those skilled in the art will readily appreciate that the implementation of the input sub-circuit, the output sub-circuit and the first reset sub-circuit is not limited thereto as long as the functions thereof can be implemented.

Fig. 5 is an equivalent circuit diagram of a pull-down node control sub-circuit according to an embodiment of the present application. As shown in fig. 5, the pull-down node control sub-circuit in the shift register provided in this embodiment includes: the first control sub-circuit, the second control sub-circuit and the second capacitor C2. Wherein, the first control sub-circuit includes: a fifth transistor M5; a control electrode of the fifth transistor M5 is connected to the control terminal IN, a first electrode of the fifth transistor M5 is connected to the first voltage signal terminal VGH, and a second electrode of the fifth transistor M5 is connected to the pull-down node PD. A second control sub-circuit comprising: a sixth transistor M6; a control electrode of the sixth transistor M6 is connected to the signal INPUT terminal INPUT, a first electrode of the sixth transistor M6 is connected to the pull-down node PD, and a second electrode of the sixth transistor M6 is connected to the second voltage signal terminal VGL. A first electrode of the second capacitor C2 is connected to the pull-down node PD, and a second electrode of the second capacitor C2 is connected to the second voltage signal terminal VGL.

Wherein, when the fifth transistor M5 is turned on and the pull-down node PD provides the signal of the first voltage signal terminal VGH, the sixth transistor M6 is turned off; when the sixth transistor M6 is turned on and the signal of the second voltage signal terminal VGL is supplied to the pull-down node PD, the fifth transistor M5 is turned off.

The second capacitor C2 is used for charging according to the signal provided by the fifth transistor M5 or the sixth transistor M6 to the pull-down node PD, or discharging according to the signal provided by the fifth transistor M5 or the sixth transistor M6 to the pull-down node PD, and maintains the level state of the pull-down node PD after charging or discharging. The fifth transistor M5 is turned on, and the pull-down node PD provides a high-level signal, so that the second capacitor C2 is charged; the sixth transistor M6 is turned on to provide a low signal to the pull-down node PD, and the second capacitor C2 discharges.

In this embodiment, an exemplary structure of the pull-down node control sub-circuit is specifically shown in fig. 5. It is easily understood by those skilled in the art that the implementation of the pull-down node control sub-circuit is not limited thereto as long as the function thereof can be achieved.

Fig. 6 is another structural diagram of a shift register according to an embodiment of the present application. Compared to the shift register shown in fig. 3, as shown in fig. 6, the shift register of the present embodiment further includes: a second reset sub-circuit and a ninth transistor M9.

A control electrode of the ninth transistor M9 is connected to the pull-down node PD, a first electrode of the ninth transistor M9 is connected to the pull-up node PU, and a second electrode of the ninth transistor M9 is connected to the signal OUTPUT terminal OUTPUT. In this embodiment, the ninth transistor M9 is provided, so that two ends of the first capacitor C1 in the output sub-circuit can be shorted at the noise release stage, thereby playing a role in resisting interference.

The second reset sub-circuit is respectively connected to the reset terminal T _ RST, the pull-up node PU, the signal OUTPUT terminal OUTPUT and the second voltage signal terminal VGL, and is configured to provide a signal of the second voltage signal terminal VGL to the pull-up node PU and the signal OUTPUT terminal OUTPUT in the empty window period under the control of the reset terminal T _ RST.

In this embodiment, the reset signal of the blank window time period is provided by adding the reset terminal T _ RST, and the pull-up node PU and the signal OUTPUT terminal OUTPUT can be kept at a low level state in the blank window time period, so that the problems of drift of transistor characteristics caused by bias voltage in a high-temperature and high-humidity environment, poor tail end lines caused by charge accumulation of the pull-up node PU, and the like are avoided, and the display quality is further improved.

Fig. 7 is an equivalent circuit diagram of a second reset sub-circuit according to an embodiment of the present application. As shown in fig. 7, the second reset sub-circuit in the shift register provided in this embodiment includes: a seventh transistor M7 and an eighth transistor M8; a control electrode of the seventh transistor M7 is connected to the reset terminal T _ RST, a first electrode of the seventh transistor M7 is connected to the pull-up node PU, and a second electrode of the seventh transistor M7 is connected to the second voltage signal terminal VGL; a control electrode of the eighth transistor M8 is connected to the reset terminal T _ RST, a first electrode of the eighth transistor M8 is connected to the signal OUTPUT terminal OUTPUT, and a second electrode of the eighth transistor M8 is connected to the second voltage signal terminal VGL.

In the present embodiment, an exemplary structure of the second reset sub-circuit is specifically shown in fig. 7. Those skilled in the art will readily appreciate that the implementation of the second reset sub-circuit is not limited thereto as long as its function can be achieved.

Fig. 8 is an equivalent circuit diagram of a shift register according to an embodiment of the present application. As shown in fig. 8, the shift register provided in this embodiment includes: an input sub-circuit, an output sub-circuit, a pull-down node control sub-circuit, a first reset sub-circuit, a second reset sub-circuit, and a ninth transistor M9. Wherein, input sub-circuit includes: a first transistor M1; an output sub-circuit comprising: a second transistor M2 and a first capacitor C1; a pull-down node control sub-circuit comprising: a fifth transistor M5, a sixth transistor M6, and a second capacitor C2; a first reset sub-circuit comprising: a third transistor M3 and a fourth transistor M4; a second reset sub-circuit comprising: a seventh transistor M7 and an eighth transistor M8.

A control electrode of the first transistor M1 is connected to the signal INPUT terminal INPUT, a first electrode of the first transistor M1 is connected to the first voltage signal terminal VGH, and a second electrode of the first transistor M1 is connected to the pull-up node PU; a control electrode of the second transistor M2 is connected to the pull-up node PU, a first electrode of the second transistor M2 is connected to the clock input terminal CLK, and a second electrode of the second transistor M2 is connected to the signal OUTPUT terminal OUTPUT; a control electrode of the third transistor M3 is connected to the pull-down node PD, a first electrode of the third transistor M3 is connected to the pull-up node PU, and a second electrode of the third transistor M3 is connected to the second voltage signal terminal VGL; a control electrode of the fourth transistor M4 is connected to the pull-down node PD, a first electrode of the fourth transistor M4 is connected to the signal OUTPUT terminal OUTPUT, and a second electrode of the fourth transistor M4 is connected to the second voltage signal terminal VGL; a control electrode of the fifth transistor M5 is connected to the control terminal IN, a first electrode of the fifth transistor M5 is connected to the first voltage signal terminal VGH, and a second electrode of the fifth transistor M5 is connected to the pull-down node PD; a control electrode of the sixth transistor M6 is connected to the signal INPUT terminal INPUT, a first electrode of the sixth transistor M6 is connected to the pull-down node PD, and a second electrode of the sixth transistor M6 is connected to the second voltage signal terminal VGL; a control electrode of the seventh transistor M7 is connected to the reset terminal T _ RST, a first electrode of the seventh transistor M7 is connected to the pull-up node PU, and a second electrode of the seventh transistor M7 is connected to the second voltage signal terminal VGL; a control electrode of the eighth transistor M8 is connected to the reset terminal T _ RST, a first electrode of the eighth transistor M8 is connected to the signal OUTPUT terminal OUTPUT, and a second electrode of the eighth transistor M8 is connected to the second voltage signal terminal VGL; a control electrode of the ninth transistor M9 is connected to the pull-down node PD, a first electrode of the ninth transistor M9 is connected to the pull-up node PU, and a second electrode of the ninth transistor M9 is connected to the signal OUTPUT terminal OUTPUT; a first electrode of the first capacitor C1 is connected to the pull-up node PU, and a second electrode of the first capacitor C1 is connected to the signal OUTPUT terminal OUTPUT; a first electrode of the second capacitor C2 is connected to the pull-down node PD, and a second electrode of the second capacitor C2 is connected to the second voltage signal terminal VGL.

In the embodiment, the transistors M1 to M9 may be both N-type thin film transistors or P-type thin film transistors, so that the process flow can be unified, the process procedures can be reduced, and the yield of the product can be improved. In addition, in consideration of the fact that the low-temperature polysilicon thin film transistor has a small leakage current, all transistors are preferably low-temperature polysilicon thin film transistors in the embodiments of the present application, and the thin film transistor may specifically be a thin film transistor with a bottom gate structure or a thin film transistor with a top gate structure, as long as the switching function can be achieved.

The technical solution of the embodiment of the present application is further described below by the working process of the shift register.

Fig. 9 is a timing diagram of an operation of a shift register according to an embodiment of the present application. As shown IN fig. 8 and 9, the shift register of the embodiment of the present application includes 9 transistor units (M1 to M9), 2 capacitor units (C1 and C2), 4 signal INPUT terminals (INPUT, T _ RST, CLK, IN), 1 signal OUTPUT terminal (OUTPUT), and 2 power supply terminals (VGH, VGL). The first voltage signal terminal VGH continuously provides a high level signal, and the second voltage signal terminal VGL continuously provides a low level signal.

The working process of the shift register provided by the embodiment includes:

in the first stage S1, i.e., the INPUT stage, the INPUT signal at the INPUT signal terminal INPUT is at a high level, and the first transistor M1 and the sixth transistor M6 are turned on. The first transistor M1 is turned on, so that the potential of the pull-up node PU is pulled high by the input signal of the first voltage signal terminal VGH, and the first capacitor C1 is charged, thereby ensuring that the first capacitor C1 is charged to saturation. At this time, the second transistor M2 is turned on, and the signal OUTPUT terminal OUTPUT OUTPUTs a low level signal since the clock input terminal CLK inputs a low level signal.

IN this stage, the input signal at the control terminal IN is at a low level, the fifth transistor M5 is turned off, and the sixth transistor M6 is turned on, so that the charge of the second capacitor C2 is released through the sixth transistor M6, and the potential of the pull-down node PD is pulled down to a low level of the second voltage signal terminal VGL. The control terminal in (n) of the nth stage shift register is connected to the signal OUTPUT terminal OUTPUT (n +3) of the (n +3) th stage shift register.

In this stage, the pull-down node PD is at a low level, and the third transistor M3, the fourth transistor M4, and the ninth transistor M9 are turned off. The third transistor M3 is turned off and will not pull down the pull-up node PU to the low level of the second voltage signal terminal VGL; the fourth transistor M4 is turned off and will not pull down the signal OUTPUT terminal OUTPUT to the low level of the second voltage signal terminal VGL.

In this stage, the input signal of the reset terminal T _ RST is at a low level, the seventh transistor M7 and the eighth transistor M8 are turned off, and the pull-up node PU and the signal OUTPUT terminal OUTPUT are not pulled down to the low level of the second voltage signal terminal VGL.

In the second stage S2, i.e., the output stage, the INPUT signal at the signal INPUT terminal INPUT is low, and the first transistor M1 and the sixth transistor M6 are turned off. The pull-up node PU continues to maintain a high level due to the holding effect of the first capacitor C1, and the high level of the pull-up node PU makes the second transistor M2 continuously turned on. The input signal of the clock input terminal CLK becomes a high level, the potential of the pull-up node PU continues to be pulled up due to the bootstrap effect of the transistor, the voltage of the pull-up node PU is amplified, and the signal OUTPUT terminal OUTPUT normally OUTPUTs a gate driving signal of the high level. The increase of the voltage of the pull-up node PU improves the charging capability of the second transistor M2, ensuring pixel charging.

IN this stage, the input signal of the control terminal IN is at a low level, and the fifth transistor M5 is turned off. Due to the holding effect of the second capacitor C2, the pull-down node PD is still in a low state, and the third transistor M3, the fourth transistor M4 and the ninth transistor M9 are turned off. The third transistor M3 and the fourth transistor M4 are turned off, and do not pull down the pull-up node PU and the signal OUTPUT terminal OUTPUT to the low potential of the second voltage signal terminal VGL.

In this stage, the voltages of the pull-up node PU and the pull-down node PD can be kept stable, so that the normal OUTPUT of the signal OUTPUT terminal OUTPUT is ensured.

IN the third stage S3, i.e., the first reset stage, the INPUT signal at the signal INPUT terminal INPUT is at a low level, the INPUT signal at the control terminal IN is at a low level, and the first transistor M1, the sixth transistor M6 and the fifth transistor M5 are turned off. The first capacitor C1 and the second capacitor C2 remain at the voltage of the second stage S2, and the pull-up node PU and the pull-down node PD keep the state of the second stage S2 unchanged.

In this stage, the input signal at the clock input terminal CLK becomes low level, and the second transistor M2 performs noise reduction on the signal OUTPUT terminal OUTPUT, so that the signal OUTPUT terminal OUTPUT is pulled to low level.

In this stage, the input signal of the reset terminal T _ RST is at a low level, the seventh transistor M2 and the eighth transistor M8 are turned off, and the pull-up node PU and the signal OUTPUT terminal OUTPUT are not pulled down to the low level of the second voltage signal terminal VGL.

In the fourth stage S4, which is the second reset stage, the INPUT signal at the signal INPUT terminal INPUT is at a low level, and the first transistor M1 and the sixth transistor M6 are turned off. The input signal at the control terminal IN becomes a high level, the fifth transistor M5 is turned on, the second capacitor C2 can be charged by the first voltage signal terminal VGH, and the pull-down node PD is pulled up to the high level of the first voltage signal terminal VGH. At this time, the third transistor M3, the fourth transistor M4, and the ninth transistor M9 are turned on. The third transistor M3 is turned on to pull down the pull-up node PU to the low level of the second voltage signal terminal VGL, and the fourth transistor M4 is turned on to pull down the signal OUTPUT terminal OUTPUT to the low level of the second voltage signal terminal VGL to discharge the first capacitor C1. At this time, the second transistor M2 is turned off. The ninth transistor M9 is turned on, so that the pull-up node PU and the signal OUTPUT terminal OUTPUT can be shorted, noise reduction is performed, and anti-interference effect is achieved.

In this stage, the input signal of the reset terminal T _ RST is low, and the seventh transistor M7 and the eighth transistor M8 are turned off.

IN the fifth stage S5, i.e., the sustain stage, the INPUT signals of the signal INPUT terminal INPUT, the control terminal IN and the reset terminal are all at low level, and the first transistor M1, the sixth transistor M6, the fifth transistor M5, the seventh transistor M7 and the eighth transistor M8 are all turned off. The pull-up node PU and the pull-down node PD keep the state of the fourth stage S4 unchanged. In this stage, the clock input terminal CLK still inputs the pulse signal.

The sixth stage S6, i.e., the third reset stage, during the blank window period, the input signal of the reset terminal T _ RST becomes a high level, the seventh transistor M7 and the eighth transistor M8 are turned on, and the first capacitor C1 and the signal OUTPUT terminal OUTPUT are discharged to maintain the low level of the pull-up node PU and the signal OUTPUT terminal OUTPUT to the second voltage signal terminal VGL.

After the fifth stage S5, the clock INPUT terminal CLK remains low until the INPUT signal at the signal INPUT terminal INPUT is high, and the process starts again from the first stage. The Time from the Time when the clock input terminal CLK stops outputting the high level to the Time when the next first stage restarts may be referred to as blank Time (Blanking Time). When the display panel normally works, the gate driving signals are required to be sequentially output from the first row of gate lines to the last row of gate lines, and after the gate driving signals of a certain row of gate lines are output, the shift register enters a blank window time period of clock input. In the embodiment, the reset terminal T _ RST is introduced into the shift register, so that the pull-up node PU and the signal OUTPUT terminal OUTPUT are kept at the low level of the second voltage signal terminal VGL in the blank window time period, and therefore, the problems of transistor characteristic drift caused by bias voltage in a high-temperature and high-humidity environment, poor terminal line caused by charge accumulated in the pull-up node PU and the like are avoided.

According to the operation process of the shift register, in the first stage S1, the sixth transistor M6 is turned on, the fifth transistor M5 is turned off, and the pull-down node PD provides the low level signal of the second voltage signal terminal VGL; in the second stage S2 and the third stage S3, the sixth transistor M6 is turned off, the fifth transistor M5 is turned off, and the pull-down node PD is maintained at a low level by the second capacitor C2; in the fourth stage S4, the fifth transistor M5 is turned on, the sixth transistor M6 is turned off, and the pull-down node PD provides a high level signal of the first voltage signal terminal VGH; in the fifth stage S5 and the sixth stage S6, the fifth transistor M5 is turned off, the sixth transistor M6 is turned off, and the pull-down node PD is maintained at a high level by the second capacitor C2. The fifth transistor M5 and the sixth transistor M6 are not turned on at the same time, so that it is avoided that the pull-down node PD is provided with a high level signal and a low level signal at the same time, and the condition that the pull-down node PD cannot be pulled down to the low level of the second voltage signal terminal VGL sufficiently is avoided.

According to the operation process of the shift register, the input signal at the control terminal IN is changed to the high level to turn on the third transistor M3 and the fourth transistor M4, so as to pull down the pull-up node PU and the signal OUTPUT terminal OUTPUT to the low level of the second voltage signal terminal VGL. By providing the OUTPUT signal of the signal OUTPUT terminal OUTPUT (n +3) of the (n +3) th stage shift register to the control terminal in (n) of the nth stage shift register, the staggered row reset can be realized, so that the noise release Time of the clock input signal CLK to the signal OUTPUT terminal OUTPUT (i.e., the third stage S3) is increased, the Tf (Fall Time ) of the signal OUTPUT terminal OUTPUT is reduced, and the display performance is improved.

Second embodiment

Based on the inventive concept of the foregoing embodiments, the embodiments of the present application further provide a driving method of a shift register. Fig. 10 is a flowchart of a driving method of a shift register according to an embodiment of the present application. As shown in fig. 10, the driving method of the shift register provided in this embodiment is applied to the shift register provided in the first embodiment, and the method includes the following steps:

101, an input sub-circuit provides a signal of a first voltage signal end to a pull-up node under the control of a signal input end, and a pull-down node control sub-circuit provides a signal of a second voltage signal end to a pull-down node under the control of a control end and the signal input end;

102, an output sub-circuit provides a signal of a clock input end to a signal output end under the control of a pull-up node;

103, the pull-down node control sub-circuit provides a signal of a first voltage signal end to the pull-down node under the control of the control end and the signal input end;

and step 104, the first reset sub-circuit provides signals of the second voltage signal end to the pull-up node and the signal output end under the control of the pull-down node.

In an exemplary embodiment, the driving method of a shift register provided in this embodiment further includes: the second reset sub-circuit provides a signal of a second voltage signal terminal to the pull-up node and the signal output terminal in the empty window time period under the control of the reset terminal.

The driving method of the shift register, the structure of the shift register and the working process thereof in this embodiment have been described in detail in the first embodiment, and are not described herein again.

Third embodiment

Based on the inventive concept of the foregoing embodiments, the present embodiment also provides a gate driving circuit. Fig. 11 is a schematic diagram of a gate driving circuit according to an embodiment of the present application. As shown in fig. 11, the gate driving circuit provided in this embodiment includes a plurality of cascaded shift registers, and the shift registers are the shift registers provided in the first embodiment, and the implementation principle and the implementation effect are similar, so that the details are not repeated herein.

The signal OUTPUT terminal OUTPUT (n) of the nth stage shift register OUTPUTs a gate driving signal to the nth row gate line of the display region, the signal OUTPUT terminal OUTPUT (n) of the nth stage shift register is connected with the signal INPUT terminal INPUT (n +1) of the (n +1) th stage shift register, and the signal OUTPUT terminal OUTPUT (n +3) of the (n +3) th stage shift register is connected with the control terminal in (n) of the nth stage shift register. The phase of the clock input signal terminal CLK (n +1) of the (n +1) th stage shift register and the phase of the input signal of the clock input signal terminal CLK (n) of the nth stage shift register may differ by 90 degrees.

Fourth embodiment

Based on the inventive concept of the foregoing embodiments, embodiments of the present application further provide a display device, which includes the gate driving circuit described in the foregoing embodiments. The display device may be: any product or component with a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like.

In the description of the embodiments of the present application, it should be understood that the terms "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. indicate orientations or positional relationships based on those shown in the drawings, and are only for convenience of description and simplicity of description, but do not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed in a particular orientation, and be operated, and therefore, should not be construed as limiting the present application.

In the description of the embodiments of the present application, it should be noted that the terms "mounted," "connected," and "connected" are to be construed broadly and may be, for example, fixedly connected, detachably connected, or integrally connected unless explicitly stated or limited otherwise; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.

Although the embodiments disclosed in the present application are described above, the descriptions are only for the convenience of understanding the present application, and are not intended to limit the present application. It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the disclosure as defined by the appended claims.

Claims

1. A shift register, comprising:

the circuit comprises an input sub-circuit, an output sub-circuit, a pull-down node control sub-circuit and a first reset sub-circuit;

the input sub-circuit is respectively connected with the signal input end, the first voltage signal end and the pull-up node and is used for providing a signal of the first voltage signal end to the pull-up node under the control of the signal input end;

the output sub-circuit is respectively connected with the pull-up node, the clock input end and the signal output end and is used for providing a signal of the clock input end for the signal output end under the control of the pull-up node;

the first reset sub-circuit is respectively connected with the pull-up node, the pull-down node, the signal output end and the second voltage signal end, and is used for providing signals of the second voltage signal end for the pull-up node and the signal output end under the control of the pull-down node;

the pull-down node control sub-circuit is respectively connected with the first voltage signal end, the control end, the signal input end, the pull-down node and the second voltage signal end, and is used for providing signals of the first voltage signal end or the second voltage signal end to the pull-down node under the control of the control end and the signal input end.

2. The shift register of claim 1, wherein the pull-down node control subcircuit comprises: a first control sub-circuit and a second control sub-circuit;

the first control sub-circuit is respectively connected with the first voltage signal end, the control end and the pull-down node, and is used for providing a signal of the first voltage signal end to the pull-down node under the control of the control end and closing the first control sub-circuit when the second control sub-circuit provides a signal of the second voltage signal end to the pull-down node;

the second control sub-circuit is respectively connected with the signal input end, the second voltage signal end and the pull-down node, and is used for providing a signal of the second voltage signal end to the pull-down node under the control of the signal input end and closing the first control sub-circuit when the first control sub-circuit provides a signal of the first voltage signal end to the pull-down node.

3. The shift register of claim 2, wherein the first control sub-circuit comprises: a control electrode of the fifth transistor is connected with the control end, a first electrode of the fifth transistor is connected with the first voltage signal end, and a second electrode of the fifth transistor is connected with the pull-down node;

the second control sub-circuit comprises: and a control electrode of the sixth transistor is connected with the signal input end, a first electrode of the sixth transistor is connected with the pull-down node, and a second electrode of the sixth transistor is connected with the second voltage signal end.

4. The shift register of claim 2, wherein the pull-down node control subcircuit further comprises: and the second capacitor is respectively connected with the pull-down node and the second voltage signal end, and is used for charging according to the signal provided by the first control sub-circuit or the second control sub-circuit to the pull-down node, or discharging according to the signal provided by the first control sub-circuit or the second control sub-circuit to the pull-down node, and maintaining the level state of the pull-down node after charging or discharging.

5. The shift register of claim 1, further comprising: and the second reset sub-circuit is respectively connected with the reset terminal, the pull-up node, the signal output terminal and the second voltage signal terminal, and is used for providing signals of the second voltage signal terminal to the pull-up node and the signal output terminal in an empty window time period under the control of the reset terminal.

6. The shift register of claim 5, wherein the second reset subcircuit comprises: a seventh transistor and an eighth transistor;

a control electrode of the seventh transistor is connected with the reset end, a first electrode of the seventh transistor is connected with the pull-up node, and a second electrode of the seventh transistor is connected with the second voltage signal end;

the control electrode of the eighth transistor is connected with the reset end, the first electrode of the eighth transistor is connected with the signal output end, and the second electrode of the eighth transistor is connected with the second voltage signal end.

7. The shift register of claim 1, further comprising: and a control electrode of the ninth transistor is connected with the pull-down node, a first electrode of the ninth transistor is connected with the pull-up node, and a second electrode of the ninth transistor is connected with the signal output end.

8. The shift register of claim 1, wherein the input sub-circuit comprises: a control electrode of the first transistor is connected with a signal input end, a first electrode of the first transistor is connected with a first voltage signal end, and a second electrode of the first transistor is connected with a pull-up node;

the output sub-circuit includes: a second transistor and a first capacitor; a control electrode of the second transistor is connected with a pull-up node, a first electrode of the second transistor is connected with a clock input end, and a second electrode of the second transistor is connected with a signal output end; a first electrode of the first capacitor is connected with a pull-up node, and a second electrode of the first capacitor is connected with a signal output end;

the first reset sub-circuit includes: a third transistor and a fourth transistor; a control electrode of the third transistor is connected with a pull-down node, a first electrode of the third transistor is connected with the pull-up node, and a second electrode of the third transistor is connected with a second voltage signal end; a control electrode of the fourth transistor is connected with the pull-down node, a first electrode of the fourth transistor is connected with the signal output end, and a second electrode of the fourth transistor is connected with the second voltage signal end;

the pull-down node control sub-circuit comprises: a fifth transistor, a sixth transistor and a second capacitor; a control electrode of the fifth transistor is connected with the control end, a first electrode of the fifth transistor is connected with the first voltage signal end, and a second electrode of the fifth transistor is connected with the pull-down node; a control electrode of the sixth transistor is connected with the signal input end, a first electrode of the sixth transistor is connected with the pull-down node, and a second electrode of the sixth transistor is connected with the second voltage signal end; a first electrode of the second capacitor is connected with a pull-down node, and a second electrode of the second capacitor is connected with a second voltage signal end;

the shift register further includes: the control electrode of the ninth transistor is connected with the pull-down node, the first electrode of the ninth transistor is connected with the pull-up node, and the second electrode of the ninth transistor is connected with the signal output end;

the second reset sub-circuit includes: a seventh transistor and an eighth transistor; a control electrode of the seventh transistor is connected with a reset end, a first electrode of the seventh transistor is connected with a pull-up node, and a second electrode of the seventh transistor is connected with a second voltage signal end; the control electrode of the eighth transistor is connected with the reset end, the first electrode of the eighth transistor is connected with the signal output end, and the second electrode of the eighth transistor is connected with the second voltage signal end.

9. A gate drive circuit, comprising: the plurality of cascaded shift registers of any one of claims 1 to 8, wherein a control terminal of the nth stage shift register is connected to a signal output terminal of the n +3 th stage shift register.

10. A display device, comprising: a gate drive circuit as claimed in claim 9.

11. A driving method of a shift register, which is applied to the shift register according to any one of claims 1 to 8, the driving method comprising:

the input sub-circuit provides a signal of a first voltage signal end to a pull-up node under the control of the signal input end, and the pull-down node control sub-circuit provides a signal of a second voltage signal end to a pull-down node under the control of the control end and the signal input end;

the output sub-circuit provides a signal of the clock input end to the signal output end under the control of the pull-up node;

the pull-down node control sub-circuit provides a signal of a first voltage signal end to a pull-down node under the control of the control end and the signal input end;

the first reset sub-circuit provides signals of the second voltage signal end to the pull-up node and the signal output end under the control of the pull-down node.

12. The driving method according to claim 11, further comprising: the second reset sub-circuit provides a signal of a second voltage signal terminal to the pull-up node and the signal output terminal in the empty window time period under the control of the reset terminal.