CN109036252B - Shifting register, driving method thereof and grid driving circuit - Google Patents
Shifting register, driving method thereof and grid driving circuit Download PDFInfo
- Publication number
- CN109036252B CN109036252B CN201811055224.7A CN201811055224A CN109036252B CN 109036252 B CN109036252 B CN 109036252B CN 201811055224 A CN201811055224 A CN 201811055224A CN 109036252 B CN109036252 B CN 109036252B
- Authority
- CN
- China
- Prior art keywords
- node
- reset
- pull
- switching transistor
- voltage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Shift Register Type Memory (AREA)
- Liquid Crystal Display Device Control (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
The invention discloses a shift register, a driving method thereof and a grid driving circuit, comprising the following steps: the device comprises an input module, an output module, a reset module and a reset control module; the control of the voltage of the reset node is realized by respectively outputting control signals to the reset control module through the first reset signal end and the second reset signal end, so that the working time of the reset module can be arbitrarily expanded under the control of the voltage of the reset node, and the discharging capacity of the shift register is effectively improved.
Description
Technical Field
The invention relates to the technical field of display, in particular to a shift register, a driving method thereof and a grid driving circuit.
Background
With the rapid development of display technology, display panels are increasingly developed toward high integration and low cost. The Array substrate line driving (GOA) technology integrates a Thin Film Transistor (TFT) Gate switch Circuit on an Array substrate of a display panel to form scanning driving of the display panel, so that a wiring space of a binding (Bonding) area and a Fan-out (Fan-out) area of a Gate Integrated Circuit (IC) can be saved, the product cost can be reduced in two aspects of material cost and preparation process, and the display panel can be designed to be symmetrical at two sides and narrow-frame; moreover, the integration process can also omit the Bonding process in the direction of a grid scanning line, thereby improving the productivity and the yield.
The general gate driving circuit is composed of a plurality of cascaded shift registers, each shift register sequentially transmits gate scanning signals to the next shift register, and thin film transistors in a pixel area are turned on line by line to complete data signal input of a pixel. However, due to the gradual development of high refresh rate (Gaming) products, the charging time of each row of pixels is less and less, and the corresponding shift register is insufficiently discharged, so that the shift register cannot normally operate, and finally, the display panel cannot normally display.
Disclosure of Invention
In view of the above, embodiments of the present invention provide a shift register, a driving method thereof, and a gate driving circuit, so as to improve a discharging capability of the shift register.
Therefore, an embodiment of the present invention provides a shift register, including: the device comprises an input module, an output module, a reset module and a reset control module;
the input module is respectively connected with a signal input end and a pull-up node and is used for writing the voltage of the signal input end into the pull-up node under the control of the voltage of the signal input end;
the output module is respectively connected with a first clock signal end, the pull-up node and a signal output end, and is used for writing the voltage of the first clock signal end into the signal output end under the control of the voltage of the pull-up node and keeping the voltage difference between the pull-up node and the signal output end stable when the pull-up node is in a floating state;
the reset module is respectively connected with a reset node, the pull-up node, a reference signal end and the signal output end and is used for writing the voltage of the reference signal end into the pull-up node and the signal output end under the control of the voltage of the reset node;
the reset control module is respectively connected with the first reset signal end, the second reset signal end and the reset node and is used for writing the voltage of the first reset signal end into the reset node under the control of the voltage of the first reset signal end and writing the voltage of the second reset signal end into the reset node under the control of the voltage of the second reset signal end.
In a possible implementation manner, in the shift register provided in the embodiment of the present invention, the shift register further includes: the pull-down control module and the pull-down module;
the pull-down control module is respectively connected with a second clock signal end, a pull-down node, the pull-up node and the reference signal end, and is used for writing the voltage of the second clock signal end into the pull-down node under the control of the voltage of the second clock signal end; and writing the voltage of the reference signal terminal into the pull-down node under the control of the voltage of the pull-up node;
the pull-down module is respectively connected with the pull-up node, the pull-down node, the signal output end and the reference signal end, and is used for writing the voltage of the reference signal end into the pull-up node and the signal output end under the control of the voltage of the pull-down node.
In a possible implementation manner, in the shift register provided in an embodiment of the present invention, the input module includes: a first switching transistor;
the gate of the first switching transistor is connected to the signal input terminal, the first pole is connected to the signal input terminal, and the second pole is connected to the pull-up node.
In a possible implementation manner, in the shift register provided in an embodiment of the present invention, the output module includes: a second switching transistor and a capacitor;
the grid electrode of the second switching transistor is connected with the pull-up node, the first pole of the second switching transistor is connected with the first clock signal end, and the second pole of the second switching transistor is connected with the signal output end;
the capacitor is connected between the pull-up node and the signal output end.
In a possible implementation manner, in the shift register provided in an embodiment of the present invention, the reset module includes: a third switching transistor and a fourth switching transistor;
the grid electrode of the third switching transistor is connected with the reset node, the first pole of the third switching transistor is connected with the reference signal end, and the second pole of the third switching transistor is connected with the pull-up node;
and the grid electrode of the fourth switching transistor is connected with the reset node, the first electrode of the fourth switching transistor is connected with the reference signal end, and the second electrode of the fourth switching transistor is connected with the signal output end.
In a possible implementation manner, in the shift register provided in an embodiment of the present invention, the reset control module includes: a fifth switching transistor and a sixth switching transistor;
a grid electrode of the fifth switching transistor is connected with the first reset signal end, a first pole of the fifth switching transistor is connected with the first reset signal end, and a second pole of the fifth switching transistor is connected with the reset node;
and the grid electrode of the sixth switching transistor is connected with the second reset signal end, the first pole of the sixth switching transistor is connected with the second reset signal end, and the second pole of the sixth switching transistor is connected with the reset node.
In a possible implementation manner, in the shift register provided in an embodiment of the present invention, the pull-down control module includes: a seventh switching transistor, an eighth switching transistor, a ninth switching transistor, and a tenth switching transistor;
a grid electrode of the seventh switching transistor is connected with the second clock signal end, a first pole is connected with the second clock signal end, and a second pole is connected with a first node;
a grid electrode of the eighth switching transistor is connected with the first node, a first pole of the eighth switching transistor is connected with the second clock signal end, and a second pole of the eighth switching transistor is connected with the pull-down node;
a gate of the ninth switching transistor is connected with the pull-up node, a first pole of the ninth switching transistor is connected with the reference signal end, and a second pole of the ninth switching transistor is connected with the pull-down node;
and the grid electrode of the tenth switching transistor is connected with the pull-up node, the first pole of the tenth switching transistor is connected with the reference signal end, and the second pole of the tenth switching transistor is connected with the first node.
In a possible implementation manner, in the shift register provided in an embodiment of the present invention, the pull-down module includes: an eleventh switching transistor and a twelfth switching transistor;
a gate of the eleventh switching transistor is connected to the pull-down node, a first pole thereof is connected to the reference signal terminal, and a second pole thereof is connected to the pull-up node;
and the grid electrode of the twelfth switching transistor is connected with the pull-down node, the first pole of the twelfth switching transistor is connected with the reference signal end, and the second pole of the twelfth switching transistor is connected with the signal output end.
Correspondingly, an embodiment of the present invention further provides a driving method of the shift register, including:
in the first stage, an input module writes the voltage of a signal input end into a pull-up node under the control of the voltage of the signal input end; the output module writes the voltage of the first clock signal end into the signal output end under the control of the voltage of the pull-up node;
in the second stage, the output module keeps the voltage difference between the pull-up node and the signal output end stable when the pull-up node is in a floating state, and writes the voltage of the first clock signal end into the signal output end under the control of the voltage of the pull-up node;
in the third stage, the reset control module writes the voltage of the first reset signal end into a reset node under the control of the voltage of the first reset signal end; the reset module writes the voltage of a reference signal end into the pull-up node and the signal output end under the control of the voltage of the reset node;
in the fourth stage, the reset control module writes the voltage of the second reset signal end into the reset node under the control of the voltage of the second reset signal end; and the reset module writes the voltage of the reference signal end into the pull-up node and the signal output end under the control of the voltage of the reset node.
Based on the same inventive concept, the embodiment of the invention also provides a gate driving circuit, which comprises a plurality of cascaded shift registers;
the signal input end of the first-stage shift register is connected with the frame trigger signal end;
except the first stage of shift register, the signal input ends of the other shift registers at each stage are respectively connected with the signal output end of the shift register at the previous stage;
the first reset signal end of each stage of shift register is connected with the signal output end of the next stage of shift register, and the second reset signal end is connected with the signal output end of the shift register at least one stage below the second reset signal end.
The invention has the following beneficial effects:
the shift register, the driving method thereof and the gate driving circuit provided by the embodiment of the invention comprise the following steps: the device comprises an input module, an output module, a reset module and a reset control module; the input module is respectively connected with the signal input end and the pull-up node and is used for writing the voltage of the signal input end into the pull-up node under the control of the voltage of the signal input end; the output module is respectively connected with the first clock signal end, the pull-up node and the signal output end and is used for writing the voltage of the first clock signal end into the signal output end under the control of the voltage of the pull-up node and keeping the voltage difference between the pull-up node and the signal output end stable when the pull-up node is in a floating state; the reset module is respectively connected with the reset node, the pull-up node, the reference signal end and the signal output end and is used for writing the voltage of the reference signal end into the pull-up node and the signal output end under the control of the voltage of the reset node; the reset control module is respectively connected with the first reset signal end, the second reset signal end and the reset node and is used for writing the voltage of the first reset signal end into the reset node under the control of the voltage of the first reset signal end and writing the voltage of the second reset signal end into the reset node under the control of the voltage of the second reset signal end. The control of the voltage of the reset node is realized by respectively outputting control signals to the reset control module through the first reset signal end and the second reset signal end, so that the working time of the reset module can be arbitrarily expanded under the control of the voltage of the reset node, and the discharging capacity of the shift register is effectively improved.
Drawings
Fig. 1 is a schematic structural diagram of a shift register according to an embodiment of the present invention;
fig. 2 is a flowchart of a driving method of a shift register according to an embodiment of the invention;
FIG. 3 is a diagram illustrating a specific structure of the shift register shown in FIG. 1;
FIG. 4 is a timing diagram illustrating operation of the shift register shown in FIG. 3;
fig. 5 is a schematic structural diagram of a shift register according to a second embodiment of the present invention;
fig. 6 is a flowchart of a driving method of a shift register according to a second embodiment of the present invention;
FIG. 7 is a diagram illustrating an embodiment of a shift register shown in FIG. 5;
FIG. 8 is a timing diagram illustrating operation of the shift register shown in FIG. 7;
fig. 9 is a schematic structural diagram of a gate driving circuit according to a third embodiment of the present invention.
Detailed Description
The following describes in detail specific embodiments of a shift register, a driving method thereof, and a gate driving circuit according to embodiments of the present invention with reference to the accompanying drawings. It should be noted that the embodiments described in this specification are only a part of the embodiments of the present invention, and not all embodiments; and in case of conflict, the embodiments and features of the embodiments in the present application may be combined with each other; moreover, all other embodiments obtained by a person of ordinary skill in the art based on the embodiments of the present invention without any creative effort belong to the protection scope of the present invention.
Example one
A shift register according to a first embodiment of the present invention, as shown in fig. 1, includes: an input module 101, an output module 102, a reset module 103 and a reset control module 104;
the INPUT module 101 is connected to the signal INPUT terminal INPUT and the pull-up node PU, respectively, and configured to write the voltage of the signal INPUT terminal INPUT into the pull-up node PU under the control of the voltage of the signal INPUT terminal INPUT;
the OUTPUT module 102 is connected to the first clock signal terminal CLKA, the pull-up node PU, and the signal OUTPUT terminal OUTPUT, respectively, and is configured to write the voltage of the first clock signal terminal CLKA into the signal OUTPUT terminal OUTPUT under the control of the voltage of the pull-up node PU, and keep a voltage difference between the pull-up node PU and the signal OUTPUT terminal OUTPUT stable when the pull-up node PU is in a floating state;
the Reset module 103 is respectively connected to the Reset node Reset, the pull-up node PU, the reference signal terminal VSS, and the signal OUTPUT terminal OUTPUT, and is configured to write the voltage of the reference signal terminal VSS into the pull-up node PU and the signal OUTPUT terminal OUTPUT under the control of the voltage of the Reset node Reset;
the Reset control module 104 is connected to the first Reset signal terminal Reset1, the second Reset signal terminal Reset2, and the Reset node Reset, respectively, and configured to write the voltage of the first Reset signal terminal Reset1 into the Reset node Reset under the control of the voltage of the first Reset signal terminal Reset1, and write the voltage of the second Reset signal terminal Reset2 into the Reset node Reset under the control of the voltage of the second Reset signal terminal Reset 2.
In the shift register provided in the first embodiment of the present invention, the control signal is output to the Reset control module 107 through the first Reset signal terminal Reset1 and the second Reset signal terminal Reset2, so as to control the voltage of the Reset node Reset, and thus the operating time of the Reset module 106 can be arbitrarily extended under the control of the voltage of the Reset node Reset, thereby effectively improving the discharging capability of the shift register and ensuring that the shift register can normally operate.
Accordingly, for the shift register, a first embodiment of the present invention further provides a driving method, as shown in fig. 2, including:
s201, in the first stage, an input module writes the voltage of a signal input end into a pull-up node under the control of the voltage of the signal input end; the output module writes the voltage of the first clock signal end into the signal output end under the control of the voltage of the pull-up node;
s202, in the second stage, the output module keeps the voltage difference between the pull-up node and the signal output end stable when the pull-up node is in a floating state, and writes the voltage of the first clock signal end into the signal output end under the control of the voltage of the pull-up node;
s203, in the third stage, the reset control module writes the voltage of the first reset signal end into a reset node under the control of the voltage of the first reset signal end; the reset module writes the voltage of the reference signal end into the pull-up node and the signal output end under the control of the voltage of the reset node;
s204, in the fourth stage, the reset control module writes the voltage of the second reset signal end into the reset node under the control of the voltage of the second reset signal end; the reset module writes the voltage of the reference signal end into the pull-up node and the signal output end under the control of the voltage of the reset node.
In order to better understand the structure and the operation principle of the shift register provided in the first embodiment of the present invention, a detailed description is given below with respect to a specific embodiment.
Specifically, the shift register with the structure shown in fig. 3 is a possible implementation manner of the shift register provided in the embodiment of the present invention.
As shown in fig. 3, the input module 101 includes: a first switching transistor M1; the gate of the first switching transistor M1 is connected to the signal INPUT terminal INPUT, the first pole is connected to the signal INPUT terminal INPUT, and the second pole is connected to the pull-up node PU.
An output module 102, comprising: a second switching transistor M2 and a capacitor C; the gate of the second switching transistor M2 is connected to the pull-up node PU, the first pole is connected to the first clock signal terminal CLKA, and the second pole is connected to the signal OUTPUT terminal OUTPUT; the capacitor C is connected between the pull-up node PU and the signal OUTPUT terminal OUTPUT.
A reset module 103, comprising: a third switching transistor M3 and a fourth switching transistor M4; the gate of the third switching transistor M3 is connected to the Reset node Reset, the first pole is connected to the reference signal terminal VSS, and the second pole is connected to the pull-up node PU; the gate of the fourth switching transistor M4 is connected to the Reset node Reset, the first pole is connected to the reference signal terminal VSS, and the second pole is connected to the signal OUTPUT terminal OUTPUT.
A reset control module 104 comprising: a fifth switching transistor M5 and a sixth switching transistor M6; a gate of the fifth switching transistor M5 is connected to the first Reset signal terminal Reset1, a first pole is connected to the first Reset signal terminal Reset1, and a second pole is connected to the Reset node Reset; the sixth switching transistor M6 has a gate connected to the second Reset signal terminal Reset2, a first pole connected to the second Reset signal terminal Reset2, and a second pole connected to the Reset node Reset.
It should be noted that, the above is only an example of the specific structure of each module in the shift register provided in the first embodiment of the present invention, and in the implementation, the specific structure of each module is not limited to the above structure provided in the first embodiment of the present invention, and may be other structures known to those skilled in the art, and is not limited herein.
The Transistor in the present invention may be a Thin Film Transistor (TFT) or a Metal Oxide Semiconductor field effect Transistor (MOS), and is not limited herein. In a specific implementation, the first and second poles of these transistors are the drain and source, respectively, and their functions can be interchanged according to the transistor type and the input signal, and are not specifically distinguished here. Generally, when the transistor is a P-type transistor, the first electrode is a source electrode, and the second electrode is a drain electrode; when the transistor is an N-type transistor, the first electrode is a drain electrode, and the second electrode is a source electrode.
The operation of the shift register shown in fig. 3 will be described, wherein in the shift register shown in fig. 3, each transistor is an N-type transistor, which is turned on under the action of a high voltage and turned off under the action of a low voltage; fig. 4 shows an operation timing diagram of the shift register, and specifically, details of the first stage T1, the second stage T2, the third stage T3, and the fourth stage T4 in the operation timing diagram shown in fig. 4 are taken as examples for description.
First stage T1: the signal INPUT terminal INPUT outputs a high voltage, the first Reset signal terminal Reset1 outputs a low voltage, the second Reset signal terminal Reset2 outputs a low voltage, and the first clock signal terminal CLKA outputs a low voltage.
The first switching transistor M1 is turned on under the control of the high voltage at the signal INPUT terminal INPUT, and the high voltage at the signal INPUT terminal INPUT is written into the pull-up node PU through the turned-on first switching transistor M1, and charges the capacitor C. The second switch transistor M2 is turned on under the control of the high voltage at the pull-up node PU, and the low voltage of the first clock signal terminal CLKA is written into the signal OUTPUT terminal OUTPUT through the turned-on second switch transistor M2.
Second stage T2: the signal INPUT terminal INPUT outputs a low voltage, the first Reset signal terminal Reset1 outputs a low voltage, the second Reset signal terminal Reset2 outputs a low voltage, and the first clock signal terminal CLKA outputs a high voltage.
Due to the bootstrap action of the capacitor C, the voltage level of the pull-up node PU is maintained at a high voltage, the second switch transistor M2 is in a conducting state under the control of the high voltage level of the pull-up node PU, and the high voltage level of the first clock signal terminal CLKA is written into the signal OUTPUT terminal OUTPUT through the conducting second switch transistor M2.
Third stage T3: the signal INPUT terminal INPUT outputs a low voltage, the first Reset signal terminal Reset1 outputs a high voltage, the second Reset signal terminal Reset2 outputs a low voltage, and the first clock signal terminal CLKA outputs a low voltage.
The fifth switching transistor M5 is in a turn-on state under the control of the high voltage of the first Reset signal terminal Reset1, so that the high voltage of the first Reset signal terminal Reset1 is written into the Reset node Reset through the turned-on fifth switching transistor M5. The third switching transistor M3 is turned on under the control of the high voltage at the Reset node Reset, so that the low voltage at the reference signal terminal VSS is written into the pull-up node PU through the turned-on third switching transistor M3, thereby resetting the pull-up node PU. The fourth switching transistor M4 is in a conducting state under the control of the high voltage of the Reset node Reset, so that the low voltage of the reference signal terminal VSS is written into the signal OUTPUT terminal OUTPUT through the conducting fourth switching transistor M4, and the Reset of the signal OUTPUT terminal OUTPUT is realized.
Fourth stage T4: the signal INPUT terminal INPUT outputs a low voltage, the first Reset signal terminal Reset1 outputs a low voltage, the second Reset signal terminal Reset2 outputs a high voltage, and the first clock signal terminal CLKA outputs a high voltage.
The sixth switching transistor M6 is in a turn-on state under the control of the high voltage of the second Reset signal terminal Reset2, so that the high voltage of the second Reset signal terminal Reset2 is written into the Reset node Reset through the turned-on sixth switching transistor M6. The third switching transistor M3 is turned on under the control of the high voltage at the Reset node Reset, so that the low voltage at the reference signal terminal VSS is written into the pull-up node PU through the turned-on third switching transistor M3, thereby further resetting the pull-up node PU. The fourth switching transistor M4 is in a conducting state under the control of the high voltage of the Reset node Reset, so that the low voltage of the reference signal terminal VSS is written into the signal OUTPUT terminal OUTPUT through the conducting fourth switching transistor M4, and the Reset of the signal OUTPUT terminal OUTPUT is further realized.
During the period thereafter, the shift register will repeat the process of T1-T4 described above.
As can be seen from the above description, in the shift register provided in the embodiment of the present invention, the voltages of the Reset nodes Reset are respectively controlled by the first Reset signal terminal Reset1 and the second Reset signal terminal Reset2, so that the discharging time duration of the shift register (i.e., the Reset time duration of the pull-up node PU and the signal OUTPUT terminal OUTPUT) is arbitrarily extended under the control of the voltages of the Reset nodes Reset, and thus the discharging capability of the shift register is effectively improved.
Example two
As shown in fig. 5, a shift register according to a second embodiment of the present invention includes: an input module 101, an output module 102, a reset module 103, a reset control module 104, a pull-down control module 105 and a pull-down module 106;
the INPUT module 101 is connected to the signal INPUT terminal INPUT and the pull-up node PU, respectively, and configured to write the voltage of the signal INPUT terminal INPUT into the pull-up node PU under the control of the voltage of the signal INPUT terminal INPUT;
the OUTPUT module 102 is connected to the first clock signal terminal CLKA, the pull-up node PU, and the signal OUTPUT terminal OUTPUT, respectively, and is configured to write the voltage of the first clock signal terminal CLKA into the signal OUTPUT terminal OUTPUT under the control of the voltage of the pull-up node PU, and keep a voltage difference between the pull-up node PU and the signal OUTPUT terminal OUTPUT stable when the pull-up node PU is in a floating state;
the Reset module 103 is respectively connected to the Reset node Reset, the pull-up node PU, the reference signal terminal VSS, and the signal OUTPUT terminal OUTPUT, and is configured to write the voltage of the reference signal terminal VSS into the pull-up node PU and the signal OUTPUT terminal OUTPUT under the control of the voltage of the Reset node Reset;
the Reset control module 104 is connected to the first Reset signal terminal Reset1, the second Reset signal terminal Reset2, and the Reset node Reset, respectively, and is configured to write the voltage of the first Reset signal terminal Reset1 into the Reset node Reset under the control of the voltage of the first Reset signal terminal Reset1, and write the voltage of the second Reset signal terminal Reset2 into the Reset node Reset under the control of the voltage of the second Reset signal terminal Reset 2;
the pull-down control module 105 is connected to the second clock signal terminal CLKB, the pull-up node PU, the pull-down node PD, and the reference signal terminal VSS, respectively, and configured to write the voltage of the second clock signal terminal CLKB into the pull-down node PD under the control of the voltage of the second clock signal terminal CLKB; writing the voltage of the reference signal terminal VSS into the pull-down node PD under the control of the voltage of the pull-up node PU;
the pull-down module 106 is connected to the pull-up node PU, the pull-down node PD, the signal OUTPUT terminal OUTPUT, and the reference signal terminal VSS, respectively, and configured to write a voltage of the reference signal terminal VSS into the pull-up node PU and the signal OUTPUT terminal OUTPUT under control of a voltage of the pull-down node PD.
In the shift register provided in the second embodiment of the present invention, the control signal is output to the Reset control module 107 through the first Reset signal terminal Reset1 and the second Reset signal terminal Reset2, so as to control the voltage of the Reset node Reset, and thus the operating time of the Reset module 106 can be arbitrarily extended under the control of the voltage of the Reset node Reset, thereby effectively improving the discharging capability of the shift register and ensuring that the shift register can normally operate.
Correspondingly, for the shift register, a second embodiment of the present invention further provides a driving method, as shown in fig. 6, including:
s601, in the first stage, an input module writes the voltage of a signal input end into a pull-up node under the control of the voltage of the signal input end; the pull-down control module writes the voltage of the reference signal end into the pull-down node under the control of the voltage of the pull-up node; the output module writes the voltage of the first clock signal end into the signal output end under the control of the voltage of the pull-up node;
s602, in the second stage, the pull-down control module writes the voltage of the reference signal end into the pull-down node under the control of the voltage of the pull-up node; the output module keeps the voltage difference between the pull-up node and the signal output end stable when the pull-up node is in a floating state, and writes the voltage of the first clock signal end into the signal output end under the control of the voltage of the pull-up node;
s603, in the third stage, the pull-down control module writes the voltage of the second clock signal end into the pull-down node under the control of the voltage of the second clock signal end; the pull-down module writes the voltage of the reference signal end into the pull-up node and the signal output end under the control of the voltage of the pull-down node; the reset control module writes the voltage of the first reset signal end into a reset node under the control of the voltage of the first reset signal end; the reset module writes the voltage of the reference signal end into the pull-up node and the signal output end under the control of the voltage of the reset node;
s604, in the fourth stage, the reset control module writes the voltage of the second reset signal end into the reset node under the control of the voltage of the second reset signal end; the reset module writes the voltage of the reference signal end into the pull-up node and the signal output end under the control of the voltage of the reset node.
In order to better understand the structure and the operation principle of the shift register provided by the second embodiment of the present invention, a detailed description is given below with respect to a specific embodiment.
Specifically, the shift register with the structure shown in fig. 7 is a possible implementation manner of the shift register provided in the second embodiment of the present invention.
As shown in fig. 7, the input module 101 includes: a first switching transistor M1; the gate of the first switching transistor M1 is connected to the signal INPUT terminal INPUT, the first pole is connected to the signal INPUT terminal INPUT, and the second pole is connected to the pull-up node PU.
An output module 102, comprising: a second switching transistor M2 and a capacitor C; the gate of the second switching transistor M2 is connected to the pull-up node PU, the first pole is connected to the first clock signal terminal CLKA, and the second pole is connected to the signal OUTPUT terminal OUTPUT; the capacitor C is connected between the pull-up node PU and the signal OUTPUT terminal OUTPUT.
A reset module 103, comprising: a third switching transistor M3 and a fourth switching transistor M4; the gate of the third switching transistor M3 is connected to the Reset node Reset, the first pole is connected to the reference signal terminal VSS, and the second pole is connected to the pull-up node PU; the gate of the fourth switching transistor M4 is connected to the Reset node Reset, the first pole is connected to the reference signal terminal VSS, and the second pole is connected to the signal OUTPUT terminal OUTPUT.
A reset control module 104 comprising: a fifth switching transistor M5 and a sixth switching transistor M6; a gate of the fifth switching transistor M5 is connected to the first Reset signal terminal Reset1, a first pole is connected to the first Reset signal terminal Reset1, and a second pole is connected to the Reset node Reset; the sixth switching transistor M6 has a gate connected to the second Reset signal terminal Reset2, a first pole connected to the second Reset signal terminal Reset2, and a second pole connected to the Reset node Reset.
A pull-down control module 105 comprising: a seventh switching transistor M7, an eighth switching transistor M8, a ninth switching transistor M9, and a tenth switching transistor M10; a gate M7 of the seventh switching transistor is connected to the second clock signal terminal CLKB, a first pole is connected to the second clock signal terminal CLKB, and a second pole is connected to the first node P1; a gate of the eighth switching transistor M8 is connected to the first node P1, a first pole is connected to the second clock signal terminal CLKB, and a second pole is connected to the pull-down node PD; a gate of the ninth switching transistor M9 is connected to the pull-up node PU, a first pole is connected to the reference signal terminal VSS, and a second pole is connected to the pull-down node PD; the gate of the tenth switching transistor M10 is connected to the pull-up node PU, the first pole is connected to the reference signal terminal VSS, and the second pole is connected to the first node P1.
A pull-down module 106, comprising: an eleventh switching transistor M11 and a twelfth switching transistor M12; a gate of the eleventh switching transistor M11 is connected to the pull-down node PD, a first pole thereof is connected to the reference signal terminal VSS, and a second pole thereof is connected to the pull-up node PU; the twelfth switching transistor M12 has a gate connected to the pull-down node PD, a first pole connected to the reference signal terminal VSS, and a second pole connected to the signal OUTPUT terminal OUTPUT.
It should be noted that, the above is only an example of the specific structure of each module in the shift register provided in the second embodiment of the present invention, and in the specific implementation, the specific structure of each module is not limited to the above structure provided in the second embodiment of the present invention, and may be another structure known to those skilled in the art, and is not limited herein.
The Transistor in the present invention may be a Thin Film Transistor (TFT) or a Metal Oxide Semiconductor field effect Transistor (MOS), and is not limited herein. In a specific implementation, the first and second poles of these transistors are the drain and source, respectively, and their functions can be interchanged according to the transistor type and the input signal, and are not specifically distinguished here. Generally, when the transistor is a P-type transistor, the first electrode is a source electrode, and the second electrode is a drain electrode; when the transistor is an N-type transistor, the first electrode is a drain electrode, and the second electrode is a source electrode.
The operation of the shift register shown in fig. 7 will be described, wherein in the shift register shown in fig. 7, each transistor is an N-type transistor, which is turned on under the action of a high voltage and turned off under the action of a low voltage; fig. 8 shows an operation timing chart corresponding to the shift register, and specifically, the first stage T1, the second stage T2, the third stage T3, and the fourth stage T4 in the operation timing chart shown in fig. 8 are taken as examples for detailed description.
First stage T1: the signal INPUT terminal INPUT outputs a high voltage, the first Reset signal terminal Reset1 outputs a low voltage, the second Reset signal terminal Reset2 outputs a low voltage, the first clock signal terminal CLKA outputs a low voltage, and the second clock signal terminal CLKB outputs a high voltage.
The first switching transistor M1 is turned on under the control of the high voltage at the signal INPUT terminal INPUT, and the high voltage at the signal INPUT terminal INPUT is written into the pull-up node PU through the turned-on first switching transistor M1, and charges the capacitor C. The tenth switching transistor M10 is in a turn-on state under the control of the high voltage of the pull-up node PU, and the low voltage of the reference signal terminal VSS is written into the first node P1 through the turned-on tenth switching transistor M10, so that the eighth switching transistor M8 is in a turn-off state under the control of the low voltage of the first node P1, and thus the high level of the second clock signal terminal CLKB is not written into the pull-down node PD. Meanwhile, the ninth switching transistor M9 is in a turned-on state under the control of the high voltage of the pull-up node PU, and the low voltage of the reference signal terminal VSS is written into the pull-down node PD through the turned-on ninth switching transistor M9, so that the eleventh switching transistor M11 and the twelfth switching transistor M12 are both in a turned-off state under the control of the low voltage of the pull-down node PD, and thus the potentials of the pull-up node PU and the signal OUTPUT terminal OUTPUT are not affected. In addition, the second switch transistor M2 is turned on under the control of the high voltage at the pull-up node PU, and the low voltage of the first clock signal terminal CLKA is written into the signal OUTPUT terminal OUTPUT through the turned-on second switch transistor M2.
Second stage T2: the signal INPUT terminal INPUT outputs a low voltage, the first Reset signal terminal Reset1 outputs a low voltage, the second Reset signal terminal Reset2 outputs a low voltage, the first clock signal terminal CLKA outputs a high voltage, and the second clock signal terminal CLKB outputs a low voltage.
Due to the bootstrap action of the capacitor C, the potential of the pull-up node PU is maintained at a high voltage, the ninth switching transistor M9 is in a conducting state under the control of the high voltage of the pull-up node PU, and the low voltage of the reference signal terminal VSS is written into the pull-down node PD through the conducting ninth switching transistor M9, so that the eleventh switching transistor M11 and the twelfth switching transistor M12 are both in a cut-off state under the control of the low voltage of the pull-down node PD, and thus the potentials of the pull-up node PU and the signal OUTPUT terminal OUTPUT cannot be affected. In addition, the second switch transistor M2 is in a conducting state under the control of the high voltage at the pull-up node PU, and the high voltage of the first clock signal terminal CLKA is written into the signal OUTPUT terminal OUTPUT through the conducting second switch transistor M2.
Third stage T3: the signal INPUT terminal INPUT outputs a low voltage, the first Reset signal terminal Reset1 outputs a high voltage, the second Reset signal terminal Reset2 outputs a low voltage, the first clock signal terminal CLKA outputs a low voltage, and the second clock signal terminal CLKB outputs a high voltage.
The seventh switching transistor M7 is in a turn-on state under the control of the high voltage of the second clock signal terminal CLKB, so that the high voltage of the second clock signal terminal CLKB is written into the first node P1 through the turned-on seventh switching transistor M7. The eighth switching transistor M8 is in a turn-on state under the control of the high voltage of the first node P1, so that the high voltage of the second clock signal terminal CLKB is written into the pull-down node PD through the turned-on eighth switching transistor M8. The eleventh switching transistor M11 is in a conducting state under the control of the high voltage of the pull-down node PD, so that the low voltage of the reference signal terminal VSS is written into the pull-up node PU through the conducting eleventh switching transistor M11, pulling down the potential of the pull-up node PU. The twelfth switching transistor M12 is in a conducting state under the control of the high voltage of the pull-down node PD, so that the low voltage of the reference signal terminal VSS is written into the signal OUTPUT terminal OUTPUT through the conducting twelfth switching transistor M12, and the potential of the signal OUTPUT terminal OUTPUT is pulled down. The fifth switching transistor M5 is in a turn-on state under the control of the high voltage of the first Reset signal terminal Reset1, so that the high voltage of the first Reset signal terminal Reset1 is written into the Reset node Reset through the turned-on fifth switching transistor M5. The third switching transistor M3 is turned on under the control of the high voltage at the Reset node Reset, so that the low voltage at the reference signal terminal VSS is written into the pull-up node PU through the turned-on third switching transistor M3, thereby resetting the pull-up node PU. The fourth switching transistor M4 is in a conducting state under the control of the high voltage of the Reset node Reset, so that the low voltage of the reference signal terminal VSS is written into the signal OUTPUT terminal OUTPUT through the conducting fourth switching transistor M4, and the Reset of the signal OUTPUT terminal OUTPUT is realized.
Fourth stage T4: the signal INPUT terminal INPUT outputs a low voltage, the first Reset signal terminal Reset1 outputs a low voltage, the second Reset signal terminal Reset2 outputs a high voltage, the first clock signal terminal CLKA outputs a high voltage, and the second clock signal terminal CLKB outputs a low voltage.
The sixth switching transistor M6 is in a turn-on state under the control of the high voltage of the second Reset signal terminal Reset2, so that the high voltage of the second Reset signal terminal Reset2 is written into the Reset node Reset through the turned-on sixth switching transistor M6. The third switching transistor M3 is turned on under the control of the high voltage at the Reset node Reset, so that the low voltage at the reference signal terminal VSS is written into the pull-up node PU through the turned-on third switching transistor M3, thereby further resetting the pull-up node PU. The fourth switching transistor M4 is in a conducting state under the control of the high voltage of the Reset node Reset, so that the low voltage of the reference signal terminal VSS is written into the signal OUTPUT terminal OUTPUT through the conducting fourth switching transistor M4, and the Reset of the signal OUTPUT terminal OUTPUT is further realized.
During the period thereafter, the shift register will repeat the process of T1-T4 described above.
As can be seen from the above description, in the shift register provided in the embodiment of the present invention, the voltages of the Reset nodes Reset are respectively controlled by the first Reset signal terminal Reset1 and the second Reset signal terminal Reset2, so that the discharging time duration of the shift register (i.e., the Reset time duration of the pull-up node PU and the signal OUTPUT terminal OUTPUT) is arbitrarily extended under the control of the voltages of the Reset nodes Reset, and thus the discharging capability of the shift register is effectively improved.
EXAMPLE III
Based on the same inventive concept, a third embodiment of the present invention provides a gate driving circuit, and since the principle of the gate driving circuit for solving the problems is similar to the principle of the shift register for solving the problems, the implementation of the gate driving circuit provided by the third embodiment of the present invention can refer to the implementation of the shift register provided by the first and second embodiments of the present invention, and repeated details are not repeated.
Specifically, the gate driving circuit provided in the third embodiment of the present invention, as shown in fig. 9, includes a plurality of cascaded shift registers provided in the first embodiment or the second embodiment of the present invention;
the signal INPUT end INPUT of the first-stage shift register A1 is connected with a frame trigger signal end STA;
except the first-stage shift register A1, the signal INPUT ends INPUT of the other shift registers are respectively connected with the signal OUTPUT end OUTPUT of the shift register of the previous stage;
the first Reset signal end Reset1 of each stage of shift register is connected with the signal OUTPUT end OUTPUT of the next stage of shift register, and the second Reset signal end Reset2 is connected with the signal OUTPUT end OUTPUT of the shift register at least one stage of lower interval; specifically, in fig. 9, the second Reset signal terminal Reset2 is connected to the signal OUTPUT terminal OUTPUT of the shift register one stage below it.
In the gate driving circuit provided in the embodiment of the present invention, by setting the first Reset signal terminal Reset1 of each shift register to be connected to the signal OUTPUT terminal OUTPUT of the next shift register, and setting the second Reset signal terminal Reset2 to be connected to the signal OUTPUT terminal OUTPUT of the shift register spaced at least one stage below the first Reset signal terminal Reset, the operating time of the Reset node Reset of each shift register is at least prolonged to the charging time of two rows of pixels, so that the shift register can be fully discharged, the discharging capability is improved, the shift register can normally operate, and the display panel can normally display.
It should be noted that those skilled in the art generally set dummy cells to provide the required signals for the first Reset signal terminal Reset1 and the second Reset signal terminal Reset2 of the shift register of the last stage.
Moreover, in this document, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (10)
1. A method of driving a shift register, comprising:
in the first stage, an input module writes the voltage of a signal input end into a pull-up node under the control of the voltage of the signal input end; the output module writes the voltage of the first clock signal end into the signal output end under the control of the voltage of the pull-up node;
in the second stage, the output module keeps the voltage difference between the pull-up node and the signal output end stable when the pull-up node is in a floating state, and writes the voltage of the first clock signal end into the signal output end under the control of the voltage of the pull-up node;
in the third stage, the reset control module writes the voltage of the first reset signal end into a reset node under the control of the voltage of the first reset signal end; the reset module writes the voltage of a reference signal end into the pull-up node and the signal output end under the control of the voltage of the reset node;
in the fourth stage, the reset control module writes the voltage of the second reset signal end into the reset node under the control of the voltage of the second reset signal end; and the reset module writes the voltage of the reference signal end into the pull-up node and the signal output end under the control of the voltage of the reset node.
2. A shift register driven by the driving method according to claim 1, comprising: the device comprises an input module, an output module, a reset module and a reset control module;
the input module is respectively connected with a signal input end and a pull-up node and is used for writing the voltage of the signal input end into the pull-up node under the control of the voltage of the signal input end;
the output module is respectively connected with a first clock signal end, the pull-up node and a signal output end, and is used for writing the voltage of the first clock signal end into the signal output end under the control of the voltage of the pull-up node and keeping the voltage difference between the pull-up node and the signal output end stable when the pull-up node is in a floating state;
the reset module is respectively connected with a reset node, the pull-up node, a reference signal end and the signal output end and is used for writing the voltage of the reference signal end into the pull-up node and the signal output end under the control of the voltage of the reset node;
the reset control module is respectively connected with the first reset signal end, the second reset signal end and the reset node and is used for writing the voltage of the first reset signal end into the reset node under the control of the voltage of the first reset signal end and writing the voltage of the second reset signal end into the reset node under the control of the voltage of the second reset signal end.
3. The shift register of claim 2, further comprising: the pull-down control module and the pull-down module;
the pull-down control module is respectively connected with a second clock signal end, a pull-down node, the pull-up node and the reference signal end, and is used for writing the voltage of the second clock signal end into the pull-down node under the control of the voltage of the second clock signal end; and writing the voltage of the reference signal terminal into the pull-down node under the control of the voltage of the pull-up node;
the pull-down module is respectively connected with the pull-up node, the pull-down node, the signal output end and the reference signal end, and is used for writing the voltage of the reference signal end into the pull-up node and the signal output end under the control of the voltage of the pull-down node.
4. A shift register as claimed in claim 2 or 3, in which the input module comprises: a first switching transistor;
the gate of the first switching transistor is connected to the signal input terminal, the first pole is connected to the signal input terminal, and the second pole is connected to the pull-up node.
5. A shift register as claimed in claim 2 or 3, in which the output module comprises: a second switching transistor and a capacitor;
the grid electrode of the second switching transistor is connected with the pull-up node, the first pole of the second switching transistor is connected with the first clock signal end, and the second pole of the second switching transistor is connected with the signal output end;
the capacitor is connected between the pull-up node and the signal output end.
6. A shift register as claimed in claim 2 or 3, in which the reset module comprises: a third switching transistor and a fourth switching transistor;
the grid electrode of the third switching transistor is connected with the reset node, the first pole of the third switching transistor is connected with the reference signal end, and the second pole of the third switching transistor is connected with the pull-up node;
and the grid electrode of the fourth switching transistor is connected with the reset node, the first electrode of the fourth switching transistor is connected with the reference signal end, and the second electrode of the fourth switching transistor is connected with the signal output end.
7. A shift register as claimed in claim 2 or 3, in which the reset control module comprises: a fifth switching transistor and a sixth switching transistor;
a grid electrode of the fifth switching transistor is connected with the first reset signal end, a first pole of the fifth switching transistor is connected with the first reset signal end, and a second pole of the fifth switching transistor is connected with the reset node;
and the grid electrode of the sixth switching transistor is connected with the second reset signal end, the first pole of the sixth switching transistor is connected with the second reset signal end, and the second pole of the sixth switching transistor is connected with the reset node.
8. The shift register of claim 3, wherein the pull-down control module comprises: a seventh switching transistor, an eighth switching transistor, a ninth switching transistor, and a tenth switching transistor;
a grid electrode of the seventh switching transistor is connected with the second clock signal end, a first pole is connected with the second clock signal end, and a second pole is connected with a first node;
a grid electrode of the eighth switching transistor is connected with the first node, a first pole of the eighth switching transistor is connected with the second clock signal end, and a second pole of the eighth switching transistor is connected with the pull-down node;
a gate of the ninth switching transistor is connected with the pull-up node, a first pole of the ninth switching transistor is connected with the reference signal end, and a second pole of the ninth switching transistor is connected with the pull-down node;
and the grid electrode of the tenth switching transistor is connected with the pull-up node, the first pole of the tenth switching transistor is connected with the reference signal end, and the second pole of the tenth switching transistor is connected with the first node.
9. The shift register of claim 3, wherein the pull-down module comprises: an eleventh switching transistor and a twelfth switching transistor;
a gate of the eleventh switching transistor is connected to the pull-down node, a first pole thereof is connected to the reference signal terminal, and a second pole thereof is connected to the pull-up node;
and the grid electrode of the twelfth switching transistor is connected with the pull-down node, the first pole of the twelfth switching transistor is connected with the reference signal end, and the second pole of the twelfth switching transistor is connected with the signal output end.
10. A gate driver circuit comprising a plurality of shift registers according to any one of claims 2 to 9 in cascade;
the signal input end of the first-stage shift register is connected with the frame trigger signal end;
except the first stage of shift register, the signal input ends of the other shift registers at each stage are respectively connected with the signal output end of the shift register at the previous stage;
the first reset signal end of each stage of shift register is connected with the signal output end of the next stage of shift register, and the second reset signal end is connected with the signal output end of the shift register at least one stage below the second reset signal end.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811055224.7A CN109036252B (en) | 2018-09-11 | 2018-09-11 | Shifting register, driving method thereof and grid driving circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811055224.7A CN109036252B (en) | 2018-09-11 | 2018-09-11 | Shifting register, driving method thereof and grid driving circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN109036252A CN109036252A (en) | 2018-12-18 |
| CN109036252B true CN109036252B (en) | 2021-08-20 |
Family
ID=64621551
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201811055224.7A Active CN109036252B (en) | 2018-09-11 | 2018-09-11 | Shifting register, driving method thereof and grid driving circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109036252B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114974153B (en) * | 2021-02-26 | 2024-01-30 | 北京京东方显示技术有限公司 | Shift register, driving circuit, driving method and display device |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102915698A (en) * | 2012-10-18 | 2013-02-06 | 京东方科技集团股份有限公司 | Shifting register unit, grid electrode drive circuit and display device |
| CN103474040A (en) * | 2013-09-06 | 2013-12-25 | 合肥京东方光电科技有限公司 | Grid electrode drive unit, grid electrode drive circuit and display device |
| KR20170078165A (en) * | 2015-12-29 | 2017-07-07 | 엘지디스플레이 주식회사 | Shift register |
| CN107274856A (en) * | 2017-08-22 | 2017-10-20 | 京东方科技集团股份有限公司 | A kind of shift register and its driving method, gate driving circuit |
| CN108389539A (en) * | 2018-03-15 | 2018-08-10 | 京东方科技集团股份有限公司 | Shift register cell, driving method, gate driving circuit and display device |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101039983B1 (en) * | 2005-03-31 | 2011-06-09 | 엘지디스플레이 주식회사 | Gate driver and display device having the same |
-
2018
- 2018-09-11 CN CN201811055224.7A patent/CN109036252B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102915698A (en) * | 2012-10-18 | 2013-02-06 | 京东方科技集团股份有限公司 | Shifting register unit, grid electrode drive circuit and display device |
| CN103474040A (en) * | 2013-09-06 | 2013-12-25 | 合肥京东方光电科技有限公司 | Grid electrode drive unit, grid electrode drive circuit and display device |
| KR20170078165A (en) * | 2015-12-29 | 2017-07-07 | 엘지디스플레이 주식회사 | Shift register |
| CN107274856A (en) * | 2017-08-22 | 2017-10-20 | 京东方科技集团股份有限公司 | A kind of shift register and its driving method, gate driving circuit |
| CN108389539A (en) * | 2018-03-15 | 2018-08-10 | 京东方科技集团股份有限公司 | Shift register cell, driving method, gate driving circuit and display device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN109036252A (en) | 2018-12-18 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN106531048B (en) | Shift register, grid driving circuit, display panel and driving method | |
| US10269282B2 (en) | Shift register, gate driving circuit, display panel and driving method | |
| US10622081B2 (en) | Shift register, gate driving circuit and display device | |
| US10803823B2 (en) | Shift register unit, gate driving circuit, and driving method | |
| US20200013473A1 (en) | Shift register, method for driving the same, gate integrated driver circuit, and display device | |
| CN107424554B (en) | Shifting register unit and driving method thereof, grid driving circuit and display device | |
| CN108597437B (en) | Shifting register, grid driving circuit, driving method of grid driving circuit and display device | |
| US10049609B2 (en) | Shift register, gate driving circuit, and display device | |
| US10283030B2 (en) | Shift register, gate driver, display panel and driving method | |
| CN107909959B (en) | Shifting register unit, driving method thereof, grid driving circuit and display device | |
| US11100841B2 (en) | Shift register, driving method thereof, gate driving circuit, and display device | |
| CN107610736B (en) | Shifting register, grid driving circuit and display device | |
| CN109410811B (en) | Shifting register, grid driving circuit and display device | |
| CN107516505B (en) | Shifting register unit and driving method thereof, grid driving circuit and display panel | |
| US11069272B2 (en) | Shift register, gate drive circuit, display panel, and driving method | |
| CN110648621B (en) | Shift register and driving method thereof, grid driving circuit and display device | |
| US20190295674A1 (en) | Shift Register Unit and Driving Method Thereof, Gate Driving Circuit, and Display Device | |
| CN109785787B (en) | Shift register, driving method thereof, gate driving circuit and display device | |
| CN109166542B (en) | Shifting register unit, driving method, grid driving circuit and display device | |
| CN111210758B (en) | Grid driving circuit and display device | |
| CN109377948B (en) | Shift register and driving method thereof, grid driving circuit and display device | |
| US11423823B2 (en) | Shift register and driving method thereof, gate driving circuit and display device capabling reset the output terminal | |
| CN110689839B (en) | Shifting register unit, driving method, grid driving circuit and display device | |
| CN107123389B (en) | Shift register, grid drive circuit and display device | |
| CN109215552B (en) | Shifting register, grid driving circuit, display panel and display device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |