CN109036252A - A kind of shift register and its driving method, gate driving circuit - Google Patents
A kind of shift register and its driving method, gate driving circuit Download PDFInfo
- Publication number
- CN109036252A CN109036252A CN201811055224.7A CN201811055224A CN109036252A CN 109036252 A CN109036252 A CN 109036252A CN 201811055224 A CN201811055224 A CN 201811055224A CN 109036252 A CN109036252 A CN 109036252A
- Authority
- CN
- China
- Prior art keywords
- node
- pull
- voltage
- reset
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
Abstract
The invention discloses a kind of shift register and its driving methods, gate driving circuit, comprising: input module, output module, reseting module and reset control module；By the first reset signal end and the second reset signal end respectively to reset control module output control signal, to realize the control to the voltage of reset node, to may make the operating time arbitrary extension of reseting module under the control of the voltage of reset node, therefore effectively increase the discharge capability of shift register.
Description
Technical field
The present invention relates to field of display technology more particularly to a kind of shift registers and its driving method, gate driving electricity
Road.
Background technique
With the rapid development of display technology, display panel increasingly develops towards the direction of high integration and low cost.
Wherein, array substrate row drives (Gate Driver on Array, GOA) technology by thin film transistor (TFT) (Thin Film
Transistor, TFT) scanning drive of the gate switch circuit integration in the array substrate of display panel with formation to display panel
It is dynamic, so as to save the binding region (Bonding) of grid integrated circuits (Integrated Circuit, IC) and be fanned out to
(Fan-out) wiring space in region not only can reduce product cost, Er Qieke in terms of material cost and preparation process two
So that display panel accomplishes that both sides are symmetrical and the design for aesthetic of narrow frame；Also, this integrated technique may be omitted with grid and sweep
The Bonding technique for retouching line direction, to improve production capacity and yield.
General gate driving circuit is made of multiple cascade shift registers, and every grade of shift register is by grid
Scanning signal successively passes to next stage shift register, opens the thin film transistor (TFT) of pixel region line by line, completes the number of pixel
It is believed that number input.However the gradually development of high refresh rate (Gaming) product, so that the charging time of every one-row pixels is increasingly
Few, corresponding shift register electric discharge is insufficient, leads to shift register cisco unity malfunction, eventually results in display panel not
It can normally show.
Summary of the invention
In view of this, the embodiment of the present invention provides a kind of shift register and its driving method, gate driving circuit, to
Improve the discharge capability of shift register.
Therefore, a kind of shift register provided in an embodiment of the present invention, comprising: input module, output module, reseting module
With reset control module；
The input module is respectively connected with signal input part, pull-up node, for the voltage in the signal input part
Control under, the pull-up node is written into the voltage of the signal input part；
The output module is respectively connected with the first clock signal terminal, the pull-up node, signal output end, in institute
Under the control for stating the voltage of pull-up node, the signal output end, Yi Ji is written into the voltage of first clock signal terminal
The pull-up node keeps the voltage difference between the pull-up node and the signal output end to stablize when being in floating；
The reseting module distinguishes phase with reset node, the pull-up node, reference signal end, the signal output end
Even, under the control of the voltage of the reset node, by the voltage at the reference signal end be written the pull-up node and
The signal output end；
The reset control module is respectively connected with the first reset signal end, the second reset signal end, the reset node,
For under the control of the voltage at first reset signal end, the reset to be written in the voltage at first reset signal end
Under node, and the control of the voltage at second reset signal end, institute is written into the voltage at second reset signal end
State reset node.
In one possible implementation, in above-mentioned shift register provided in an embodiment of the present invention, further includes: under
Draw control module and pull-down module；
The pull-down control module and second clock signal end, pull-down node, the pull-up node, the reference signal end
It is respectively connected with, under the control of the voltage of the second clock signal end, the voltage of the second clock signal end to be write
Enter the pull-down node；And under the control of the voltage in the pull-up node, institute is written into the voltage at the reference signal end
State pull-down node；
The pull-down module and the pull-up node, the pull-down node, the signal output end, the reference signal end
It is respectively connected with, under the control of the voltage of the pull-down node, the pull-up to be written in the voltage at the reference signal end
Node and the signal output end.
In one possible implementation, in above-mentioned shift register provided in an embodiment of the present invention, the input
Module, comprising: first switch transistor；
The grid of the first switch transistor is connected with the signal input part, the first pole and the signal input part phase
Even, the second pole is connected with the pull-up node.
In one possible implementation, in above-mentioned shift register provided in an embodiment of the present invention, the output
Module, comprising: second switch transistor and capacitor；
The grid of the second switch transistor is connected with the pull-up node, the first pole and first clock signal terminal
It is connected, the second pole is connected with the signal output end；
The capacitance connection is between the pull-up node and the signal output end.
In one possible implementation, in above-mentioned shift register provided in an embodiment of the present invention, the reset
Module, comprising: third switching transistor and the 4th switching transistor；
The grid of the third switching transistor is connected with the reset node, the first pole and reference signal end phase
Even, the second pole is connected with the pull-up node；
The grid of 4th switching transistor is connected with the reset node, the first pole and reference signal end phase
Even, the second pole is connected with the signal output end.
In one possible implementation, in above-mentioned shift register provided in an embodiment of the present invention, the reset
Control module, comprising: the 5th switching transistor and the 6th switching transistor；
The grid of 5th switching transistor is connected with first reset signal end, and the first pole and described first resets
Signal end is connected, and the second pole is connected with the reset node；
The grid of 6th switching transistor is connected with second reset signal end, and the first pole and described second resets
Signal end is connected, and the second pole is connected with the reset node.
In one possible implementation, in above-mentioned shift register provided in an embodiment of the present invention, the drop-down
Control module, comprising: the 7th switching transistor, the 8th switching transistor, the 9th switching transistor and the tenth switching transistor；
The grid of 7th switching transistor is connected with the second clock signal end, the first pole and the second clock
Signal end is connected, and the second pole is connected with first node；
The grid of 8th switching transistor is connected with the first node, the first pole and the second clock signal end
It is connected, the second pole is connected with the pull-down node；
The grid of 9th switching transistor is connected with the pull-up node, the first pole and reference signal end phase
Even, the second pole is connected with the pull-down node；
The grid of tenth switching transistor is connected with the pull-up node, the first pole and reference signal end phase
Even, the second pole is connected with the first node.
In one possible implementation, in above-mentioned shift register provided in an embodiment of the present invention, the drop-down
Module, comprising: the 11st switching transistor and the 12nd switching transistor；
The grid of 11st switching transistor is connected with the pull-down node, the first pole and reference signal end phase
Even, the second pole is connected with the pull-up node；
The grid of 12nd switching transistor is connected with the pull-down node, the first pole and reference signal end phase
Even, the second pole is connected with the signal output end.
Correspondingly, the embodiment of the invention also provides a kind of driving methods of above-mentioned shift register, comprising:
First stage, input module write the voltage of the signal input part under the control of the voltage of signal input part
Enter pull-up node；Letter is written under the control of the voltage of the pull-up node, by the voltage of the first clock signal terminal in output module
Number output end；
Second stage, the output module keep the pull-up node and institute when the pull-up node is in floating
The voltage difference stated between signal output end is stablized, and believes first clock under the control of the voltage in the pull-up node
The signal output end is written in the voltage at number end；
Phase III resets control module under the control of the voltage at the first reset signal end, described first is resetted and is believed
Number end voltage be written reset node；Reseting module is under the control of the voltage of the reset node, by the electricity at reference signal end
The pull-up node and the signal output end is written in pressure；
Fourth stage is answered under the control of voltage of the reset control module at the second reset signal end by described second
The reset node is written in the voltage of position signal end；The reseting module is under the control of the voltage of the reset node, by institute
The pull-up node and the signal output end is written in the voltage for stating reference signal end.
Based on the same inventive concept, the embodiment of the invention also provides a kind of gate driving circuit, including it is cascade multiple
Above-mentioned shift register；
The signal input part of first order shift register is connected with frame trigger signal end；
In addition to the first order shift register, the signal input part of remaining shift register at different levels respectively with upper level
Shift register signal output end be connected；
First reset signal end of shift registers at different levels is connected with the signal output end of next stage shift register, and second
Reset signal end is connected with the signal output end of the shift register of its lower interval at least one level.
The present invention has the beneficial effect that:
Shift register and its driving method provided in an embodiment of the present invention, gate driving circuit, comprising: input module,
Output module, reseting module and reset control module；Input module is respectively connected with signal input part, pull-up node, is used for
Under the control of the voltage of signal input part, the voltage write-in pull-up node at end is input a signal into；Output module and the first clock are believed
Number end, pull-up node, signal output end are respectively connected with, under the control of the voltage of pull-up node, by the first clock signal
Signal output end is written in the voltage at end, and keep when pull-up node be in floating pull-up node and signal output end it
Between voltage difference stablize；Reseting module is respectively connected with reset node, pull-up node, reference signal end, signal output end, is used for
Under the control of the voltage of reset node, pull-up node and signal output end is written into the voltage at reference signal end；Reset control
Module is respectively connected with the first reset signal end, the second reset signal end, reset node, for the electricity at the first reset signal end
Under the control of pressure, reset node, and the control of the voltage at the second reset signal end is written into the voltage at the first reset signal end
Under system, reset node is written into the voltage at the second reset signal end.Pass through the first reset signal end and the second reset signal end point
Not to control module output control signal is resetted, to realize the control to the voltage of reset node, thus in the electricity of reset node
It may make the operating time arbitrary extension of reseting module under the control of pressure, therefore effectively increase the electric discharge energy of shift register
Power.
Detailed description of the invention
Fig. 1 is the structural schematic diagram for the shift register that the embodiment of the present invention one provides；
Fig. 2 is the flow chart of the driving method for the shift register that the embodiment of the present invention one provides；
Fig. 3 is a kind of concrete structure schematic diagram of shift register shown in Fig. 1；
Fig. 4 is the working timing figure of shift register shown in Fig. 3；
Fig. 5 is the structural schematic diagram of shift register provided by Embodiment 2 of the present invention；
Fig. 6 is the flow chart of the driving method of shift register provided by Embodiment 2 of the present invention；
Fig. 7 is a kind of concrete structure schematic diagram of shift register shown in Fig. 5；
Fig. 8 is the working timing figure of shift register shown in Fig. 7；
Fig. 9 is the structural schematic diagram for the gate driving circuit that the embodiment of the present invention three provides.
Specific embodiment
With reference to the accompanying drawing, to shift register provided in an embodiment of the present invention and its driving method, gate driving circuit
Specific embodiment be described in detail.It should be noted that this specification described embodiment is only the present invention one
Section Example, instead of all the embodiments；And in the absence of conflict, in the embodiment and embodiment in the application
Feature can be combined with each other；In addition, based on the embodiments of the present invention, those of ordinary skill in the art are not making creation
Property labour under the premise of all other embodiment obtained, shall fall within the protection scope of the present invention.
Embodiment one
A kind of shift register that the embodiment of the present invention one provides, as shown in Figure 1, comprising: input module 101 exports mould
Block 102, reseting module 103 and reset control module 104；
Input module 101 and signal input part INPUT, pull-up node PU are respectively connected with, in signal input part INPUT
Voltage control under, input a signal into end INPUT voltage write-in pull-up node PU；
Output module 102 is respectively connected with the first clock signal terminal CLKA, pull-up node PU, signal output end OUTPUT,
For under the control of the voltage of pull-up node PU, signal output end to be written in the voltage of the first clock signal terminal CLKA
OUTPUT, and the electricity when pull-up node PU is in floating between holding pull-up node PU and signal output end OUTPUT
Pressure difference is stablized；
Reseting module 103 and reset node Reset, pull-up node PU, reference signal end VSS, signal output end OUTPUT
It is respectively connected with, under the control of the voltage of reset node Reset, pull-up node to be written in the voltage of reference signal end VSS
PU and signal output end OUTPUT；
Reset control module 104 and the first reset signal end Reset1, the second reset signal end Reset2, reset node
Reset is respectively connected with, under the control of the voltage of the first reset signal end Reset1, by the first reset signal end Reset1
Voltage write-in reset node Reset, and the control of the voltage in the second reset signal end Reset2 under, by second reset believe
Number end Reset2 voltage be written reset node Reset.
In the above-mentioned shift register that the embodiment of the present invention one provides, pass through the first reset signal end Reset1 and second
Reset signal end Reset2 is respectively to the output control signal of control module 107 is resetted, to realize the voltage to reset node Reset
Control, to may make the operating time arbitrary extension of reseting module 106 under the control of the voltage of reset node Reset,
Therefore the discharge capability for effectively increasing shift register, ensure that shift register can work normally.
Correspondingly, for above-mentioned shift register, the embodiment of the present invention one additionally provides a kind of driving method, such as Fig. 2 institute
Show, comprising:
S201, first stage, input module under the control of the voltage of signal input part, write by the voltage for inputting a signal into end
Enter pull-up node；Output module is defeated by the voltage write-in signal of the first clock signal terminal under the control of the voltage of pull-up node
Outlet；
S202, second stage, output module keep pull-up node and signal to export when pull-up node is in floating
Voltage difference between end is stablized, and signal is written in the voltage of the first clock signal terminal under the control of the voltage of pull-up node
Output end；
S203, phase III reset control module under the control of the voltage at the first reset signal end, first are resetted and is believed
Number end voltage be written reset node；Reseting module writes the voltage at reference signal end under the control of the voltage of reset node
Enter pull-up node and signal output end；
S204, fourth stage reset control module under the control of the voltage at the second reset signal end, second are resetted and is believed
Number end voltage be written reset node；Reseting module writes the voltage at reference signal end under the control of the voltage of reset node
Enter pull-up node and signal output end.
The structure and working principle for the above-mentioned shift register that embodiment one provides for a better understanding of the present invention, below
It is described in detail with a specific embodiment.
Specifically, the shift register of structure shown in Fig. 3 is the one kind for the shift register that the embodiment of the present invention one provides
Possible implementation.
As shown in figure 3, input module 101, comprising: first switch transistor M1；The grid of first switch transistor M1 with
Signal input part INPUT is connected, and the first pole is connected with signal input part INPUT, and the second pole is connected with pull-up node PU.
Output module 102, comprising: second switch transistor M2 and capacitor C；The grid and pull-up of second switch transistor M2
Node PU is connected, and the first pole is connected with the first clock signal terminal CLKA, and the second pole is connected with signal output end OUTPUT；Capacitor C
It is connected between pull-up node PU and signal output end OUTPUT.
Reseting module 103, comprising: third switching transistor M3 and the 4th switching transistor M4；Third switching transistor M3
Grid be connected with reset node Reset, the first pole is connected with reference signal end VSS, and the second pole is connected with pull-up node PU；The
The grid of four switching transistor M4 is connected with reset node Reset, and the first pole is connected with reference signal end VSS, the second pole and letter
Number output end OUTPUT is connected.
Reset control module 104, comprising: the 5th switching transistor M5 and the 6th switching transistor M6；5th switch crystal
The grid of pipe M5 is connected with the first reset signal end Reset1, and the first pole is connected with the first reset signal end Reset1, the second pole
It is connected with reset node Reset；The grid of 6th switching transistor M6 is connected with the second reset signal end Reset2, the first pole with
Second reset signal end Reset2 is connected, and the second pole is connected with reset node Reset.
It should be noted that the above is only each moulds in the above-mentioned shift register for illustrating the present invention the offer of embodiment one
The specific structure of block, in the specific implementation, the specific structure of each module are not limited to above structure provided in an embodiment of the present invention, also
Can be skilled person will appreciate that other structures, it is not limited here.
Also, transistor mentioned in the present invention can be thin film transistor (TFT) (TFT, Thin Film Transistor),
It is also possible to metal oxide semiconductor field effect tube (MOS, Metal Oxide Semiconductor), it is not limited here.
In specific implementation, the first pole and the second pole of these transistors are respectively to drain and source electrode, according to transistor types and defeated
Enter the difference of signal, function can be interchanged, and not do specific differentiation herein.Generally, when transistor is P-type transistor, the
One extremely source electrode, second extremely drains；When transistor is N-type transistor, first extremely drains, the second extremely source electrode.
The shift register course of work shown in Fig. 3 is described below, wherein shift register shown in Fig. 3
In, each transistor is N-type transistor, is connected under action of high voltage, is ended under low-voltage effect；Shift register pair
The working timing figure answered selects first stage T1 in working timing figure shown in Fig. 4, second stage as shown in figure 4, specifically
It describes in detail for T2, phase III T3 and fourth stage T4.
First stage T1: signal input part INPUT output HIGH voltage, the first reset signal end Reset1 export low-voltage,
Second reset signal end Reset2 exports low-voltage, and the first clock signal terminal CLKA exports low-voltage.
First switch transistor M1 is in the conductive state under the control of the high voltage of signal input part INPUT, and signal is defeated
Enter to hold first switch transistor M1 write-in pull-up node PU of the high voltage of INPUT through being connected, and charges to capacitor C.The
Two switching transistor M2 are in the conductive state under the control of the high voltage of pull-up node PU, the first clock signal terminal CLKA's
Signal output end OUTPUT is written in second switch transistor M2 of the low-voltage through being connected.
Second stage T2: signal input part INPUT output low-voltage, the first reset signal end Reset1 export low-voltage,
Second reset signal end Reset2 exports low-voltage, the first clock signal terminal CLKA output HIGH voltage.
Because of the boot strap of capacitor C, so that the current potential of pull-up node PU maintains high voltage, second switch transistor M2 is upper
Draw node PU high voltage control under, it is in the conductive state, the high voltage of the first clock signal terminal CLKA through being connected second
Signal output end OUTPUT is written in switching transistor M2.
Phase III T3: signal input part INPUT output low-voltage, the first reset signal end Reset1 output HIGH voltage,
Second reset signal end Reset2 exports low-voltage, and the first clock signal terminal CLKA exports low-voltage.
5th switching transistor M5 is in the conductive state under the control of the high voltage of the first reset signal end Reset1,
So that reset node Reset is written in the 5th switching transistor M5 of the high voltage of the first reset signal end Reset1 through being connected.The
Three switching transistor M3 are in the conductive state under the control of the high voltage of reset node Reset, so that reference signal end VSS
Third switching transistor M3 of the low-voltage through being connected pull-up node PU is written, realize the reset to pull-up node PU.4th opens
Transistor M4 is closed under the control of the high voltage of reset node Reset, it is in the conductive state, so that reference signal end VSS's is low
Signal output end OUTPUT is written in the 4th switching transistor M4 of the voltage through being connected, and signal output end OUTPUT is answered in realization
Position.
Fourth stage T4: signal input part INPUT output low-voltage, the first reset signal end Reset1 export low-voltage,
Second reset signal end Reset2 output HIGH voltage, the first clock signal terminal CLKA output HIGH voltage.
6th switching transistor M6 is in the conductive state under the control of the high voltage of the second reset signal end Reset2,
So that reset node Reset is written in the 6th switching transistor M6 of the high voltage of the second reset signal end Reset2 through being connected.The
Three switching transistor M3 are in the conductive state under the control of the high voltage of reset node Reset, so that reference signal end VSS
Third switching transistor M3 of the low-voltage through being connected pull-up node PU is written, further realize the reset to pull-up node PU.
4th switching transistor M4 is in the conductive state under the control of the high voltage of reset node Reset, so that reference signal end
Signal output end OUTPUT is written in the 4th switching transistor M4 of the low-voltage of VSS through being connected, and further realizes and exports to signal
Hold the reset of OUTPUT.
Period hereafter, shift register will repeat the process of above-mentioned T1-T4.
Seen from the above description, in shift register provided in an embodiment of the present invention, pass through the first reset signal end
Reset1 and the second reset signal end Reset2 control the voltage to reset node Reset respectively, so that in reset node Reset
Voltage control under, the electric discharge duration (i.e. the reset duration of pull-up node PU and signal output end OUTPUT) of shift register
By arbitrary extension, therefore effectively increase the discharge capability of shift register.
Embodiment two
A kind of shift register provided by Embodiment 2 of the present invention, as shown in Figure 5, comprising: input module 101 exports mould
Block 102, reseting module 103 reset control module 104, pull-down control module 105 and pull-down module 106；
Input module 101 and signal input part INPUT, pull-up node PU are respectively connected with, in signal input part INPUT
Voltage control under, input a signal into end INPUT voltage write-in pull-up node PU；
Output module 102 is respectively connected with the first clock signal terminal CLKA, pull-up node PU, signal output end OUTPUT,
For under the control of the voltage of pull-up node PU, signal output end to be written in the voltage of the first clock signal terminal CLKA
OUTPUT, and the electricity when pull-up node PU is in floating between holding pull-up node PU and signal output end OUTPUT
Pressure difference is stablized；
Reseting module 103 and reset node Reset, pull-up node PU, reference signal end VSS, signal output end OUTPUT
It is respectively connected with, under the control of the voltage of reset node Reset, pull-up node to be written in the voltage of reference signal end VSS
PU and signal output end OUTPUT；
Reset control module 104 and the first reset signal end Reset1, the second reset signal end Reset2, reset node
Reset is respectively connected with, under the control of the voltage of the first reset signal end Reset1, by the first reset signal end Reset1
Voltage write-in reset node Reset, and the control of the voltage in the second reset signal end Reset2 under, by second reset believe
Number end Reset2 voltage be written reset node Reset；
Pull-down control module 105 and second clock signal end CLKB, pull-up node PU, pull-down node PD, reference signal end
VSS is respectively connected with, under the control of the voltage of second clock signal end CLKB, by the voltage of second clock signal end CLKB
Pull-down node PD is written；And under the control of the voltage in pull-up node PU, by the voltage write-in drop-down section of reference signal end VSS
Point PD；
Pull-down module 106 and pull-up node PU, pull-down node PD, signal output end OUTPUT, reference signal end VSS distinguish
It is connected, under the control of the voltage of pull-down node PD, pull-up node PU and signal to be written in the voltage of reference signal end VSS
Output end OUTPUT.
In above-mentioned shift register provided by Embodiment 2 of the present invention, pass through the first reset signal end Reset1 and second
Reset signal end Reset2 is respectively to the output control signal of control module 107 is resetted, to realize the voltage to reset node Reset
Control, to may make the operating time arbitrary extension of reseting module 106 under the control of the voltage of reset node Reset,
Therefore the discharge capability for effectively increasing shift register, ensure that shift register can work normally.
Correspondingly, for above-mentioned shift register, the embodiment of the present invention two additionally provides a kind of driving method, such as Fig. 6 institute
Show, comprising:
S601, first stage, input module under the control of the voltage of signal input part, write by the voltage for inputting a signal into end
Enter pull-up node；Pull-down control module is under the control of the voltage of pull-up node, by the voltage write-in drop-down section at reference signal end
Point；Signal output end is written under the control of the voltage of pull-up node, by the voltage of the first clock signal terminal in output module；
S602, second stage, pull-down control module is under the control of the voltage of pull-up node, by the voltage at reference signal end
Pull-down node is written；Output module keeps the electricity between pull-up node and signal output end when pull-up node is in floating
Pressure difference is stablized, and signal output end is written in the voltage of the first clock signal terminal under the control of the voltage of pull-up node；
S603, phase III, pull-down control module believe second clock under the control of the voltage of second clock signal end
Number end voltage be written pull-down node；Pull-down module writes the voltage at reference signal end under the control of the voltage of pull-down node
Enter pull-up node and signal output end；Control module is resetted under the control of the voltage at the first reset signal end, and first is resetted
Reset node is written in the voltage of signal end；Reseting module is under the control of the voltage of reset node, by the voltage at reference signal end
Pull-up node and signal output end is written；
S604, fourth stage reset control module under the control of the voltage at the second reset signal end, second are resetted and is believed
Number end voltage be written reset node；Reseting module writes the voltage at reference signal end under the control of the voltage of reset node
Enter pull-up node and signal output end.
The structure and working principle for the above-mentioned shift register that embodiment two provides for a better understanding of the present invention, below
It is described in detail with a specific embodiment.
Specifically, the shift register of structure shown in Fig. 7 is one kind of shift register provided by Embodiment 2 of the present invention
Possible implementation.
As shown in fig. 7, input module 101, comprising: first switch transistor M1；The grid of first switch transistor M1 with
Signal input part INPUT is connected, and the first pole is connected with signal input part INPUT, and the second pole is connected with pull-up node PU.
Output module 102, comprising: second switch transistor M2 and capacitor C；The grid and pull-up of second switch transistor M2
Node PU is connected, and the first pole is connected with the first clock signal terminal CLKA, and the second pole is connected with signal output end OUTPUT；Capacitor C
It is connected between pull-up node PU and signal output end OUTPUT.
Reseting module 103, comprising: third switching transistor M3 and the 4th switching transistor M4；Third switching transistor M3
Grid be connected with reset node Reset, the first pole is connected with reference signal end VSS, and the second pole is connected with pull-up node PU；The
The grid of four switching transistor M4 is connected with reset node Reset, and the first pole is connected with reference signal end VSS, the second pole and letter
Number output end OUTPUT is connected.
Reset control module 104, comprising: the 5th switching transistor M5 and the 6th switching transistor M6；5th switch crystal
The grid of pipe M5 is connected with the first reset signal end Reset1, and the first pole is connected with the first reset signal end Reset1, the second pole
It is connected with reset node Reset；The grid of 6th switching transistor M6 is connected with the second reset signal end Reset2, the first pole with
Second reset signal end Reset2 is connected, and the second pole is connected with reset node Reset.
Pull-down control module 105, comprising: the 7th switching transistor M7, the 8th switching transistor M8, the 9th switching transistor
M9 and the tenth switching transistor M10；The grid M7 of 7th switching transistor is connected with second clock signal end CLKB, the first pole with
Second clock signal end CLKB is connected, and the second pole is connected with first node P1；The grid and first segment of 8th switching transistor M8
Point P1 is connected, and the first pole is connected with second clock signal end CLKB, and the second pole is connected with pull-down node PD；9th switching transistor
The grid of M9 is connected with pull-up node PU, and the first pole is connected with reference signal end VSS, and the second pole is connected with pull-down node PD；The
The grid of ten switching transistor M10 is connected with pull-up node PU, and the first pole is connected with reference signal end VSS, the second pole and first
Node P1 is connected.
Pull-down module 106, comprising: the 11st switching transistor M11 and the 12nd switching transistor M12；11st switch
The grid of transistor M11 is connected with pull-down node PD, and the first pole is connected with reference signal end VSS, the second pole and pull-up node PU
It is connected；The grid of 12nd switching transistor M12 is connected with pull-down node PD, and the first pole is connected with reference signal end VSS, and second
Pole is connected with signal output end OUTPUT.
It should be noted that the above is only each moulds in the above-mentioned shift register for illustrating the present invention the offer of embodiment two
The specific structure of block, in the specific implementation, the specific structure of each module are not limited to above structure provided in an embodiment of the present invention, also
Can be skilled person will appreciate that other structures, it is not limited here.
Also, transistor mentioned in the present invention can be thin film transistor (TFT) (TFT, Thin Film Transistor),
It is also possible to metal oxide semiconductor field effect tube (MOS, Metal Oxide Semiconductor), it is not limited here.
In specific implementation, the first pole and the second pole of these transistors are respectively to drain and source electrode, according to transistor types and defeated
Enter the difference of signal, function can be interchanged, and not do specific differentiation herein.Generally, when transistor is P-type transistor, the
One extremely source electrode, second extremely drains；When transistor is N-type transistor, first extremely drains, the second extremely source electrode.
The shift register course of work shown in Fig. 7 is described below, wherein shift register shown in Fig. 7
In, each transistor is N-type transistor, is connected under action of high voltage, is ended under low-voltage effect；Shift register pair
The working timing figure answered selects first stage T1 in working timing figure shown in Fig. 8, second stage as shown in figure 8, specifically
It describes in detail for T2, phase III T3 and fourth stage T4.
First stage T1: signal input part INPUT output HIGH voltage, the first reset signal end Reset1 export low-voltage,
Second reset signal end Reset2 exports low-voltage, and the first clock signal terminal CLKA exports low-voltage, second clock signal end
CLKB output HIGH voltage.
First switch transistor M1 is in the conductive state under the control of the high voltage of signal input part INPUT, and signal is defeated
Enter to hold first switch transistor M1 write-in pull-up node PU of the high voltage of INPUT through being connected, and charges to capacitor C.The
Ten switching transistor M10 are in the conductive state under the control of the high voltage of pull-up node PU, the low electricity of reference signal end VSS
Press the tenth switching transistor M10 through being connected that first node P1 is written, so that the 8th switching transistor M8 is first node P1's
Under the control of low-voltage, it is in off state, so that pull-down node PD will not be written in the high level of second clock signal end CLKB.
Meanwhile the 9th switching transistor M9 under the control of the high voltage of pull-up node PU, in the conductive state, reference signal end VSS
Nineth switching transistor M9 of the low-voltage through being connected pull-down node PD is written, cause the 11st switching transistor M11 and the tenth
Two switching transistor M12 are in off state under the control of the low-voltage of pull-down node PD, thus will not be to pull-up node
The current potential of PU and signal output end OUTPUT impact.In addition, high voltage of the second switch transistor M2 in pull-up node PU
Control under, it is in the conductive state, the low-voltage of the first clock signal terminal CLKA through being connected second switch transistor M2 write-in
Signal output end OUTPUT.
Second stage T2: signal input part INPUT output low-voltage, the first reset signal end Reset1 export low-voltage,
Second reset signal end Reset2 exports low-voltage, the first clock signal terminal CLKA output HIGH voltage, second clock signal end
CLKB exports low-voltage.
Because of the boot strap of capacitor C, so that the current potential of pull-up node PU maintains high voltage, the 9th switching transistor M9 is upper
In the conductive state under the control for drawing the high voltage of node PU, nineth switch of the low-voltage of reference signal end VSS through being connected is brilliant
Pull-down node PD is written in body pipe M9, causes the 11st switching transistor M11 and the 12nd switching transistor M12 in pull-down node PD
Low-voltage control under, off state is in, thus will not be to the current potential of pull-up node PU and signal output end OUTPUT
It impacts.In addition, second switch transistor M2 is under the control of the high voltage of pull-up node PU, and it is in the conductive state, first
Signal output end OUTPUT is written in second switch transistor M2 of the high voltage of clock signal terminal CLKA through being connected.
Phase III T3: signal input part INPUT output low-voltage, the first reset signal end Reset1 output HIGH voltage,
Second reset signal end Reset2 exports low-voltage, and the first clock signal terminal CLKA exports low-voltage, second clock signal end
CLKB output HIGH voltage.
7th switching transistor M7 is in the conductive state under the control of the high voltage of second clock signal end CLKB, makes
It obtains seventh switching transistor M7 of the high voltage of second clock signal end CLKB through being connected and first node P1 is written.8th switch is brilliant
Body pipe M8 is in the conductive state under the control of the high voltage of first node P1, so that the height electricity of second clock signal end CLKB
Press the 8th switching transistor M8 through being connected that pull-down node PD is written.Height of the 11st switching transistor M11 in pull-down node PD
It is in the conductive state under the control of voltage, so that ten one switching transistor of the low-voltage of reference signal end VSS through being connected
Pull-up node PU is written in M11, drags down the current potential of pull-up node PU.Height electricity of the 12nd switching transistor M12 in pull-down node PD
It is in the conductive state under the control of pressure, so that ten two switching transistor M12 of the low-voltage of reference signal end VSS through being connected
Signal output end OUTPUT is written, drags down signal output end OUTPUT current potential.5th switching transistor M5 is in the first reset signal
It is in the conductive state under the control for holding the high voltage of Reset1, so that the high voltage of the first reset signal end Reset1 is through being connected
The 5th switching transistor M5 be written reset node Reset.High voltage of the third switching transistor M3 in reset node Reset
It is in the conductive state under control, so that pull-up is written in third switching transistor M3 of the low-voltage of reference signal end VSS through being connected
Node PU realizes the reset to pull-up node PU.Control of the 4th switching transistor M4 in the high voltage of reset node Reset
Under, it is in the conductive state, so that fourth switching transistor M4 write-in signal output of the low-voltage of reference signal end VSS through being connected
OUTPUT is held, realizes the reset to signal output end OUTPUT.
Fourth stage T4: signal input part INPUT output low-voltage, the first reset signal end Reset1 export low-voltage,
Second reset signal end Reset2 output HIGH voltage, the first clock signal terminal CLKA output HIGH voltage, second clock signal end
CLKB exports low-voltage.
6th switching transistor M6 is in the conductive state under the control of the high voltage of the second reset signal end Reset2,
So that reset node Reset is written in the 6th switching transistor M6 of the high voltage of the second reset signal end Reset2 through being connected.The
Three switching transistor M3 are in the conductive state under the control of the high voltage of reset node Reset, so that reference signal end VSS
Third switching transistor M3 of the low-voltage through being connected pull-up node PU is written, further realize the reset to pull-up node PU.
4th switching transistor M4 is in the conductive state under the control of the high voltage of reset node Reset, so that reference signal end
Signal output end OUTPUT is written in the 4th switching transistor M4 of the low-voltage of VSS through being connected, and further realizes and exports to signal
Hold the reset of OUTPUT.
Period hereafter, shift register will repeat the process of above-mentioned T1-T4.
Seen from the above description, in shift register provided in an embodiment of the present invention, pass through the first reset signal end
Reset1 and the second reset signal end Reset2 control the voltage to reset node Reset respectively, so that in reset node Reset
Voltage control under, the electric discharge duration (i.e. the reset duration of pull-up node PU and signal output end OUTPUT) of shift register
By arbitrary extension, therefore effectively increase the discharge capability of shift register.
Embodiment three
Based on the same inventive concept, the embodiment of the present invention three provides a kind of gate driving circuit, due to the gate driving
The principle that circuit solves the problems, such as is similar to the principle that above-mentioned shift register solves the problems, such as, therefore, the embodiment of the present invention three provides
The gate driving circuit implementation may refer to the embodiment of the present invention one, two offer above-mentioned shift register implementation, weight
Multiple place repeats no more.
Specifically, the gate driving circuit that the embodiment of the present invention three provides, as shown in figure 9, including cascade multiple hairs
The above-mentioned shift register that bright embodiment one or two provides；
The signal input part INPUT of first order shift register A1 is connected with frame trigger signal end STA；
In addition to first order shift register A1, the signal input part INPUT of remaining shift register at different levels respectively with it is upper
The signal output end OUTPUT of the shift register of level-one is connected；
The signal output end of first reset signal end Reset1 and next stage shift register of shift registers at different levels
OUTPUT is connected, the signal output end of the shift register of the second reset signal end Reset2 and its lower interval at least one level
OUTPUT is connected；Specifically, in Fig. 9, the letter of the shift register of the second reset signal end Reset2 and its lower interval level-one
Number output end OUTPUT is connected.
It is multiple by shift registers at different levels are arranged first in above-mentioned gate driving circuit provided in an embodiment of the present invention
Position signal end Reset1 be connected with the signal output end OUTPUT of next stage shift register, the second reset signal end Reset2 and
The signal output end OUTPUT of the shift register of its lower interval at least one level is connected, so that the reset section of shift register at different levels
The working time of point Reset at least extends to the charging time of two row pixels, to ensure that shift register can carry out sufficiently
Electric discharge, improves discharge capability, so that shift register can be normally carried out work, display panel can normally be shown.
It should be noted that it is afterbody shift register that those skilled in the art, which generally pass through setting dummy unit,
The first reset signal end Reset1 and the second reset signal end Reset2 provide desired signal.
In addition, herein, such as first and second etc relational terms be used merely to by an entity or operation with
Another entity or operation distinguish, and without necessarily requiring or implying between these entities or operation, there are any this realities
The relationship or sequence on border.
Obviously, various changes and modifications can be made to the invention without departing from essence of the invention by those skilled in the art
Mind and range.In this way, if these modifications and changes of the present invention belongs to the range of the claims in the present invention and its equivalent technologies
Within, then the present invention is also intended to include these modifications and variations.
Claims (10)
1. a kind of shift register characterized by comprising input module, output module, reseting module and reset control mould
Block；
The input module is respectively connected with signal input part, pull-up node, the control for the voltage in the signal input part
Under system, the pull-up node is written into the voltage of the signal input part；
The output module is respectively connected with the first clock signal terminal, the pull-up node, signal output end, for described
Under the control for drawing the voltage of node, the signal output end is written into the voltage of first clock signal terminal, and described
Pull-up node keeps the voltage difference between the pull-up node and the signal output end to stablize when being in floating；
The reseting module is respectively connected with reset node, the pull-up node, reference signal end, the signal output end, is used
Under the control in the voltage of the reset node, the pull-up node and the letter is written into the voltage at the reference signal end
Number output end；
The reset control module is respectively connected with the first reset signal end, the second reset signal end, the reset node, is used for
Under the control of the voltage at first reset signal end, the reset is written into the voltage at first reset signal end and is saved
Under point, and the control of the voltage at second reset signal end, described in the voltage write-in by second reset signal end
Reset node.
2. shift register as described in claim 1, which is characterized in that further include: pull-down control module and pull-down module；
The pull-down control module and second clock signal end, pull-down node, the pull-up node, the reference signal end are distinguished
It is connected, under the control of the voltage of the second clock signal end, institute to be written in the voltage of the second clock signal end
State pull-down node；And under the control of the voltage in the pull-up node, by the write-in of the voltage at the reference signal end it is described under
Draw node；
The pull-down module and the pull-up node, the pull-down node, the signal output end, the reference signal end are distinguished
It is connected, under the control of the voltage of the pull-down node, the pull-up node to be written in the voltage at the reference signal end
With the signal output end.
3. shift register as claimed in claim 1 or 2, which is characterized in that the input module, comprising: first switch is brilliant
Body pipe；
The grid of the first switch transistor is connected with the signal input part, and the first pole is connected with the signal input part,
Second pole is connected with the pull-up node.
4. shift register as claimed in claim 1 or 2, which is characterized in that the output module, comprising: second switch is brilliant
Body pipe and capacitor；
The grid of the second switch transistor is connected with the pull-up node, the first pole and the first clock signal terminal phase
Even, the second pole is connected with the signal output end；
The capacitance connection is between the pull-up node and the signal output end.
5. shift register as claimed in claim 1 or 2, which is characterized in that the reseting module, comprising: third switch is brilliant
Body pipe and the 4th switching transistor；
The grid of the third switching transistor is connected with the reset node, and the first pole is connected with the reference signal end, the
Two poles are connected with the pull-up node；
The grid of 4th switching transistor is connected with the reset node, and the first pole is connected with the reference signal end, the
Two poles are connected with the signal output end.
6. shift register as claimed in claim 1 or 2, which is characterized in that the reset control module, comprising: the 5th opens
Close transistor and the 6th switching transistor；
The grid of 5th switching transistor is connected with first reset signal end, the first pole and first reset signal
End is connected, and the second pole is connected with the reset node；
The grid of 6th switching transistor is connected with second reset signal end, the first pole and second reset signal
End is connected, and the second pole is connected with the reset node.
7. shift register as claimed in claim 2, which is characterized in that the pull-down control module, comprising: the 7th switch is brilliant
Body pipe, the 8th switching transistor, the 9th switching transistor and the tenth switching transistor；
The grid of 7th switching transistor is connected with the second clock signal end, the first pole and the second clock signal
End is connected, and the second pole is connected with first node；
The grid of 8th switching transistor is connected with the first node, the first pole and the second clock signal end phase
Even, the second pole is connected with the pull-down node；
The grid of 9th switching transistor is connected with the pull-up node, and the first pole is connected with the reference signal end, the
Two poles are connected with the pull-down node；
The grid of tenth switching transistor is connected with the pull-up node, and the first pole is connected with the reference signal end, the
Two poles are connected with the first node.
8. shift register as claimed in claim 2, which is characterized in that the pull-down module, comprising: the 11st switch crystal
Pipe and the 12nd switching transistor；
The grid of 11st switching transistor is connected with the pull-down node, and the first pole is connected with the reference signal end,
Second pole is connected with the pull-up node；
The grid of 12nd switching transistor is connected with the pull-down node, and the first pole is connected with the reference signal end,
Second pole is connected with the signal output end.
9. a kind of driving method of such as described in any item shift registers of claim 1-8 characterized by comprising
First stage, input module, will be in the voltage write-ins of the signal input part under the control of the voltage of signal input part
Draw node；Output module is defeated by the voltage write-in signal of the first clock signal terminal under the control of the voltage of the pull-up node
Outlet；
Second stage, the output module keep the pull-up node and the letter when the pull-up node is in floating
Voltage difference between number output end is stablized, and by first clock signal terminal under the control of the voltage in the pull-up node
Voltage the signal output end is written；
Phase III resets control module under the control of the voltage at the first reset signal end, by first reset signal end
Voltage be written reset node；Reseting module writes the voltage at reference signal end under the control of the voltage of the reset node
Enter the pull-up node and the signal output end；
Fourth stage resets described second and believes under the control of voltage of the reset control module at the second reset signal end
The reset node is written in the voltage at number end；The reseting module is under the control of the voltage of the reset node, by the ginseng
The pull-up node and the signal output end is written in the voltage for examining signal end.
10. a kind of gate driving circuit, which is characterized in that including cascade multiple such as the described in any item shiftings of claim 1-8
Bit register；
The signal input part of first order shift register is connected with frame trigger signal end；
In addition to the first order shift register, the signal input part of remaining shift register at different levels respectively with the shifting of upper level
The signal output end of bit register is connected；
First reset signal end of shift registers at different levels is connected with the signal output end of next stage shift register, and second resets
Signal end is connected with the signal output end of the shift register of its lower interval at least one level.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811055224.7A CN109036252B (en) | 2018-09-11 | 2018-09-11 | Shifting register, driving method thereof and grid driving circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811055224.7A CN109036252B (en) | 2018-09-11 | 2018-09-11 | Shifting register, driving method thereof and grid driving circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN109036252A true CN109036252A (en) | 2018-12-18 |
| CN109036252B CN109036252B (en) | 2021-08-20 |
Family
ID=64621551
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201811055224.7A Active CN109036252B (en) | 2018-09-11 | 2018-09-11 | Shifting register, driving method thereof and grid driving circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109036252B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114974153A (en) * | 2021-02-26 | 2022-08-30 | 北京京东方显示技术有限公司 | Shift register, driving circuit, driving method and display device |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060221041A1 (en) * | 2005-03-31 | 2006-10-05 | Lg.Philips Lcd Co., Ltd. | Gate driver and display device having the same |
| CN102915698A (en) * | 2012-10-18 | 2013-02-06 | 京东方科技集团股份有限公司 | Shifting register unit, grid electrode drive circuit and display device |
| CN103474040A (en) * | 2013-09-06 | 2013-12-25 | 合肥京东方光电科技有限公司 | Grid electrode drive unit, grid electrode drive circuit and display device |
| KR20170078165A (en) * | 2015-12-29 | 2017-07-07 | 엘지디스플레이 주식회사 | Shift register |
| CN107274856A (en) * | 2017-08-22 | 2017-10-20 | 京东方科技集团股份有限公司 | A kind of shift register and its driving method, gate driving circuit |
| CN108389539A (en) * | 2018-03-15 | 2018-08-10 | 京东方科技集团股份有限公司 | Shift register cell, driving method, gate driving circuit and display device |
-
2018
- 2018-09-11 CN CN201811055224.7A patent/CN109036252B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060221041A1 (en) * | 2005-03-31 | 2006-10-05 | Lg.Philips Lcd Co., Ltd. | Gate driver and display device having the same |
| CN102915698A (en) * | 2012-10-18 | 2013-02-06 | 京东方科技集团股份有限公司 | Shifting register unit, grid electrode drive circuit and display device |
| CN103474040A (en) * | 2013-09-06 | 2013-12-25 | 合肥京东方光电科技有限公司 | Grid electrode drive unit, grid electrode drive circuit and display device |
| KR20170078165A (en) * | 2015-12-29 | 2017-07-07 | 엘지디스플레이 주식회사 | Shift register |
| CN107274856A (en) * | 2017-08-22 | 2017-10-20 | 京东方科技集团股份有限公司 | A kind of shift register and its driving method, gate driving circuit |
| CN108389539A (en) * | 2018-03-15 | 2018-08-10 | 京东方科技集团股份有限公司 | Shift register cell, driving method, gate driving circuit and display device |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114974153A (en) * | 2021-02-26 | 2022-08-30 | 北京京东方显示技术有限公司 | Shift register, driving circuit, driving method and display device |
| CN114974153B (en) * | 2021-02-26 | 2024-01-30 | 北京京东方显示技术有限公司 | Shift register, driving circuit, driving method and display device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN109036252B (en) | 2021-08-20 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN104464600B (en) | Shifting register unit, driving method of shifting register unit, shifting register circuit and display device | |
| CN105118473B (en) | Shift register cell, shift register and driving method, array base palte | |
| CN106157923B (en) | Shift register cell and its driving method, gate driving circuit, display device | |
| CN106448536B (en) | Shift register, gate driving circuit, display panel and driving method | |
| CN107464521B (en) | Shift register cell, gate driving circuit and driving method, display device | |
| CN107039017A (en) | Shift register cell and its driving method, gate driving circuit, display device | |
| CN105632562B (en) | A kind of shift register, gate driving circuit, display panel and display device | |
| CN105679229A (en) | Shifting register unit, driving method, grid electrode driving circuit and display device | |
| CN105528985A (en) | Shift register unit, driving method and display device | |
| CN106504720A (en) | Shift register cell and its driving method, gate drive apparatus and display device | |
| CN107424554A (en) | Shift register cell and its driving method, gate driving circuit, display device | |
| CN104575430A (en) | Shifting register unit, drive method thereof, gate drive circuit and display device | |
| CN108648705A (en) | Shift register cell and driving method, gate driving circuit and display device | |
| CN105185339A (en) | Shift register unit, grid line drive unit and drive method | |
| CN107945765A (en) | Shift-register circuit and its control method, gate driving circuit, display device | |
| CN105938711A (en) | Gate driver on array (GOA) circuit and driving method | |
| CN106157874A (en) | Shift register cell, driving method, gate driver circuit and display device | |
| CN106910452B (en) | Shift register cell, its driving method, gate driving circuit and display device | |
| CN103208263A (en) | Shift register, display device, gate drive circuit and driving method | |
| CN109192238A (en) | Shift register cell and its driving method, gate driving circuit and display device | |
| CN204406959U (en) | Shift register cell, shift-register circuit and display device | |
| CN110648621B (en) | Shift register and driving method thereof, grid driving circuit and display device | |
| CN106057116A (en) | Shift register unit, driving method, gate driving circuit and display device | |
| CN107358906A (en) | Shift register cell and its driving method, gate driving circuit, display device | |
| CN108766336A (en) | Shift register, phase inverter production method, gate driving circuit and display device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |