CN110910813A

CN110910813A - Shifting register, driving method thereof and grid driving circuit

Info

Publication number: CN110910813A
Application number: CN201911320645.2A
Authority: CN
Inventors: 闫伟; 王珍; 王争奎; 张寒; 秦文文; 张健; 王德帅; 孙建
Original assignee: BOE Technology Group Co Ltd
Current assignee: BOE Technology Group Co Ltd
Priority date: 2019-12-19
Filing date: 2019-12-19
Publication date: 2020-03-24
Anticipated expiration: 2039-12-19
Also published as: CN110910813B

Abstract

A shift register, a driving method thereof and a grid driving circuit are provided, wherein the shift register comprises: an input sub-circuit for providing a signal of a first signal terminal to a pull-up node under control of a signal input terminal, an output sub-circuit for providing a signal of a first clock terminal to a signal output terminal under control of the pull-up node and the first power terminal, a pull-up sub-circuit for providing a signal of a second clock terminal to the pull-down node under control of a second clock terminal, a node pull-down sub-circuit for providing a signal of the second power terminal to the pull-down node under control of the pull-up node and the signal output terminal, and a noise reduction sub-circuit for providing a signal of the second power terminal to the pull-up node and the signal output terminal under control of the pull-down node and the signal output terminal. The application avoids the large current in the shift register, further reduces the power consumption of the shift register, and improves the working stability, the use reliability and the display effect of the display panel.

Description

Shifting register, driving method thereof and grid driving circuit

Technical Field

The present disclosure relates to the field of display technologies, and in particular, to a shift register, a driving method thereof, and a gate driving circuit.

Background

In recent years, flat panel displays, such as Thin Film Transistor-Liquid Crystal Display (TFT-LCD) panels and Active Matrix Organic Light Emitting Diode (AMOLED) panels, have been widely used in electronic products such as televisions and mobile phones because of their advantages of Light weight, Thin thickness, and low power consumption.

With the development of technology, a high-resolution and narrow-frame display panel is becoming a trend, and for this reason, a Gate Driver on Array (GOA) technology is developed, where the GOA technology refers to a technology in which GOA circuits for driving Gate lines are disposed on two sides of an effective display area of an Array substrate in a display panel, and the GOA circuits include a plurality of shift registers.

In the related art, a large current exists in the working process of the shift register, so that the power consumption of the shift register is large, and the working stability, the use reliability and the display effect of the display panel are reduced.

Content of application

The embodiment of the application provides a shift register, a driving method thereof and a gate driving circuit, which can reduce the power consumption of the shift register and improve the working stability, the use reliability and the display effect of a display panel.

In a first aspect, the present application provides a shift register comprising: an input sub-circuit, an output sub-circuit, a node pull-up sub-circuit, a node pull-down sub-circuit, and a noise reduction sub-circuit;

the input sub-circuit is respectively connected with the signal input end, the first signal end and the pull-up node and is used for providing a signal of the first signal end to the pull-up node under the control of the signal input end;

the output sub-circuit is respectively connected with the first power supply end, the first clock end, the pull-up node and the signal output end, and is used for providing a signal of the first clock end for the signal output end under the control of the pull-up node and the first power supply end;

the node pull-up sub-circuit is respectively connected with the second clock end and the pull-down node and is used for providing a signal of the second clock end to the pull-down node under the control of the second clock end;

the node pull-down sub-circuit is respectively connected with the pull-up node, the pull-down node, the signal output end and the second power supply end and is used for providing a signal of the second power supply end to the pull-down node under the control of the pull-up node and the signal output end;

the noise reduction sub-circuit is respectively connected with the pull-up node, the pull-down node, the signal output end and the second power supply end and is used for providing signals of the second power supply end for the pull-up node and the signal output end under the control of the pull-down node and the signal output end.

Optionally, the shift register further includes: the touch control circuit comprises a first reset sub-circuit, a second reset sub-circuit and a touch control sub-circuit;

the first reset sub-circuit is respectively connected with the first reset terminal, the pull-up node and the second signal terminal, and is used for providing a signal of the second signal terminal to the pull-up node under the control of the first reset terminal;

the second reset sub-circuit is respectively connected with the second reset terminal, the pull-up node and the second power supply terminal, and is used for providing a signal of the second power supply terminal to the pull-up node under the control of the second reset terminal;

the touch control sub-circuit is respectively connected with the touch control enabling end, the signal output end and the second power end and is used for providing a signal of the second power end for the signal output end under the control of the touch control enabling end.

Optionally, the input sub-circuit comprises: a first transistor;

a control electrode of the first transistor is connected with a signal input end, a first electrode of the first transistor is connected with a first signal end, and a second electrode of the first transistor is connected with a pull-up node;

the output sub-circuit includes: a second transistor, a third transistor, and a first capacitor;

a control electrode of the second transistor is connected with a first end of the first capacitor, a first electrode of the second transistor is connected with a first clock end, and a second electrode of the second transistor is connected with a signal output end;

a control electrode of the third transistor is connected with a first power end, a first electrode of the third transistor is connected with a pull-up node, and a second electrode of the third transistor is connected with a first end of the first capacitor;

and the second end of the first capacitor is connected with the signal output end.

Optionally, the node pull-up sub-circuit comprises: a fourth transistor;

a control electrode and a first electrode of the fourth transistor are connected with a second clock end, and a second electrode of the fourth transistor is connected with a pull-down node;

the noise reduction sub-circuit comprises: fifth to seventh transistors and a second capacitor;

a control electrode of the fifth transistor is connected with a pull-down node, a first electrode of the fifth transistor is connected with a second electrode of the sixth transistor, and the second electrode of the fifth transistor is connected with a second power supply end;

a control electrode of the sixth transistor is connected with the signal output end, and a first electrode of the sixth transistor is connected with the pull-up node;

a control electrode of the seventh transistor is connected with a pull-down node, a first electrode of the seventh transistor is connected with a signal output end, and a second electrode of the seventh transistor is connected with a second power supply end;

and the first end of the second capacitor is connected with the pull-down node, and the second end of the second capacitor is connected with the signal output end.

Optionally, the node pull-down sub-circuit comprises: eighth to tenth transistors;

a control electrode of the eighth transistor is connected with the signal output end, a first electrode of the eighth transistor is connected with the pull-down node, and a second electrode of the eighth transistor is connected with a first electrode of the ninth transistor;

a control electrode of the ninth transistor is connected with the pull-up node, and a second electrode of the ninth transistor is connected with a second power supply end;

a control electrode of the tenth transistor is connected with the signal output end, a first electrode of the tenth transistor is connected with the pull-down node, and a second electrode of the tenth transistor is connected with the second power supply end.

Optionally, the first reset sub-circuit comprises: an eleventh transistor;

a control electrode of the eleventh transistor is connected with a first reset end, a first electrode of the eleventh transistor is connected with a pull-up node, and a second electrode of the eleventh transistor is connected with a second signal end;

the second reset sub-circuit includes: a twelfth transistor;

a control electrode of the twelfth transistor is connected with a second reset end, a first electrode of the twelfth transistor is connected with a pull-up node, and a second electrode of the twelfth transistor is connected with a second power supply end;

the touch subcircuit includes: a thirteenth transistor;

a control electrode of the thirteenth transistor is connected with the touch enable end, a first electrode of the thirteenth transistor is connected with the signal output end, and a second electrode of the thirteenth transistor is connected with the second power supply end.

Optionally, the shift register further includes: the touch control circuit comprises a first reset sub-circuit, a second reset sub-circuit and a touch control sub-circuit; the input sub-circuit includes: a first transistor; the output sub-circuit includes: a second transistor, a third transistor, and a first capacitor; the node pull-up sub-circuit comprises: a fourth transistor; the noise reduction sub-circuit comprises: fifth to seventh transistors and a second capacitor; the node pull-down sub-circuit comprises: eighth to tenth transistors; the first reset sub-circuit includes: an eleventh transistor; the second reset sub-circuit includes: a twelfth transistor; the touch subcircuit includes: a thirteenth transistor;

the second end of the first capacitor is connected with the signal output end;

the first end of the second capacitor is connected with the pull-down node, and the second end of the second capacitor is connected with the signal output end;

a control electrode of the tenth transistor is connected with the signal output end, a first electrode of the tenth transistor is connected with the pull-down node, and a second electrode of the tenth transistor is connected with the second power supply end;

Optionally, when the level of the clock signal at the first clock end is an active level, the level of the clock signal at the second clock end is an inactive level, and when the level of the clock signal at the second clock end is an active level, the level of the clock signal at the first clock end is an inactive level.

In a second aspect, the present application also provides a gate driving circuit, including: a plurality of cascaded shift registers.

Optionally, the gate driving circuit includes: an initial signal end and a reset control end;

the signal input end of the first-stage shift register is connected with the initial signal end, the signal output end of the Nth-stage shift register is connected with the signal input end of the (N +1) th-stage shift register, and the signal output end of the (N +1) th-stage shift register is connected with the first reset end of the Nth-stage shift register; and the second reset terminals of all the stages of shift registers are connected with the reset control terminal.

In a third aspect, the present application further provides a driving method of a shift register, which is applied to the shift register, and in a display period, the method includes:

under the control of the signal input end, the input sub-circuit provides a signal of a first signal end to the pull-up node; under the control of the second clock end, the node pull-up sub-circuit provides a signal of the second clock end to the pull-down node;

under the control of the pull-up node and the first power supply end, the output sub-circuit provides a signal of the first clock end for the signal output end; under the control of the pull-up node and the signal output end, the node pull-down sub-circuit provides a signal of a second power supply end to the pull-down node;

the noise reduction sub-circuit provides the signal of the second power supply terminal to the pull-up node and the signal output terminal under the control of the pull-down node and the signal output terminal.

Optionally, the method further comprises: the first reset sub-circuit provides a signal of the second signal terminal to the pull-up node under the control of the first reset terminal.

The embodiment of the application provides a shift register, a driving method thereof and a gate driving circuit, wherein the shift register comprises: an input sub-circuit, an output sub-circuit, a node pull-up sub-circuit, a node pull-down sub-circuit, and a noise reduction sub-circuit; the input sub-circuit is respectively connected with the signal input end, the first signal end and the pull-up node and is used for providing a signal of the first signal end to the pull-up node under the control of the signal input end; the output sub-circuit is respectively connected with the first power supply end, the first clock end, the pull-up node and the signal output end and is used for providing a signal of the first clock end for the signal output end under the control of the pull-up node and the first power supply end; the node pull-up sub-circuit is respectively connected with the second clock end and the pull-down node and is used for providing a signal of the second clock end to the pull-down node under the control of the second clock end; the node pull-down sub-circuit is respectively connected with the pull-up node, the pull-down node, the signal output end and the second power supply end and is used for providing a signal of the second power supply end to the pull-down node under the control of the pull-up node and the signal output end; and the noise reduction sub-circuit is respectively connected with the pull-up node, the pull-down node, the signal output end and the second power supply end and is used for providing signals of the second power supply end for the pull-up node and the signal output end under the control of the pull-down node and the signal output end. According to the embodiment of the application, the node pull-down sub-circuit is arranged, the pull-up node and the signal output end simultaneously control signals of the pull-down node, so that the situation that a large current exists in the shift register is avoided, the power consumption of the shift register is further reduced, and the working stability, the use reliability and the display effect of the display panel are improved.

Additional features and advantages of the application will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by the practice of the application. Other advantages of the application may be realized and attained by the instrumentalities and combinations particularly pointed out in the specification, claims, and drawings.

Drawings

The accompanying drawings are included to provide an understanding of the present disclosure and are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the examples serve to explain the principles of the disclosure and not to limit the disclosure.

Fig. 1 is a schematic structural diagram of a shift register according to an embodiment of the present application;

fig. 2 is a schematic structural diagram of a shift register according to an embodiment of the present application;

FIG. 3 is an equivalent circuit diagram of an input sub-circuit provided in an embodiment of the present application;

fig. 4 is an equivalent circuit diagram of an output sub-circuit provided in an embodiment of the present application;

fig. 5 is an equivalent circuit diagram of a node pull-up sub-circuit provided in the embodiment of the present application;

FIG. 6 is an equivalent circuit diagram of a noise reduction sub-circuit provided in an embodiment of the present application;

fig. 7 is an equivalent circuit diagram of a node pull-down sub-circuit according to an embodiment of the present disclosure;

fig. 8 is an equivalent circuit diagram of a first reset sub-circuit provided in an embodiment of the present application;

fig. 9 is an equivalent circuit diagram of a second reset sub-circuit provided in an embodiment of the present application;

fig. 10 is an equivalent circuit diagram of a touch sub-circuit according to an embodiment of the present disclosure;

fig. 11 is an equivalent circuit diagram of a shift register according to an embodiment of the present application;

FIG. 12 is a timing diagram illustrating an operation of a shift register according to an embodiment of the present disclosure;

fig. 13 is a schematic structural diagram of a gate driving circuit according to an embodiment of the present disclosure;

fig. 14 is a flowchart of a driving method of a shift register according to an embodiment of the present application.

Detailed Description

The present application describes embodiments, but the description is illustrative rather than limiting and it will be apparent to those of ordinary skill in the art that many more embodiments and implementations are possible within the scope of the embodiments described herein. Although many possible combinations of features are shown in the drawings and discussed in the detailed description, many other combinations of the disclosed features are possible. Any feature or element of any embodiment may be used in combination with or instead of any other feature or element in any other embodiment, unless expressly limited otherwise.

The present application includes and contemplates combinations of features and elements known to those of ordinary skill in the art. The embodiments, features and elements disclosed in the present application may also be combined with any conventional features or elements to form a unique application as defined in the claims. Any feature or element of any embodiment may be combined with features or elements from other applications to form yet another unique application defined by the claims. Thus, it should be understood that any of the features shown and/or discussed in this application may be implemented alone or in any suitable combination. Accordingly, the embodiments are not limited except as by the appended claims and their equivalents. Furthermore, various modifications and changes may be made within the scope of the appended claims.

Further, in describing representative embodiments, the specification may have presented the method and/or process as a particular sequence of steps. However, to the extent that the method or process does not rely on the particular order of steps set forth herein, the method or process should not be limited to the particular sequence of steps described. Other orders of steps are possible as will be understood by those of ordinary skill in the art. Therefore, the particular order of the steps set forth in the specification should not be construed as limitations on the claims. Further, the claims directed to the method and/or process should not be limited to the performance of their steps in the order written, and one skilled in the art can readily appreciate that the sequences may be varied and still remain within the spirit and scope of the embodiments of the present application.

Unless otherwise defined, technical or scientific terms used throughout the disclosure of the embodiments of the present application shall have the ordinary meaning as understood by those having ordinary skill in the art to which the present application belongs. The use of "first," "second," and similar terms in the embodiments of the present application do not denote any order, quantity, or importance, but rather the terms are used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

It will be appreciated by those skilled in the art that the transistors employed in all embodiments of the present application may be thin film transistors or field effect transistors or other devices having the same characteristics. Preferably, the thin film transistor used in the embodiment of the present application may be an oxide semiconductor transistor. Since the source and drain of the transistor used herein are symmetrical, the source and drain may be interchanged. In the embodiment of the present application, in order to distinguish two electrodes of a transistor except for a gate, one of the electrodes is referred to as a first electrode, the other electrode is referred to as a second electrode, the first electrode may be a source or a drain, the second electrode may be a drain or a source, and the gate of the transistor is referred to as a control electrode.

Some embodiments of the present application provide a shift register, and fig. 1 is a schematic structural diagram of a shift register provided in an embodiment of the present application, and as shown in fig. 1, the shift register provided in the embodiment of the present application includes: an input sub-circuit, an output sub-circuit, a node pull-up sub-circuit, a node pull-down sub-circuit, and a noise reduction sub-circuit.

Specifically, the INPUT sub-circuit is respectively connected to the signal INPUT terminal INPUT, the first signal terminal CN and the pull-up node PU, and is configured to provide a signal of the first signal terminal CN to the pull-up node PU under the control of the signal INPUT terminal INPUT; the output sub-circuit is respectively connected with the first power supply end VGH, the first clock end CLK1, the pull-up node PU and the signal output end OUT and is used for providing a signal of the first clock end CLK1 for the signal output end OUT under the control of the pull-up node PU and the first power supply end VGH; a node pull-up sub-circuit respectively connected to the second clock terminal CLK2 and the pull-down node PD for providing a signal of the second clock terminal CLK2 to the pull-down node PD under the control of the second clock terminal CLK 2; the node pull-down sub-circuit is respectively connected with the pull-up node PU, the pull-down node PD, the signal output end OUT and the second power supply end VGL, and is used for providing a signal of the second power supply end VGL to the pull-down node PD under the control of the pull-up node PU and the signal output end OUT; and the noise reduction sub-circuit is respectively connected with the pull-up node PU, the pull-down node PD, the signal output end OUT and the second power supply end VGL and is used for providing signals of the second power supply end VGL for the pull-up node PU and the signal output end OUT under the control of the pull-down node PD and the signal output end OUT.

In this embodiment, the shift register includes: the display device comprises a display stage and a touch stage, wherein in the display stage, the first power supply end VGH continuously provides a first level signal, the second power supply end VGL continuously provides a second level signal, an output signal of the signal output end OUT is a pulse signal, and in the touch stage, the signal output end OUT does not output a signal.

The shift register provided in the embodiment of the present application includes: an input sub-circuit, an output sub-circuit, a node pull-up sub-circuit, a node pull-down sub-circuit, and a noise reduction sub-circuit; the input sub-circuit is respectively connected with the signal input end, the first signal end and the pull-up node and is used for providing a signal of the first signal end to the pull-up node under the control of the signal input end; the output sub-circuit is respectively connected with the first power supply end, the first clock end, the pull-up node and the signal output end and is used for providing a signal of the first clock end for the signal output end under the control of the pull-up node and the first power supply end; the node pull-up sub-circuit is respectively connected with the second clock end and the pull-down node and is used for providing a signal of the second clock end to the pull-down node under the control of the second clock end; the node pull-down sub-circuit is respectively connected with the pull-up node, the pull-down node, the signal output end and the second power supply end and is used for providing a signal of the second power supply end to the pull-down node under the control of the pull-up node and the signal output end; and the noise reduction sub-circuit is respectively connected with the pull-up node, the pull-down node, the signal output end and the second power supply end and is used for providing signals of the second power supply end for the pull-up node and the signal output end under the control of the pull-down node and the signal output end. According to the embodiment of the application, the node pull-down sub-circuit is arranged, the pull-up node and the signal output end simultaneously control signals of the pull-down node, so that the situation that a large current exists in the shift register is avoided, the power consumption of the shift register is further reduced, and the working stability, the use reliability and the display effect of the display panel are improved.

Optionally, fig. 2 is another schematic structural diagram of the shift register provided in the embodiment of the present application, and as shown in fig. 2, the shift register provided in the embodiment of the present application further includes: the touch control circuit comprises a first reset sub-circuit, a second reset sub-circuit and a touch control sub-circuit.

Specifically, the first reset sub-circuit is respectively connected to the first reset terminal RST1, the pull-up node PU, and the second signal terminal CNB, and is configured to provide a signal of the second signal terminal CNB to the pull-up node PU under the control of the first reset terminal RST 1; the second reset sub-circuit is respectively connected with the second reset terminal RST2, the pull-up node PU and the second power supply terminal VGL, and is used for providing a signal of the second power supply terminal VGL to the pull-up node PU under the control of the second reset terminal RST 2; and the touch control sub-circuit is respectively connected with the touch control enable terminal EN, the signal output terminal OUT and the second power supply terminal VGL, and is used for providing a signal of the second power supply terminal VGL for the signal output terminal OUT under the control of the touch control enable terminal EN.

In this embodiment, in the display phase, the levels of the input signals of the touch enable terminal EN and the second reset terminal RST2 are inactive levels, and in the touch phase, the levels of the input signals of the touch enable terminal EN and the second reset terminal RST2 are active levels.

According to the embodiment of the application, the first reset sub-circuit and the second reset sub-circuit are added in the shift register, so that the noise in the shift register can be reduced, the working stability, the use reliability and the display effect of the display panel are further improved, and in addition, the touch sub-circuit is added in the shift register, so that the application range of the display panel can be further improved.

Optionally, fig. 3 is an equivalent circuit diagram of an input sub-circuit provided in the embodiment of the present application, and as shown in fig. 3, the input sub-circuit in the shift register provided in the embodiment of the present application includes: the first transistor M1.

Specifically, a control electrode of the first transistor M1 is connected to the signal INPUT terminal INPUT, a first electrode of the first transistor M1 is connected to the first signal terminal CN, and a second electrode of the first transistor M1 is connected to the pull-up node PU.

In the present embodiment, an exemplary structure of the input sub-circuit is specifically shown in fig. 3. It is easily understood by those skilled in the art that the implementation of the input sub-circuit is not limited thereto as long as the function thereof can be achieved.

Optionally, fig. 4 is an equivalent circuit diagram of an output sub-circuit provided in the embodiment of the present application, and as shown in fig. 4, the output sub-circuit in the shift register provided in the embodiment of the present application includes: a second transistor M2, a third transistor M3, and a first capacitor C1.

Specifically, a control electrode of the second transistor M2 is connected to a first end of the first capacitor C1, a first electrode of the second transistor M2 is connected to the first clock terminal CLK1, and a second electrode of the second transistor M2 is connected to the signal output terminal OUT; a control electrode of the third transistor M3 is connected to the first power source terminal VGH, a first electrode of the third transistor M3 is connected to the pull-up node PU, and a second electrode of the third transistor M3 is connected to the first end of the first capacitor C1; the second terminal of the first capacitor C1 is connected to the signal output terminal OUT.

In the present embodiment, an exemplary structure of the output sub-circuit is specifically shown in fig. 4. Those skilled in the art will readily appreciate that the implementation of the output sub-circuit is not limited thereto as long as its function can be achieved.

Optionally, fig. 5 is an equivalent circuit diagram of a node pull-up sub-circuit provided in the embodiment of the present application, and as shown in fig. 5, the node pull-up sub-circuit in the shift register provided in the embodiment of the present application includes: and a fourth transistor M4.

Specifically, the control electrode and the first electrode of the fourth transistor M4 are connected to the second clock terminal CLK2, and the second electrode of the fourth transistor M4 is connected to the pull-down node PD.

In the present embodiment, an exemplary structure of the node pull-up sub-circuit is specifically shown in fig. 5. Those skilled in the art will readily appreciate that the implementation of the node pull-up sub-circuit is not so limited, so long as its functionality is achieved.

Optionally, fig. 6 is an equivalent circuit diagram of the noise reduction sub-circuit provided in the embodiment of the present application, and as shown in fig. 6, the noise reduction sub-circuit in the shift register provided in the embodiment of the present application includes: fifth to seventh transistors M5 to M7 and a second capacitor C2.

Specifically, a control electrode of the fifth transistor M5 is connected to the pull-down node PD, a first electrode of the fifth transistor M5 is connected to the second electrode of the sixth transistor M6, and a second electrode of the fifth transistor M5 is connected to the second power source terminal VGL; a control electrode of the sixth transistor M6 is connected to the signal output terminal OUT, and a first electrode of the sixth transistor M6 is connected to the pull-up node PU; a control electrode of the seventh transistor M7 is connected to the pull-down node PD, a first electrode of the seventh transistor M7 is connected to the signal output terminal OUT, and a second electrode of the seventh transistor M7 is connected to the second power source terminal VGL; a first terminal of the second capacitor C2 is connected to the pull-down node PD, and a second terminal of the second capacitor C2 is connected to the signal output terminal OUT.

In the present embodiment, an exemplary structure of the noise reduction sub-circuit is specifically shown in fig. 6. It is easily understood by those skilled in the art that the implementation of the input sub-circuit is not limited thereto as long as the function thereof can be achieved.

Optionally, fig. 7 is an equivalent circuit diagram of a node pull-down sub-circuit provided in the embodiment of the present application, and as shown in fig. 7, the node pull-down sub-circuit in the shift register provided in the embodiment of the present application includes: the eighth transistor M8 to the tenth transistor M10.

Specifically, a control electrode of the eighth transistor M8 is connected to the signal output terminal OUT, a first electrode of the eighth transistor M8 is connected to the pull-down node PD, and a second electrode of the eighth transistor M8 is connected to a first electrode of the ninth transistor M9; a control electrode of the ninth transistor M9 is connected to the pull-up node PU, and a second electrode of the ninth transistor M9 is connected to the second power source terminal VGL; a control electrode of the tenth transistor M10 is connected to the signal output terminal OUT, a first electrode of the tenth transistor M10 is connected to the pull-down node PD, and a second electrode of the tenth transistor M10 is connected to the second power source terminal VGL.

In the present embodiment, an exemplary structure of the node pull-down sub-circuit is specifically shown in fig. 7. Those skilled in the art will readily appreciate that the implementation of the node pull-down sub-circuit is not limited thereto as long as its functionality is achieved.

Optionally, fig. 8 is an equivalent circuit diagram of a first reset sub-circuit provided in the embodiment of the present application, and as shown in fig. 8, the first reset sub-circuit in the shift register provided in the embodiment of the present application includes: an eleventh transistor M11.

Specifically, a control electrode of the eleventh transistor M11 is connected to the first reset terminal RST1, a first electrode of the eleventh transistor M11 is connected to the pull-up node PU, and a second electrode of the eleventh transistor M11 is connected to the second signal terminal CNB.

In the present embodiment, an exemplary structure of the first reset sub-circuit is specifically shown in fig. 8. It is easily understood by those skilled in the art that the implementation of the first reset sub-circuit is not limited thereto as long as the function thereof can be achieved.

Optionally, fig. 9 is an equivalent circuit diagram of a second reset sub-circuit provided in the embodiment of the present application, and as shown in fig. 9, the second reset sub-circuit in the shift register provided in the embodiment of the present application includes: and a twelfth transistor M12.

Specifically, a control electrode of the twelfth transistor M12 is connected to the second reset terminal RST2, a first electrode of the twelfth transistor M12 is connected to the pull-up node PU, and a second electrode of the twelfth transistor M12 is connected to the second power source terminal VGL.

In the present embodiment, an exemplary structure of the second reset sub-circuit is specifically shown in fig. 9. Those skilled in the art will readily appreciate that the implementation of the second reset sub-circuit is not limited thereto as long as its function can be achieved.

Optionally, fig. 10 is an equivalent circuit diagram of the touch sub-circuit provided in the embodiment of the present application, and as shown in fig. 10, the touch sub-circuit in the shift register provided in the embodiment of the present application includes: a thirteenth transistor M13.

Specifically, a control electrode of the thirteenth transistor M13 is connected to the touch enable terminal EN, a first electrode of the thirteenth transistor M13 is connected to the signal output terminal OUT, and a second electrode of the thirteenth transistor M13 is connected to the second power source terminal VGL.

In the present embodiment, an exemplary structure of the touch sub-circuit is specifically shown in fig. 10. Those skilled in the art will readily understand that the implementation of the touch sub-circuit is not limited thereto as long as the functions thereof can be implemented.

Fig. 11 is an equivalent circuit diagram of a shift register provided in the embodiment of the present application, and as shown in fig. 11, the shift register provided in the embodiment of the present application further includes: the touch control circuit comprises a first reset sub-circuit, a second reset sub-circuit and a touch control sub-circuit; the input sub-circuit includes: a first transistor M1; the output sub-circuit includes: a second transistor M2, a third transistor M3, and a first capacitor C1; the node pull-up sub-circuit includes: a fourth transistor M4; the noise reduction sub-circuit includes: fifth to seventh transistors M5 to M7 and a second capacitor C2; the node pull-down sub-circuit includes: eighth to tenth transistors M8 to M10; the first reset sub-circuit includes: an eleventh transistor M11; the second reset sub-circuit includes: a twelfth transistor M12; the touch sub-circuit includes: a thirteenth transistor M13.

Specifically, a control electrode of the first transistor M1 is connected to the signal INPUT terminal INPUT, a first electrode of the first transistor M1 is connected to the first signal terminal CN, and a second electrode of the first transistor M1 is connected to the pull-up node PU; a control electrode of the second transistor M2 is connected to the first end of the first capacitor C1, a first electrode of the second transistor M2 is connected to the first clock terminal CLK1, and a second electrode of the second transistor M2 is connected to the signal output terminal OUT; a control electrode of the third transistor M3 is connected to the first power source terminal VGH, a first electrode of the third transistor M3 is connected to the pull-up node PU, and a second electrode of the third transistor M3 is connected to the first end of the first capacitor C1; a second terminal of the first capacitor C1 is connected to the signal output terminal OUT; a control electrode and a first electrode of the fourth transistor M4 are connected to the second clock terminal CLK2, and a second electrode of the fourth transistor M4 is connected to the pull-down node PD; a control electrode of the fifth transistor M5 is connected to the pull-down node PD, a first electrode of the fifth transistor M5 is connected to a second electrode of the sixth transistor M6, and a second electrode of the fifth transistor M5 is connected to the second power source terminal VGL; a control electrode of the sixth transistor M6 is connected to the signal output terminal OUT, and a first electrode of the sixth transistor M6 is connected to the pull-up node PU; a control electrode of the seventh transistor M7 is connected to the pull-down node PD, a first electrode of the seventh transistor M7 is connected to the signal output terminal OUT, and a second electrode of the seventh transistor M7 is connected to the second power source terminal VGL; a first end of the second capacitor C2 is connected to the pull-down node PD, and a second end of the second capacitor C2 is connected to the signal output terminal OUT; a control electrode of the eighth transistor M8 is connected to the signal output terminal OUT, a first electrode of the eighth transistor M8 is connected to the pull-down node PD, and a second electrode of the eighth transistor M8 is connected to a first electrode of the ninth transistor M9; a control electrode of the ninth transistor M9 is connected to the pull-up node PU, and a second electrode of the ninth transistor M9 is connected to the second power source terminal VGL; a control electrode of the tenth transistor M10 is connected to the signal output terminal OUT, a first electrode of the tenth transistor M10 is connected to the pull-down node PD, and a second electrode of the tenth transistor M10 is connected to the second power source terminal VGL; a control electrode of the eleventh transistor M11 is connected to the first reset terminal RST1, a first electrode of the eleventh transistor M11 is connected to the pull-up node PU, and a second electrode of the eleventh transistor M11 is connected to the second signal terminal CNB; a control electrode of the twelfth transistor M12 is connected to the second reset terminal RST2, a first electrode of the twelfth transistor M12 is connected to the pull-up node PU, and a second electrode of the twelfth transistor M12 is connected to the second power source terminal VGL; a control electrode of the thirteenth transistor M13 is connected to the touch enable terminal EN, a first electrode of the thirteenth transistor M13 is connected to the signal output terminal OUT, and a second electrode of the thirteenth transistor M13 is connected to the second power source terminal VGL.

Alternatively, when the level of the clock signal of the first clock terminal CLK1 is an active level, the level of the clock signal of the second clock terminal CLK2 is an inactive level, and when the level of the clock signal of the second clock terminal CLK2 is an active level, the level of the clock signal of the first clock terminal CLK1 is an inactive level.

The duration of the pulse of the clock signal at the first clock terminal CLK1 being an active level signal is equal to the duration of the pulse of the clock signal at the second clock terminal CLK2 being an active level signal.

In the embodiment, the transistors M1 to M13 may be both N-type thin film transistors or P-type thin film transistors, so that the process flow can be unified, the process can be reduced, and the yield of the product can be improved. In addition, in consideration of the fact that the low-temperature polysilicon thin film transistor has a small leakage current, all transistors are preferably low-temperature polysilicon thin film transistors in the embodiments of the present application, and the thin film transistor may specifically be a thin film transistor with a bottom gate structure or a thin film transistor with a top gate structure, as long as the switching function can be achieved.

The technical solution of the embodiment of the present application is further described below by the working process of the shift register.

Taking the transistors M1 to M13 in the shift register provided in the embodiment of the present application as an example, and fig. 12 is an operation timing diagram of the shift register provided in the embodiment of the present application, as shown in fig. 11 and 12, the shift register provided in the embodiment of the present application includes 13 transistor units (M1 to M13), 1 capacitor (C1 and C2), 8 signal INPUT terminals (INPUT, RST1, RST2, CN, CNB, CLK1, CLK2 and EN), 1 signal output terminal (OUT), and 2 power supply terminals (VGH and VGL).

Specifically, the working process of the shift register includes a display stage and a touch stage, in the touch stage, the level of the input signal of the touch enable terminal EN is continuously high, the thirteenth transistor M13 is continuously turned on, and at this time, the shift register does not output. In the display stage, the working process of the display stage comprises the following steps: the first stage to the sixth stage.

In the display phase, the first power supply terminal VGH continuously provides a high level signal; the second power source terminal VGL continuously supplies a low level signal, and the third transistor M3 is continuously turned on due to the first power source terminal VGH continuously supplying a high level signal, and the level of the pull-up node PU is equal to the level of the first terminal of the first capacitor C1.

Specifically, the working process of the display phase comprises the following steps:

in the first stage T1, i.e., the INPUT stage, when the levels of the INPUT signals at the signal INPUT terminal INPUT and the first signal terminal CN are high, the level of the clock signal at the second clock terminal CLK2 is high for half of the time, and is low for half of the time, the level of the INPUT signal at the signal INPUT terminal INPUT is high, the first transistor M1 is turned on, the level of the pull-up node PU is pulled up, the first capacitor C1 is charged, the second transistor M2 is turned on, and since the level of the clock signal at the first clock terminal CLK1 is low, the level of the output signal at the signal output terminal OUT is low, i.e., the signal output terminal OUT does not output a signal, when the level of the clock signal at the second clock terminal CLK2 is high, the fourth transistor M4 is turned on, the pull-down node PD is pulled up, the second capacitor C2 is charged, and when the level of the clock signal at the second clock terminal CLK2 is low, the fourth transistor M4 is turned off, the second capacitor C2 is discharged, the level of the pull-down node PD is still high, that is, the level of the pull-down node PD continues to be the high level in this stage, since the level of the pull-down node PD continues to be the high level, the fifth transistor M5 and the seventh transistor M7 continue to be turned on, although the ninth transistor M9 is turned on while the level of the pull-up node PU is high, since the level of the output signal of the signal output terminal OUT is low, therefore, the sixth transistor M6, the eighth transistor M8, and the tenth transistor M10 are turned off, since the eighth transistor M8 and the tenth transistor M10 are turned off, the level of the pull-down node PD is not pulled down at this stage, and in addition, since the sixth transistor M6 is turned off, the level of the pull-up node PU is not pulled low, and since the seventh transistor M7 is turned on, the level of the input signal at the signal output terminal OUT is further pulled low.

In the second stage T2, i.e. the output stage, the level of the clock signal at the first clock terminal CLK1 is high, the level of the signal at the signal INPUT terminal INPUT is low, the first transistor M1 is turned off, the level of the clock signal at the first clock terminal CLK1 is high, under the bootstrap action of the first capacitor C1, the level of the pull-up node PU is pulled high, the high level of the pull-up node PU turns on the second transistor M2 and the ninth transistor M9, the signal output terminal OUT outputs the signal at the first clock terminal CLK1, i.e. the level of the output signal at the signal output terminal OUT is high, and in addition, the increase of the level of the pull-up node PU improves the turn-on capability of the second transistor M2, and ensures the pixel charging. The level of the clock signal of the second clock terminal CLK2 is low level, the fourth transistor M4 is turned off, the sixth transistor M6, the eighth transistor M8 and the tenth transistor M10 are turned on because the level of the output signal of the signal output terminal OUT is high level, the level of the pull-down node PD is low level because the eighth transistor M8, the ninth transistor M9 and the tenth transistor M10 are turned on, and the fifth transistor M5 and the seventh transistor M7 are turned off, so the levels of the signals of the pull-up node PU and the signal output terminal OUT are not pulled down, and normal output of the shift register can be ensured.

In the third stage T3, the level of the clock signal of the first clock terminal CLK1 is low, the level of the pull-up node PU starts to decrease but does not decrease to the level of the signal of the second power source terminal, the low level of the pull-up node PU turns off the second transistor M2 and the ninth transistor M9, the signal output terminal OUT is not output, the level of the clock signal of the second clock terminal CLK2 is low, the level of the pull-down node PD continues to be low, and the fifth transistor M5 and the seventh transistor M7 are turned off.

A fourth phase T4, that is, a reset phase, in which the level of the input signal of the first reset terminal RST1 is high, the level of the clock signal of the second clock terminal CLK2 is high, the level of the input signal of the first reset terminal RST1 is high, the eleventh transistor M11 is turned on, the level of the pull-up node PU is pulled down due to the level of the input signal of the second signal terminal CNB being low, the second transistor M2 and the ninth transistor M9 are turned off, the second transistor M2 is turned off, so that the signal output terminal OUT does not output a signal, the fourth transistor M4 is turned on due to the level of the clock signal of the second clock terminal CLK2 being high, the pull-down node PD is pulled up, the second capacitor C2 is charged, the level of the pull-down node PD is high, that is, the level of the fifth transistor M5 and the seventh transistor M7 are turned on continuously because the level of the pull-down node PD is high, since the level of the output signal of the signal output terminal OUT is at a low level, the sixth transistor M6, the eighth transistor M8, and the tenth transistor M10 are turned off, and since the eighth transistor M8, the ninth transistor M9, and the tenth transistor M10 are turned off, the level of the pull-down node PD is not pulled down at this stage, the seventh transistor M7 is continuously turned on, and the level of the input signal of the signal output terminal OUT is continuously pulled down to reduce noise.

In the fifth stage T5, the level of the clock signal of the first clock terminal CLK1 is high half of the time and low half of the time, but since the level of the pull-up node PU is low, the second transistor M2 and the ninth transistor M9 are turned off, so that the signal output terminal OUT does not output a signal, since the level of the pull-down node PD is high, the fifth transistor M5 and the seventh transistor M7 are continuously turned on, and since the level of the output signal of the signal output terminal OUT is low, the sixth transistor M6, the eighth transistor M8 and the tenth transistor M10 are turned off, and since the eighth transistor M8, the ninth transistor M9 and the tenth transistor M10 are turned off, the level of the pull-down node PD is not pulled down, the seventh transistor M7 is continuously turned on, and the level of the input signal of the signal output terminal OUT is continuously pulled low to reduce noise.

In the sixth stage T6, the level of the clock signal of the second clock terminal CLK2 is high level for half time and low level for half time, the second transistor M2 and the ninth transistor M9 are turned off due to the pull-up node PU being pulled low, the second transistor M2 is turned off, and therefore, the signal output terminal OUT does not output a signal, when the level of the clock signal of the second clock terminal CLK2 is high level, the fourth transistor M4 is turned on, the pull-down node PD is pulled high, the second capacitor C2 is charged, when the level of the clock signal of the second clock terminal CLK2 is low level, the fourth transistor M4 is turned off, the second capacitor C2 is discharged, the level of the pull-down node PD is still high level, that is, in this stage, the level of the pull-down node PD continues to be high level, because the level of the pull-down node PD continues to be high level, the fifth transistor M5 and the seventh transistor M7 continue to be turned on because the level of the output signal output terminal OUT is low level, therefore, the sixth transistor M6, the eighth transistor M8, and the tenth transistor M10 are turned off, and since the eighth transistor M8, the ninth transistor M9, and the tenth transistor M10 are turned off, the level of the pull-down node PD is not pulled low in this stage, the seventh transistor M7 is continuously turned on, and the level of the input signal at the signal output terminal OUT is continuously pulled low to reduce noise.

After the reset period T4, the shift register of this stage continues to execute the fifth and sixth periods until the signal INPUT terminal INPUT receives a high signal again.

In the first stage T1, by setting the eighth transistor M8 controlled by the signal output terminal OUT, a large current generated by a path formed between the fourth transistor M4 and the ninth transistor M9 is avoided, power consumption generated by the shift register is greatly reduced, and meanwhile, by setting the sixth transistor M6 controlled by the signal output terminal OUT, a path between the pull-up node PU and the fifth transistor M5 is avoided, the level of the pull-up node PU is prevented from being pulled down, and it is ensured that the shift register can normally operate.

In this embodiment, in the display phase, the signal at the signal INPUT terminal INPUT is a pulse signal, and is high level only in the INPUT phase; the output signal of the signal output end OUT is a pulse signal and is high level only in the output stage; the input signal of the first reset terminal RST1 is a pulse signal and is high only in the reset phase.

Based on the same application concept, an embodiment of the present application further provides a gate driving circuit, and fig. 13 is a schematic structural diagram of the gate driving circuit provided in the embodiment of the present application, as shown in fig. 13, the gate driving circuit provided in the embodiment of the present application includes: a plurality of cascaded shift registers.

The shift register provided in the foregoing embodiments has similar implementation principles and implementation effects, and is not described herein again.

Optionally, as shown in fig. 13, the gate driving circuit provided in the embodiment of the present application includes: an initial signal terminal STV and a reset control terminal RST.

Specifically, a signal INPUT end INPUT of the first-stage shift register GOA (1) is connected to the initial signal end STV, a signal output end OUT of the nth-stage shift register GOA (N) is connected to a signal INPUT end INPUT of the (N +1) th-stage shift register GOA (N +1), and a signal output end OUT of the (N +1) th-stage shift register GOA (N +1) is connected to a first reset end RST1 of the nth-stage shift register GOA (N); the second reset terminals RST2 of all the stage shift registers are connected to a reset control terminal RST.

Based on the same application concept, an embodiment of the present application further provides a driving method of a shift register, which is applied to the shift register, fig. 14 is a flowchart of the driving method of the shift register provided in the embodiment of the present application, and as shown in fig. 14, the driving method of the shift register provided in the embodiment of the present application specifically includes the following steps in a display period:

step 100, under the control of a signal input end, an input sub-circuit provides a signal of a first signal end to a pull-up node; under the control of the second clock terminal, the node pull-up sub-circuit provides a signal of the second clock terminal to the pull-down node.

200, under the control of a pull-up node and a first power supply end, an output sub-circuit provides a signal of a first clock end for a signal output end; under the control of the pull-up node and the signal output terminal, the node pull-down sub-circuit provides a signal of the second power supply terminal to the pull-down node.

Step 300, under the control of the pull-down node and the signal output terminal, the noise reduction sub-circuit provides the signal of the second power supply terminal to the pull-up node and the signal output terminal.

Optionally, the driving method of the shift register provided in the embodiment of the present application further includes: the first reset sub-circuit provides a signal of the second signal terminal to the pull-up node under the control of the first reset terminal.

Optionally, in the touch stage, the driving method of the shift register provided in the embodiment of the present application further includes: and under the control of the touch control enabling end, providing a signal of a second power end to the signal output end.

Optionally, in the touch stage, the driving method of the shift register provided in the embodiment of the present application further includes: and under the control of the second reset terminal, providing a signal of the second power terminal to the pull-up node.

The drawings of the embodiments of the present application relate only to the structures related to the embodiments of the present application, and other structures may refer to general designs.

Although the embodiments disclosed in the present application are described above, the descriptions are only for the convenience of understanding the present application, and are not intended to limit the present application. It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the disclosure as defined by the appended claims.

Claims

1. A shift register, comprising: an input sub-circuit, an output sub-circuit, a node pull-up sub-circuit, a node pull-down sub-circuit, and a noise reduction sub-circuit;

2. The shift register of claim 1, further comprising: the touch control circuit comprises a first reset sub-circuit, a second reset sub-circuit and a touch control sub-circuit;

3. The shift register of claim 1, wherein the input sub-circuit comprises: a first transistor;

4. The shift register of claim 1, wherein the node pull-up subcircuit comprises: a fourth transistor;

5. The shift register of claim 1, wherein the node pull-down subcircuit comprises: eighth to tenth transistors;

6. The shift register of claim 2, wherein the first reset subcircuit comprises: an eleventh transistor;

the second reset sub-circuit includes: a twelfth transistor;

the touch subcircuit includes: a thirteenth transistor;

7. The shift register of claim 1, further comprising: the touch control circuit comprises a first reset sub-circuit, a second reset sub-circuit and a touch control sub-circuit; the input sub-circuit includes: a first transistor; the output sub-circuit includes: a second transistor, a third transistor, and a first capacitor; the node pull-up sub-circuit comprises: a fourth transistor; the noise reduction sub-circuit comprises: fifth to seventh transistors and a second capacitor; the node pull-down sub-circuit comprises: eighth to tenth transistors; the first reset sub-circuit includes: an eleventh transistor; the second reset sub-circuit includes: a twelfth transistor; the touch subcircuit includes: a thirteenth transistor;

the second end of the first capacitor is connected with the signal output end;

8. The shift register of claim 1, wherein the level of the clock signal of the second clock terminal is an inactive level when the level of the clock signal of the first clock terminal is an active level, and the level of the clock signal of the first clock terminal is an inactive level when the level of the clock signal of the second clock terminal is an active level.

9. A gate drive circuit, comprising: a plurality of cascaded shift registers as claimed in any one of claims 1 to 8.

10. A gate drive circuit as claimed in claim 9, wherein the gate drive circuit comprises: an initial signal end and a reset control end;

11. A method for driving a shift register, which is applied to the shift register according to any one of claims 1 to 10, and which includes, during a display period:

12. The method of claim 11, further comprising: the first reset sub-circuit provides a signal of the second signal terminal to the pull-up node under the control of the first reset terminal.