CN104575437B - Shifting register, driving method of shifting register, grid driving circuit and display device - Google Patents

Shifting register, driving method of shifting register, grid driving circuit and display device Download PDF

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Publication number
CN104575437B
CN104575437B CN201510065143.5A CN201510065143A CN104575437B CN 104575437 B CN104575437 B CN 104575437B CN 201510065143 A CN201510065143 A CN 201510065143A CN 104575437 B CN104575437 B CN 104575437B
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signal
current potential
nodal point
potential
switching transistor
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CN201510065143.5A
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CN104575437A (en
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闫岩
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京东方科技集团股份有限公司
北京京东方显示技术有限公司
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Abstract

The invention discloses a shifting register, a driving method of the shifting register, a grid driving circuit and a display device. The shifting register comprises an input module, an output module, a reset module and a discharging module; as the discharging module can control the electric potential of a second node as a first electric potential after the electric potential of a reset signal is a first electric potential and before the electric potential of a triggering signal is the first electric potential, and a reference signal is provided to a first node and a signal output end when the electric potential of the second node is the first electric potential, the first node and the signal output end can be ensured to be effectively discharged within a time period after the electric potential of the reset signal of the shifting register is the first electric potential and before the electric potential of the triggering signal is the first electric potential, so that the output accuracy of the shifting register is ensured.

Description

A kind of shift register, its driving method, gate driver circuit and display device

Technical field

The present invention relates to display technology field, more particularly, to a kind of shift register, its driving method, gate driver circuit And display device.

Background technology

In TFT thin film transistor monitor, generally pass through gate driver circuit each thin film transistor (TFT) to pixel region The grid of (tft, thin film transistor) provides gate drive signal.Gate driver circuit can pass through array processes It is formed on the array base palte of liquid crystal display, i.e. array base palte row cutting (gate driver on array, goa) technique, This integrated technique not only saves cost, and can accomplish the symmetrical design for aesthetic in liquid crystal panel (panel) both sides, with When, also eliminate binding (bonding) region and the fan-out of grid integrated circuits (ic, integrated circuit) (fan-out) wiring space, such that it is able to realize the design of narrow frame.

Existing goa circuit, as shown in Figure 1a, is made up of multiple shift registers, each shift register be used for The grid line that the signal output part of this shift register is connected provides gated sweep signal, and posts to the upper displacement being adjacent The reset signal end input reset signal of storage, to the signal input part input triggering of the next shift register being adjacent Signal.As shown in Figure 1 b, be an existing shift register structural representation, using 4 thin film transistor (TFT) m1-m4 and Individual electric capacity c1 can realize most basic shift-register functions, and concrete operating principle is as follows: in the input of trigger input end During high potential signal, the conducting of first film transistor m1 is that pu node charges to pull-up node, now the 3rd thin film transistor (TFT) m3 Conducting;When clock signal clk end input high potential signal, the 3rd thin film transistor (TFT) m3 of conducting makes signal output part output The high potential signal that output clock signal clk end provides, simultaneously because pu node is further pulled up by the boot strap of electric capacity c1; Afterwards, during reset signal reset end input high potential signal, the second thin film transistor (TFT) m2 and the 4th thin film transistor (TFT) m4 conducting, To pu node and signal output part output electric discharge.

It is known that in goa circuit, synchronization, only when the high electricity of signal output part output of level shift register Position signal, the signal output part of other level shift registers is required to export low-potential signal.But in existing shift LD In device, the such as shift register shown in Fig. 1 b, only in reset signal reset end input high potential signal ability to pu node and Signal output part output discharges, and the duration that reset signal reset end inputs high potential signal is only next stage displacement The signal output part output of depositor exports the time of high potential signal, then when the signal output part of level shift register In output needs the other time of output low-potential signal, because the drain electrode of m3 connects clock signal clk end, the therefore drain electrode of m3 There is electric capacity and grid between, so that the current potential of the grid of m3 can be affected by exchange clock signal, work for a long time The potential duration leading to m3 grid raises, and makes m3 in the conduction state, then as long as when clock signal clk is high potential signal When, the signal output part output of shift register will export high potential signal, thus it is wrong to lead to shift register to occur Export by mistake.

Content of the invention

In view of this, the embodiment of the present invention provides a kind of shift register, its driving method, gate driver circuit and display Device, for solving the problems, such as that what existing shift register existed be susceptible to output error.

Therefore, embodiments provide a kind of shift register, comprising: input module, output module and reset mould Block and discharge module;Wherein,

Described input module, in response to trigger, under the control of described trigger, controls described first segment The current potential of point is the first current potential, and the current potential of secondary nodal point is the second current potential, and described output module is charged;Described first Node is on the described input module of connection, the wire of described output module, described reseting module and described discharge module;Institute State secondary nodal point to be located on the wire connecting described reseting module and described discharge module;

Described output module, for when the current potential of described primary nodal point is the first current potential, clock signal being supplied to letter Number outfan;

Described reseting module, in response to reset signal, under the control of described reset signal, controls described first segment The current potential of point is the second current potential, and the current potential of described secondary nodal point is the first current potential, and described discharge module is charged, and Reference signal is supplied to signal output part;

Discharge module, for the current potential to described trigger after the current potential of described reset signal is the first current potential be Before first current potential, control described secondary nodal point current potential be the first current potential, and described secondary nodal point current potential be first During current potential, reference signal is supplied to described primary nodal point and described signal output part;

The effective impulse signal of described trigger is high potential signal, and described first current potential is high potential, described second Current potential is electronegative potential, and described reference signal is low-potential direct signal;The effective impulse signal of described trigger is electronegative potential Signal, described first current potential is electronegative potential, and described second current potential is high potential, and described reference signal is high potential direct current signal.

In a kind of possible embodiment, in above-mentioned shift register provided in an embodiment of the present invention,

Described input module, specifically includes: first switch transistor and second switch transistor;Wherein,

Described first switch transistor, its grid and source electrode are used to receive described trigger, drain electrode and described first Node is connected;

Described second switch transistor, its grid is used for receiving described trigger, and source electrode is used for receiving described reference letter Number, drain electrode is connected with described secondary nodal point.

In a kind of possible embodiment, in above-mentioned shift register provided in an embodiment of the present invention,

Described output module, specifically includes: the 3rd switching transistor and the first electric capacity;Wherein,

Described 3rd switching transistor, its grid is connected with described primary nodal point, and source electrode is used for receiving described clock signal, Drain electrode is connected with described signal output part;

Described first capacitance connection is between the grid of described 3rd switching transistor and drain electrode.

In a kind of possible embodiment, in above-mentioned shift register provided in an embodiment of the present invention,

Described reseting module, specifically includes: the 4th switching transistor, the 5th switching transistor and the 6th switching transistor; Wherein,

Described 4th switching transistor, its grid is used for receiving described reset signal, and source electrode is used for receiving described reference letter Number, its drain electrode is connected with described primary nodal point;

Described 5th switching transistor, its grid is used for receiving described reset signal, and source electrode is used for receiving described reference letter Number, its drain electrode is connected with described signal output part;

Described 6th switching transistor, its grid and source electrode are used to receive described reset signal, its drain electrode and described the Two nodes are connected.

In a kind of possible embodiment, in above-mentioned shift register provided in an embodiment of the present invention,

Described discharge module, specifically includes: the 7th switching transistor, the 8th switching transistor and the second electric capacity;Wherein,

Described 7th switching transistor, its grid is connected with described secondary nodal point, and source electrode is used for receiving described reference signal, Drain electrode is connected with described signal output part;

Described 8th switching transistor, its grid is connected with described secondary nodal point, and source electrode is used for receiving described reference signal, Drain electrode is connected with described primary nodal point;

Described second capacitance connection is between the grid and source electrode of described 7th switching transistor.

In a kind of possible embodiment, in above-mentioned shift register provided in an embodiment of the present invention,

When the effective impulse signal of described trigger is high potential signal, all switching transistors are n-type transistor;

When the effective impulse signal of described trigger is low-potential signal, all switching transistors are p-type transistor.

Correspondingly, the embodiment of the present invention additionally provides a kind of driving method of any of the above-described kind of shift register, comprising:

In input phase, described output module, in response to trigger, under the control of described trigger, controls described The current potential of primary nodal point is the first current potential, and the current potential of secondary nodal point is the second current potential, and described output module is charged;Institute State output module and clock signal is supplied to signal output part;

In the output stage, it is the first current potential that described output module keeps the current potential of described primary nodal point, and by described clock Signal is supplied to signal output part;

In reseting stage, described reseting module, in response to reset signal, under the control of described reset signal, controls described The current potential of primary nodal point is the second current potential, and the current potential of described secondary nodal point is the first current potential, and described discharge module is filled Electricity, and reference signal is supplied to signal output part;Described discharge module by reference signal be supplied to described primary nodal point and Described signal output part;

In discharge regime, it is the first current potential that described discharge module controls the current potential of secondary nodal point, and reference signal is provided To described primary nodal point and described signal output part.

Correspondingly, the embodiment of the present invention additionally provides a kind of gate driver circuit, and the multiple present invention including cascade are implemented Any of the above-described kind of shift register that example provides;Wherein,

In addition to first order shift register, the signal output part of remaining every one-level shift register is respectively to being adjacent Upper level shift register input reset signal;

In addition to afterbody shift register, the signal output part of remaining every one-level shift register respectively to its phase Adjacent next stage shift register input trigger;

The trigger that described first order shift register is received is inputted by frame start signal end;

Described gate driver circuit sequentially exports the raster data model letter of the signal output part output of shift registers at different levels Number.

Correspondingly, the embodiment of the present invention additionally provides a kind of display device, including above-mentioned provided in an embodiment of the present invention A kind of gate driver circuit.

Above-mentioned shift register provided in an embodiment of the present invention, its driving method, gate driver circuit and display device, move Bit register includes: input module, output module and reseting module and discharge module;Because discharge module can be in reset signal Current potential be after the first current potential to trigger current potential be the first current potential before, the current potential controlling secondary nodal point is the first electricity Position, and when the current potential of secondary nodal point is the first current potential, reference signal is supplied to primary nodal point and signal output part;Thus Can ensure that this shift register after the current potential of reset signal is the first current potential to trigger current potential be the first current potential In time period before, primary nodal point and signal output part are effectively discharged, and then be ensure that shift register output Accuracy.

Brief description

Fig. 1 a is the structural representation of existing goa circuit;

Fig. 1 b is the structural representation of existing shift register;

Fig. 2 is the structural representation of shift register provided in an embodiment of the present invention;

Fig. 3 a is one of concrete structure schematic diagram of shift register provided in an embodiment of the present invention;

Fig. 3 b is the two of the concrete structure schematic diagram of shift register provided in an embodiment of the present invention;

Fig. 4 a is the circuit sequence schematic diagram of the shift register shown in Fig. 3 a;

Fig. 4 b is the circuit sequence schematic diagram of the shift register shown in Fig. 3 b;

Fig. 5 is the schematic flow sheet of the driving method of shift register provided in an embodiment of the present invention;

Fig. 6 is the structural representation of gate driver circuit provided in an embodiment of the present invention.

Specific embodiment

Below in conjunction with the accompanying drawings, to shift register provided in an embodiment of the present invention, its driving method, gate driver circuit and The specific embodiment of display device is described in detail.

A kind of shift register provided in an embodiment of the present invention, as shown in Figure 2, comprising: input module 1, output module 2 and Reseting module 3 and discharge module 4;Wherein,

Input module 1, in response to trigger input, under the control of trigger input, controls first segment The current potential of point pu is the first current potential, and the current potential of secondary nodal point pd is the second current potential, and output module 2 is charged;First segment Point pu is on connection input module 1, the wire of output module 2, reseting module 3 and discharge module 4;Secondary nodal point pd is located at Connect on reseting module 3 and the wire of discharge module 4;

Output module 2, for when the current potential of primary nodal point pu is the first current potential, clock signal clk being supplied to signal Outfan;

Reseting module 3, in response to reset signal reset, under the control of reset signal reset, controls first segment The current potential of point pu is the second current potential, and the current potential of secondary nodal point pd is the first current potential, and discharge module 4 is charged, and will Reference signal vref is supplied to signal output part output;

Discharge module 4, for the electricity to trigger input after the current potential of reset signal reset is the first current potential Position is for before the first current potential, controlling the current potential of secondary nodal point pd to be the first current potential, and is first in the current potential of secondary nodal point pd During current potential, reference signal vref is supplied to primary nodal point pu and signal output part output;

The effective impulse signal of trigger input is high potential signal, and the first current potential is high potential, and the second current potential is low Current potential, reference signal vref is low-potential direct signal;The effective impulse signal of trigger input is low-potential signal, the One current potential is electronegative potential, and the second current potential is high potential, and reference signal vref is high potential direct current signal.

Above-mentioned shift register provided in an embodiment of the present invention, comprising: input module, output module and reseting module and put Electric module;Because discharge module can the current potential to trigger be the first electricity after the current potential of reset signal is the first current potential Before position, the current potential controlling secondary nodal point is the first current potential, and will be with reference to letter when the current potential of secondary nodal point is the first current potential Number it is supplied to primary nodal point and signal output part;Thereby may be ensured that this shift register is the first electricity in the current potential of reset signal After position, the current potential to trigger is in the time period before the first current potential, and primary nodal point and signal output part are carried out effectively Electric discharge, and then ensure that the accuracy of shift register output.

With reference to specific embodiment, the present invention is described in detail.It should be noted that in the present embodiment be in order to Preferably explain the present invention, but do not limit the present invention.

Specifically, in above-mentioned shift register provided in an embodiment of the present invention, as shown in Figure 3 a and Figure 3 b shows, input module 1, specifically may include that first switch transistor m1 and second switch transistor m2;Wherein,

First switch transistor m1, its grid and source electrode are used to receive trigger input, drain electrode and primary nodal point pu It is connected;

Second switch transistor m2, its grid is used for receiving trigger input, and source electrode is used for receiving reference signal Vref, drain electrode is connected with secondary nodal point pd.

In above-mentioned shift register provided in an embodiment of the present invention, first switch transistor and second switch transistor can Think n-type transistor or p-type transistor.As shown in Figure 3 a, when first switch transistor m1 and second switch transistor When m2 is n-type transistor, when trigger input is high potential signal, first switch transistor m1 and second switch transistor M2 turns on, when trigger input is low-potential signal, first switch transistor m1 and second switch transistor m2 cut-off.Instead It, as shown in Figure 3 b, when first switch transistor m1 and second switch transistor m2 is p-type transistor, trigger input During for low-potential signal, first switch transistor m1 and second switch transistor m2 conducting, trigger input is believed for high potential Number when, first switch transistor m1 and second switch transistor m2 cut-off.

The above is only the concrete structure illustrating input module in shift register, in the specific implementation, input module Concrete structure be not limited to said structure provided in an embodiment of the present invention, can also be skilled person will appreciate that other knot Structure, here does not limit.

Specifically, in above-mentioned shift register provided in an embodiment of the present invention, as shown in Figure 3 a and Figure 3 b shows, output module 2, specifically may include that the 3rd switching transistor m3 and the first electric capacity c1;Wherein,

3rd switching transistor m3, its grid is connected with primary nodal point pu, and source electrode is used for receiving clock signal clk, drain electrode It is connected with signal output part output;

First electric capacity c1 is connected between the grid of the 3rd switching transistor m3 and drain electrode.

Specifically, in above-mentioned shift register provided in an embodiment of the present invention, the 3rd switching transistor m3 can be N-shaped Transistor or p-type transistor.As shown in Figure 3 a, when the 3rd switching transistor m3 is n-type transistor, primary nodal point When the current potential of pu is high potential, the 3rd switching transistor m3 conducting, when the current potential of primary nodal point pu is electronegative potential, the 3rd switch is brilliant Body pipe m3 ends.The operation principle of this output module is, when input module 1 charges to the first electric capacity c1, primary nodal point pu's Current potential is high potential, the 3rd switching transistor m3 conducting, and now, clock signal clk of electronegative potential passes through the 3rd switch of conducting Transistor m3 is supplied to signal output part output, afterwards, when clock signal clk is changed into high potential from electronegative potential, the first electricity The current potential holding one end that c1 is connected with the 3rd switching transistor m3 grid is also changed into high potential from electronegative potential, according to the first electric capacity c1 Boot strap, one end that the first electric capacity c1 is connected with primary nodal point pu is further pulled up, so that the 3rd switching transistor The current potential of the grid of m3 keeps high potential, so that clock signal clk by high potential that the 3rd switching transistor m3 can be stable It is supplied to signal output part output.

Conversely, as shown in Figure 3 b, when the 3rd switching transistor m3 is p-type transistor, the current potential of primary nodal point pu is low During current potential, the 3rd switching transistor m3 conducting, when the current potential of primary nodal point pu is high potential, the 3rd switching transistor m3 cut-off. The operation principle of this output module is, when input module 1 charges to the first electric capacity c1, the current potential of primary nodal point pu is low electricity Position, the 3rd switching transistor m3 conducting, now, clock signal clk of high potential is carried by the 3rd switching transistor m3 of conducting Supply signal output part output, afterwards, when clock signal clk is changed into electronegative potential from high potential, the first electric capacity c1 and the 3rd The current potential of one end that switching transistor m3 grid is connected also is changed into electronegative potential from high potential, and the bootstrapping according to the first electric capacity c1 is made With, one end that the first electric capacity c1 is connected with primary nodal point pu is dragged down further, so that the grid of the 3rd switching transistor m3 Current potential keep electronegative potential so that what the 3rd switching transistor m3 can be stable is supplied to letter by clock signal clk of electronegative potential Number outfan output.

The above is only the concrete structure illustrating output module in shift register, in the specific implementation, output module Concrete structure be not limited to said structure provided in an embodiment of the present invention, can also be skilled person will appreciate that other knot Structure, here does not limit.

Specifically, in above-mentioned shift register provided in an embodiment of the present invention, as shown in Figure 3 a and Figure 3 b shows, reseting module 3, specifically may include that the 4th switching transistor m4, the 5th switching transistor m5 and the 6th switching transistor m6;Wherein,

4th switching transistor m4, its grid is used for receiving reset signal reset, and source electrode is used for receiving reference signal Vref, its drain electrode is connected with primary nodal point pu;

5th switching transistor m5, its grid is used for receiving reset signal reset, and source electrode is used for receiving reference signal Vref, its output that is connected with signal output part that drains;

6th switching transistor m6, its grid and source electrode are used to receive reset signal reset, and it drains and secondary nodal point Connected pd.

In above-mentioned shift register provided in an embodiment of the present invention, the 4th switching transistor m4, the 5th switching transistor M5 and the 6th switching transistor m6 can be n-type transistor or p-type transistor.As shown in Figure 3 a, when the 4th switch is brilliant When body pipe m4, the 5th switching transistor m5 and the 6th switching transistor m6 are n-type transistor, reset signal reset is high potential During signal, the 4th switching transistor m4, the 5th switching transistor m5 and the conducting of the 6th switching transistor m6, reset signal reset During for low-potential signal, the 4th switching transistor m4, the 5th switching transistor m5 and the cut-off of the 6th switching transistor m6.Conversely, As shown in Figure 3 b, when the 4th switching transistor m4, the 5th switching transistor m5 and the 6th switching transistor m6 are p-type transistor When, when reset signal reset is low-potential signal, the 4th switching transistor m4, the 5th switching transistor m5 and the 6th switch are brilliant Body pipe m6 turns on, when reset signal reset is high potential signal, the 4th switching transistor m4, the 5th switching transistor m5 and the Six switching transistor m6 cut-offs.

The above is only the concrete structure illustrating reseting module in shift register, in the specific implementation, reseting module Concrete structure be not limited to said structure provided in an embodiment of the present invention, can also be skilled person will appreciate that other knot Structure, here does not limit.

Specifically, in above-mentioned shift register provided in an embodiment of the present invention, as shown in Figure 3 a and Figure 3 b shows, discharge module 4, specifically may include that the 7th switching transistor m7, the 8th switching transistor m8 and the second electric capacity c2;Wherein,

7th switching transistor m7, its grid is connected with secondary nodal point pd, and source electrode is used for receiving reference signal vref, drain electrode It is connected with signal output part output;

8th switching transistor m8, its grid is connected with secondary nodal point pd, and source electrode is used for receiving reference signal vref, drain electrode It is connected with primary nodal point pu;

Second electric capacity c2 is connected between grid and the source electrode of the 7th switching transistor m7.

Specifically, in above-mentioned shift register provided in an embodiment of the present invention, the 7th switching transistor m7 and the 8th is opened Closing transistor m8 can be n-type transistor or p-type transistor.As shown in Figure 3 a, when the 7th switching transistor m7 and When eight switching transistors m8 are n-type transistor, when the current potential of secondary nodal point pd is high potential, the 7th switching transistor m7 and the 8th Switching transistor m8 turns on, when the current potential of secondary nodal point pd is electronegative potential, the 7th switching transistor m7 and the 8th switching transistor M8 ends.The operation principle of this discharge module is, when reseting module 3 charges to the second electric capacity c2, the current potential of secondary nodal point pd For high potential, the 7th switching transistor m7 and the conducting of the 8th switching transistor m8, now, reference signal vref of electronegative potential is passed through The 7th switching transistor m7 being respectively turned on is supplied to signal output part output, is carried by the 8th switching transistor m8 of conducting Supply first segment pu, afterwards until the current potential of trigger input is changed into high potential, the second electric capacity c2 and reference signal vref phase The current potential of one end even remains electronegative potential, according to the boot strap of the second electric capacity c2, the second electric capacity c2 and secondary nodal point pd Connected one end equally remains high potential during charging, so that the 7th switching transistor m7 and the 8th switching transistor m8 Grid current potential keep high potential, thus by reference signal vref of electronegative potential pass through turn on the 7th switching transistor m7 carry Supply signal output part output, is supplied to first segment pu by the 8th switching transistor m8 of conducting, to keep defeated to signal Go out to hold the continuous discharge of the first segment pu of output.

Conversely, as shown in Figure 3 b, when the 7th switching transistor m7 and the 8th switching transistor m8 are p-type transistor, the When the current potential of two node pd is electronegative potential, the 7th switching transistor m7 and the 8th switching transistor m8 turn on, secondary nodal point pd's When current potential is high potential, the 7th switching transistor m7 and the 8th switching transistor m8 are ended.The operation principle of this discharge module is, When reseting module 3 charges to the second electric capacity c2, the current potential of secondary nodal point pd is electronegative potential, the 7th switching transistor m7 and the 8th Switching transistor m8 turns on, and now, the 7th switching transistor m7 that reference signal vref of high potential is passed through to be respectively turned on provides To signal output part output, first segment pu is supplied to by the 8th switching transistor m8 of conducting, afterwards up to trigger The current potential of input is changed into electronegative potential, and the current potential of one end that the second electric capacity c2 is connected with reference signal vref remains high potential, According to the boot strap of the second electric capacity c2, one end that the second electric capacity c2 is connected with secondary nodal point pd equally remains during charging Electronegative potential, so that the current potential of the grid of the 7th switching transistor m7 and the 8th switching transistor m8 keeps electronegative potential, thus will Reference signal vref of high potential is supplied to signal output part output by the 7th switching transistor m7 of conducting, by conducting The 8th switching transistor m8 be supplied to first segment pu, to keep the type discharge to the first segment pu of signal output part output Electricity.

The above is only the concrete structure illustrating discharge module in shift register, in the specific implementation, discharge module Concrete structure be not limited to said structure provided in an embodiment of the present invention, can also be skilled person will appreciate that other knot Structure, here does not limit.

It is preferred that in above-mentioned shift register provided in an embodiment of the present invention, switching transistor generally individually adopts identical The transistor of material, in the specific implementation, when the effective impulse signal of trigger is high potential signal, all switching transistors All using n-type transistor;When the effective impulse signal of trigger is low-potential signal, all switching transistors are all using p-type Transistor.

It should be noted that the switching transistor mentioned in the above embodiment of the present invention can be thin film transistor (TFT) (tft, Thin film transistor) or metal oxide semiconductor field effect tube (mos, metal oxide Scmiconductor), here does not limit.In being embodied as, the source electrode of these switching transistors and drain electrode are according to transistor Type and the difference of input signal, its function can be exchanged, and here does not do concrete differentiation.

With reference to the work to embodiment of the present invention shift register as a example the shift register shown in Fig. 3 a and Fig. 3 b Process is described.High potential signal is represented with 1,0 expression low-potential signal in described below.

Example one:

As a example shift register shown in by Fig. 3 a, all switching transistors in shift register are n-type transistor, Corresponding input and output sequential enters as shown in fig. 4 a.Specifically, choose t1 in input and output sequential chart as shown in fig. 4 a~ T4 four-stage.

In t1 stage, input=1, clk=0, reset=0.Due to reset=0, the therefore the 4th switching transistor m4, 5th switching transistor m5 and the 6th switching transistor m6 are in cut-off state;Due to input=1, therefore first switch crystal Pipe m1 and second switch transistor m2 conducting, trigger input of high potential passes through the first switch transistor m1 biography of conducting Defeated therefore the current potential of primary nodal point pu is high potential to primary nodal point pu, and the first electric capacity c1 starts to charge up, the first segment of high potential Point pu controls the 3rd switching transistor m3 in the conduction state, and clock signal clk of electronegative potential passes through the 3rd switch crystalline substance of conducting Body pipe is supplied to signal output part output;Meanwhile, reference signal vref of electronegative potential passes through the second switch transistor of conducting M2 is transferred to secondary nodal point pd, and the current potential of secondary nodal point pd is electronegative potential, and the therefore the 7th switching transistor m7 and the 8th switch are brilliant Body pipe m8 is in cut-off state;Therefore signal output part output exports low-potential signal.

In t2 stage, input=0, clk=1, reset=0.Due to reset=0, the therefore the 4th switching transistor m4, 5th switching transistor m5 and the 6th switching transistor m6 are in cut-off state;Due to input=0, therefore first switch crystal Pipe m1 and second switch transistor m2 is in cut-off state;Due to clk=1, the therefore first electric capacity c1 and the 3rd switching transistor The current potential of one end that m3 grid is connected is changed into high potential from electronegative potential, according to the boot strap of the first electric capacity c1, the first electric capacity c1 The one end being connected with primary nodal point pu is further pulled up, so that the current potential of the grid of the 3rd switching transistor m3 keeps high electricity Position, what the 3rd switching transistor m3 was stable is supplied to signal output part output by clock signal clk of high potential;Therefore signal Outfan output exports high potential signal.

In t3 stage, input=0, clk=0, reset=1.Due to input=0, therefore first switch transistor m1 and Second switch transistor m2 is in cut-off state;Due to reset=1, the therefore the 4th switching transistor m4, the 5th switching transistor M5 and the 6th switching transistor m6 are in the conduction state, and the 4th switching transistor m4 of conducting is by reference signal vref of electronegative potential It is supplied to primary nodal point pu, the therefore current potential of primary nodal point pu is electronegative potential, and the 3rd switching transistor m3 is in cut-off state, the One electric capacity c1 is discharged, and reset signal reset of high potential is supplied to secondary nodal point by the 6th switching transistor m6 of conducting Pd, the therefore current potential of secondary nodal point pd are high potential, and the second electric capacity c2 starts to charge up, because the current potential of the pd of secondary nodal point is height Current potential, the therefore the 7th switching transistor m7 and the 8th switching transistor m8 are in the conduction state, the 7th switching transistor of conducting Reference signal vref of electronegative potential is supplied to signal output part output by m7, and the 8th switching transistor m8 of conducting is by electronegative potential Reference signal vref be supplied to first segment pu, therefore, the current potential of primary nodal point pu is electronegative potential, and signal output part output is defeated Go out low-potential signal.

In t4 stage, input=0, reset=0, clk=0 or clk=1.Due to input=0, therefore first switch is brilliant Body pipe m1 and second switch transistor m2 is in cut-off state;Due to reset=0, the therefore the 4th switching transistor m4, the 5th open Close transistor m5 and the 6th switching transistor m6 is in cut-off state;Due to the second electric capacity c2 be connected with reference signal vref one The current potential at end remains electronegative potential, and according to the boot strap of the second electric capacity c2, the second electric capacity c2 is connected with secondary nodal point pd One end remains high potential during charging, so that the 7th switching transistor m7 and the 8th switching transistor m8 are on shape State, reference signal vref of electronegative potential is supplied to signal output part output by the 7th switching transistor m7 of conducting, conducting Reference signal vref of electronegative potential is supplied to first segment pu by the 8th switching transistor m8, and the therefore current potential of primary nodal point pu is low Current potential, the 3rd switching transistor m3 is in cut-off state, therefore, no matter clock signal clk is high potential or electronegative potential, clock Signal clk will not be transferred to signal output part output all the time, and signal output part output is the reference letter exporting electronegative potential Number vref;Therefore signal output part output exports low-potential signal.

Above-mentioned shift register provided in an embodiment of the present invention, by the 7th switching transistor m7, the 8th switching transistor M8 and the effect of the second electric capacity c2, make shift register remain the electricity of primary nodal point pu and signal output part in discharge regime Position is electronegative potential, thus the accuracy of the output signal ensureing.

Example two:

As a example shift register shown in by Fig. 3 b, all switching transistors in shift register are p-type transistor, Corresponding input and output sequential enters as shown in Figure 4 b.Specifically, choose t1 in input and output sequential chart as shown in Figure 4 b~ T4 four-stage.

In t1 stage, input=0, clk=1, reset=1.Due to reset=1, the therefore the 4th switching transistor m4, 5th switching transistor m5 and the 6th switching transistor m6 are in cut-off state;Due to input=0, therefore first switch crystal Pipe m1 and second switch transistor m2 conducting, trigger input of electronegative potential passes through the first switch transistor m1 biography of conducting Defeated therefore the current potential of primary nodal point pu is electronegative potential to primary nodal point pu, and the first electric capacity c1 starts to charge up, the first segment of electronegative potential Point pu controls the 3rd switching transistor m3 in the conduction state, and clock signal clk of high potential passes through the 3rd switch crystalline substance of conducting Body pipe is supplied to signal output part output;Meanwhile, reference signal vref of high potential passes through the second switch transistor of conducting M2 is transferred to secondary nodal point pd, and the current potential of secondary nodal point pd is high potential, and the therefore the 7th switching transistor m7 and the 8th switch are brilliant Body pipe m8 is in cut-off state;Therefore signal output part output exports high potential signal.

In t2 stage, input=1, clk=0, reset=1.Due to reset=1, the therefore the 4th switching transistor m4, 5th switching transistor m5 and the 6th switching transistor m6 are in cut-off state;Due to input=1, therefore first switch crystal Pipe m1 and second switch transistor m2 is in cut-off state;Due to clk=0, the therefore first electric capacity c1 and the 3rd switching transistor The current potential of one end that m3 grid is connected is changed into electronegative potential from high potential, according to the boot strap of the first electric capacity c1, the first electric capacity c1 The one end being connected with primary nodal point pu is dragged down further, so that the current potential of the grid of the 3rd switching transistor m3 keeps low electricity Position, what the 3rd switching transistor m3 was stable is supplied to signal output part output by clock signal clk of electronegative potential;Therefore signal Outfan output exports low-potential signal.

In t3 stage, input=1, clk=1, reset=0.Due to input=1, therefore first switch transistor m1 and Second switch transistor m2 is in cut-off state;Due to reset=0, the therefore the 4th switching transistor m4, the 5th switching transistor M5 and the 6th switching transistor m6 are in the conduction state, and the 4th switching transistor m4 of conducting is by reference signal vref of high potential It is supplied to primary nodal point pu, the therefore current potential of primary nodal point pu is high potential, and the 3rd switching transistor m3 is in cut-off state, the One electric capacity c1 is discharged, and reset signal reset of electronegative potential is supplied to secondary nodal point by the 6th switching transistor m6 of conducting Pd, the therefore current potential of secondary nodal point pd are electronegative potential, and the second electric capacity c2 starts to charge up, because the current potential of the pd of secondary nodal point is low Current potential, the therefore the 7th switching transistor m7 and the 8th switching transistor m8 are in the conduction state, the 7th switching transistor of conducting Reference signal vref of high potential is supplied to signal output part output by m7, and the 8th switching transistor m8 of conducting is by high potential Reference signal vref be supplied to first segment pu, therefore, the current potential of primary nodal point pu is high potential, and signal output part output is defeated Go out high potential signal.

In t4 stage, input=1, reset=1, clk=0 or clk=1.Due to input=1, therefore first switch is brilliant Body pipe m1 and second switch transistor m2 is in cut-off state;Due to reset=1, the therefore the 4th switching transistor m4, the 5th open Close transistor m5 and the 6th switching transistor m6 is in cut-off state;Due to the second electric capacity c2 be connected with reference signal vref one The current potential at end remains high potential, and according to the boot strap of the second electric capacity c2, the second electric capacity c2 is connected with secondary nodal point pd One end remains electronegative potential during charging, so that the 7th switching transistor m7 and the 8th switching transistor m8 are on shape State, reference signal vref of high potential is supplied to signal output part output by the 7th switching transistor m7 of conducting, conducting Reference signal vref of high potential is supplied to first segment pu by the 8th switching transistor m8, and the therefore current potential of primary nodal point pu is height Current potential, the 3rd switching transistor m3 is in cut-off state, therefore, no matter clock signal clk is high potential or electronegative potential, clock Signal clk will not be transferred to signal output part output all the time, and signal output part output is the reference letter exporting high potential Number vref;Therefore signal output part output exports high potential signal.

Above-mentioned shift register provided in an embodiment of the present invention, by the 7th switching transistor m7, the 8th switching transistor M8 and the effect of the second electric capacity c2, make shift register remain the electricity of primary nodal point pu and signal output part in discharge regime Position is high potential, thus the accuracy of the output signal ensureing.

Based on same inventive concept, the embodiment of the present invention additionally provides the driving method of any of the above-described kind of shift register, As shown in figure 5, specifically may comprise steps of:

S501, in input phase, output module in response to trigger, under the control of trigger, control first segment The current potential of point is the first current potential, and the current potential of secondary nodal point is the second current potential, and output module is charged;Output module by when Clock signal is supplied to signal output part;

S502, in the output stage, it is the first current potential that output module keeps the current potential of primary nodal point, and clock signal is provided To signal output part;

S503, in reseting stage, reseting module in response to reset signal, under the control of reset signal, control first segment The current potential of point is the second current potential, and the current potential of secondary nodal point is the first current potential, and discharge module is charged, and will be with reference to letter Number it is supplied to signal output part;Reference signal is supplied to primary nodal point and signal output part by discharge module;

S504, in discharge regime, it is the first current potential that discharge module controls the current potential of secondary nodal point, and reference signal is provided To primary nodal point and signal output part.

Based on same inventive concept, the embodiment of the present invention additionally provides a kind of gate driver circuit, as shown in fig. 6, including Any of the above-described kind of shift register: the sr (1) of multiple present example offers of cascade, sr (2) ... sr (n) ... sr (n-1), sr (n) (common n shift register, 1≤n≤n),

In addition to first order shift register sr (1), the signal output part of remaining every one-level shift register sr (n) Output_n (1≤n≤n) is respectively to upper level shift register sr (n-1) input reset signal reset being adjacent;

In addition to afterbody shift register sr (n), the signal output part of remaining every one-level shift register sr (n) Output_n (1≤n≤n) is respectively to next stage shift register sr (n+1) input trigger input being adjacent;

Trigger input of first order shift register sr (1) is inputted by frame start signal stv end;

Gate driver circuit sequentially exports the grid of the signal output part output_n output of shift registers sr (n) at different levels Pole drive signal.

Further, in above-mentioned gate driver circuit provided in an embodiment of the present invention, clock signal clk and reference signal Vref inputs in shift registers at different levels.

Based on same inventive concept, the embodiment of the present invention additionally provides a kind of display device, including above-mentioned raster data model Circuit, provides scanning signal by this gate driver circuit for each grid line on array base palte in display device, it is embodied as Can be found in the description of above-mentioned gate driver circuit, something in common repeats no more.

A kind of shift register provided in an embodiment of the present invention, its driving method, gate driver circuit and display device, move Bit register includes: input module, output module and reseting module and discharge module;Because discharge module can be in reset signal Current potential be after the first current potential to trigger current potential be the first current potential before, the current potential controlling secondary nodal point is the first electricity Position, and when the current potential of secondary nodal point is the first current potential, reference signal is supplied to primary nodal point and signal output part;Thus Can ensure that this shift register after the current potential of reset signal is the first current potential to trigger current potential be the first current potential In time period before, primary nodal point and signal output part are effectively discharged, and then be ensure that shift register output Accuracy.

Obviously, those skilled in the art can carry out the various changes and modification essence without deviating from the present invention to the present invention God and scope.So, if these modifications of the present invention and modification belong to the scope of the claims in the present invention and its equivalent technologies Within, then the present invention is also intended to comprise these changes and modification.

Claims (9)

1. a kind of shift register is it is characterised in that include: input module, output module, reseting module and discharge module;Its In,
Described input module, in response to trigger, under the control of described trigger, controls the current potential of primary nodal point For the first current potential, the current potential of secondary nodal point is the second current potential, and described output module is charged;Described primary nodal point is located at Connect described input module, on the wire of described output module, described reseting module and described discharge module;Described second section Point is located on the wire connecting described reseting module and described discharge module;
Described output module, for when the current potential of described primary nodal point is the first current potential, clock signal being supplied to signal defeated Go out end;
Described reseting module, in response to reset signal, under the control of described reset signal, controls described primary nodal point Current potential is the second current potential, and the current potential of described secondary nodal point is the first current potential, and described discharge module is charged, and will join Examine signal and be supplied to signal output part;
Discharge module, is first for the current potential to described trigger after the current potential of described reset signal is the first current potential Before current potential, control described secondary nodal point current potential be the first current potential, and described secondary nodal point current potential be the first current potential When reference signal is supplied to described primary nodal point and described signal output part;
When the effective impulse signal of described trigger is high potential signal, described first current potential is high potential, described second electricity Position is electronegative potential, and described reference signal is low-potential direct signal;When the effective impulse signal of described trigger is electronegative potential Signal, described first current potential is electronegative potential, and described second current potential is high potential, and described reference signal is high potential direct current signal.
2. shift register as claimed in claim 1, it is characterised in that described input module, specifically includes: first switch is brilliant Body pipe and second switch transistor;Wherein,
Described first switch transistor, its grid and source electrode are used to receive described trigger, drain electrode and described primary nodal point It is connected;
Described second switch transistor, its grid is used for receiving described trigger, and source electrode is used for receiving described reference signal, leakage Pole is connected with described secondary nodal point.
3. shift register as claimed in claim 1, it is characterised in that described output module, specifically includes: the 3rd switch is brilliant Body pipe and the first electric capacity;Wherein,
Described 3rd switching transistor, its grid is connected with described primary nodal point, and source electrode is used for receiving described clock signal, drain electrode It is connected with described signal output part;
Described first capacitance connection is between the grid of described 3rd switching transistor and drain electrode.
4. shift register as claimed in claim 1, it is characterised in that described reseting module, specifically includes: the 4th switch is brilliant Body pipe, the 5th switching transistor and the 6th switching transistor;Wherein,
Described 4th switching transistor, its grid is used for receiving described reset signal, and source electrode is used for receiving described reference signal, its Drain electrode is connected with described primary nodal point;
Described 5th switching transistor, its grid is used for receiving described reset signal, and source electrode is used for receiving described reference signal, its Drain electrode is connected with described signal output part;
Described 6th switching transistor, its grid and source electrode are used to receive described reset signal, and it drains and described second section Point is connected.
5. shift register as claimed in claim 1, it is characterised in that described discharge module, specifically includes: the 7th switch is brilliant Body pipe, the 8th switching transistor and the second electric capacity;Wherein,
Described 7th switching transistor, its grid is connected with described secondary nodal point, and source electrode is used for receiving described reference signal, drain electrode It is connected with described signal output part;
Described 8th switching transistor, its grid is connected with described secondary nodal point, and source electrode is used for receiving described reference signal, drain electrode It is connected with described primary nodal point;
Described second capacitance connection is between the grid and source electrode of described 7th switching transistor.
6. the shift register as described in any one of claim 1-5 is it is characterised in that work as the effective impulse of described trigger Signal is high potential signal, and all switching transistors are n-type transistor;
When the effective impulse signal of described trigger is low-potential signal, all switching transistors are p-type transistor.
7. a kind of driving method of the shift register as described in any one as claim 1-6 is it is characterised in that include:
In input phase, described output module, in response to trigger, under the control of described trigger, controls described first The current potential of node is the first current potential, and the current potential of secondary nodal point is the second current potential, and described output module is charged;Described defeated Go out module and clock signal is supplied to signal output part;
In the output stage, it is the first current potential that described output module keeps the current potential of described primary nodal point, and by described clock signal It is supplied to signal output part;
In reseting stage, described reseting module, in response to reset signal, under the control of described reset signal, controls described first The current potential of node is the second current potential, and the current potential of described secondary nodal point is the first current potential, and described discharge module is charged, with And reference signal is supplied to signal output part;Reference signal is supplied to described primary nodal point and described letter by described discharge module Number outfan;
In discharge regime, it is the first current potential that described discharge module controls the current potential of secondary nodal point, and reference signal is supplied to institute State primary nodal point and described signal output part.
8. a kind of gate driver circuit is it is characterised in that include the displacement as described in multiple any one as claim 1-6 of cascade Depositor;Wherein,
In addition to first order shift register, the signal output part of remaining every one-level shift register is upper to be adjacent respectively One-level shift register inputs reset signal;
In addition to afterbody shift register, the signal output part of remaining every one-level shift register is respectively to being adjacent Next stage shift register inputs trigger;
The trigger that described first order shift register is received is inputted by frame start signal end;
Described gate driver circuit sequentially exports the gate drive signal of the signal output part output of shift registers at different levels.
9. a kind of display device is it is characterised in that include gate driver circuit as claimed in claim 8.
CN201510065143.5A 2015-02-06 2015-02-06 Shifting register, driving method of shifting register, grid driving circuit and display device CN104575437B (en)

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