JPH03192599A - Shift register circuit - Google Patents

Abstract

PURPOSE:To increase the shift speed 2 folds simultaneously contrive to decrease the element number per bit of a shift register circuit by cascade connecting the bit part making the logical output of an input signal and an output signal of latch part to the bit output signal. CONSTITUTION:When the input signal S1 and clock signal Sphi inputted to the shift register circuit 10, the latch signal SL of the latch part 1 becomes L from the rising point of the signal S1, and since the signal Sphi is H at the falling point of the signal S1 going from H to the L, the output signal SA of the bit part 10A to be H becomes H. Then, at the point of the signal Sphi changed from H to L the signal SL goes to H, and cascade output signal SM inputting to the bit part 10B becomes the inverse of signal of the signal SL, the output signal SB of the bit part 10B becomes H and continues to the rising point of the suc ceeding signal So. Consequently, by cascade connecting of same circuit 10 the data can be transmitted to the high-order bit at every half period of the signal Sphi i.e. at double speed and the the number of elements can be decreased.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a shift register circuit.

[Conventional technology]

FIG. 4 is a circuit diagram of an example of a conventional shift register circuit.

The shift register circuit 30 has two clock signals Ss, S; which have the same circuit configuration and are supplied to the transfer gates TG+, TG2 and the clocked inverter IC1+rc, and which have opposite phases. Latch parts 1 and 2 are connected in cascade, and the first part of latch part 2 is
A bit section 30A outputs a first bit output signal S from the bit end TA of the bit section 30A, and a bit section 30A having the same circuit configuration as the bit section 30A inputs the bit output signal S1 and outputs a second bit output signal S from the bit end Ts. Bit part 30. have.

The latch unit 1 receives an input signal S at its input terminal, inputs clock signals Sφ, S; at its gate, and transfers a transfer signal S.
It has a first transfer gate T G 1 that transmits T to the input terminal of an inverter 1 of an anti-parallel circuit of an inverter 1 and a clocked inverter C 1 .

FIG. 5 is a waveform diagram of various signals for explaining the operation of the circuit of FIG. 4.

As shown in FIG. 5, input signal S1 and clock signal Ss
, Ss, the first rising point of the clock signal S is set to 10 and the transfer signal of the latch unit 2)TG
2 becomes conductive (hereinafter abbreviated as "on"), and bit part 3
The output signal S of 0A is a high level "H" tonal.

Next, the second rising time t! of the clock signal S! 1 bit part 30. The output signal S of I becomes high level "H".

At this time, the output signal S of the bit section 30A is at a low level "
It becomes “L”.

As explained above, the conventional shift register circuit 30 operates at the rising time t4 which occurs every cycle τ of the clock signal S. At t5, data is transmitted to the upper bits, that is, from the bit section 30A to the bit section 30B.

[Problem to be solved by the invention]

The conventional shift register circuit described above uses 1 of the clock φ.
Since the value of each bit changes at the rising edge of each cycle and the data is shifted to the upper bits, the shift speed is slow.

Furthermore, two latch circuits are used for each bit, which has the disadvantage of requiring a large number of elements.

An object of the present invention is to provide a shift register circuit with a high bit shift speed and a small number of elements.

[Means to solve the problem]

The shift register circuit of the present invention has a first transfer gate, the input signal being input to one end of the transfer gate, and the other end being connected to the input end of the inverter of an anti-parallel circuit of an inverter and a clocked inverter to output a latch signal. a latch unit having one input terminal receiving the input signal and the other input terminal inputting the latch signal;

(B) a first bit output terminal that outputs the R signal as an IU power signal; and a cascade output terminal that outputs an inverted signal of the latch signal as a cascade output signal; Input the cascade output signal,
a second latch section that has the same circuit configuration as the first latch section and in which the clock signal supplied to the transfer gate and the clocked inverter is in an opposite phase relationship with the first latch section; and a second bit output terminal corresponding to the first bit output terminal.

Furthermore, the shift register circuit of the present invention has the following characteristics: (b) The input signal is input to one end of the transfer gate, and the other end is connected to the input end of the inverter of the anti-parallel circuit of an inverter and a clocked inverter to output a latch signal. a first bit output terminal whose one input terminal receives the input signal and whose other input terminal inputs the latch signal and outputs a NOR signal as a bit output signal; a first bit portion having a cascade pressure end that outputs the signal as a cascade output signal; (B) an input end inputting the cascade output signal;
a second latch part having the same circuit configuration as the first latch part and in which a clock signal supplied to the transfer gate and the clocked inverter is in an opposite phase relationship with the first latch part; a second bit output terminal, an input terminal of which inputs the cascade output signal, and a second bit output terminal whose other input terminal inputs the latch signal and outputs an AND signal as a bit ratio signal; It is composed of:

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram of a first embodiment of the present invention.

The shift register circuit 10 has the same circuit configuration, and the phase relationship between the transfer gates TG1゜TG of the latch sections 1 and 2 and the clock signals S, , S' of the clocked inverters CI', , OL are mutually different. The two bit parts 10A and 10B, which are in opposite phase, are connected to the cascade output terminal T.
They are configured in a cascade connection via M.

The bit section 10A has the latch section 2 of the bit section 30A of the conventional shift register circuit 30 shown in FIG. A NOR circuit NOR is added to supply the signal SA to the first bit end TA as the first bit output signal SA.

FIG. 2 is a waveform diagram of various signals for explaining the operation of the circuit of FIG. 1.

When the input signal Sr or the clock signal S is input to the shift register circuit 10 of FIG. is high level “H”
Since the clock signal Sφ is at the high level "H" at the falling time t1 when the clock signal Sφ changes from the low level "L" to the low level "L",
The output signal SA of the bit section 10A becomes high level "H".

Next, at time t2, the clock signal S changes from high level "H" to low level "L", so the latch signal SL becomes high level "H" and the bit part 10B
The cascade output signal SM input to the cascade output signal SM becomes an inverted signal of the latch signal SL.

Therefore, at this time t2, bit portion 10! The output signal Sm of l becomes high level “H” and the next clock signal S
, continues until the rising time t.

As explained above, data is transmitted to the upper bits, that is, from the bit part 10A to the bit part 10B not only at the rising time t1 of the shift register circuit 10 shown in FIG. 1 but also at the falling time t2 of the work signal Sφ. will be done.

Therefore, by cascading a number of circuits having the structure of the shift register circuit 10, data is transmitted to the upper bits at the rising and falling edges that occur every half cycle of the clock signal S, as shown in FIG. The transmission speed is twice that of the conventional shift register circuit 30 shown in FIG.

Furthermore, the shift register circuit 10 shown in FIG. 1 has 14 elements per 1 bit, which is 2 fewer elements than the 16 elements in the conventional shift register circuit 3o shown in FIG.

However, the number of elements in the shift register circuit is 2 inverters.
4 clocked inverters.

4 2-person NOR circuits and 2 transfer gates
It is calculated as an individual.

FIG. 3 is a circuit diagram of a second embodiment of the present invention.

The shift register circuit 20 includes two bit units 20A in which the phase relationship of the clock signals S d tS of the transfer gates TG, TG2 of the latch unit 1.2 and the clocked inverters CI, , CI2 are in opposite phases to each other. ,
20□ are connected in cascade via the cascade output terminal Ty.

The bit section 20A is constructed by removing the inverter from the bit section 10A shown in FIG.

Further, the bit section 20B removes the inverter 2 of the bit section 10B in FIG. 1, and ANDs the NOR circuit NOR.
It is constructed by replacing it with a circuit AND.

The operation of the shift register circuit 200 shown in FIG.
Although it is similar to the embodiment described above, the number of circuit elements per 2 bits is 26, compared to 32 of the conventional shift register circuit 30.
The number of elements can be further reduced compared to the 28 elements in the circuit IO of the first embodiment.

〔Effect of the invention〕

As explained above, the present invention connects bit units in which the bit output signal is the logical output of an input signal and the output signal of the latch unit, so that the input data is
Since 2 bits are shifted in one period of
It has the effect of being twice as fast.

Further, there is an effect that the number of elements per one bit of the shift register circuit can be reduced.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a first embodiment of the present invention, and FIG. 2 is a circuit diagram of a first embodiment of the present invention.
3 is a circuit diagram of the second embodiment of the present invention, FIG. 4 is a circuit diagram of an example of a conventional level shift circuit, and FIG. 4 is a waveform diagram of signals of various parts for explaining the operation of the circuit of FIG. 4. FIG. 1.2...Latch part, 10.20...
Shift register circuit, 10A, 10B, 20A
, 20B...Bit part, CI+...
・First affected inverter, SA, SB...
...First. Second bit output signal, SL...Input signal, SL...Latch signal, 8...
- Cascade output signal, S, ... clock signal, T G +, T G 2 ... 1st. 2nd transfer game), Tyu,... Cascade output terminal.

Claims (1)

[Claims] 1. (A) An input signal is input to one end of the transfer gate, and the other end is connected to the input end of the inverter of an anti-parallel circuit of an inverter and a clocked inverter to output a latch signal. a first latch section; a first bit output terminal having one input terminal receiving the input signal and the other input terminal inputting the latch signal to output a NOR signal as a bit output signal; a first having a cascade output terminal that outputs an inverted signal of
(B) an input terminal inputs the cascade output signal, has the same circuit configuration as the first latch section, and a clock signal supplied to the transfer gate and the clocked inverter is connected to the first latch section; a bit section having a second latch section having an opposite phase relationship with the latch section, and a second bit output terminal corresponding to the first bit output terminal. register circuit. 2. (A) A first latch unit, into which the input signal is input to one end of the transfer gate, and the other end is connected to the input end of the inverter of an anti-parallel circuit of an inverter and a clocked inverter, and outputs a latch signal; , a first bit output terminal whose one input terminal receives the input signal and whose other input terminal inputs the latch signal and outputs the NOR signal as a bit output signal; and a first bit output terminal which outputs the latch signal as a cascade output signal. a first bit section having a cascade output terminal; (B) an input terminal inputting the cascade output signal;
a second latch part having the same circuit configuration as the first latch part and in which a clock signal supplied to the transfer gate and the clocked inverter is in an opposite phase relationship with the first latch part; a second bit output terminal, an input terminal of which inputs the cascade output signal, and a second bit output terminal whose other input terminal inputs the latch signal and outputs an AND signal as a bit output signal; A shift register circuit characterized by: