GB1413044A - Counter provided with complementary field effect transistor inverters - Google Patents

Abstract

1413044 Electronic counters TOKYO SHIBAURA ELECTRIC CO Ltd 21 Feb 1973 [25 Feb 1972] 8409/73 Heading G4A [Also in Division H3] A binary counter employing complementary FETs comprises a cascaded connection of at least a first, a second and third inverters 1-3, the output of the third inverter 3 being connected to the input of the first inverter 1, clock signals Q 1 , Q 1 for causing at least two inverters 1, 2 to operate alternately whereby an output signal having a frequency equal to half that of the clock signals is obtained from the output of one of the inverters. In operation, when the clock signals Q 1 , Q 1 are in their "0", "1" states respectively FETs 13, 14 are conductive while FETs 23, 24 are non-conductive so that clocked inverter 1 alone is operative. An input of "1" is inverted by 12 to a "0" which is-stored by an input capacitance ca. Subsequently inverter 1 is turned off and inverter 2 rendered operative so that FET 21 inverts the stored "0" to a "1" which is stored in a capacitance cb and also inverted by FET 32 to a "0" level which is fed back to input of 1. A further cycle of the clock pulses is required before the output at Q 2 returns to the "1" level thus achieving a division by two of the clock pulse rate. The third inverter 3 may also be clocked by the pulses applied to the second inverter and may also be interposed between the first and second inverters. The inverters may be rearranged (Fig. 3, not shown) so that the input is applied to FETs 13, 14 with the clock pulses applied to FETs 11, 12. In an alternative embodiment (see Fig. 5A), the first and third inverters are clocked, a fourth inverter 50 is connected at the output of the third inverter and a fifth and a sixth inverters 4, 6 clocked by the pulses applied to the third, first inverters respectively are connected between the output and input of the second, fourth inverters respectively for maintaining the logic levels at the outputs of the first, third inverters. The second and fourth inverters may each include a NAND gate to one input of which a control signal is applied to inhibit or to initiate counting. In the embodiment of Fig. 6A (not shown), the second and fourth inverters include NOR gates for resetting the counter. In the embodiment of Fig. 7A (not shown), the first and third inverters include NAND gates for resetting the counter. In the embodiment of Fig. 8A (not shown), the fifth, sixth feed-back inverters include NAND gates. A multi-stage counter may be built by cascading a number of binary counters with complementary outputs derived from each stage being used as clock inputs for the following stage.