SU784007A1 - Frequency divider with 2n-1 scaling factor - Google Patents

Description

f

The invention relates to the field of Internet technology and can be used in digital information processing devices in measuring devices and computing devices.

The known frequency divider with the coefficient “recalculation of 2N-1”, contains a L-bit shift register, an additional trigger, an element NOT and two JO elements and-NOT.

The disadvantage of the known divider is its relative complexity -.

A frequency divider with a recalculation factor of 2N-1 is known, containing a 15 Nr-regular shift register, each bit of which is built on a D-trigger f and an input bus that is connected to the clock inputs of the shift register bits, the inverse output of the last-0 whose bit is connected to the inputs D and set to the first bit of the shift register O.

A disadvantage of the known divider is the asymmetry of the output signal 25.

The aim of the invention is to obtain a symmetric output signal.

To achieve this goal, a frequency divider with a coefficient of

conversion volume. 2N-1, containing an N-bit shift register, each bit of which is built on an i-trigger, and a wired tire. Which is connected to the clock inputs of the bits of the shift register, the inverse output of the last bit of which is connected to the inputs D and set to the first bit of the shift register, is entered and set up a new trigger, the setting input is

which is connected to the input bus as well.

1 - with inverse

installation input

.vkomtsom last bit shift register.

The drawing shows a schematic diagram of a frequency divider with a conversion factor of five.

The divider contains shift register bits 1-3 on D-flip-flops, installation trigger 4 and input bus 5.

Input bus 5 is connected to clock inputs of shift register bits 1-3 and to the installation input in О of the setting trigger 4, the installation input in which is connected to the inverse output of the shift register discharge 3 and to the inputs D and the installation in О of the shift register 1 .

The divider works in the following way.

In the initial state of the bit of the register, C15wigs 1-3 are in the zero state, i.e. the shift register is in the state 00.0. At the direct output of flip-flop 4, which is the output of the device, there is also a zero potential. When the front edge of the first clock pulse arrives on the input bus, the register shift shifts to a fine 100, when it arrives before--. of the front of the second clock pulse, the shift register goes to state 110, when the front of the third clock pulse arrives, the shift register goes to state 011, and at the forward output of trigger 4 (delayed by the sum of the switching times of bit 3 and trigger 4) there is a single potential. When,., “The leading edge of the fourth so-called pulse arrives, the shift register transfers to state 001, when the leading edge of the fifth clock pulse increases, the shift register returns to the initial state, i.e. in 000, at the direct output of the flip-flop 4 is maintained. unit potential (for .. tigo, that the zero potential. on its input of the installation in 1 sfranfl longer for the delay time of triggered discharge 3 than. on the input of the installation, in O), with the arrival of the trailing edge. the pulse at the direct output of trigger 4 appears zero zero and the device returns to its original state.

Thus, the frequency divider synchronously forms on the prmb m output

trigger pulses whose duration is equal., .... - T .2iB ..

BYU M 2..

where N is the number of triggers in the Divisor ;; follow-up period

m, ..

pulses. The period of the output pulses is equal to h (2N-1). It should be noted that in the proposed device, state 111 is excluded in the shift register with feedback, but any other state can be excluded. The latter is achieved by connecting the installation input to

"I jl I

Oh some kind of bit

or

the shift register to the corresponding output of the shift register previous in the ring bit. In this case, when propagating in the ring register N units and zeros, of course.

trigger 4

0 installation input

should be connected to the direct output; - the last lap L of the shift register.

Claims (1)

. Invention Formula Frequency Divider 5 recalculation of 2N-1, containing an M-bit shift register, each bit of which is built on a D-flip-flop, and an input bus, which is connected to the clock inputs of the register bits 0 shift, the inverse output of the last bit of which is connected to the inputs of the Pi installation and about the first discharge of the shift register, which is used to obtain with a symmetrical Output signal, an installation trigger has been entered into it. input set to which connection is with the input bus, and the installation input in. - with the inverse output of the last bit of the shift register. /