SU782164A1 - Decimal counter - Google Patents

Description

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The invention relates to a pulse technique, in particular to a counter and pulses, and can be used for counting and dividing binary signal sequences in various 5 digital computing and measuring systems.

A known counter with a natural counting order is known, built according to a scheme with parallel transfer based on RS flip-flops with control circuits: forming four one-cycle T-flip-flop counters with six potential logical elements AND, OR}. 15

The disadvantages of this decimal counter are the relatively low speed and significant hardware costs.

Also known is a counter containing 20 RS-flip-flops and ten logic elements, the inverse output of the first RS-flip-flop is connected to the BccJM input by the first logic element, the output of which is connected to the first-25th input of the second logic element, the output of which is connected to the input setting the first RS-flip-flop, the inverse output of the second RS-flip-flop co. dinen with the first permit entry 30

The third logic element, the output of which is connected to the first input of a fourth logic element, the output of which is connected to the installation input of the second 5th Trigger; the inverse input of the third RS flip-flop is connected to the first enabling input of the fifth logic element, the output of which is connected to the first input of the sixth logical element, the output of which is connected to the installation input of the third RS flip-flop, the output of the seventh logic element is connected to the first input of the eighth logic element, the output of which is connected to the input of the installation The ki of the fourth RS flip-flop, and the second inputs of the second, fourth, sixth, and eighth, as well as the first input of the ninth logic element are connected to the input of the decimal counter 2j.

The disadvantage of this decimal counter is that its performance is slow.

A: The purpose of the invention is to increase the speed: activity.

The goal is achieved by the fact that in a decimal counter containing four RS flip-flops and ten logic elements, the inverse output,

rii pBoro RS-flip-flop is connected to the lane;. um and the course of the first logical; ale; .:: g1ta, the output of which is connected to the BtJM pen by the input of the second logic element, the output of which is connected to input 6 of the first RS flip-flop, the inverse output of the second RS flip-flop

connected to the first allow entry

the third logical element, the output of which is connected to the first input, of the fourth logical element, the output of which is connected to the input of the mouth y6SiKH Stbp6V6; RS-trigger, inverse output of the third RS-trigger is connected to the first enable input of the fifth logic element, the output of which is connected to the first input of the sixth logic element, output of the second is connected to the input of the third RS-trigger, the output of the seventh logical element of the next With the first input of the eighth logic element, the output of which is connected to the installation input of the fourth RS flip-flop, and the second inputs of the second, fourth, sixth and eighth

as well as the first input of the ninth logical element is connected to the input of the decimal counter, the output of the ninth logical element is connected to the output of the tenth counter, the reset input of the fourth RS-tpniger, the first input of the first RS ‑ reset and the third; in toro t - ё Peo1 togb W): Shesh and the input of the tenth of the logical element „„ 1ShzG and from 81g G1: YedaySht by the input of the ninth logical element, the third input of which is connected to the fourth input of the third and 4etEiej) Td logical elements of the J. the input of the sixth logical element

output 10gx:; of whom the element and the input of the seventh logical element, the first permitting input of which is connected to the nepBtavT pat peiuya input of the tenth one; logical element, the second permitting the inputs of the third; the fifth element and the first output of the first RS-flip-flop, whose setup input is connected to the second BXOJJOM nepSo o logical. logic element, the output of the fourth лог y logic element is connected to the second reset input of the first RS flip-flop, the input of the third logic element, the fifth inputs of the second and sixth logic elements and the fourth input smogo logic element output is coupled to torogo with mp etim s fi & S / t

reset the first RS flip-flop, the first input reset the second RS-flip-flop and the reset input of the third RS-tIpGepal p1p my vyhdd which is connected to the second permitting input of the seventh logic element, the third permitting input of which is connected to the NbJM dp output of the second RS-trigger, and the third enabling input the input of the fifth logical element, the input of which is connected to the sixth inputs of the second and fourth logical elements, the fifth input of the eighth logical element, the output of the sixth, logical element, as well as the fourth reset input of the first of the RS-flip-flop and a second reset input of the second RS-flip-flop, and the forward and inverse outputs of the fourth RS-TpKrrepa connected respectively to the second input of the resolving i yuschim tenth logic gate and permitting the third input of the third logic element.

The drawing shows a structural

0 scheme of the tenth counter.

 The decimal counter contains four RS-flip-flops 1-4 and ten logic elements 5-14, the inverse output of the first RS-flip-flop 1 is connected to the first input of the first logic element 5 / whose output is connected to the first input-the second logical element b, the output of which connected to the installation input of the first RS-flip-flop,

Q inverse output of the second RS-flip-flop

2 is connected to the first permissive input of the third logic element 7, the output of which is connected to the first input of a fourth element

C 8, the output of which is connected to the input of the installation of the second RS-flip-flop 2, the inverse output of the third RS-flip-flop

3connected to the first enabling input of the fifth logical element 9 whose output is connected to the first

P the input of the sixth logical element / ta 10, the output of which is the connection of the third-set trigger of the third RS flip-flop 3, the input of the seventh logical element 1 is connected to the first input of the eighth

5 logic element 12, the output of which is connected to the input of the installation of the fourth RS-flip-flop 4, and the second inputs of the SECOND b, the fourth 8, the sixth 10 and the eighth 12, as well as the first

0 input of ninth 13 logical elements are connected to the input of 15 decimal counter, the output of ninth logical element 13 is connected to output 16 of decimal counter, reset input of the fourth RS flip-flop 4, first reset input of the first RS-flip-flop 1, third inputs of the second 6 and the fourth 8 logical elements and the input of the tenth of the logical element 14, the output of which

Q is connected to the second input of the ninth IG-th element 13, the third input of which is connected to the fourth inputs of the first and fourth 8 logical Elements, the third input of the sixth

5 10 logical element, output

the eighth logic element 12 and the input of the seventh 11 logic element, the first enabling input of which is connected to the first allowing input of the tenth logical element 14, the second allowing inputs of the third 7 and the fifth 9 logic elements and the first output of the first RS trigger 1, the installation input which is connected to the second input of the first logic element 5, the fifth input of the fourth logic element 9, the fourth input of the sixth logic element 10, the third input of the eighth logic element 12 and the fourth input of the nine logic element 13, the output of the fourth logic element 8 is connected to the second reset input of the first trigger 1, the input of the third logic element 7, the fifth inputs of the second 6 and sixth 10 logic elements and the fourth input of the eighth logical element 12, the output of which is connected to the third reset input the first RS flip-flop 1, the first reset input of the second RS-flip-flop 2 and the reset input of the third RS-flip-flop 3, the direct output of which is connected to the second Elm permitting input of the seventh logic element 11, the third permitting input connected to the direct output of the second RS-flip-flop 2 and the third permitting input of the fifth logic element 9, the input of which is connected to the sixth inputs of the second b and fourth 8 logic elements, the fifth input of the eighth logical element 12, the output of the sixth logic element 10, and also with the fourth reset input of the first trigger 1 and the second reset input of the second RS-trigger 2, and the direct and inverse outputs of the fourth RS-trigger 4 are connected respectively to the second enabling input of the tenth logic element 14 and the third allowing input of the third AND gate 7.

The grand counter operates as follows.

Suppose that in the initial state .RS-triggers 1-4 are at zero, t. on their direct outputs there is a logical zero (low potential), and in the inverse outputs there is a logical unit (high potential) and suppose that at output 15 the signal is equal to a logical unit. Then at the outputs of elements 6, 8, 10 and 12 and at the output of element 13 there is a logical zero. Since RS flip-flops 1-4 in the state of logical zero, t, signals from the direct outputs of these flip-flops set logical units at the outputs of elements 7, 9, 11 and 14, and only the output of element 5 establishes a logical zero.

The input unit of this element is supplied with a logical unit from the inverse output of the RS flip-flop 1. Thus, the distribution of the logical signals in the device at the initial moment of time is determined. When the value of the signal at input 16 changes from one to zero, elements 6, 8, 10, and 12 are set to the first state (1000). The logical unit from the output of element b, firstly, blocks subsequent possible changes to the signals at the outputs of elements 5 and 13, secondly, sets the RS flip-flop 1 to a single logical state. At the same time on the

The output of this trigger is a logical unit, and at the inverse output is a logical zero, which does not change the state of element 5, since this element is blocked by a logical one from the output of the element

0 6, a, the unit from the fifth output of the first RS flip-flop 1, arriving at the input of the resolution of element 7, sets at the output of element 7 a logical zero. In this state, the device

5 remains until the next change of the signal at input 15. The appearance at the input 15 of the logical unit sets output code 6, 8, 10, and 12 for the output code (0000). At the same time

0 the output of element 5 appears logical unit. The states of the remaining circuit elements do not change until the next change at input 15. The second pulse (zero) at input 15

5 sets the second state (0100). Unit from item output

8 blocks the change of state of element 7 and sets RS-flip-flops.

1 and 2, respectively, in a logical state of zero and one. Wherein

0 unit with inverse trigger output

2 sets zero at the output of element 5. The output state of element 7 does not change, although at the input of the resolution of this element appears

5 logical zero from the output R5-TpHrrepa 1. The new change of the signal at input 15 from the logical zero to the logical unit again sets the code (0000). Next, the operation of the device

0 occurs as described: the 3rd pulse sets the code at the output of RS-flip-flops 1-4 code (1100), 4th - (0010), 5th - (1010), 6th (0110), 7-6y - (1110), 8th (0001),

5 9th - (1001). Before the 10th pulse at the outputs of the elements 5j 7,

9 and 11 there appears a logical one, and at the output of element 14, a logical zero. Therefore, from the arrival of the 10th pulse, element 9 is triggered, the logical unit from its output blocks element 14, blocks the operation of elements b and 8, and sets the triggers 1 and 4 to the zero logical state. In this case, the output

five

the element 5 appears logical zero, from to / 1 in the input 16 of the logical unit despotic counter goes to its original state.

Thus, at the outputs of the RS-triggers 1-4, a binary code of 1-2-4-8 is formed, and at the output of element 13 there is a signal to divide the input frequency by the 10th-tenth pulse.

Claims (2)

1.Bukreev I.N., et al. Microelectronic circuits of digital devices, K., Soviet radio, 1975, p.180, Fig.5.17, 2. Elektronik, 1971, Heft 1, S. 26, Btld 4 (prototype). S TK 5T ff five S i to i GTL