SU1001485A1 - Binary pulse number multiplier - Google Patents

Description

(5) PULTIER MULTIPLE OF NUMBER OF PULSES

one

The invention relates to computing and can be used in computing devices designed to perform the operation of counting the number of pulses while simultaneously multiplying the result by an arbitrary pre-specified positive natural number.

A binary multiplier of the number of pulses is known, which contains a trigger in each category, AND elements, and OR 1 elements.

The disadvantage of this device lies in its limited functionality. The multiplication factor can only take two fixed values of ± 5.

A binary multiplier of the number of pulses is known, containing an input bus and M bits, the first bit contains a trigger, each subsequent bit contains a trigger and an AND element in each bit, except the first one,

the trigger control input is connected to the first input of the element And the subsequent bit, the second input of the element And which is connected to the direct output of the trigger of the previous bit, the output of the element And is connected to the control input of the trigger, the first and second inputs of the second And element are connected respectively to the bus potential units and with a direct output trigger of the first bit, the output bus is connected to the counting inputs of the trigger bits of bits J.

A disadvantage of the known device is the limitations of the functions. opportunities. The multiplication factor can take only one value +1. .

The purpose of the invention is to expand the functional capabilities of the device in terms of ensuring the multiplication of the number of pulses by any natural positive number. The goal is achieved by the fact that the binary multiplier of the number of pulses containing the input bus and M bits, the first bit contains a trigger, each post bit contains a trigger and the first element M, in each bit, except the first one, which controls the trigger input is connected to the first input of the first element and the subsequent discharge, the second input of the first element and of which is connected to the direct output of the previous discharge trigger, in each bit, starting from the K-th, where K is less than M, the output of the first element And is connected to the control input trigger Pa, the bus input is connected to the counting inputs of the triggers, control buses, logical zero and one potential buses are inserted, a switch is inserted into the first discharge, and a switch from the second to K-1 is inserted into the first discharge, Three NO elements, in each bit from the first to the K-1 potential bus, logical zero and one are connected respectively to the first and second information inputs of the switch, the control inputs of which are connected to the corresponding control buses, the switch output is connected to the control input trigger The relay in each rade from the second to K-1-Y output of the first element I is connected to the third information input of the switch and connected via the first element NOT to the fourth information input of the switch, the fifth one and the sixth information inputs of which are connected respectively to the output The second element And with the output of the second element NOT, the input of which is connected to the output of the second element And, the first input of which is connected to the first input of the first element And, the second input of which is connected to the input of the third element NOT, the output of which is connected to the second second-input AND gate, the figure shows a binary UMN resident number of pulses with a coefficient multiplying +3. In the drawing marked triggers 1-1 5; switches elements And elements NOT input bus 5; tires 6 and 7 potentials, respectively, logical zero and one; bus 8 control. Input bus 5 is connected to counting inputs of flip-flops, the control inputs of which are connected respectively to the outputs of switches and to the outputs of elements AND 3 5 and the outputs of switches 2 and 3 and the output of element And are connected respectively to the first inputs of elements And,, the second inputs of which are connected respectively; Respectively, with the direct outputs, the three 1-hero bus 8 of the control is connected to the corresponding control inputs of the switches, the first and second information inputs of which are connected respectively to the buses 6 and 7 of the logical zero potentials, and the units, the third information inputs of the switches. and connected respectively to the outputs of the elements. And and and are connected respectively to the inputs of the elements NOT .and whose outputs are connected respectively to the fourth information inputs of the switches and the fifth information inputs of which are connected respectively to the outputs of the elements And and and connected to the inputs i of the elements HE and 5, respectively, which outputs are connected respectively, with the sixth information inputs of the switches and the outputs of the switches and are connected respectively with the first inputs of the elements And and. the second inputs of which are connected to the outputs of the elements NOT and whose inputs are connected respectively to the direct outputs of the triggers U-1 and. , At the outputs of the switches, depending on the setting of the buses 10, six functions are formed, two of which are the potentials-logical zero and one, and the other four are functions of the arguments x.- and a .., where x-d - De l the enable signal for switching the i-ro trigger, a– is the signal at the forward output of the i-rb trigger. The table below. Figure 1 gives a correspondence between the switch state number and the logic function at the switch output. The configuration of the switches depending on the predefined coefficients is made in accordance with Table 2.

The method of mathematical induction (Table 2) is divided into any number of lines (i.e. multiplication coefficients). From Table 2 it can be seen that for any line, which, in turn, corresponds to the selected multiplication factor, there is a bit, after which the setting of the subsequent bit switches is constant and equal to 2.

Considering that this setting corresponds to the implementation of the function xa; (Table I, and it is obvious that for all subsequent bits of the multiplier of the device 2 the inter-bit transfer is realized by the elements AND

We consider the operation of the pulse multiplier by the example of the multiplier mode by -3. In this case, control buses are supplied to the control buses 8 (tables 2), which would switch the switches of the first, second and third bits, respectively.

Switch State

About I111I

Poi

11-211

ll / jll

llrll

in the first, third and fifth state, and the switches of all subsequent bits - in the second state. The outputs of the switches of the first, second and third bits will be respectively the following logical functions

H and x

XH, - and all subsequent bits are functions,. When you configure switches, and

as described above, the triggers of the device in FIG. 1 will successively on receipt of clock pulses in bus 8 take the following states: 00000, 11000, 01100,

10010, 10010, 00110, 11110,01001 ITD-.

Thus, the device multiplies each successive pulse by a factor of 3 and summarizes the result, and when changing the multiplication factor, switching of switches is required according to table 2.

Table 1

Logic function on switch output

 but.

N

N Table 2

100НВ58

continued .2 Discharges The state of the commutators in the multiplication factor multiplier N. 123

Claims (1)

Invention Formula Binary multiplier of the number of pulses containing the input bus and M bits, the first bit contains a trigger, each subsequent bit contains a trigger and the first element AND, in each bit, except the first, the control input of the trigger is connected to the first input of the first element And the next bit, the second input of the first element And which is connected to the direct output of the trigger of the previous bit, in each category, starting from K-th, where K is less than M, the output of the first element And is connected to the control input of the trigger, the input bus is connected to counting trigger inputs, characterized in that, in order to expand the functionality, control buses, logical potentials zero and one buses are introduced into it, a switch is inserted into the first bit, and a switch is inserted into each bit from second to K-1, And and the three elements are NOT, in each bit from the first to the K-1 bus of the potentials of logical zero and one are connected respectively with the first and second information inputs 100U8510, Continued table. 2 The switch's dies, the control inputs of which are connected to the corresponding control buses, the switch output is connected to the trigger control input, in each bit from the second on K-1-th output of the first element And is connected to the third information input of the switch and connected through the first element NOT to the fourth information input of the switch, the fifth and the sixth informational inputs of which are connected respectively to the output of the second element I and to the output of the second element NOT, the input of which is connected to the output of the second element And, the first input of which is connected to the first input of the first element And, the second input of which is connected to the input of the third element NOT, the output of which is connected to the second input of the second element And,, Sources of information taken into account in the examination 1, USSR Author's Certificate No. 6600D8, cl. H 03 K 23/00, 1976. 2, Bukreev I, N, et al. Microelectronic circuits of digital devices, Moscow, Soviet radio, 1975, p. 168, fig. B. (prototype). bit binary