SU834928A1 - Sounter with 2 plus 1 scaling factor - Google Patents

Description

one

The invention relates to computing in a t-technician and can be used to calculate the pulse frequency division.

A counter with a recalculation coefficient of 2 + 1 is known, which contains an n-bit binary counter, two BANKS, the NOT element, the AND element, and two countable flip-flops l. ,

A disadvantage of the known device is relative complexity.

A counter is known that contains an input bus, a cable from a cable, P-counting triggers, two AND-NOT elements, an additional counting trigger, a delay element and a transfer element, the first input of which is connected to the input of the delay element, with the input bus and with the first input of the first element IS-NOT, the output of which is connected to the clock input of the first counting trigger, the inverse output of each counting trigger is connected to the clock input of the next counting trigger, the inputs of the second element IS-NOT with & D with all the counting triggers, the input The settings of which are set to zero are connected to the reset bus, the output of the second element is NOT connected to the input of the installation to zero of an additional counting trigger, the clock input of which is connected to the output of the delay element, and the first and second outputs are respectively to the second inputs of the pass-through transfer element and the first element AND-NOT 2.

The disadvantages of a known device are its relative complexity, which reduces reliability and relatively low speed.

The purpose of the invention is to increase speed and reliability.

 The goal is achieved by the fact that in a counter with a conversion factor,

5 containing the input bus, reset bus, P-counting triggers and two AND-NOT elements, the first input and output of the first AND-NE element are connected respectively to the input bus and to the clock input of the first counting trigger, the inputs of the second AND-NE element are connected to direct outputs of the counting triggers, the installation inputs to zero of which are connected to the reset bus, the inverse output of the double counting trigger is connected to the clock input of the subsequent counting trigger, the third AND fourth elements, the output of the second element AND are entered -NOT

0 is connected to the second input of the first

element AND-NOT and with the first input of the third element AND-NOT, the output of which is connected to the first input of the fourth element AND-NOT, the output of which is connected to the second input of the third, to the third input of the first and to the first input of the fifth elements AND-NOT, the output of the fifth element AND-NOT is connected to the first input of the sixth element AND-NOT, the output of which is connected to the second BXO of the fifth and the additional input of the second AND-NOT element, the second booms of the fourth and sixth INE elements are connected respectively to the input bus and to the right last three counts out gager

The drawing shows a three-bit counter,

The counter contains the counting trigger and 1-3, the element 4 AND-NOT, the input bus 5, the elements 6-10 AND-NOT, the bus 11 reset.

In the drawing, the input bus 5 is connected to the first input element 4 AND-NOT and the first input element 8 AND-NOT, the output of which is connected to the first inputs of elements 7 and 9 AND-NOT and the second input element 4 AND-NOT, the output connected with a clock input of the first counting trigger 1, the inverse output of which. connected to the clock input of the counting trigger 2, the inverse output of which is connected to the TaKTOBbfM input of the counting trigger 3, the reset bus 11 is connected to the inputs of the installation in zero of the counting triggers 1-3 ,. The direct outputs of which are connected to the inputs of element 6 NAND, the output of which is connected to the third input of element 4 NAND, and the second input of element 7 NAND, whose output is connected to the second input of element 8 NAND, the output of element 10 NAND connected to the auxiliary input of the element b-AND-NOT and with the second input of the element 9 AND-NOT, the output of which is connected to the first input of the element 10 AND-NOT-, the second input of which is connected to the direct output of the counting trigger 3.

The device works as follows.

Suppose that at the initial time T the triggers 1-3 are in the state O and at the outputs of elements 6,8,10 - high potentials, and at the outputs of elements 4, 7, 9 low potentials. On the input bus 5 comes the first a negative pulse and at the output of element 4 a positive pulse appears, on the leading edge of which trigger 1 is set to state 1. When the next pulses arrive, the binary counter on triggers 1–3 begins to fill.

After the arrival of the seventh pulse, all three triggers 1,2 and 3 are in state 1, and a low potential appears at the output of element 6.

since all its inputs are high potentials.

The low potential from the output of element b enters the input of element 7 and a high potential appears at its output.

After the end of the seventh pulse on bus 5, a high potential appears, which, entering the input of element 8, causes a low potential at the output of element 8, since at this moment high potentials are acting on all inputs of element 8. one .

The low potential from the output of element 8 enters the inputs of elements 4.7 and 9 and causes a high potential at the output of element 9. High potentials at the direct output of the trigger 3 and at the output of element 9 cause a high potential at the output of element b.

After the eighth pulse arrives, bus 5- at the input of element 4 shows a negative potential, which keeps element 4 in a state with a high potential at the output, and, when it enters the input of element 8, it causes a high potential for its output. A high potential from the output of element 8 enters the input of element 7 and causes a low potential at the output of element 7, since at both inputs of element 7 there are high potentials.

After the end of the eighth pulse at the output of element 4, a low potential appears, and when the ninth pulse arrives on bus 5, a high potential appears at the output of element 4, which causes a transition of triggers 1-3 to state O. Low potential from a single output trigger 3 is fed to the input element 10 and causes at its output a high potential, which in turn causes a low potential at the output of element 9.

When the next nine pulses arrive at the counter input, the counter operates in the same way.

Thus, after the arrival of every ninth pulse, a positive pulse appears at bus 5 at the output of element 10.

Claims (2)

1. Author's certificate of the USSR 530468, cl. H 03 K 23/26, 1976. 2. Authors certificate of the USSR 281545, cl. H 03 K 23/00, 1972 {prototype).