SU369708A1 - LIBRARY I - Google Patents

Description

one

The invention relates to the field of pulsed technology and can be used in various forming devices.

A gated pulse driver is known that contains triggers with separate inputs, coincidence circuits, and inverters.

However, the known device contains an excessive static trigger, which complicates the circuit.

In order to simplify the circuit in the proposed former, the output of the unit arm of the first trigger is connected to the first inputs of the first and second coincidence circuits, and the output of the zero arm to the first inputs of the second and third coincidence circuits, the unit output of the second trigger is connected to the first inputs of the fifth and sixth coincidence circuits , the outputs of the second and third, fifth and sixth coincidence circuits are connected to the inputs of the elements forming the single and zero shoulders of the first and second triggers, the second inputs of the first, third and sixth coincidence circuits are combined and n connected to the output of the first inverter, the input of which is connected to the second inputs of the second, third and fifth coincidence circuits, the output of the first inverter is connected to the third inputs of the fifth and second coincidence circuits, and its input connected to the third input of the fourth co-ownership circuit is gating device input.

FIG. 1 shows a diagram of the proposed device; FIG. 2 - time diagram of work. Device contains static triggers.

1 and 2 with separate inputs, AND-HE 3-8 logic circuits for three inputs, inverters 9 and 10, input terminal 11, bus 12 clock pulses, output terminals 13 and 14, respectively, on the leading and trailing edges of the input pulse and bus 15 reset.

The device works as follows. The initial state of the circuit is set by a low-potential impulse coming through the reset bus 15, while at the terminal

// there is a low potential of the input pulse, and the clock 12 goes along bus 12 (see Fig. 2, a, b). At the output of the trigger 2, the output 16 of the trigger / low potential is set, and the output 17 of the trigger 1,

at the outputs of the matching circuits 3-5, 7 and 5 and at the output of the inverter 9, a high potential; at the outputs of the matching circuit 6 and the inverter 10 (see Fig. 2, 0), pulses are inverted with respect to the incoming

bus 12 clock pulses.

In the case of a high potential at terminal 11, a high potential of a clock pulse across busbar 12 through a coincidence circuit 4 triggers trigger 2 (see Fig. 2, d) and prepares a coincidence circuit 7 for operation, with the output circuit 6 a high potential arises, and a low potential at the output of the inverter 9.

The next time the potential changes across bus 12 from high to low through the coincidence circuit 7, a trigger is triggered /, the front edge of the first output pulse is formed at the device terminal 13 (see Fig. 2, e), the trigger output 16. and at the output 17, a low potential (see Fig. 2, g, h), the coincidence circuit 4 is reset.

When the low potential of bus 12 changes to high through the coincidence circuit 5, the trigger 2 is reset, a high potential is established at the output of the matching circuit 7, and the trailing edge of the first output pulse is formed at the device terminal 13, and 5, inverted clock pulses are generated.

At the moment of occurrence, a high potential is established at the terminal P of the low-potential device of the input pulse at the output of the inverter 9, and through the coincidence circuit 3, a trigger 2 is triggered, at the output of which a high potential is established and prepares the coincidence circuit 8 for operation. The output of the coincidence circuit 3 is low potential, and the coincidence circuit 5 is reset.

When the potential of bus 12 changes from high to low through the coincidence circuit 8, the trigger / and the coincidence circuit 3 are reset, and the leading edge of the second output pulse is formed on the terminal 14 of the device (see Fig. 2, s).

The next time the potential changes across bus 12 from low to high through coincidence circuit 6, trigger 2 and coincidence circuit 8 are reset, the trailing edge of the second output pulse is formed at device terminal 14, and inverted clock pulses are output at the output of coincidence circuit 6.

Next, the device operates in a similar way, providing the formation of clock pulses along the leading and trailing edges of the input pulse.

Subject invention

A gated pulse driver containing triggers with separate inputs, matching circuits and inverters, characterized in that, in order to simplify the circuit,

the output of the unit arm of the first trigger is connected to the first inputs of the first and second coincidence circuits, and the output of the zero arm to the first inputs of the second and third coincidence circuits, the unit output of the second trigger is connected to the first inputs of the fifth and sixth coincidence circuits, outputs of the second and third, n of the one and sixth coincidence circuits are connected to the inputs of the elements forming the single and zero shoulders of the first and second triggers, the second inputs of the first, third and sixth coincidence circuits are combined and connected to the output of the first inverter, whose input is connected to the second inputs of the second, third and fifth coincidence circuits, the output of the first inverter

connected to the third inputs of the fifth and sixth coincidence circuits, and its input connected to the third input of the fourth coincidence circuit is a gate input of the device.

(Rig.2