SU1619387A1 - Clocking device - Google Patents

Abstract

The invention relates to a pulse technique and can be used in automation and computing devices. The purpose of the invention is to expand the functionality by ensuring the formation of a burst of pulses of undistorted duration is achieved by introducing output buses 13-2-13 M, inverter 8, counter 9 pulses, and block 10 of elements of coincidence. The device also contains the triggers 1.2, the elements AND-NOT 3,4,5,6, the inverter 7, the output bus 13.1, "I am 11 clock pulses, the bus 12 control. 1 irt. &

Description

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The invention relates to a pulse technique and can be used in automation and computing devices.

 The purpose of the invention is to enhance the functionality by ensuring the formation of a controlled burst of undistorted duration.

The drawing shows an electrical functional circuit diagram of the device.

The synchronization device contains the first 1 and second 2 triggers, the first to the fourth elements are NOT-3-6, the first 7 and the second 8 inverters, the counter 9 pulses, the block of 10 elements matching

The forward output of the first trigger 1 is connected to the first input of the first element AND-HE 3, the second input of which is connected to the clock bus 11 and through the first inverter 7 to the first input of the second element AND-HE 4, the second input of which is connected to the control bus 12, output - with the start input of the first trigger 1, the first reset input of which is connected to the third input of the second element AND-NO 4 and with the output of the third element AND-HE 5, the first input of which is connected to the direct output of the second trigger 2, and strobi- the input of the block 10 elements match En with the output of the first element AND-NOT 3, the counting input of the pulse counter 9 and the first input of the fourth element AND-NOT 6, the second input of which through the second inverter 8 is connected to the control bus 12, the output - to the reset input of the second trigger 2 and the second reset input the first trigger 1, the inverse output of which is connected to the reset input of the pulse counter 9, the outputs of which are connected to the corresponding inputs of the block of 10 coincidence elements, the last of the inputs of which is connected to the start input of the second trigger 2 and the second input of the third And- element E 5 outputs - with corresponding output lines 13.1,13.2 ... 13.N.

The synchronization device operates as follows.

At the initial time, the low potential on bus 12 triggers 1 and 2, counter 9 (through inverter 8 and element 6) are zeroed.

When a control pulse arrives on bus 12, for example, when a clock arrives on bus 11, the output of element 3 appears only after the passage of the clock pulse, since a negative signal from the output of inverter 7 blocks the passage through element 4.

0 At the end of the passage of tact; pulse, the positive potential from the output of the inverter 7 is fed to the input of element 4, and then from its output to the S input of trigger 1 and sets it to one state. A single potential arrives at the input of element 3, allowing the passage of clock pulses to the C input of counter 9. Output clock pulses are formed on buses 13.1, 13, 2, 13, 13. The duration of the output pulse is equal to the duration of the clock pulse. Upon the arrival of the N-clock pulse, trigger 2 is set to a single state. A slice of the N-clock pulse at the output of element 5 produces a low level signal, which sets trigger 1 to the zero state, thereby prohibiting

0 much further work of the circuit until the next clock pulse arrives.

Thus, on buses 13.1, 13.2, ..., 13.N are formed successively in synchronism with the clock pulses N pulses of the clock grid.

If the synchronization signal on the control bus 12 is terminated before N output pulses have time to be generated, the synchronization circuit will be zeroed out and further work will be prohibited at the moment of time corresponding to a low level on the bus 11 clock pulses. Moreover, with the last output pulse, a duration is formed equal to the duration of the previous output pulses.

The total number of generated Q output pulses is less than N and is proportional to the duration of the synchronization signal.

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Claims (1)

Invention Formula A synchronization device containing the first trigger, the direct output of which is connected to the first input 16 the house of the first NAND element, whose input is connected to the clock bus and through the first inverter, the torus to the first input of the second NAND element, the second input of which is connected to the control bus, the output to the start input of the first trigger, the first reset input of which connected to the third one by the input of the second NAND element and the output of the third NAND element, the first input of which is connected to the direct output of the second trigger, the fourth NAND element, the first and second output buses, characterized in that, in order to expand the functional opportunities and by ensuring the formation of a controlled burst of pulses of undistorted duration, n-output buses are introduced into it, a second inverter, a counter im76 o pulses and a block of coincidence elements, whose gate input is connected to the output of the first NAND element, to the counting input of the pulse counter and to the first input of the fourth NAND element, the second input of which through the second inverter is connected to the control bus, the output to the reset input of the second the trigger and the second reset input of the first trigger, the inverse output of which is connected to the reset input of the pulse counter, the outputs of which are connected to the corresponding inputs of the block of coincidence elements, the last of which inputs are connected to the input home run of the second flip-flop and a second input of the third AND-NOT outputs - a corresponding output tires.