SU1679611A1 - Clock pulses synchronization unit - Google Patents

Description

The invention relates to a pulse technique and can be used in devices of automation and computing. The purpose of the invention is to improve the reliability of work - achieved by the introduction of the trigger 5, elements 8 and 9 of the match. The device also contains triggers 1-4, elements 6 and 7 of coincidence, counter 10 of coincidence, control bus 11, bus 12 clock pulses, output bus 13, code bus 14. 1 Il.

1679611

1679611

The invention relates to a pulse

technology and can be * used in devices of automation and computing.

The purpose of the invention is to increase reliability.

The drawing shows the electrical functional diagram of the device.

The clock synchronization device contains the first-fifth triggers 1-5, the first-fourth elements 6-9 matches, the pulse counter 10, the ϋ- and K-inputs of the first trigger 1 are connected to the control bus 11, the direct output is connected to the ϋ-input of the second trigger 2 The direct output of which is connected to the first input of the first coincidence element 6, the second input of which is connected to the output of the pulse counter 10 and to the K input of the third trigger 3, the 5 input of which is connected to the output of the first coincidence element 6, direct output with the input the fourth trigger 4, the C input of which is connected to With the input of the first 1 and second 2 triggers, with a bus 12 clock pulses and with a counting input of the counter 10 pulses, direct output with the first input of the second coincidence element 7, the output of which is connected to the output bus 13 and with the 5 input of the fifth trigger 5, the second input - with the direct output of the third trigger; the 3.5 input of which is connected to the counting resolution enable input of the pulse counter 10, whose information inputs are connected to the code bus 14, and the inverse output of the fourth trigger 4 is connected to the first input of the third coincidence element 8, the output of which dinene with K-input of the second trigger 2, the second input with the inverse output of the fifth trigger 5, the direct output of which is connected to the first input of the fourth coincidence element 9, the second input of which is connected to the bus 12 clock pulses, the output to the C-input of the fifth trigger 5 , ϋ-input of which is connected to the direct output of the first trigger 1.

The clock synchronization device operates as follows.

In the initial state, the triggers 1-5 are in the state of logical "0", at the output of the counter 10 there is a positive potential. With the arrival of a high-level information signal, bus 11 is triggered by trigger 1 and the logical 1 is written. With the arrival of the clock edge, bus 12 is written to trigger 1. If the duration of the information signal is less than 1 / ίτ, where ίτ is the frequency of the pulses bus 12, before the arrival of the next clock pulse trigger 1 returns to the logical state "0"

input K and trigger 2 remains in its original state, i.e. Short-term positive interference is suppressed. If the duration of the information signal is greater than 1 / ίτ, then the logical "1" is recorded in trigger 2, from the direct output of which is fed to the first input of element 6. At the output. The last signal appears low level, which is fed to the 5-input of trigger 4 and translates it in the state of logical "1". With the arrival of the third clock pulse, trigger 3 is set to the logical state "1", a low-level potential appears at its inverse output, which is fed to the second input of element 8. A low-level signal appears at the output of the input, which blocks the trigger 2 at the K input against interference type "dopant". Thus, at the outputs of the flip-flop 2 and the element 6 along the front of the second clock signal is formed of duration 1 / ί _τ, which is output from the element 6 is input to preset counter 10. Counter 10 records information about the delay of the input signal from the code bus 14, providing the required phase mismatch between the input and output signals.After the number of counting clock pulses reaches the value of the set delay, a negative polarity pulse of duration 1 appears at the transfer output of counter 10 / 2 ί _τ> which goes to the K input of the trigger 3 and puts it into the logical state "0." The high level signal from the inverse output of the trigger 4 goes to the second input of the element 7, at the output to An expensive low level signal appears. With the arrival of the front of the next clock pulse, the trigger 3 is switched to the logical "0" state, from its direct output the low level signal goes to the first input of the element 7. Thus, the output pulse of the 7 generates an output pulse of negative polarity of 1/2 1/2 _τ duration, which 5-input translates trigger 5 into a logical "1" state.

The low level signal from the inverse output of the trigger 5 is fed to the second input of the element 8, prohibiting logical signal "1" passing through the element 8, coming to its first input from the inverse output of the trigger 3 with 1/2 ί _γ delay relative to the signal on the second input element 8. When the condition Tz> Tc is fulfilled, trigger 1 is in the logical "0" state. where tz is the delay time,

five

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installed on the counter; g _with - the duration of the information signal. At the ϋ-input of the trigger 5 there is a logical signal "1". On a slice of the clock pulse trigger 5 is transferred to a state of logical "O". The low level signal from the direct output of the trigger 5, which arrives at the first input of the element 9. Prohibits the arrival of clock pulses at the C input of the trigger 5 and thereby blocks its operation. At the inverse output of the trigger 5, a high level signal appears, which, by the second input of the element 8, removes blocking on the P input of the trigger 2. The device is reset. If the condition Gz> Tc is not met, then the triggers 1 and 5 are in the logical "1" state, the high level signal is present at the O input of the trigger 5 and with the arrival of the next clock pulse the state of the trigger 5 does not change. The Element 8 is closed and the trigger 2 is blocked. The device is in the blocking state until a high-level information signal arrives at its input. With the arrival of the information signal of the low level on the information input of the device over the clock pulse slice, the trigger 5 self-blocks and allows the blocking of the P input of trigger 2 through element 8, the device is reset.

The use of the invention allows to increase the reliability of the device in the work due to its additional blocking after actuation of a high level information signal at the time of its presence at its input. Additional blocking is implemented on the trigger 5, the coincidence element 9 and the element 8 allows to increase the phase difference between the input and output signals of the device to the value Δφ <T _С , where Δφ is the phase difference; T _{with the} period of the information signal,

Claims (1)

Claim synchronization device containing the first, second, third and fourth triggers, ϋ- and P-inputs of the first of which are connected to the control bus, direct output - to the вход-input of the second trigger, the direct output of which is connected to the first input of the first coincidence element, the second input of which is connected to the output of the pulse counter and - P-input of the third trigger, 5-input of which is connected to the output of the first element of coincidence, direct output - with ϋ-input of the fourth trigger, whose input is connected to C-input of the first trigger, with counting counter input and pulses and a clock bus, direct output to the first input of the second coincidence element, the output of which is connected to the output bus, and the information inputs of the pulse counter are connected to a code bus, different in that, in order to improve the reliability of operation, the first and second elements are entered into it matches, the fifth trigger, the 5th input of which is connected to the output of the second coincidence element, the second input of which is with the direct output of the third trigger, the 5th input of which is connected to the enable input of the pulse counter, and the inverse output The fourth trigger is connected to the first input of the third coincidence element, the output of which is connected to the P input of the second trigger, the second input to the inverse output of the fifth trigger, the direct output of which is connected to the first input of the fourth coincidence element, the second input of which is connected to the clock pulse bus, the output is with the C-input of the fifth trigger, the ϋ-input of which is connected to the third output of the first trigger.