SU839027A1 - Random pulse synchronizing device - Google Patents

Description

The invention relates to a pulse technique and can be used for separation in time of two sequences of random pulses, in particular, to obtain reciprocal signals of type 3 recording-reading, -count-reversal, etc. I A device containing a clock, counting trigger , triggers, logic circuits, and inverters that are polled by the outputs of a counting trigger. However, in a known device, the pulses at the outputs do not shift between themselves and can overlap (the degree of overlap is determined by The parameters of the output pulses to the leg-count of the trigger) and the duration of the input pulses must be less than the period of the following clock pulses. The closest technical solution to the present invention is a device for synchronizing pulse sequences containing triggers of type RS, countable trigger, AND, OR 2 elements. However, such a device has a low noise immunity - for longer pulses at the inputs over -j T, where T is the period following clock pulses, cxeivbi is excited — the number of output pulses is greater than the number of input pulses. The purpose of the invention is to improve the noise immunity of the device. This goal is achieved by the fact that a device for synchronizing random pulses, containing two channels, each of which consists of two D; - triggers, an inverter is inputted, the input of which is connected to the clock pulse bus and the synchronization input of the second trigger channel, and the output is connected to the synchronization input of the second, second channel trigger, and in each channel the synchronization input of the first trigger is connected to the input buses and the output is. with the enable input of the second trigger, the first output of which is connected to, the permission input, the first trigger, whose installation input is connected to the second output of the second trigger of this channel and to the installation input of the second trigger of another channel ala FIG. 1 shows a functional diagram of the device; in FIG. 2 - time diagrams of voltages at various points.

. A device for synchronizing random pulses contains two channels 1 and 2, and an inverter 3. Each synchronization channel consists of two D.-flip-flops, the first 4 and 5, and the second b and 7, respectively. The inputs of the flip-flops 4 and 5 are connected to the input buses 8 and 9, and the outputs of the flip-flops 4 and 5 are connected respectively to the enabling inputs of the flip-flops 6 and 7. The clock pulses are fed from the bus 10 to the input of the inverter 3 and the synchronization input of the flip-flop 6. The first outputs 11 and 12 of the flip-flops 6 and 7 are connected respectively to the resolution inputs of the flip-flops 4 and 5, and the second outputs 13 and 14 respectively to the installation inputs of the flip-flops 4 and 5 and in addition, the output 13 of the flip-flop b is connected to the input of the flip-flop 7, and the output 14 of the trigger 7 is connected to the input of the installation of the trigger 6. The output 15 of the inverter 3 is connected to the synchronization input of the trigger 7.

The device works as follows.

When pulses arrive at the buses 8 and 9, the triggers 4 and 5 are simultaneously cocked on their front Front. A single impulse is applied to the enable inputs Di of triggers b and 7 and a trigger b is coaxed to the forward positive edge of the clock sequence from bus 10 then from exit 13, trigger 4 is reset and trigger 7 is retained in the initial state. Upon the arrival of the second clock pulse from the bus 10, trigger b is reset, the trigger 4 and trigger 7 are reset, the enabling (zero) potential is applied to the D input of the trigger 4 from output 11. After that, a trigger is reset on the positive edge of the pulse from the output 15 of inverter 3 7, resetting flip-flop 5 and holding flip-flop 6 from output 14 of flip-flop 7, and when the second positive impulse arrives - resetting flip-flop 7, removing the installation signal from flip-flops 5 and 6 through output 14 of flip-flop 7, the enable potential is applied to input D of flip-flop 5 s output 12 mp ggera 7.

Thus, the device for synchronization of random I1 pulses generates pulses along two kangs of duration T with the arrangement

jT regardless of the duration of the input pulses. It should be noted that the proposed device generates only a synchronous pulse at the output signal at the input irrespective of their duration, which allows increasing the noise immunity of the device and extends its range of application.

Claims (2)

1. USSR author's certificate I 611294, cl. H 03 K 5/00, 1978. 2. USSR author's certificate No. 487457, cl. H 03 K 5/00, 1975.